Merge branch 'master' into sdtwigg_connectwrap_renamechisel3

1 files changed, 4 insertions, 3 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 459a3b67..12ae7e6b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -15,8 +15,8 @@ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransfo
   * of) other Data objects.
   */
 sealed abstract class Aggregate extends Data {
-  private[chisel3] def cloneTypeWidth(width: Width): this.type = cloneType
-  private[chisel3] def width: Width = flatten.map(_.width).reduce(_ + _)
+  private[core] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[core] def width: Width = flatten.map(_.width).reduce(_ + _)
 }
 
 object Vec {
@@ -388,5 +388,6 @@ class Bundle extends Aggregate {
 }
 
 private[core] object Bundle {
-  val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits", "chiselCloneType")
+  val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits",
+                      "widthOption", "chiselCloneType")
 }