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authorJack Koenig2019-04-23 16:24:19 -0700
committerGitHub2019-04-23 16:24:19 -0700
commit9bef2461e55c724354f20bce0d32c7f5e6ac45ff (patch)
treec0db6362db710d8069d5b7e147d6b65486d632ea /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
parent32acdcf63ab74e7d47d7600f2211a72dd19280c3 (diff)
Change size of memories from Int to BigInt (#1076)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 51b45828..64148170 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -89,9 +89,9 @@ trait VecFactory extends SourceInfoDoc {
}
/** Truncate an index to implement modulo-power-of-2 addressing. */
- private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { // scalastyle:ignore line.size.limit
+ private[core] def truncateIndex(idx: UInt, n: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { // scalastyle:ignore line.size.limit
// scalastyle:off if.brace
- val w = BigInt(n-1).bitLength
+ val w = (n-1).bitLength
if (n <= 1) 0.U
else if (idx.width.known && idx.width.get <= w) idx
else if (idx.width.known) idx(w-1,0)