Fix treatment of Vec of Analog and Vec of Bundle of Analog (#1091)

* IO(Analog) fixed for RawModule

* Add a Analog Port for RawModule test & spec

* Fixes around Module instantiation and ports in AnalogPortRawModuleTest

* Shorten Comment

* Add Data.isSynthesizable to distinguish SampleElementBinding

This helps clarify the notion of being bound but not hardware.
Data.topBindingOpt is now used to get the *actual* top binding,
including across SampleElements (eg. in Analog checking that the top is
bound to a Port or a Wire)

* Fix pretty printing for Vec

* Refactor tests for Vec of Analog, add test for Vec of Bundle of Analog

1 files changed, 2 insertions, 3 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index c75974f0..7e3920eb 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -136,7 +136,8 @@ object Vec extends VecFactory
 sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int)
     extends Aggregate with VecLike[T] {
   override def toString: String = {
-    s"$sample_element[$length]$bindingToString"
+    val elementType = sample_element.cloneType
+    s"$elementType[$length]$bindingToString"
   }
 
   private[core] override def typeEquivalent(that: Data): Boolean = that match {
@@ -155,8 +156,6 @@ sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int)
       child.bind(ChildBinding(this), resolvedDirection)
     }
 
-    // Note: this differs from the Aggregate.bind behavior on an empty Vec, since this looks at the
-    // sample element instead of actual elements.
     direction = sample_element.direction
   }