diff options
| author | Jim Lawson | 2016-09-28 08:43:59 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-28 09:25:32 -0700 |
| commit | 2edfe895e4ff9f751c52904f73fe701502aa926a (patch) | |
| tree | 5fc05aacab0938b53dedd5375e644fb3dd3dff18 /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | |
| parent | 0c73611321cf12ff07c68e867f94430a329075e7 (diff) | |
Don't use firrtlDirection for direction checks - fix #298.
firrtlDirection should only be used for emitting firrtl. Any checks on the actual direction should use the bound Direction `dir`.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 6baf5202..a0eefbfe 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -63,7 +63,7 @@ object Vec { val maxWidth = elts.map(_.width).reduce(_ max _) val vec = Wire(new Vec(t.cloneTypeWidth(maxWidth), elts.length)) def doConnect(sink: T, source: T) = { - if (elts.head.flatten.exists(_.firrtlDirection != Direction.Unspecified)) { + if (elts.head.flatten.exists(_.dir != Direction.Unspecified)) { sink bulkConnect source } else { sink connect source |