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authorJim Lawson2016-08-30 16:13:41 -0700
committerJim Lawson2016-08-30 16:13:41 -0700
commit19b7f92504dadce9226126751e25d8abbe17fcc3 (patch)
treebe8a8c0b92c567c4ec94b7c5a08e223eca6fa969 /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
parent8002f7ac6731b1da5e0d8e7b1536995a23878037 (diff)
parent0c34480c5049c000e03b7b1a174e4bd6cca682cb (diff)
Merge branch 'master' into gsdt
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 5e410ebd..5d294ea9 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -395,6 +395,6 @@ class Bundle extends Aggregate {
}
private[core] object Bundle {
- val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits",
- "widthOption", "chiselCloneType")
+ val keywords = List("flip", "asInput", "asOutput", "cloneType", "chiselCloneType", "toBits",
+ "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent")
}