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authorJim Lawson2016-10-05 16:18:59 -0700
committerGitHub2016-10-05 16:18:59 -0700
commit0675d2443c07bbd43723bf57694b688d2df08498 (patch)
tree5566195d427b5d75031726002f6b96d5742e3c08 /chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
parent7981c6d9e6d25fb27b25e1427794775c9f934a09 (diff)
parenta18002c879d14b6c51cd49311a3b2a99a6a204fc (diff)
Merge pull request #315 from ucb-bar/fix-rocket-chip
Give <> and := legacy behavior in compatibility mode
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 7b759493..9d8a9061 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -17,6 +17,8 @@ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransfo
sealed abstract class Aggregate extends Data {
private[core] def cloneTypeWidth(width: Width): this.type = cloneType
private[core] def width: Width = flatten.map(_.width).reduce(_ + _)
+ private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+ pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
}
object Vec {