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| author | Schuyler Eldridge | 2019-08-14 17:12:00 -0400 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-08-27 20:43:29 -0400 |
| commit | c485a3a89b80d7a5069f00a7cd8ebdfce0a84991 (patch) | |
| tree | a1d7ac067875bd4d8062d6d748a8e04e2982d151 /chiselFrontend/src/main/scala/chisel3/RawModule.scala | |
| parent | 4eff16bd76a461d76c52103b49889947ac1c9573 (diff) | |
Test stack trace trimming for ChiselStage
Use FIRRTL stage-style testing to check stdout printing without and
with --full-stacktrace.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/RawModule.scala')
0 files changed, 0 insertions, 0 deletions