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authorJack Koenig2019-08-13 15:06:58 +0530
committerGitHub2019-08-13 15:06:58 +0530
commit24dddea6dccea5a570cece78324a5db624c7303a (patch)
treeb03fa616d0b8796548604a3d2b564fd17cf4e2d8 /chiselFrontend/src/main/scala/chisel3/CompileOptions.scala
parentfddb5943b1d36925a5435d327c3312572e98ca58 (diff)
Add support for asynchronous reset (#1011)
Adds new AsyncReset and "abstract" Reset types. Reset is inferred in FIRRTL to be either AsyncReset or Bool. The "reset type" of a register is set by the type of its reset signal: val asyncReset: AsyncReset = IO(Input(AsyncReset())) val syncReset: Bool = IO(Input(Bool())) val abstractReset: Reset = IO(Input(Reset())) val asyncReg = withReset(asyncReset) { RegInit(0.U) } val syncReg = withReset(syncReset) { RegInit(0.U) } val inferredReg = withReset(abstractReset) { RegInit(0.U) } AsyncReset can be cast to and from Bool. Whereas synchronous reset is equivalent to a mux in front of a flip-flop and thus can be driven by logic, asynchronous reset requires that the reset value is a constant. This is checked in FIRRTL. Inference of the concrete type of a Reset occurs based on the type the Reset's drivers. This inference is very simple, it is simple forward propagation of the type, but it allows for writing blocks and modules that are agnostic to the reset type. In particular, the implicit `reset` value in MultiIOModule and thus Module is now concretely an instance of Reset and thus will be inferred in FIRRTL.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/CompileOptions.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/CompileOptions.scala12
1 files changed, 9 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala
index 33a41b72..ed410c6e 100644
--- a/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/CompileOptions.scala
@@ -20,6 +20,8 @@ trait CompileOptions {
val checkSynthesizable: Boolean
// Require explicit assignment of DontCare to generate "x is invalid"
val explicitInvalidate: Boolean
+ // Should the reset type of Module be a Bool or a Reset
+ val inferModuleReset: Boolean
}
object CompileOptions {
@@ -48,7 +50,9 @@ object ExplicitCompileOptions {
// Check that referenced Data have actually been declared.
val checkSynthesizable: Boolean,
// Require an explicit DontCare assignment to generate a firrtl DefInvalid
- val explicitInvalidate: Boolean
+ val explicitInvalidate: Boolean,
+ // Should the reset type of Module be a Bool or a Reset
+ val inferModuleReset: Boolean
) extends CompileOptions
// Collection of "not strict" connection compile options.
@@ -59,7 +63,8 @@ object ExplicitCompileOptions {
dontTryConnectionsSwapped = false,
dontAssumeDirectionality = false,
checkSynthesizable = false,
- explicitInvalidate = false
+ explicitInvalidate = false,
+ inferModuleReset = false
)
// Collection of "strict" connection compile options, preferred for new code.
@@ -69,6 +74,7 @@ object ExplicitCompileOptions {
dontTryConnectionsSwapped = true,
dontAssumeDirectionality = true,
checkSynthesizable = true,
- explicitInvalidate = true
+ explicitInvalidate = true,
+ inferModuleReset = true
)
}