Repackagecore rebase (#1078)

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

* Move Aggregate, Clock, Mem, Printf, Reg

* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

* Revive core package object to provide aliases for moved definitions.

* Cleanup package definitions; eliminate ambiguous implicits

* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

* Put BitPat back in chisel3.util

* More experimental motion - avoid multiple import definitions.

* Add experimental.FixedPoint alias

* Add EnumType definition to core package.
Update deprecated messages to refer to correct object

* Move FixedPoint into the experimental package (but keep it in Bits.scala).

* Add missing implicits to core/package - compatibility

* Cleanup: update ScalaDoc references; remove unused imports

* Add Reset alias to core/package

* Use common 3.2 version in deprecation warning

* Move Binding from core to internal.

* Optimize imports.

* Repair IntelliJ's overly cleanliness.

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

* Change == to reference equality (eq) in Data print (#1044)

* Remove @chiselName from MixedVec (#1045)

* Fix enum annotations (#936)

* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style

* Add Record to type hierarchy documentation

* Undeprecate isLit (#1048)

* move doNotDedup to experimental (#1008)

* Aggregate coverage - aggregate tests but not publishing (#1040)

Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.

* Check field referential equality in autoclonetype (#1047)

* Allow naming annotation to work outside builder context (#1051)

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Make core.DontCare private to chisel3 (#1054)

Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Detect bundle aliasing (#1050)

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Optimize imports.

* Move Analog to experimental.

* More repackage cleanup - reduce differences with master.

* Cleanup chisel3 references.

* More chisel3 reference cleanup.

* Merge cleanup.

* Remove unused import

* Bump core deprecation to 3.3

* Move DontCare back into Data.scala inside package internal

* Re-indent experimental/internal package code

* Move code back to original files - facilitate comparison with other branches

* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

* More master diff minimization.

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Move Analog to experimental.

More repackage cleanup - reduce differences with master.

Cleanup chisel3 references.

More chisel3 reference cleanup.

* Fix wrong directionality for Vec(Flipped())

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Put BitPat back in chisel3.util

More experimental motion - avoid multiple import definitions.

Add experimental.FixedPoint alias

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Add Reset alias to core/package

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Repair IntelliJ's overly cleanliness.

Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Merge cleanup.

Remove unused import

Bump core deprecation to 3.3

Move DontCare back into Data.scala inside package internal

Re-indent experimental/internal package code

Move code back to original files - facilitate comparison with other branches

Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

More master diff minimization.

Fix minor discrepancies with repackagecore-testbed

* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`

* Move the BaseModule object into the internal package.

1 files changed, 181 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/BlackBox.scala
new file mode 100644
index 00000000..f29962d7
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/BlackBox.scala
@@ -0,0 +1,181 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.experimental.{BaseModule, Param}
+import chisel3.internal.BaseBlackBox
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl._
+import chisel3.internal.throwException
+import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
+
+package internal {
+
+  private[chisel3] abstract class BaseBlackBox extends BaseModule
+
+}
+
+package experimental {
+
+  /** Parameters for BlackBoxes */
+  sealed abstract class Param
+  case class IntParam(value: BigInt) extends Param
+  case class DoubleParam(value: Double) extends Param
+  case class StringParam(value: String) extends Param
+  /** Unquoted String */
+  case class RawParam(value: String) extends Param
+
+  /** Defines a black box, which is a module that can be referenced from within
+    * Chisel, but is not defined in the emitted Verilog. Useful for connecting
+    * to RTL modules defined outside Chisel.
+    *
+    * A variant of BlackBox, this has a more consistent naming scheme in allowing
+    * multiple top-level IO and does not drop the top prefix.
+    *
+    * @example
+    * Some design require a differential input clock to clock the all design.
+    * With the xilinx FPGA for example, a Verilog template named IBUFDS must be
+    * integrated to use differential input:
+    * {{{
+    *  IBUFDS #(.DIFF_TERM("TRUE"),
+    *           .IOSTANDARD("DEFAULT")) ibufds (
+    *   .IB(ibufds_IB),
+    *   .I(ibufds_I),
+    *   .O(ibufds_O)
+    *  );
+    * }}}
+    *
+    * To instantiate it, a BlackBox can be used like following:
+    * {{{
+    * import chisel3._
+    * import chisel3.experimental._
+    *
+    * // Example with Xilinx differential buffer IBUFDS
+    * class IBUFDS extends ExtModule(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
+    *                                    "IOSTANDARD" -> "DEFAULT"
+    *                      )) {
+    *   val O = IO(Output(Clock()))
+    *   val I = IO(Input(Clock()))
+    *   val IB = IO(Input(Clock()))
+    * }
+    * }}}
+    * @note The parameters API is experimental and may change
+    */
+  abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Param]) extends BaseBlackBox {
+    private[chisel3] override def generateComponent(): Component = {
+      require(!_closed, "Can't generate module more than once")
+      _closed = true
+
+      val names = nameIds(classOf[ExtModule])
+
+      // Name ports based on reflection
+      for (port <- getModulePorts) {
+        require(names.contains(port), s"Unable to name port $port in $this")
+        port.setRef(ModuleIO(this, _namespace.name(names(port))))
+      }
+
+      // All suggestions are in, force names to every node.
+      // While BlackBoxes are not supposed to have an implementation, we still need to call
+      // _onModuleClose on all nodes (for example, Aggregates use it for recursive naming).
+      for (id <- getIds) {
+        id._onModuleClose
+      }
+
+      val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)}
+      val component = DefBlackBox(this, name, firrtlPorts, SpecifiedDirection.Unspecified, params)
+      _component = Some(component)
+      component
+    }
+
+    private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
+      implicit val sourceInfo = UnlocatableSourceInfo
+
+      for (x <- getModulePorts) {
+        pushCommand(DefInvalid(sourceInfo, x.ref))
+      }
+    }
+  }
+}
+
+/** Defines a black box, which is a module that can be referenced from within
+  * Chisel, but is not defined in the emitted Verilog. Useful for connecting
+  * to RTL modules defined outside Chisel.
+  *
+  * @example
+  * Some design require a differential input clock to clock the all design.
+  * With the xilinx FPGA for example, a Verilog template named IBUFDS must be
+  * integrated to use differential input:
+  * {{{
+  *  IBUFDS #(.DIFF_TERM("TRUE"),
+  *           .IOSTANDARD("DEFAULT")) ibufds (
+  *   .IB(ibufds_IB),
+  *   .I(ibufds_I),
+  *   .O(ibufds_O)
+  *  );
+  * }}}
+  *
+  * To instantiate it, a BlackBox can be used like following:
+  * {{{
+  * import chisel3._
+  * import chisel3.experimental._
+  *
+  * // Example with Xilinx differential buffer IBUFDS
+  * class IBUFDS extends BlackBox(Map("DIFF_TERM" -> "TRUE", // Verilog parameters
+  *                                   "IOSTANDARD" -> "DEFAULT"
+  *                      )) {
+  *   val io = IO(new Bundle {
+  *     val O = Output(Clock()) // IO names will be the same
+  *     val I = Input(Clock())  // (without 'io_' in prefix)
+  *     val IB = Input(Clock()) //
+  *   })
+  * }
+  * }}}
+  * @note The parameters API is experimental and may change
+  */
+abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox { // scalastyle:ignore line.size.limit
+  def io: Record
+
+  // Allow access to bindings from the compatibility package
+  protected def _compatIoPortBound() = portsContains(io) // scalastyle:ignore method.name
+
+  private[chisel3] override def generateComponent(): Component = {
+    _compatAutoWrapPorts()  // pre-IO(...) compatibility hack
+
+    // Restrict IO to just io, clock, and reset
+    require(io != null, "BlackBox must have io")
+    require(portsContains(io), "BlackBox must have io wrapped in IO(...)")
+    require(portsSize == 1, "BlackBox must only have io as IO")
+
+    require(!_closed, "Can't generate module more than once")
+    _closed = true
+
+    val namedPorts = io.elements.toSeq.reverse  // ListMaps are stored in reverse order
+
+    // setRef is not called on the actual io.
+    // There is a risk of user improperly attempting to connect directly with io
+    // Long term solution will be to define BlackBox IO differently as part of
+    //   it not descending from the (current) Module
+    for ((name, port) <- namedPorts) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+
+    // We need to call forceName and onModuleClose on all of the sub-elements
+    // of the io bundle, but NOT on the io bundle itself.
+    // Doing so would cause the wrong names to be assigned, since their parent
+    // is now the module itself instead of the io bundle.
+    for (id <- getIds; if id ne io) {
+      id._onModuleClose
+    }
+
+    val firrtlPorts = namedPorts map {namedPort => Port(namedPort._2, namedPort._2.specifiedDirection)}
+    val component = DefBlackBox(this, name, firrtlPorts, io.specifiedDirection, params)
+    _component = Some(component)
+    component
+  }
+
+  private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
+    for ((_, port) <- io.elements) {
+      pushCommand(DefInvalid(UnlocatableSourceInfo, port.ref))
+    }
+  }
+}