Repackagecore rebase (#1078)

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

* Move Aggregate, Clock, Mem, Printf, Reg

* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

* Revive core package object to provide aliases for moved definitions.

* Cleanup package definitions; eliminate ambiguous implicits

* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

* Put BitPat back in chisel3.util

* More experimental motion - avoid multiple import definitions.

* Add experimental.FixedPoint alias

* Add EnumType definition to core package.
Update deprecated messages to refer to correct object

* Move FixedPoint into the experimental package (but keep it in Bits.scala).

* Add missing implicits to core/package - compatibility

* Cleanup: update ScalaDoc references; remove unused imports

* Add Reset alias to core/package

* Use common 3.2 version in deprecation warning

* Move Binding from core to internal.

* Optimize imports.

* Repair IntelliJ's overly cleanliness.

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

* Change == to reference equality (eq) in Data print (#1044)

* Remove @chiselName from MixedVec (#1045)

* Fix enum annotations (#936)

* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style

* Add Record to type hierarchy documentation

* Undeprecate isLit (#1048)

* move doNotDedup to experimental (#1008)

* Aggregate coverage - aggregate tests but not publishing (#1040)

Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.

* Check field referential equality in autoclonetype (#1047)

* Allow naming annotation to work outside builder context (#1051)

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Make core.DontCare private to chisel3 (#1054)

Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Detect bundle aliasing (#1050)

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Optimize imports.

* Move Analog to experimental.

* More repackage cleanup - reduce differences with master.

* Cleanup chisel3 references.

* More chisel3 reference cleanup.

* Merge cleanup.

* Remove unused import

* Bump core deprecation to 3.3

* Move DontCare back into Data.scala inside package internal

* Re-indent experimental/internal package code

* Move code back to original files - facilitate comparison with other branches

* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

* More master diff minimization.

* Try to eliminate JVM hang due to static initialization deadlock (#1053)

* Ignore empty aggregates elements when binding aggregate direction (#946)

Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction

* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates

* Implement connectFromBits in ChiselEnum (#1052)

This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf

* Move Analog to experimental.

More repackage cleanup - reduce differences with master.

Cleanup chisel3 references.

More chisel3 reference cleanup.

* Fix wrong directionality for Vec(Flipped())

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063

* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Put BitPat back in chisel3.util

More experimental motion - avoid multiple import definitions.

Add experimental.FixedPoint alias

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Add Reset alias to core/package

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Repair IntelliJ's overly cleanliness.

Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
 and deal with the subsequent fallout.

Move Aggregate, Clock, Mem, Printf, Reg

Move almost all chisel3.core definitions to chisel3 or chisel3.experimental

Revive core package object to provide aliases for moved definitions.

Cleanup package definitions; eliminate ambiguous implicits

Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.

Add EnumType definition to core package.
Update deprecated messages to refer to correct object

Move FixedPoint into the experimental package (but keep it in Bits.scala).

Add missing implicits to core/package - compatibility

Cleanup: update ScalaDoc references; remove unused imports

Use common 3.2 version in deprecation warning

Move Binding from core to internal.

Optimize imports.

Merge cleanup.

Remove unused import

Bump core deprecation to 3.3

Move DontCare back into Data.scala inside package internal

Re-indent experimental/internal package code

Move code back to original files - facilitate comparison with other branches

Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.

More master diff minimization.

Fix minor discrepancies with repackagecore-testbed

* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`

* Move the BaseModule object into the internal package.

1 files changed, 139 insertions, 0 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/Annotation.scala
new file mode 100644
index 00000000..506ec282
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/Annotation.scala
@@ -0,0 +1,139 @@
+// See LICENSE for license details.
+
+package chisel3.experimental
+
+import scala.language.existentials
+
+import chisel3.internal.{Builder, InstanceId}
+import chisel3.{CompileOptions, Data}
+import firrtl.Transform
+import firrtl.annotations.Annotation
+import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
+
+/** Interface for Annotations in Chisel
+  *
+  * Defines a conversion to a corresponding FIRRTL Annotation
+  */
+trait ChiselAnnotation {
+  /** Conversion to FIRRTL Annotation */
+  def toFirrtl: Annotation
+}
+object ChiselAnnotation {
+  @deprecated("Write a custom ChiselAnnotation subclass instead", "3.1")
+  def apply(component: InstanceId, transformClass: Class[_ <: Transform], value: String): ChiselLegacyAnnotation =
+    ChiselLegacyAnnotation(component, transformClass, value)
+  @deprecated("Write a custom ChiselAnnotation subclass instead", "3.1")
+  def unapply(anno: ChiselAnnotation): Option[(InstanceId, Class[_ <: Transform], String)] =
+    anno match {
+      case ChiselLegacyAnnotation(c, t, v) => Some(c, t, v)
+      case _ => None
+    }
+}
+
+/** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present
+  * during a run of
+  * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.experimental\.RawModule)* Driver.execute]].
+  * Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
+  * FIRRTL.
+  */
+// TODO There should be a FIRRTL API for this instead
+trait RunFirrtlTransform extends ChiselAnnotation {
+  def transformClass: Class[_ <: Transform]
+}
+
+// This exists for implementation reasons, we don't want people using this type directly
+final case class ChiselLegacyAnnotation private[chisel3] (
+    component: InstanceId,
+    transformClass: Class[_ <: Transform],
+    value: String) extends ChiselAnnotation with RunFirrtlTransform {
+  def toFirrtl: Annotation = Annotation(component.toNamed, transformClass, value)
+}
+private[chisel3] object ChiselLegacyAnnotation
+
+object annotate { // scalastyle:ignore object.name
+  def apply(anno: ChiselAnnotation): Unit = {
+    Builder.annotations += anno
+  }
+}
+
+/** Marks that a signal should not be removed by Chisel and Firrtl optimization passes
+  *
+  * @example {{{
+  * class MyModule extends Module {
+  *   val io = IO(new Bundle {
+  *     val a = Input(UInt(32.W))
+  *     val b = Output(UInt(32.W))
+  *   })
+  *   io.b := io.a
+  *   val dead = io.a +% 1.U // normally dead would be pruned by DCE
+  *   dontTouch(dead) // Marking it as such will preserve it
+  * }
+  * }}}
+  *
+  * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations
+  * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods
+  * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically.
+  */
+object dontTouch { // scalastyle:ignore object.name
+  /** Marks a signal to be preserved in Chisel and Firrtl
+    *
+    * @note Requires the argument to be bound to hardware
+    * @param data The signal to be marked
+    * @return Unmodified signal `data`
+    */
+  def apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T = {
+    if (compileOptions.checkSynthesizable) {
+      requireIsHardware(data, "Data marked dontTouch")
+    }
+    annotate(new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(data.toNamed) })
+    data
+  }
+}
+
+/** Marks that a module to be ignored in Dedup Transform in Firrtl pass
+  *
+  * @example {{{
+  *  def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
+  *    val m = Module(new Module {
+  *      val io = IO(new Bundle {
+  *        val a = Input(UInt(32.W))
+  *        val b = Input(UInt(32.W))
+  *        val out = Output(UInt(32.W))
+  *      })
+  *      override def desiredName = "adder_" + myNname
+  *      io.out := io.a + io.b
+  *    })
+  *    doNotDedup(m)
+  *    m.io.a := a
+  *    m.io.b := b
+  *    m.io.out
+  *  }
+  *
+  *class AdderTester extends Module
+  *  with ConstantPropagationTest {
+  *  val io = IO(new Bundle {
+  *    val a = Input(UInt(32.W))
+  *    val b = Input(UInt(32.W))
+  *    val out = Output(Vec(2, UInt(32.W)))
+  *  })
+  *
+  *  io.out(0) := fullAdder(io.a, io.b, "mod1")
+  *  io.out(1) := fullAdder(io.a, io.b, "mod2")
+  * }
+  * }}}
+  *
+  * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations
+  * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods
+  * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically.
+  */
+
+object doNotDedup { // scalastyle:ignore object.name
+  /** Marks a module to be ignored in Dedup Transform in Firrtl
+    *
+    * @param data The module to be marked
+    * @return Unmodified signal `module`
+    */
+   def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
+    annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) })
+  }
+}