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authorJim Lawson2020-01-07 14:35:18 -0800
committerGitHub2020-01-07 14:35:18 -0800
commitc4aa70f64ad5ecd8a5557ad0e4777f245768d865 (patch)
treea447f56b55065bdc2f4e05e0195f050e2cb431db /chiselFrontend/src/main/scala/chisel3/Aggregate.scala
parent2224274cc5a42caa1e74b45573b4c7c09c85d227 (diff)
parentd4300b9deae6dde7ce0f314ea73a9ca4a1c3868c (diff)
Merge branch 'master' into add-asbool-to-clock
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/Aggregate.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/Aggregate.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
index 42b40ed9..8141fdba 100644
--- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
@@ -43,7 +43,7 @@ sealed abstract class Aggregate extends Data {
}
}
- override def litOption: Option[BigInt] = ??? // TODO implement me
+ override def litOption: Option[BigInt] = None // TODO implement me
/** Returns a Seq of the immediate contents of this Aggregate, in order.
*/