summaryrefslogtreecommitdiff
path: root/build.sc
diff options
context:
space:
mode:
authorJack2022-01-12 04:27:19 +0000
committerJack2022-01-12 04:27:19 +0000
commit29df513e348cc809876893f650af8180f0190496 (patch)
tree06daaea954b4e5af7113f06e4bdbb78b33515cb3 /build.sc
parent5242ce90659decb9058ee75db56e5c188029fbf9 (diff)
parent747d16311bdf185d2e98e452b14cb5d8ccca004c (diff)
Merge branch 'master' into 3.5-release
Diffstat (limited to 'build.sc')
-rw-r--r--build.sc3
1 files changed, 2 insertions, 1 deletions
diff --git a/build.sc b/build.sc
index 3a4b4157..a26770cd 100644
--- a/build.sc
+++ b/build.sc
@@ -1,6 +1,7 @@
import mill._
import mill.scalalib._
import mill.scalalib.publish._
+import mill.scalalib.scalafmt._
import coursier.maven.MavenRepository
import $ivy.`com.lihaoyi::mill-contrib-buildinfo:$MILL_VERSION`
import mill.contrib.buildinfo.BuildInfo
@@ -29,7 +30,7 @@ def getTestVersion(dep: String, org: String = "edu.berkeley.cs") = {
}
// Since chisel contains submodule core and macros, a CommonModule is needed
-trait CommonModule extends CrossSbtModule with PublishModule {
+trait CommonModule extends CrossSbtModule with PublishModule with ScalafmtModule {
def firrtlModule: Option[PublishModule] = None
def firrtlIvyDeps = if (firrtlModule.isEmpty) Agg(