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| author | Abongwa Bonalais | 2021-10-21 07:08:10 +0100 |
|---|---|---|
| committer | GitHub | 2021-10-21 06:08:10 +0000 |
| commit | cc84773743a092c901dbbcdf04bed01d310f2705 (patch) | |
| tree | 1dd89e19b0b08188f376666d2a68817c4899b5be /README.md | |
| parent | d6907893f019ee86573dc81768884150e541dba3 (diff) | |
Create CONTRIBUTING.md (#2191)
* Create CONTRIBUTING.md
* Update README.md
Added guide for new contributors
* Update CONTRIBUTING.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update CONTRIBUTING.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update README.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update CONTRIBUTING.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update CONTRIBUTING.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update CONTRIBUTING.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update README.md
updated link to CONTRIBUTING.md
* Update README.md
updated link to CONTRIBUTING.md
* Update README.md
* Update README.md
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update README.md
Reposition contributing guide
* Update CONTRIBUTING.md
removed verilog guide
Co-authored-by: Megan Wachs <megan@sifive.com>
* Update README.md
Added verilog tutorial link to useful resources area.
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -120,6 +120,8 @@ If you insist on setting up your own project, the magic SBT lines are: libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4" libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.3.4" % "test" ``` +### Guide For New Contributors +If you are trying to make a contribution to this project, please read [CONTRIBUTING.md](https://github.com/Burnleydev1/chisel3/blob/recent_PR/CONTRIBUTING.md) ### Design Verification @@ -136,6 +138,7 @@ These simulation-based verification tools are available for Chisel: - [**ScalaDoc**](https://www.chisel-lang.org/api/latest/chisel3/index.html), a listing, description, and examples of the functionality exposed by Chisel - [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel - [**Website**](https://www.chisel-lang.org) ([source](https://github.com/freechipsproject/www.chisel-lang.org/)) +- [**asic-world**](http://www.asic-world.com/verilog/veritut.html) If you aren't familiar with verilog, this is a good tutorial. If you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/chisel3-vs-chisel2.html). |