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| author | Adam Izraelevitz | 2020-08-21 12:02:26 -0700 |
|---|---|---|
| committer | GitHub | 2020-08-21 19:02:26 +0000 |
| commit | 7edba2d10f980016462f917c6d21d64585ddfd6b (patch) | |
| tree | 3eb2a106b0e528b1ae8ed05b54200f828902de09 /README.md | |
| parent | 70fd01d4b0ad18a87bc46558ff246254792aa9b8 (diff) | |
Added website docs and mdoc. (#1560)
* Added website docs and mdoc. Removed all warnings
* Updated README and added build to circle ci
* Added how to build documentation, deprecated wiki
* Fix copypasta
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -1,4 +1,4 @@ - + --- @@ -26,7 +26,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt Consider an FIR filter that implements a convolution operation, as depicted in this block diagram: -<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/fir_filter.svg?sanitize=true" width="512" /> +<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/docs/src/images/fir_filter.svg?sanitize=true" width="512" /> While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such: |