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| author | mergify[bot] | 2021-11-21 05:45:01 +0000 |
|---|---|---|
| committer | GitHub | 2021-11-21 05:45:01 +0000 |
| commit | 7adc8063570994dc87a9bfe151b6800d45e26bbc (patch) | |
| tree | a69854ddb53c1b6540d78e3eb2b50d589168ccfe /README.md | |
| parent | aadd08e1e88947b615749be139ce36f4fbbbedf0 (diff) | |
| parent | 0a8bc71dde53f45672eb249454262a6a31c27e93 (diff) | |
Merge branch 'master' into update/sbt-mdoc-2.2.24
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -120,6 +120,8 @@ If you insist on setting up your own project, the magic SBT lines are: libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4" libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.3.4" % "test" ``` +### Guide For New Contributors +If you are trying to make a contribution to this project, please read [CONTRIBUTING.md](https://github.com/Burnleydev1/chisel3/blob/recent_PR/CONTRIBUTING.md) ### Design Verification @@ -136,6 +138,8 @@ These simulation-based verification tools are available for Chisel: - [**ScalaDoc**](https://www.chisel-lang.org/api/latest/chisel3/index.html), a listing, description, and examples of the functionality exposed by Chisel - [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel - [**Website**](https://www.chisel-lang.org) ([source](https://github.com/freechipsproject/www.chisel-lang.org/)) +- [**Scastie (3.5.0-RC1)**](https://scastie.scala-lang.org/KtzZQ3nFTea9KoNh0tRqtg) +- [**asic-world**](http://www.asic-world.com/verilog/veritut.html) If you aren't familiar with verilog, this is a good tutorial. If you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/chisel3-vs-chisel2.html). |