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authorJim Lawson2019-03-20 16:57:24 -0700
committerAlbert Magyar2019-03-20 16:57:24 -0700
commit5f8344cb2ef3571a1fe01e8a2b6827fa4ff1b2e0 (patch)
tree36f6457ee071507e48ea8cdb25293bd114683acc /README.md
parent1894319c712628c22ccbc9c174505f9c1c186b69 (diff)
Replace textual release version with Shields SemVer badge. (#1043)
* Replace textual release version with Shields SemVer badge. * Provide useful button action for release badge.
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[![Join the chat at https://gitter.im/freechipsproject/chisel3](https://badges.gitter.im/freechipsproject/chisel3.svg)](https://gitter.im/freechipsproject/chisel3?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
[![CircleCI](https://circleci.com/gh/freechipsproject/chisel3/tree/master.svg?style=shield)](https://circleci.com/gh/freechipsproject/chisel3/tree/master)
+[![GitHub tag (latest SemVer)](https://img.shields.io/github/tag/freechipsproject/chisel3.svg?label=release)](https://github.com/freechipsproject/chisel3/releases/latest)
Chisel is a new hardware construction language to support advanced hardware design and circuit generation.
The latest iteration of [Chisel](https://chisel.eecs.berkeley.edu/) is Chisel3,
which uses Firrtl as an intermediate hardware representation language.
Chisel3 releases are available as jars on Sonatype/Nexus/Maven and as tagged branches on the [releases tab](https://github.com/freechipsproject/chisel3/releases) of this repository.
-The latest release is [3.1.3](https://github.com/freechipsproject/chisel3/releases/tag/v3.1.3).
Please visit the [Wiki](https://github.com/ucb-bar/chisel3/wiki) for documentation!