Add source info / compile options transforms to Mem accessors (#744)

Fixes #708

3 files changed, 41 insertions, 3 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 72d91c3c..2c8e1a1e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -46,12 +46,18 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId {
   /** Creates a read/write accessor into the memory with dynamic addressing.
     * See the class documentation of the memory for more detailed information.
     */
-  def apply(idx: UInt)(implicit compileOptions: CompileOptions): T = makePort(UnlocatableSourceInfo, idx, MemPortDirection.INFER)
+  def apply(x: UInt): T = macro SourceInfoTransform.xArg
+
+  def do_apply(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
+    makePort(sourceInfo, idx, MemPortDirection.INFER)
 
   /** Creates a read accessor into the memory with dynamic addressing. See the
     * class documentation of the memory for more detailed information.
     */
-  def read(idx: UInt)(implicit compileOptions: CompileOptions): T = makePort(UnlocatableSourceInfo, idx, MemPortDirection.READ)
+  def read(x: UInt): T = macro SourceInfoTransform.xArg
+
+  def do_read(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
+    makePort(sourceInfo, idx, MemPortDirection.READ)
 
   /** Creates a write accessor into the memory.
     *
@@ -144,7 +150,9 @@ object SyncReadMem {
   * result is undefined (unlike Vec, where the last assignment wins)
   */
 sealed class SyncReadMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
-  def read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+  def read(x: UInt, en: Bool): T = macro SourceInfoTransform.xEnArg
+
+  def do_read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     val a = Wire(UInt())
     var port: Option[T] = None
     when (enable) {
diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
index b7d40901..47c77c98 100644
--- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala
@@ -123,6 +123,10 @@ class SourceInfoTransform(val c: Context) extends AutoSourceTransform {
   def xyArg(x: c.Tree, y: c.Tree): c.Tree = {
     q"$thisObj.$doFuncTerm($x, $y)($implicitSourceInfo, $implicitCompileOptions)"
   }
+
+  def xEnArg(x: c.Tree, en: c.Tree): c.Tree = {
+    q"$thisObj.$doFuncTerm($x, $en)($implicitSourceInfo, $implicitCompileOptions)"
+  }
 }
 
 class CompileOptionsTransform(val c: Context) extends AutoSourceTransform {
diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
new file mode 100644
index 00000000..81b5307c
--- /dev/null
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -0,0 +1,26 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import chisel3.util._
+import chisel3.testers.BasicTester
+
+class MemVecTester extends BasicTester {
+  val mem = Mem(2, Vec(2, UInt(8.W)))
+
+  // Circuit style tester is definitely the wrong abstraction here
+  val (cnt, wrap) = Counter(true.B, 2)
+  mem(0)(0) := 1.U
+
+  when (cnt === 1.U) {
+    assert(mem.read(0.U)(0) === 1.U)
+    stop()
+  }
+}
+
+class MemorySpec extends ChiselPropSpec {
+  property("Mem of Vec should work") {
+    assertTesterPasses { new MemVecTester }
+  }
+}