Remove all references to Backends, only backend is FIRRTL

3 files changed, 3 insertions, 54 deletions

diff --git a/src/main/scala/Chisel/Backend.scala b/src/main/scala/Chisel/Backend.scala
deleted file mode 100644
index 9b8bfb6d..00000000
--- a/src/main/scala/Chisel/Backend.scala
+++ /dev/null
@@ -1,10 +0,0 @@
-package Chisel
-import Chisel._
-
-class Backend;
-class FloBackend extends Backend;
-class CppBackend extends Backend;
-class VerilogBackend extends Backend;
-class FPGABackend extends Backend;
-class DotBackend extends Backend;
-class SysCBackend extends Backend;
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index f561e156..5baaafaf 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -264,7 +264,6 @@ object Driver extends FileSystemUtilities{
         case "--vcd" => isVCD = true
         case "--vcdMem" => isVCDMem = true
         case "--v" => backendName = "v"
-        // case "--moduleNamePrefix" => Backend.moduleNamePrefix = args(i + 1); i += 1
         case "--inlineMem" => isInlineMem = true
         case "--noInlineMem" => isInlineMem = false
         case "--assert" => isAssert = true
@@ -300,21 +299,6 @@ object Driver extends FileSystemUtilities{
             isDebug = true
             emitTempNodes = true
         }
-          /*
-        // Dreamer configuration flags
-        case "--numRows" => {
-          if (backend.isInstanceOf[FloBackend]) {
-            backend.asInstanceOf[FloBackend].DreamerConfiguration.numRows = args(i+1).toInt
-          }
-          i += 1
-        }
-        case "--numCols" => {
-          if (backend.isInstanceOf[FloBackend]) {
-            backend.asInstanceOf[FloBackend].DreamerConfiguration.numCols = args(i+1).toInt
-          }
-          i += 1
-        }
-           */
         case any => ChiselError.warning("'" + arg + "' is an unknown argument.")
       }
       i += 1
@@ -323,17 +307,6 @@ object Driver extends FileSystemUtilities{
     if (!isVCD) {
       isVCDinline = false
     }
-    // Set the backend after we've interpreted all the arguments.
-    // (The backend may want to configure itself based on the arguments.)
-    backend = backendName match  {
-      case "v" => new VerilogBackend
-      case "c" => new CppBackend
-      case "flo" => new FloBackend
-      case "dot" => new DotBackend
-      case "fpga" => new FPGABackend
-      case "sysc" => new SysCBackend
-      case _ => Class.forName(backendName).newInstance.asInstanceOf[Backend]
-    }
   }
 
   var warnInputs = false
@@ -370,7 +343,6 @@ object Driver extends FileSystemUtilities{
   var hasMem = false
   var hasSRAM = false
   var sramMaxSize = 0
-  var backend: Backend = null
   var topComponent: Module = null
   val components = ArrayBuffer[Module]()
   val sortedComps = ArrayBuffer[Module]()
diff --git a/src/main/scala/Chisel/Tester.scala b/src/main/scala/Chisel/Tester.scala
index c92abfeb..f8fb23fc 100644
--- a/src/main/scala/Chisel/Tester.scala
+++ b/src/main/scala/Chisel/Tester.scala
@@ -50,7 +50,7 @@ class Snapshot(val t: Int) {
 }
 
 class ManualTester[+T <: Module]
-    (val c: T, val isT: Boolean = true) {
+    (val c: T, val isT: Boolean = true, val skipVPDMessage: Boolean = true) {
   var testIn:  InputStream  = null
   var testOut: OutputStream = null
   var testErr: InputStream  = null
@@ -360,18 +360,6 @@ class ManualTester[+T <: Module]
     val target = "cd " + Driver.targetDir + " && ./" + n
     val cmd = target
     println("RUNNING " + cmd)
-    /*
-      (if (Driver.backend.isInstanceOf[FloBackend]) {
-         val dir = Driver.backend.asInstanceOf[FloBackend].floDir
-         val command = ArrayBuffer(dir + "fix-console", ":is-debug", "true", ":filename", target + ".hex", ":flo-filename", target + ".mwe.flo")
-         if (Driver.isVCD) { command ++= ArrayBuffer(":is-vcd-dump", "true") }
-         if (Driver.emitTempNodes) { command ++= ArrayBuffer(":emit-temp-nodes", "true") }
-         command ++= ArrayBuffer(":target-dir", Driver.targetDir)
-         command.mkString(" ")
-      } else {
-         target + (if (Driver.backend.isInstanceOf[VerilogBackend]) " -q +vcs+initreg+0 " else "")
-      })
-     */
     println("SEED " + Driver.testerSeed)
     println("STARTING " + n)
     val processBuilder = Process(Seq("bash", "-c", cmd))
@@ -380,8 +368,7 @@ class ManualTester[+T <: Module]
     waitForStreams()
     t = 0
     reset(5)
-    // Skip vpd message
-    if (Driver.backend.isInstanceOf[VerilogBackend] && Driver.isDebug) {
+    if (skipVPDMessage) {
       var vpdmsg = testIn.read
       while (vpdmsg != '\n' && vpdmsg != -1)
         vpdmsg = testIn.read
@@ -411,7 +398,7 @@ class ManualTester[+T <: Module]
   }
 }
 
-class Tester[+T <: Module](c: T, isTrace: Boolean = true) extends ManualTester(c, isTrace) {
+class Tester[+T <: Module](c: T, isTrace: Boolean = true, skipVPDMessage: Boolean = false) extends ManualTester(c, isTrace, skipVPDMessage) {
   start()
 }