Suppress some scala compiler warnings

@unchecked is better than matching on _ in this case, because we want to
fail on an unexpected case, rather than silently proceed.

2 files changed, 8 insertions, 8 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index efecf343..2599a20a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -124,7 +124,7 @@ object BiConnect {
     if( (left_mod == context_mod) &&
         (right_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
       // Thus, right node better be a port node and thus have a direction hint
-      (left_direction, right_direction) match {
+      ((left_direction, right_direction): @unchecked) match {
         //    CURRENT MOD   CHILD MOD
         case (Some(Input),  Some(Input))  => issueConnectL2R(left, right)
         case (None,         Some(Input))  => issueConnectL2R(left, right)
@@ -142,7 +142,7 @@ object BiConnect {
     else if( (right_mod == context_mod) &&
              (left_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
       // Thus, left node better be a port node and thus have a direction hint
-      (left_direction, right_direction) match {
+      ((left_direction, right_direction): @unchecked) match {
         //    CHILD MOD     CURRENT MOD
         case (Some(Input),  Some(Input))  => issueConnectR2L(left, right)
         case (Some(Input),  None)         => issueConnectR2L(left, right)
@@ -158,7 +158,7 @@ object BiConnect {
 
     // CASE: Context is same module that both left node and right node are in
     else if( (context_mod == left_mod) && (context_mod == right_mod) ) {
-      (left_direction, right_direction) match {
+      ((left_direction, right_direction): @unchecked) match {
         //    CURRENT MOD   CURRENT MOD
         case (Some(Input),  Some(Output)) => issueConnectL2R(left, right)
         case (Some(Input),  None)         => issueConnectL2R(left, right)
@@ -209,7 +209,7 @@ object BiConnect {
              (right_mod._parent.map(_ == context_mod).getOrElse(false))
     ) {
       // Thus both nodes must be ports and have a direction hint
-      (left_direction, right_direction) match {
+      ((left_direction, right_direction): @unchecked) match {
         //    CHILD MOD     CHILD MOD
         case (Some(Input),  Some(Output)) => issueConnectR2L(left, right)
         case (Some(Output), Some(Input))  => issueConnectL2R(left, right)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
index ef48709b..fcb14e6f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -115,7 +115,7 @@ object MonoConnect {
 
     // CASE: Context is same module that both left node and right node are in
     if( (context_mod == sink_mod) && (context_mod == source_mod) ) {
-      (sink_direction, source_direction) match {
+      ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CURRENT MOD   CURRENT MOD
         case (Some(Output), _) => issueConnect(sink, source)
@@ -128,7 +128,7 @@ object MonoConnect {
     else if( (sink_mod == context_mod) &&
              (source_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
       // Thus, right node better be a port node and thus have a direction
-      (sink_direction, source_direction) match {
+      ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CURRENT MOD   CHILD MOD
         case (None,         Some(Output)) => issueConnect(sink, source)
@@ -151,7 +151,7 @@ object MonoConnect {
     else if( (source_mod == context_mod) &&
              (sink_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
       // Thus, left node better be a port node and thus have a direction
-      (sink_direction, source_direction) match {
+      ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CHILD MOD     CURRENT MOD
         case (Some(Input),  _) => issueConnect(sink, source)
@@ -167,7 +167,7 @@ object MonoConnect {
              (source_mod._parent.map(_ == context_mod).getOrElse(false))
     ) {
       // Thus both nodes must be ports and have a direction
-      (sink_direction, source_direction) match {
+      ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CHILD MOD     CHILD MOD
         case (Some(Input),  Some(Input))  => issueConnect(sink, source)