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authorchick2016-11-09 15:57:06 -0800
committerducky2016-11-21 12:48:10 -0800
commitbb1cb894f6f1c88e0d60de1501e86d68de7c0f76 (patch)
tree1b308a6e4de6635012c6f91ae32699ee6132fbfe
parentdd28ef5d95e49c2822f9e37e8011ceab69cad532 (diff)
first attack on creating a range api for chisel3
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala9
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala57
-rw-r--r--coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala3
3 files changed, 68 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 4a09c70e..83733089 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -563,6 +563,10 @@ private[core] sealed trait UIntFactory {
result.binding = LitBinding()
result
}
+ /** Create a UInt with the specified range */
+ def apply(range: Range): UInt = {
+ width(range.getWidth)
+ }
/** Create a UInt with a specified width - compatibility with Chisel2. */
// NOTE: This resolves UInt(width = 32)
@@ -728,6 +732,11 @@ object SInt {
/** Create an SInt literal with specified width. */
def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+ /** Create a SInt with the specified range */
+ def apply(range: Range): SInt = {
+ width(range.getWidth)
+ }
+
def Lit(value: BigInt): SInt = Lit(value, Width())
def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
/** Create an SInt literal with specified width. */
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 17b869f2..d463d78e 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -109,6 +109,63 @@ case class Index(imm: Arg, value: Arg) extends Arg {
override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
}
+object Range {
+ def log2Up(value: BigInt): Int = {
+ require(value >= 0)
+ 1 max (value-1).bitLength
+ }
+}
+
+/*sealed abstract class Range {
+
+}*/
+sealed trait Bound
+sealed trait NumericBound[T] extends Bound {
+ val value: T
+}
+sealed case class Open[T](value: T) extends NumericBound[T]
+sealed case class Closed[T](value: T) extends NumericBound[T]
+
+sealed trait Range {
+ val min: Bound
+ val max: Bound
+ def getWidth: Width
+}
+
+sealed trait KnownIntRange extends Range {
+ val min: NumericBound[Int]
+ val max: NumericBound[Int]
+
+ require( (min, max) match {
+ case (low, Open(high_val)) => low.value < high_val
+ case (Open(low_val), high) => low_val < high.value
+ case (Closed(low_val), Closed(high_val)) => low_val <= high_val
+ })
+}
+
+sealed case class KnownUIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange {
+ require (min.value >= 0)
+
+ def getWidth: Width = max match {
+ case Open(v) => Width(BigInt(v - 1).bitLength.max(1))
+ case Closed(v) => Width(BigInt(v).bitLength.max(1))
+ }
+}
+
+sealed case class KnownSIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange {
+
+ val maxWidth = max match {
+ case Open(v) => Width(BigInt(v - 1).bitLength + 1)
+ case Closed(v) => Width(BigInt(v).bitLength + 1)
+ }
+ val minWidth = min match {
+ case Open(v) => Width(BigInt(v + 1).bitLength + 1)
+ case Closed(v) => Width(BigInt(v).bitLength + 1)
+ }
+ def getWidth: Width = maxWidth.max(minWidth)
+
+}
+
object Width {
def apply(x: Int): Width = KnownWidth(x)
def apply(): Width = UnknownWidth()
diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
index 20142d5d..ff5ba953 100644
--- a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
@@ -90,6 +90,7 @@ class RangeTransform(val c: Context) {
c.warning(c.enclosingPosition, s"$startInclusive ${showRaw(minArg)} ${showRaw(maxArg)} $endInclusive")
- q""
+ q"_root_.chisel3.internal.firrtl"
+
}
}