diff options
| author | ducky | 2016-11-17 11:21:59 -0800 |
|---|---|---|
| committer | ducky | 2016-11-21 13:31:12 -0800 |
| commit | b0cc0c93a80aec5bed54cfb11923636c09b7e180 (patch) | |
| tree | 5d3edabd4010cfb0e8dce125f39e89ee904143a0 | |
| parent | 9e32a39bda3fba11e6b0990e6ad5e7e17b5d8364 (diff) | |
SInt conversion finished, everything builds again
| -rw-r--r-- | build.sbt | 5 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 17 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/package.scala | 65 | ||||
| -rw-r--r-- | src/main/scala/chisel3/compatibility.scala | 1 | ||||
| -rw-r--r-- | src/main/scala/chisel3/package.scala | 2 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/AnnotatingExample.scala | 22 | ||||
| -rw-r--r-- | src/test/scala/chiselTests/DriverSpec.scala | 4 |
7 files changed, 81 insertions, 35 deletions
@@ -18,7 +18,8 @@ lazy val commonSettings = Seq ( version := "3.1-SNAPSHOT", git.remoteRepo := "git@github.com:ucb-bar/chisel3.git", autoAPIMappings := true, - scalaVersion := "2.11.7" + scalaVersion := "2.11.7", + scalacOptions := Seq("-deprecation") ) val defaultVersions = Map("firrtl" -> "1.1-SNAPSHOT") @@ -82,7 +83,7 @@ lazy val chiselSettings = Seq ( "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) } }, - + // Tests from other projects may still run concurrently. parallelExecution in Test := true, diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 7e467b88..aa73abf5 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg]) } val w = x - y + 1 if (isLit()) { - ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w) + ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w.W) } else { Binding.checkSynthesizable(this, s"'this' ($this)") pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y))) @@ -403,7 +403,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None) private[chisel3] def toType = s"UInt$width" override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = - value.asUInt(width).asInstanceOf[this.type] + value.asUInt(width.W).asInstanceOf[this.type] // TODO: refactor to share documentation with Num or add independent scaladoc final def unary_- (): UInt = macro SourceInfoTransform.noArg @@ -563,13 +563,13 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None) private[chisel3] def toType = s"SInt$width" override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = - SInt(value, width).asInstanceOf[this.type] + value.asSInt(width.W).asInstanceOf[this.type] final def unary_- (): SInt = macro SourceInfoTransform.noArg final def unary_-% (): SInt = macro SourceInfoTransform.noArg - def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt(0) - this - def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt(0) -% this + def unary_- (implicit sourceInfo: SourceInfo): SInt = 0.S - this + def unary_-% (implicit sourceInfo: SourceInfo): SInt = 0.S -% this /** add (default - no growth) operator */ override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo): SInt = @@ -637,7 +637,7 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None) final def abs(): UInt = macro SourceInfoTransform.noArg - def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt) + def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < 0.S, (-this).asUInt, this.asUInt) override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): SInt = binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, that) @@ -675,8 +675,7 @@ trait SIntFactory { } /** Create an SInt literal with specified width. */ - protected def Lit(value: BigInt, width: Width): SInt = { - + protected[chisel3] def Lit(value: BigInt, width: Width): SInt = { val lit = SLit(value, width) val result = new SInt(lit.width, Some(lit)) // Bind result to being an Literal @@ -685,6 +684,8 @@ trait SIntFactory { } } +object SInt extends SIntFactory + // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth // operations on a Bool make sense? /** A data type for booleans, defined as a single bit indicating true or false. diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala index 554e6238..7fb05c75 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/package.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala @@ -18,23 +18,62 @@ package chisel3 { * Prefer storing the result and then extracting from it. */ implicit class fromIntToLiteral(val x: Int) { - def U: UInt = UInt.Lit(BigInt(x), Width()) // scalastyle:ignore method.name - def S: SInt = SInt(BigInt(x), Width()) // scalastyle:ignore method.name + /** Int to UInt conversion, recommended style for constants. + */ + def U: UInt = UInt.Lit(BigInt(x), Width()) // scalastyle:ignore method.name + /** Int to SInt conversion, recommended style for constants. + */ + def S: SInt = SInt.Lit(BigInt(x), Width()) // scalastyle:ignore method.name + /** Int to UInt conversion, recommended style for variables. + */ def asUInt(): UInt = UInt.Lit(x, Width()) - def asSInt(): SInt = SInt(x, Width()) - def asUInt(width: Int): UInt = UInt.Lit(x, Width(width)) - def asSInt(width: Int): SInt = SInt(x, Width(width)) + /** Int to SInt conversion, recommended style for variables. + */ + def asSInt(): SInt = SInt.Lit(x, Width()) + /** Int to UInt conversion with specified width, recommended style for variables. + */ + def asUInt(width: Width): UInt = UInt.Lit(x, width) + /** Int to SInt conversion with specified width, recommended style for variables. + */ + def asSInt(width: Width): SInt = SInt.Lit(x, width) + + /** Int to UInt conversion with specified width, recommended style for variables. + */ + //def asUInt(width: Int): UInt = UInt.Lit(x, Width(width)) + /** Int to SInt conversion with specified width, recommended style for variables. + */ + //def asSInt(width: Int): SInt = SInt(x, Width(width)) + } implicit class fromBigIntToLiteral(val x: BigInt) { - def U: UInt = UInt.Lit(x, Width()) // scalastyle:ignore method.name - def S: SInt = SInt(x, Width()) // scalastyle:ignore method.name + /** Int to UInt conversion, recommended style for constants. + */ + def U: UInt = UInt.Lit(x, Width()) // scalastyle:ignore method.name + /** Int to SInt conversion, recommended style for constants. + */ + def S: SInt = SInt.Lit(x, Width()) // scalastyle:ignore method.name + /** Int to UInt conversion, recommended style for variables. + */ def asUInt(): UInt = UInt.Lit(x, Width()) - def asSInt(): SInt = SInt(x, Width()) - def asUInt(width: Int): UInt = UInt.Lit(x, Width(width)) - def asSInt(width: Int): SInt = SInt(x, width) + /** Int to SInt conversion, recommended style for variables. + */ + def asSInt(): SInt = SInt.Lit(x, Width()) + /** Int to UInt conversion with specified width, recommended style for variables. + */ + def asUInt(width: Width): UInt = UInt.Lit(x, width) + /** Int to SInt conversion with specified width, recommended style for variables. + */ + def asSInt(width: Width): SInt = SInt.Lit(x, width) + + /** Int to UInt conversion with specified width, recommended style for variables. + */ + // def asUInt(width: Int): UInt = UInt.Lit(x, Width(width)) + /** Int to SInt conversion with specified width, recommended style for variables. + */ + // def asSInt(width: Int): SInt = SInt(x, width) } implicit class fromStringToLiteral(val x: String) { @@ -65,11 +104,15 @@ package chisel3 { } implicit class fromBooleanToLiteral(val x: Boolean) { - def B: Bool = Bool(x) // scalastyle:ignore method.name + def B: Bool = Bool(x) // scalastyle:ignore method.name } implicit class fromDoubleToLiteral(val x: Double) { def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint) } + + implicit class fromIntToWidth(val x: Int) { + def W: Width = Width(x) // scalastyle:ignore method.name + } } }
\ No newline at end of file diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 69d02f9c..a9365ac3 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -147,6 +147,7 @@ package object Chisel { // scalastyle:ignore package.object.name implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x) implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x) implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x) + implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x) type BackendCompilationUtilities = chisel3.BackendCompilationUtilities val Driver = chisel3.Driver diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 1161a1ca..1a100480 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -180,7 +180,7 @@ package object chisel3 { // scalastyle:ignore package.object.name implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x) implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x) implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x) - + implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x) implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal { final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala index 04228d6b..0be3ba59 100644 --- a/src/test/scala/chiselTests/AnnotatingExample.scala +++ b/src/test/scala/chiselTests/AnnotatingExample.scala @@ -24,8 +24,8 @@ import scala.util.DynamicVariable class SomeSubMod(param1: Int, param2: Int) extends Module { val io = new Bundle { - val in = UInt(INPUT, 16) - val out = SInt(OUTPUT, 32) + val in = Input(UInt(16.W)) + val out = Output(SInt(32.W)) } val annotate = MyBuilder.myDynamicContext.annotationMap @@ -36,18 +36,18 @@ class SomeSubMod(param1: Int, param2: Int) extends Module { class AnnotatingExample extends Module { val io = new Bundle { - val a = UInt(INPUT, 32) - val b = UInt(INPUT, 32) - val e = Bool(INPUT) - val z = UInt(OUTPUT, 32) - val v = Bool(OUTPUT) + val a = Input(UInt(32.W)) + val b = Input(UInt(32.W)) + val e = Input(Bool()) + val z = Output(UInt(32.W)) + val v = Output(Bool()) val bun = new Bundle { - val nested_1 = UInt(INPUT, 12) - val nested_2 = Bool(OUTPUT) + val nested_1 = Input(UInt(12.W)) + val nested_2 = Output(Bool()) } } - val x = Reg(UInt(width = 32)) - val y = Reg(UInt(width = 32)) + val x = Reg(UInt(32.W)) + val y = Reg(UInt(32.W)) val subModule1 = Module(new SomeSubMod(1, 2)) val subModule2 = Module(new SomeSubMod(3, 4)) diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala index 4f9619e3..d77dbaf1 100644 --- a/src/test/scala/chiselTests/DriverSpec.scala +++ b/src/test/scala/chiselTests/DriverSpec.scala @@ -8,8 +8,8 @@ import org.scalatest.{Matchers, FreeSpec} class DummyModule extends Module { val io = IO(new Bundle { - val in = UInt(INPUT, 1) - val out = UInt(OUTPUT, 1) + val in = Input(UInt(1.W)) + val out = Output(UInt(1.W)) }) io.out := io.in } |
