Move migration info to wiki.

1 files changed, 0 insertions, 33 deletions

diff --git a/README.md b/README.md
index 531fe67e..387ee637 100644
--- a/README.md
+++ b/README.md
@@ -5,39 +5,6 @@ It is currently in BETA VERSION, so some Chisel features may change in the comin
 Please visit the [Wiki](https://github.com/ucb-bar/chisel3/wiki) for a more
 detailed description.
 
-## Chisel2 Migration
-For those moving from Chisel2, there were some backwards incompatible changes
-and your RTL needs to be modified to work with Chisel3. The required
-modifications are:
-
- - Wire declaration style:
-   ```
-   val wire = Bits(width = 15)
-   ```
-   becomes (in Chisel3):
-   ```
-   val wire = Wire(Bits(width = 15))
-   ```
-
- - Sequential memories:
-   ```
-   val addr = Reg(UInt())
-   val mem = Mem(UInt(width=8), 1024, seqRead = true)
-   val dout = when(enable) { mem(addr) }
-   ```
-   becomes (in Chisel3):
-   ```
-   val addr = UInt()
-   val mem = SeqMem(1024, UInt(width=8))
-   val dout = mem.read(addr, enable)
-   ```
-
-   Notice the address register is now internal to the SeqMem(), but the data
-   will still return on the subsequent cycle.
-
-Please refer to the [Chisel3 compatibility section](https://github.com/ucb-bar/chisel#chisel3)
-for instructions on preparing your Chisel2 designs for Chisel3.
-
 ## Overview
 Chisel3 is much more modular than Chisel2, and the compilation pipeline looks
 like: