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| author | Richard Lin | 2016-03-10 17:55:08 -0800 |
|---|---|---|
| committer | Richard Lin | 2016-03-10 17:55:08 -0800 |
| commit | 62794befadd8477af26919e453d4bdbbad83dd1f (patch) | |
| tree | 92252ecea61e5fdbccd07731cfacc60b85b6a873 | |
| parent | 38c381af64ac75e013f67a576c142254b5b7fd50 (diff) | |
| parent | b2155c0e058580c044af43347d777e9ebc2a699d (diff) | |
Merge pull request #117 from ucb-bar/readmechisel2compatibilitymode
Add pointer to Chisel3 compatibility on Chisel2 README.
| -rw-r--r-- | README.md | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -34,6 +34,9 @@ modifications are: Notice the address register is now internal to the SeqMem(), but the data will still return on the subsequent cycle. +Please refer to the [Chisel3 compatibility section](https://github.com/ucb-bar/chisel#chisel3) +for instructions on preparing your Chisel2 designs for Chisel3. + ## Overview Chisel3 is much more modular than Chisel2, and the compilation pipeline looks like: |