toBits and fromBits must be inverse operations

For Vec and Bundle, toBits and fromBits got the flattening order wrong
and so weren't inverses of each other.

1 files changed, 2 insertions, 2 deletions

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 3e03b199..eadba100 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -337,7 +337,7 @@ abstract class Data(dirArg: Direction) extends Id {
   def fromBits(n: Bits): this.type = {
     var i = 0
     val wire = Wire(this.cloneType)
-    for (x <- wire.flatten.reverse) {
+    for (x <- wire.flatten) {
       x := n(i + x.getWidth-1, i)
       i += x.getWidth
     }
@@ -962,7 +962,7 @@ class Bundle(dirArg: Direction = NO_DIR) extends Aggregate(dirArg) {
         }
       }
     }
-    elts sortWith (_._2._id < _._2._id)
+    elts sortWith (_._2._id > _._2._id)
   }
   override def collectElts =
     sortedElts.foreach(e => setFieldForId(cid, e._2.cid, e._1))