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| author | Andrew Waterman | 2015-07-28 04:34:04 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-07-28 04:34:04 -0700 |
| commit | 344978a378e5297d43a4159f6ae6f81ab4eede6b (patch) | |
| tree | 9068bdb7decc3533ec61c2c7558833d388679a22 | |
| parent | 98fcd9f0efd26f7af668f834acd2d6733a48b1b0 (diff) | |
Add missing Vec operator
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index fce33253..22bb555c 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -488,6 +488,9 @@ class Vec[T <: Data](elts: Iterable[T], dirArg: Direction = NO_DIR) extends Aggr def <> (that: Iterable[T]): Unit = this <> Vec(that).asInstanceOf[Data] + def := (that: Iterable[T]): Unit = + this := Vec(that).asInstanceOf[Data] + override def isReg = elt0.isReg override def isFlip = { val isSubFlip = elt0.isFlip |