Merge pull request #112 from ucb-bar/rocket-chip

Remove scalastyle test hook

3 files changed, 10 insertions, 4 deletions

diff --git a/build.sbt b/build.sbt
index 9d75cac1..3cd496bb 100644
--- a/build.sbt
+++ b/build.sbt
@@ -68,8 +68,6 @@ lazy val chiselBuildSettings = Seq (
   // Tests from other projects may still run concurrently.
   parallelExecution in Test := true,
 
-  (scalastyleConfig in Test) := baseDirectory.value / "scalastyle-test-config.xml",
-
   javacOptions ++= Seq("-target", "1.7")
   //  Hopefully we get these options back in Chisel3
   //  scalacOptions in (Compile, doc) <++= (baseDirectory in LocalProject("chisel"), version) map { (bd, v) =>
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index a6f61f69..61b74dcd 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -114,6 +114,13 @@ object Driver extends BackendCompilationUtilities {
     f
   }
 
-  // FIXME: This is hard coded and should come in from a command-line argument
-  def targetDir(): String = { "vsim/generated-src" }
+  private var target_dir: Option[String] = None
+  def parseArgs(args: Array[String]): Unit = {
+    for (i <- 0 until args.size) {
+      if (args(i) == "--targetDir")
+        target_dir = Some(args(i+1))
+    }
+  }
+
+  def targetDir(): String = { target_dir.get }
 }
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 750e8712..349f8b18 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -11,6 +11,7 @@ import java.io.File
   def run[T <: Module] (args: Array[String], gen: () => T) = {
     def circuit = Driver.elaborate(gen)
     def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+    Driver.parseArgs(args)
     Driver.dumpFirrtl(circuit, Option(output_file))
   }
 }