Remove implementation details from scaladoc.

You didn't want it, so Imma getting rid of it...

3 files changed, 15 insertions, 37 deletions

diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index 3d419934..de77a7e7 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -170,30 +170,19 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] {
   def write(idx: UInt, data: T): Unit
 
   /** Outputs true if p outputs true for every element.
-    *
-    * This generates into a function evaluation followed by a logical AND
-    * reduction.
     */
   def forall(p: T => Bool): Bool = (this map p).fold(Bool(true))(_ && _)
 
   /** Outputs true if p outputs true for at least one element.
-    *
-    * This generates into a function evaluation followed by a logical OR
-    * reduction.
     */
   def exists(p: T => Bool): Bool = (this map p).fold(Bool(false))(_ || _)
 
   /** Outputs true if the vector contains at least one element equal to x (using
     * the === operator).
-    *
-    * This generates into an equality comparison followed by a logical OR
-    * reduction.
     */
   def contains(x: T)(implicit evidence: T <:< UInt): Bool = this.exists(_ === x)
 
   /** Outputs the number of elements for which p is true.
-    *
-    * This generates into a function evaluation followed by a set bit counter.
     */
   def count(p: T => Bool): UInt = PopCount((this map p).toSeq)
 
@@ -203,23 +192,18 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] {
   private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i))
 
   /** Outputs the index of the first element for which p outputs true.
-    *
-    * This generates into a function evaluation followed by a priority mux.
     */
   def indexWhere(p: T => Bool): UInt = PriorityMux(indexWhereHelper(p))
 
   /** Outputs the index of the last element for which p outputs true.
-    *
-    * This generates into a function evaluation followed by a priority mux.
     */
   def lastIndexWhere(p: T => Bool): UInt = PriorityMux(indexWhereHelper(p).reverse)
 
   /** Outputs the index of the element for which p outputs true, assuming that
     * the there is exactly one such element.
     *
-    * This generates into a function evaluation followed by a one-hot mux. The
-    * implementation may be more efficient than a priority mux, but incorrect
-    * results are possible if there is not exactly one true element.
+    * The implementation may be more efficient than a priority mux, but
+    * incorrect results are possible if there is not exactly one true element.
     *
     * @note the assumption that there is only one element for which p outputs
     * true is NOT checked (useful in cases where the condition doesn't always
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 20136be3..41f13c48 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -27,7 +27,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   override def <> (that: Data): Unit = this := that
 
   /** Returns the specified bit on this wire as a [[Bool]], statically
-    * addressed. Generates no logic.
+    * addressed.
     */
   final def apply(x: BigInt): Bool = {
     if (x < 0) {
@@ -41,7 +41,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   }
 
   /** Returns the specified bit on this wire as a [[Bool]], statically
-    * addressed. Generates no logic.
+    * addressed.
     *
     * @note convenience method allowing direct use of Ints without implicits
     */
@@ -49,13 +49,13 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     apply(BigInt(x))
 
   /** Returns the specified bit on this wire as a [[Bool]], dynamically
-    * addressed. Generates logic: implemented as a variable shifter.
+    * addressed.
     */
   final def apply(x: UInt): Bool =
     (this >> x)(0)
 
   /** Returns a subset of bits on this wire from `hi` to `lo` (inclusive),
-    * statically addressed. Generates no logic.
+    * statically addressed.
     *
     * @example
     * {{{
@@ -106,8 +106,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   /** Returns this wire statically left shifted by the specified amount,
     * inserting zeros into the least significant bits.
     *
-    * The width of the output is `other` larger than the input. Generates no
-    * logic.
+    * The width of the output is `other` larger than the input.
     */
   def << (other: Int): Bits
 
@@ -115,7 +114,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
     * inserting zeros into the least significant bits.
     *
     * The width of the output is `pow(2, width(other))` larger than the input.
-    * Generates a dynamic shifter.
     */
   def << (other: UInt): Bits
 
@@ -126,20 +124,18 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   /** Returns this wire statically right shifted by the specified amount,
     * inserting zeros into the most significant bits.
     *
-    * The width of the output is the same as the input. Generates no logic.
+    * The width of the output is the same as the input.
     */
   def >> (other: Int): Bits
 
   /** Returns this wire dynamically right shifted by the specified amount,
     * inserting zeros into the most significant bits.
     *
-    * The width of the output is the same as the input. Generates a dynamic
-    * shifter.
+    * The width of the output is the same as the input.
     */
   def >> (other: UInt): Bits
 
-  /** Returns the contents of this wire as a [[Vec]] of [[Bool]]s. Generates no
-    * logic.
+  /** Returns the contents of this wire as a [[Vec]] of [[Bool]]s.
     */
   def toBools: Vec[Bool] = Vec.tabulate(this.getWidth)(i => this(i))
 
@@ -173,7 +169,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   /** Returns this wire concatenated with `other`, where this wire forms the
     * most significant part and `other` forms the least significant part.
     *
-    * The width of the output is sum of the inputs. Generates no logic.
+    * The width of the output is sum of the inputs.
     */
   def ## (other: Bits): UInt = {
     val w = this.width + other.width
@@ -249,12 +245,12 @@ abstract trait Num[T <: Data] {
   def >= (b: T): Bool
 
   /** Outputs the minimum of `this` and `b`. The resulting width is the max of
-    * the operands. Generates a comparison followed by a mux.
+    * the operands.
     */
   def min(b: T): T = Mux(this < b, this.asInstanceOf[T], b)
 
   /** Outputs the maximum of `this` and `b`. The resulting width is the max of
-    * the operands. Generates a comparison followed by a mux.
+    * the operands.
     */
   def max(b: T): T = Mux(this < b, b, this.asInstanceOf[T])
 }
diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index 85a436ed..679b8eb8 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -74,8 +74,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   private[Chisel] def flatten: IndexedSeq[Bits]
 
   /** Creates an new instance of this type, unpacking the input Bits into
-    * structured data. Generates no logic (should be either wires or a syntactic
-    * transformation).
+    * structured data.
     *
     * This performs the inverse operation of toBits.
     *
@@ -94,8 +93,7 @@ abstract class Data(dirArg: Direction) extends HasId {
     wire.asInstanceOf[this.type]
   }
 
-  /** Packs the value of this object as plain Bits. Generates no logic (should
-    * be either wires or a syntactic transformation).
+  /** Packs the value of this object as plain Bits.
     *
     * This performs the inverse operation of fromBits(Bits).
     */