Check module-specific compile options.

Import chisel3.NotStrict.CompileOptions in Chisel package.
Add CompileOptions tests.

6 files changed, 196 insertions, 13 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 857b25aa..969e5654 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package chisel3.core
 
 import chisel3.internal.Builder.{compileOptions, pushCommand}
@@ -70,7 +72,7 @@ object BiConnect {
         // Verify right has no extra fields that left doesn't have
         for((field, right_sub) <- right_b.elements) {
           if(!left_b.elements.isDefinedAt(field)) {
-            if (compileOptions.connectFieldsMustMatch) {
+            if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
               throw MissingLeftFieldException(field)
             }
           }
@@ -81,7 +83,7 @@ object BiConnect {
             right_b.elements.get(field) match {
               case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
               case None => {
-                if (compileOptions.connectFieldsMustMatch) {
+                if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
                   throw MissingRightFieldException(field)
                 }
               }
@@ -167,7 +169,7 @@ object BiConnect {
         case (None,         Some(Input))  => issueConnectR2L(left, right)
 
         case (Some(Input),  Some(Input))  => {
-          if (compileOptions.dontAssumeDirectionality) {
+          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
             throw BothDriversException
           } else {
             (left.binding, right.binding) match {
@@ -179,7 +181,7 @@ object BiConnect {
           }
         }
         case (Some(Output), Some(Output)) => {
-          if (compileOptions.dontAssumeDirectionality) {
+          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
             throw BothDriversException
           } else {
             (left.binding, right.binding) match {
@@ -191,7 +193,7 @@ object BiConnect {
           }
         }
         case (None,         None)         => {
-          if (compileOptions.dontAssumeDirectionality) {
+          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
             throw UnknownDriverException
           } else {
             issueConnectR2L(left, right)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index a32d3ade..b36794f1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -1,6 +1,6 @@
 package chisel3.core
 
-import chisel3.internal.Builder.compileOptions
+import chisel3.internal.Builder.{compileOptions, forcedModule}
 
 /**
  * The purpose of a Binding is to indicate what type of hardware 'entity' a
@@ -91,7 +91,7 @@ object Binding {
           element.binding = binder(unbound)
         }
           // If autoIOWrap is enabled and we're rebinding a PortBinding, just ignore the rebinding.
-        case portBound @ PortBinding(_, _) if (!compileOptions.requireIOWrap && binder.isInstanceOf[PortBinder]) =>
+        case portBound @ PortBinding(_, _) if (!(compileOptions.requireIOWrap || forcedModule.compileOptions.requireIOWrap)&& binder.isInstanceOf[PortBinder]) =>
         case binding => throw AlreadyBoundException(binding.toString)
       }
     )
@@ -145,7 +145,7 @@ object Binding {
         case binding =>
           // The following kludge is an attempt to provide backward compatibility
           // It should be done at at higher level.
-          if ((compileOptions.requireIOWrap || !elementOfIO(element)))
+          if ((compileOptions.requireIOWrap || forcedModule.compileOptions.requireIOWrap || !elementOfIO(element)))
             throw NotSynthesizableException
           else
             Binding.bind(element, PortBinder(element._parent.get), "Error: IO")
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
index 66729bac..41754827 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -79,7 +79,7 @@ object MonoConnect {
             source_b.elements.get(field) match {
               case Some(source_sub) => connect(sourceInfo, sink_sub, source_sub, context_mod)
               case None => {
-                if (compileOptions.connectFieldsMustMatch) {
+                if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
                   throw MissingFieldException(field)
                 }
               }
@@ -134,13 +134,13 @@ object MonoConnect {
         case (Some(Output), Some(Output)) => issueConnect(sink, source)
         case (Some(Output), Some(Input))  => issueConnect(sink, source)
         case (_,            None) => {
-          if (!compileOptions.dontAssumeDirectionality) {
+          if (!(compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality)) {
             issueConnect(sink, source)
           } else {
             throw UnreadableSourceException
           }
         }
-        case (Some(Input),  Some(Output)) if (!compileOptions.dontTryConnectionsSwapped) => issueConnect(source, sink)
+        case (Some(Input),  Some(Output)) if (!(compileOptions.dontTryConnectionsSwapped || context_mod.compileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink)
         case (Some(Input),  _)    => throw UnwritableSinkException
       }
     }
@@ -172,7 +172,7 @@ object MonoConnect {
         case (Some(Input),  Some(Output)) => issueConnect(sink, source)
         case (Some(Output), _)            => throw UnwritableSinkException
         case (_,            None) => {
-          if (!compileOptions.dontAssumeDirectionality) {
+          if (!(compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality)) {
             issueConnect(sink, source)
           } else {
             throw UnreadableSourceException
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index b77c9a31..36c88245 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 object Reg {
   private[core] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
     if (t ne null) {
-      if (Builder.compileOptions.declaredTypeMustBeUnbound) {
+      if (Builder.compileOptions.declaredTypeMustBeUnbound || Builder.forcedModule.compileOptions.declaredTypeMustBeUnbound) {
         Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?")
       }
       t.chiselCloneType
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 35c44330..8524ea2a 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -4,6 +4,7 @@
 // moving to the more standard package naming convention chisel3 (lowercase c).
 
 package object Chisel {     // scalastyle:ignore package.object.name
+  import chisel3.NotStrict.CompileOptions
   type Direction = chisel3.core.Direction
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
new file mode 100644
index 00000000..5bd3f959
--- /dev/null
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -0,0 +1,180 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import org.scalatest._
+import chisel3._
+import chisel3.core.Binding.BindingException
+import chisel3.testers.BasicTester
+
+class CompileOptionsSpec extends ChiselFlatSpec {
+
+  class SmallBundle extends Bundle {
+    val f1 = UInt(width = 4)
+    val f2 = UInt(width = 5)
+    override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type]
+  }
+  class BigBundle extends SmallBundle {
+    val f3 = UInt(width = 6)
+    override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
+  }
+
+  "A Module with missing bundle fields when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class ConnectFieldMismatchModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(new SmallBundle)
+          val out = Output(new BigBundle)
+        })
+        io.out := io.in
+      }
+      elaborate { new ConnectFieldMismatchModule() }
+    }
+  }
+
+  "A Module with missing bundle fields when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class ConnectFieldMismatchModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(new SmallBundle)
+        val out = Output(new BigBundle)
+      })
+      io.out := io.in
+    }
+    elaborate { new ConnectFieldMismatchModule() }
+  }
+
+  "A Module in which a Reg is created with a bound type when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [BindingException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class CreateRegFromBoundTypeModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(new SmallBundle)
+          val out = Output(new BigBundle)
+        })
+        val badReg = Reg(UInt(7, width=4))
+      }
+      elaborate { new CreateRegFromBoundTypeModule() }
+    }
+  }
+
+  "A Module in which a Reg is created with a bound type when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class CreateRegFromBoundTypeModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(new SmallBundle)
+        val out = Output(new BigBundle)
+      })
+      val badReg = Reg(UInt(7, width=4))
+    }
+    elaborate { new CreateRegFromBoundTypeModule() }
+  }
+
+
+  "A Module with wrapped IO when compiled with Strict.CompileOption " should "not throw an exception" in {
+    import chisel3.Strict.CompileOptions
+
+    class RequireIOWrapModule extends Module {
+      val io = IO(new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      })
+      io.out := io.in(1)
+    }
+    elaborate { new RequireIOWrapModule() }
+}
+
+  "A Module with unwrapped IO when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class RequireIOWrapModule extends Module {
+      val io = new Bundle {
+        val in = UInt(width = 32).asInput
+        val out = Bool().asOutput
+      }
+      io.out := io.in(1)
+    }
+      elaborate { new RequireIOWrapModule() }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class SimpleModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(width = 3))
+          val out = Output(UInt(width = 4))
+        })
+      }
+      class SwappedConnectionModule extends SimpleModule {
+        val child = Module(new SimpleModule)
+        io.in := child.io.out
+      }
+      elaborate { new SwappedConnectionModule() }
+    }
+  }
+
+  "A Module connecting output as source to input as sink when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class SimpleModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(width = 3))
+        val out = Output(UInt(width = 4))
+      })
+    }
+    class SwappedConnectionModule extends SimpleModule {
+      val child = Module(new SimpleModule)
+      io.in := child.io.out
+    }
+    elaborate { new SwappedConnectionModule() }
+  }
+
+  "A Module with directionless connections when compiled with Strict.CompileOption " should "throw an exception" in {
+    a [ChiselException] should be thrownBy {
+      import chisel3.Strict.CompileOptions
+
+      class SimpleModule extends Module {
+        val io = IO(new Bundle {
+          val in = Input(UInt(width = 3))
+          val out = Output(UInt(width = 4))
+        })
+        val noDir = Wire(UInt(width = 3))
+      }
+
+      class DirectionLessConnectionModule extends SimpleModule {
+        val a = UInt(0, width = 3)
+        val b = Wire(UInt(width = 3))
+        val child = Module(new SimpleModule)
+        b := child.noDir
+      }
+      elaborate { new DirectionLessConnectionModule() }
+    }
+  }
+
+  "A Module with directionless connections when compiled with NotStrict.CompileOption " should "not throw an exception" in {
+    import chisel3.NotStrict.CompileOptions
+
+    class SimpleModule extends Module {
+      val io = IO(new Bundle {
+        val in = Input(UInt(width = 3))
+        val out = Output(UInt(width = 4))
+      })
+      val noDir = Wire(UInt(width = 3))
+    }
+
+    class DirectionLessConnectionModule extends SimpleModule {
+      val a = UInt(0, width = 3)
+      val b = Wire(UInt(width = 3))
+      val child = Module(new SimpleModule)
+      b := child.noDir
+    }
+    elaborate { new DirectionLessConnectionModule() }
+  }
+}