diff options
| author | Andrew Waterman | 2015-10-30 15:03:40 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-10-30 15:03:40 -0700 |
| commit | 178f5c564e9ab0594656185e2e0a5bcc029d5743 (patch) | |
| tree | ac2495c592bf6ed5e084085db3e18787cb46da36 | |
| parent | b225e7d011bf6c3f0ec0a65751b3dc0e412dfe65 (diff) | |
| parent | b43551f807cd4a826862366aa6c184189a3b731e (diff) | |
Merge pull request #47 from ucb-bar/corebitsfix
Fix whitespace in Bits
| -rw-r--r-- | src/main/scala/Chisel/Bits.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala index 021532a1..ddef7603 100644 --- a/src/main/scala/Chisel/Bits.scala +++ b/src/main/scala/Chisel/Bits.scala @@ -42,7 +42,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: /** Returns the specified bit on this wire as a [[Bool]], statically * addressed. Generates no logic. - * + * * @note convenience method allowing direct use of Ints without implicits */ final def apply(x: Int): Bool = @@ -149,9 +149,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: * 3 and value 7 (0b111) would become a SInt with value -1 */ def asSInt(): SInt - + /** Reinterpret cast to an UInt. - * + * * @note value not guaranteed to be preserved: for example, a SInt of width * 3 and value -1 (0b111) would become an UInt with value 7 */ @@ -159,7 +159,7 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: /** Reinterpret cast to Bits. */ def asBits(): Bits = asUInt - + @deprecated("Use asSInt, which makes the reinterpret cast more explicit", "chisel3") final def toSInt(): SInt = asSInt @deprecated("Use asUInt, which makes the reinterpret cast more explicit", "chisel3") |