diff options
| author | mergify[bot] | 2022-09-15 20:46:10 +0000 |
|---|---|---|
| committer | GitHub | 2022-09-15 20:46:10 +0000 |
| commit | 03f62c8c9bc2f6cc65ab34b8902f5e9a61701595 (patch) | |
| tree | e47638a53fa9307acb45ea6703760e961a03d932 | |
| parent | a7e44dfacda7d8d85c35598a470a0e0aee013483 (diff) | |
Change description for SInt unary negation (#2729) (#2734)
Referenced to: chipsalliance/chisel3#2728
(cherry picked from commit a4dae9c340c71c063cf0fdec290a6e011b82746d)
Co-authored-by: Marco Origlia <30799310+moriglia@users.noreply.github.com>
| -rw-r--r-- | core/src/main/scala/chisel3/Bits.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala index 72094a65..70704e01 100644 --- a/core/src/main/scala/chisel3/Bits.scala +++ b/core/src/main/scala/chisel3/Bits.scala @@ -896,7 +896,7 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S private[chisel3] override def cloneTypeWidth(w: Width): this.type = new SInt(w).asInstanceOf[this.type] - /** Unary negation (expanding width) + /** Unary negation (constant width) * * @return a hardware $coll equal to zero minus this $coll * $constantWidth |