Fixes from lfcode.cariscv

PMP enforecement from Qemu breaks boot cycle. This fix is from
upstream repo here: https://github.com/lf-/xv6-riscv/

3 files changed, 34 insertions, 2 deletions

diff --git a/kernel/param.h b/kernel/param.h
index 7852ddb..bece2eb 100644
--- a/kernel/param.h
+++ b/kernel/param.h
@@ -1,5 +1,5 @@
 #define NPROC        64  // maximum number of processes
-#define NCPU          1  // maximum number of CPUs
+#define NCPU          2  // maximum number of CPUs
 #define NOFILE       16  // open files per process
 #define NFILE       100  // open files per system
 #define NINODE       50  // maximum number of active i-nodes
diff --git a/kernel/riscv.h b/kernel/riscv.h
index 0aec003..25614b1 100644
--- a/kernel/riscv.h
+++ b/kernel/riscv.h
@@ -38,6 +38,29 @@ w_mepc(uint64 x)
   asm volatile("csrw mepc, %0" : : "r" (x));
 }
 
+// physical memory protection CSRs
+#define PMP_R (1L << 0)
+#define PMP_W (1L << 1)
+#define PMP_X (1L << 2)
+// naturally aligned power of two
+#define PMP_MATCH_NAPOT (3L << 3)
+
+// we only implement accessing one PMP register
+
+// write to the first 8 PMP configuration registers
+static inline void
+w_pmpcfg0(uint64 x)
+{
+  asm volatile("csrw pmpcfg0, %0" : : "r" (x));
+}
+
+// write to the address for PMP region 0
+static inline void
+w_pmpaddr0(uint64 x)
+{
+  asm volatile("csrw pmpaddr0, %0" : : "r" (x));
+}
+
 // Supervisor Status Register, sstatus
 
 #define SSTATUS_SPP (1L << 8)  // Previous mode, 1=Supervisor, 0=User
diff --git a/kernel/start.c b/kernel/start.c
index 1876680..2d89d90 100644
--- a/kernel/start.c
+++ b/kernel/start.c
@@ -44,7 +44,16 @@ start()
   // keep each CPU's hartid in its tp register, for cpuid().
   int id = r_mhartid();
   w_tp(id);
-
+  
+  // allow access to all physical memory by S mode
+    // see figure 3.27 "PMP address register format, RV64" and table 3.10 "NAPOT
+  // range encoding in PMP address and configuration registers" in the RISC-V
+  // privileged specification
+  // we set the bits such that this matches any 56-bit physical address
+  w_pmpaddr0((~0ULL) >> 10);
+  // then we allow the access
+  w_pmpcfg0(PMP_R | PMP_W | PMP_X | PMP_MATCH_NAPOT);  
+  
   // switch to supervisor mode and jump to main().
   asm volatile("mret");
 }