summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/nanopb/pb.h (renamed from src/pb.h)0
-rw-r--r--lib/nanopb/pb_common.c (renamed from src/pb_common.c)0
-rw-r--r--lib/nanopb/pb_common.h (renamed from src/pb_common.h)0
-rw-r--r--lib/nanopb/pb_decode.c (renamed from src/pb_decode.c)0
-rw-r--r--lib/nanopb/pb_decode.h (renamed from src/pb_decode.h)0
-rw-r--r--lib/nanopb/pb_encode.c (renamed from src/pb_encode.c)0
-rw-r--r--lib/nanopb/pb_encode.h (renamed from src/pb_encode.h)0
-rw-r--r--makefile91
-rw-r--r--ports/stm32f4/STM32F401CCUx_FLASH.ld (renamed from STM32F401CCUx_FLASH.ld)0
-rw-r--r--ports/stm32f4/STM32F405RGTx_FLASH.ld209
-rw-r--r--ports/stm32f4/makefile42
-rw-r--r--ports/stm32f4/src/port.h12
-rw-r--r--ports/stm32f4/src/stm32f4xx_hal_conf.h (renamed from src/stm32f4xx_hal_conf.h)0
-rw-r--r--ports/stm32f4/src/stm32f4xx_hal_msp.c (renamed from src/stm32f4xx_hal_msp.c)0
-rw-r--r--ports/stm32f4/src/stm32f4xx_it.c (renamed from src/stm32f4xx_it.c)0
-rw-r--r--ports/stm32f4/src/stm32f4xx_it.h (renamed from src/stm32f4xx_it.h)0
-rw-r--r--ports/stm32f4/src/system_stm32f4xx.c (renamed from src/system_stm32f4xx.c)0
-rw-r--r--ports/stm32f4/startup_stm32f401xc.s (renamed from startup_stm32f401xc.s)0
-rw-r--r--ports/stm32f4/startup_stm32f405xx.s516
-rw-r--r--src/main.c797
-rw-r--r--src/main.h2
-rw-r--r--src/master.c (renamed from src/main-master.c)0
-rw-r--r--src/slave.c (renamed from src/main-slave.c)4
23 files changed, 799 insertions, 874 deletions
diff --git a/src/pb.h b/lib/nanopb/pb.h
index fc0f387..fc0f387 100644
--- a/src/pb.h
+++ b/lib/nanopb/pb.h
diff --git a/src/pb_common.c b/lib/nanopb/pb_common.c
index dfc5a05..dfc5a05 100644
--- a/src/pb_common.c
+++ b/lib/nanopb/pb_common.c
diff --git a/src/pb_common.h b/lib/nanopb/pb_common.h
index 47fa2c9..47fa2c9 100644
--- a/src/pb_common.h
+++ b/lib/nanopb/pb_common.h
diff --git a/src/pb_decode.c b/lib/nanopb/pb_decode.c
index f936412..f936412 100644
--- a/src/pb_decode.c
+++ b/lib/nanopb/pb_decode.c
diff --git a/src/pb_decode.h b/lib/nanopb/pb_decode.h
index b64d95a..b64d95a 100644
--- a/src/pb_decode.h
+++ b/lib/nanopb/pb_decode.h
diff --git a/src/pb_encode.c b/lib/nanopb/pb_encode.c
index 409fec3..409fec3 100644
--- a/src/pb_encode.c
+++ b/lib/nanopb/pb_encode.c
diff --git a/src/pb_encode.h b/lib/nanopb/pb_encode.h
index 88e246a..88e246a 100644
--- a/src/pb_encode.h
+++ b/lib/nanopb/pb_encode.h
diff --git a/makefile b/makefile
index 640d80d..b53a7a5 100644
--- a/makefile
+++ b/makefile
@@ -1,18 +1,4 @@
-##########################################################################################################################
-# File automatically-generated by tool: [projectgenerator] version: [3.5.2] date: [Mon Mar 23 16:58:19 EDT 2020]
-##########################################################################################################################
-
-# ------------------------------------------------
-# Generic Makefile (based on gcc)
-#
-# ChangeLog :
-# 2017-02-10 - Several enhancements + project update mode
-# 2015-07-22 - first version
-# ------------------------------------------------
-
-######################################
-# target
-######################################
+# Target also determines which file is being compiled
TARGET = master
@@ -34,40 +20,16 @@ BUILD_DIR = build
######################################
# source
######################################
-# C sources
+# C sources for all ports
C_SOURCES = \
-src/main-master.c \
-src/stm32f4xx_it.c \
-src/stm32f4xx_hal_msp.c \
-src/system_stm32f4xx.c \
-src/pb_decode.c \
-src/pb_encode.c \
-src/pb_common.c \
+lib/nanopb/pb_decode.c \
+lib/nanopb/pb_encode.c \
+lib/nanopb/pb_common.c \
src/handshake.pb.c \
src/data.pb.c \
-lib/f4/stm32f4xx_hal_i2c.c \
-lib/f4/stm32f4xx_hal_i2c_ex.c \
-lib/f4/stm32f4xx_hal_rcc.c \
-lib/f4/stm32f4xx_hal_rcc_ex.c \
-lib/f4/stm32f4xx_hal_flash.c \
-lib/f4/stm32f4xx_hal_flash_ex.c \
-lib/f4/stm32f4xx_hal_flash_ramfunc.c \
-lib/f4/stm32f4xx_hal_gpio.c \
-lib/f4/stm32f4xx_hal_dma_ex.c \
-lib/f4/stm32f4xx_hal_dma.c \
-lib/f4/stm32f4xx_hal_pwr.c \
-lib/f4/stm32f4xx_hal_pwr_ex.c \
-lib/f4/stm32f4xx_hal_cortex.c \
-lib/f4/stm32f4xx_hal.c \
-lib/f4/stm32f4xx_hal_exti.c \
-lib/f4/stm32f4xx_hal_tim.c \
-lib/f4/stm32f4xx_hal_tim_ex.c \
-lib/f4/stm32f4xx_hal_uart.c
-
-# ASM sources
-ASM_SOURCES = \
-startup_stm32f401xc.s
+# set the main C source based on whether we're compiling the master or slave
+C_SOURCES+=$(addprefix src/, $(TARGET).c)
#######################################
# binaries
@@ -88,46 +50,29 @@ SZ = $(PREFIX)size
endif
HEX = $(CP) -O ihex
BIN = $(CP) -O binary -S
-
+
#######################################
# CFLAGS
#######################################
-# cpu
-CPU = -mcpu=cortex-m4
-
-# fpu
-FPU = -mfpu=fpv4-sp-d16
-
-# float-abi
-FLOAT-ABI = -mfloat-abi=hard
-
-# mcu
-MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
-
# macros for gcc
# AS defines
AS_DEFS =
-# C defines
-C_DEFS = \
--DUSE_HAL_DRIVER \
--DSTM32F401xC
-
-
# AS includes
AS_INCLUDES =
-# C includes
+# General C includes for all ports. Since CMSIS is being included, that means this is restricted to ARM ports
C_INCLUDES = \
-Isrc \
--Ilib/f4 \
--Ilib/f4/Legacy \
-Ilib/cmsis \
--Ilib/cmsis/f4
-
-
+-Ilib/nanopb
+# Define the chip we're building for and include its makefile
+PORT = stm32f4
+PORT_DIR = ports/$(PORT)
+include $(PORT_DIR)/makefile
+ASM_SOURCES=$(PORT_DIR)/$(ASM_FILE)
# compile gcc flags
ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
@@ -138,21 +83,19 @@ ifeq ($(DEBUG), 1)
CFLAGS += -g -gdwarf-2
endif
-
# Generate dependency information
CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
-
#######################################
# LDFLAGS
#######################################
# link script
-LDSCRIPT = STM32F401CCUx_FLASH.ld
+# LDSCRIPT = STM32F401CCUx_FLASH.ld
# libraries
LIBS = -lc -lm -lnosys
LIBDIR =
-LDFLAGS = $(MCU) -specs=nosys.specs -specs=nano.specs -u _printf_float -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
+LDFLAGS = $(MCU) -specs=nosys.specs -specs=nano.specs -u _printf_float -T$(PORT_DIR)/$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
# default action: build all
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
diff --git a/STM32F401CCUx_FLASH.ld b/ports/stm32f4/STM32F401CCUx_FLASH.ld
index 4f0561c..4f0561c 100644
--- a/STM32F401CCUx_FLASH.ld
+++ b/ports/stm32f4/STM32F401CCUx_FLASH.ld
diff --git a/ports/stm32f4/STM32F405RGTx_FLASH.ld b/ports/stm32f4/STM32F405RGTx_FLASH.ld
new file mode 100644
index 0000000..cfa7433
--- /dev/null
+++ b/ports/stm32f4/STM32F405RGTx_FLASH.ld
@@ -0,0 +1,209 @@
+/*
+******************************************************************************
+**
+
+** File : LinkerScript.ld
+**
+** Author : Auto-generated by System Workbench for STM32
+**
+** Abstract : Linker script for STM32F405RGTx series
+** 1024Kbytes FLASH and 128Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed “as is,” without any warranty
+** of any kind.
+**
+*****************************************************************************
+** @attention
+**
+** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+** 1. Redistributions of source code must retain the above copyright notice,
+** this list of conditions and the following disclaimer.
+** 2. Redistributions in binary form must reproduce the above copyright notice,
+** this list of conditions and the following disclaimer in the documentation
+** and/or other materials provided with the distribution.
+** 3. Neither the name of STMicroelectronics nor the names of its contributors
+** may be used to endorse or promote products derived from this software
+** without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000; /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
+CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 64K
+FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ _siccmram = LOADADDR(.ccmram);
+
+ /* CCM-RAM section
+ *
+ * IMPORTANT NOTE!
+ * If initialized variables will be placed in this section,
+ * the startup code needs to be modified to copy the init-values.
+ */
+ .ccmram :
+ {
+ . = ALIGN(4);
+ _sccmram = .; /* create a global symbol at ccmram start */
+ *(.ccmram)
+ *(.ccmram*)
+
+ . = ALIGN(4);
+ _eccmram = .; /* create a global symbol at ccmram end */
+ } >CCMRAM AT> FLASH
+
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/ports/stm32f4/makefile b/ports/stm32f4/makefile
new file mode 100644
index 0000000..c3701b9
--- /dev/null
+++ b/ports/stm32f4/makefile
@@ -0,0 +1,42 @@
+# Makefile for the STM32F4 port
+
+# These variables are dependent on the target MCU
+LDSCRIPT=STM32F405RGTx_FLASH.ld
+ASM_FILE=startup_stm32f405xx.s
+C_DEFS += \
+-DSTM32F405xx
+
+FLOAT-ABI = -mfloat-abi=hard
+CPU = -mcpu=cortex-m4
+FPU = -mfpu=fpv4-sp-d16
+MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
+
+# Library files common to all F4 MCUs
+C_SOURCES += \
+lib/f4/stm32f4xx_hal_i2c.c \
+lib/f4/stm32f4xx_hal_i2c_ex.c \
+lib/f4/stm32f4xx_hal_rcc.c \
+lib/f4/stm32f4xx_hal_rcc_ex.c \
+lib/f4/stm32f4xx_hal_flash.c \
+lib/f4/stm32f4xx_hal_flash_ex.c \
+lib/f4/stm32f4xx_hal_flash_ramfunc.c \
+lib/f4/stm32f4xx_hal_gpio.c \
+lib/f4/stm32f4xx_hal_dma_ex.c \
+lib/f4/stm32f4xx_hal_dma.c \
+lib/f4/stm32f4xx_hal_pwr.c \
+lib/f4/stm32f4xx_hal_pwr_ex.c \
+lib/f4/stm32f4xx_hal_cortex.c \
+lib/f4/stm32f4xx_hal.c \
+lib/f4/stm32f4xx_hal_exti.c \
+lib/f4/stm32f4xx_hal_tim.c \
+lib/f4/stm32f4xx_hal_tim_ex.c \
+lib/f4/stm32f4xx_hal_uart.c \
+ports/stm32f4/src/stm32f4xx_it.c \
+ports/stm32f4/src/stm32f4xx_hal_msp.c \
+ports/stm32f4/src/system_stm32f4xx.c \
+
+C_INCLUDES += \
+-Ilib/f4 \
+-Ilib/f4/Legacy \
+-Ilib/cmsis/f4 \
+-Iports/stm32f4/src
diff --git a/ports/stm32f4/src/port.h b/ports/stm32f4/src/port.h
new file mode 100644
index 0000000..ffbbe9e
--- /dev/null
+++ b/ports/stm32f4/src/port.h
@@ -0,0 +1,12 @@
+/**
+ *
+ * @brief Port specific includes go in this file
+ *
+*/
+
+#ifndef __PORT_H
+#define __PORT_H
+
+#include "stm32f4xx_hal.h"
+
+#endif
diff --git a/src/stm32f4xx_hal_conf.h b/ports/stm32f4/src/stm32f4xx_hal_conf.h
index e7e342a..e7e342a 100644
--- a/src/stm32f4xx_hal_conf.h
+++ b/ports/stm32f4/src/stm32f4xx_hal_conf.h
diff --git a/src/stm32f4xx_hal_msp.c b/ports/stm32f4/src/stm32f4xx_hal_msp.c
index d19bcec..d19bcec 100644
--- a/src/stm32f4xx_hal_msp.c
+++ b/ports/stm32f4/src/stm32f4xx_hal_msp.c
diff --git a/src/stm32f4xx_it.c b/ports/stm32f4/src/stm32f4xx_it.c
index caabfb4..caabfb4 100644
--- a/src/stm32f4xx_it.c
+++ b/ports/stm32f4/src/stm32f4xx_it.c
diff --git a/src/stm32f4xx_it.h b/ports/stm32f4/src/stm32f4xx_it.h
index 0f787d0..0f787d0 100644
--- a/src/stm32f4xx_it.h
+++ b/ports/stm32f4/src/stm32f4xx_it.h
diff --git a/src/system_stm32f4xx.c b/ports/stm32f4/src/system_stm32f4xx.c
index 7745026..7745026 100644
--- a/src/system_stm32f4xx.c
+++ b/ports/stm32f4/src/system_stm32f4xx.c
diff --git a/startup_stm32f401xc.s b/ports/stm32f4/startup_stm32f401xc.s
index c4078d3..c4078d3 100644
--- a/startup_stm32f401xc.s
+++ b/ports/stm32f4/startup_stm32f401xc.s
diff --git a/ports/stm32f4/startup_stm32f405xx.s b/ports/stm32f4/startup_stm32f405xx.s
new file mode 100644
index 0000000..b2ad563
--- /dev/null
+++ b/ports/stm32f4/startup_stm32f405xx.s
@@ -0,0 +1,516 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32f405xx.s
+ * @author MCD Application Team
+ * @brief STM32F405xx Devices vector table for GCC based toolchains.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FSMC_IRQHandler /* FSMC */
+ .word SDIO_IRQHandler /* SDIO */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word CAN2_TX_IRQHandler /* CAN2 TX */
+ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .word CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word HASH_RNG_IRQHandler /* Hash and Rng */
+ .word FPU_IRQHandler /* FPU */
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FSMC_IRQHandler
+ .thumb_set FSMC_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX0_IRQHandler
+ .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+
+ .weak CAN2_RX1_IRQHandler
+ .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+
+ .weak CAN2_SCE_IRQHandler
+ .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak HASH_RNG_IRQHandler
+ .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
diff --git a/src/main.c b/src/main.c
deleted file mode 100644
index 3ab25ac..0000000
--- a/src/main.c
+++ /dev/null
@@ -1,797 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
-******************************************************************************
-* @file : main.c
-* @brief : Main program body
-******************************************************************************
-* @attention
-*
-*
-******************************************************************************
-*/
-
-/* Standard library includes */
-#include <stdio.h>
-
-/* Library includes */
-#include <pb_encode.h>
-#include <pb_decode.h>
-#include "handshake.pb.h"
-
-/* Project includes */
-#include "devices.h"
-#include "config.h"
-#include "main.h"
-
-/* Private Macros */
-#define device_MDR s2m_MDR_response
-#define GET_IDX_FROM_ADDR(i2c_addr) i2c_addr-1
-#define GET_BIT_FROM_IDX(a, b) a[b>>5]&(1<<(b%32))
-#define SET_BIT_FROM_IDX(a, b) a[b>>5]|=(1<<(b%32))
-#define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
-
-#define I2C_ADDRESS 0x05
-#define BUS_DEVICE_LIMIT 128
-
-/* Macro to toggle between master and slave firmware */
-#define MASTER
-
-/* Private globals */
-I2C_HandleTypeDef hi2c1;
-UART_HandleTypeDef huart1;
-
-device_info_t *device_info[BUS_DEVICE_LIMIT] = {NULL};
-subscription_info_t* subs_info[BUS_DEVICE_LIMIT];
-uint32_t allocated[4]={0};
-uint8_t dev_sts[BUS_DEVICE_LIMIT] = {OFFLINE};
-
-/* Function prototypes */
-void SystemClock_Config(void);
-static void MX_GPIO_Init(void);
-static void MX_I2C1_Init(void);
-static void MX_USART1_UART_Init(void);
-
-bool decode_subscriptions_callback(pb_istream_t *istream, const pb_field_t *field, void **args);
-hs_status_t handshake(uint32_t i2c_addr);
-bool todo_hs_or_not_todo_hs(uint8_t i2c_addr);
-state_t get_state_from_hs_status(uint16_t device_addr, hs_status_t hs_status);
-bool encode_subscription_callback(pb_ostream_t *ostream, const pb_field_t *field, void * const *arg);
-
-
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void)
-{
- /* MCU Configuration */
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
- HAL_Init();
-
- /* Configure the system clock */
- SystemClock_Config();
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- MX_I2C1_Init();
- MX_USART1_UART_Init();
-
-#ifdef TESTING_ENABLE
-#ifdef MASTER
- uint8_t reset_string[] = "\r\n\n==========MASTER RESET=========\r\n\n";
- HAL_UART_Transmit(&huart1, reset_string, sizeof(reset_string), 100);
-#else
- uint8_t reset_string[] = "\r\n\n==========SLAVE RESET=========\r\n\n";
- HAL_UART_Transmit(&huart1, reset_string, sizeof(reset_string), 100);
-#endif /* MASTER */
-#endif /* TESTING_ENABLE */
-
-#ifdef MASTER
- hs_status_t hs_status;
- for (int curr_addr=0; curr_addr < 10; curr_addr++) {
- if (todo_hs_or_not_todo_hs(curr_addr)) {
- hs_status = handshake(curr_addr);
- dev_sts[GET_IDX_FROM_ADDR(curr_addr)] = get_state_from_hs_status(curr_addr, hs_status);
- }
- }
-
-#else /* Slave code*/
- {
- uint8_t MDR_buf[128], debug_buf[128], term[]="\r\n";
- size_t MDR_enc_size;
- s2m_MDR_response res;
- res.MDR_version=1.1;
- res.module_id = 1;
- res.module_class=1;
- res.entity_id=32;
-
- res.subscriptions.funcs.encode=encode_subscription_callback;
- pb_ostream_t ostream = pb_ostream_from_buffer(MDR_buf, sizeof(MDR_buf));
- if(!pb_encode(&ostream, s2m_MDR_response_fields, &res)){
-#ifdef DEBUG_ENABLE
- uint8_t err_buf[] = "MDR encoding error\r\n";
- HAL_UART_Transmit(&huart1, err_buf, sizeof(err_buf), 100);
-#endif
- while(1) {
- HAL_GPIO_TogglePin(led_GPIO_Port, led_Pin);
- HAL_Delay(500);
- }
- }
- MDR_enc_size = ostream.bytes_written;
-#ifdef TESTING_ENABLE
- sprintf((char*)debug_buf, "MDR Encoded size: %d\r\n", MDR_enc_size);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-
- uint8_t bufbuf[] = "MDR Buffer: ";
- HAL_UART_Transmit(&huart1, bufbuf, sizeof(bufbuf), 100);
- for(int x=0; x<MDR_enc_size; x++) {
- sprintf((char*)debug_buf+x, "%x", MDR_buf[x]);
- }
- HAL_UART_Transmit(&huart1, debug_buf, MDR_enc_size, 100);
- HAL_UART_Transmit(&huart1, term, 2, 100);
- memset(debug_buf, 0, 128);
-#endif
-
- uint8_t MDR_ACK_buf[8] = {0};
- s2m_MDR_req_ACK ack;
- ack.MDR_res_length = MDR_enc_size;
- pb_ostream_t MDR_ack_ostream = pb_ostream_from_buffer(MDR_ACK_buf,
- sizeof(MDR_ACK_buf));
- if(!pb_encode(&MDR_ack_ostream, s2m_MDR_req_ACK_fields, &ack)) {
-#ifdef DEBUG_ENABLE
- uint8_t errbuf[] = "MDR ACK encoding error\r\n";
- HAL_UART_Transmit(&huart1, errbuf, sizeof(errbuf), 100);
-#endif /* DEBUG_ENABLE */
- while(1) {
- HAL_GPIO_TogglePin(led_GPIO_Port, led_Pin);
- HAL_Delay(500);
- }
- }
- size_t MDR_ack_size = MDR_ack_ostream.bytes_written;
-#ifdef TESTING_ENABLE
- sprintf((char*)debug_buf, "MDR ACK Encoded size: %d\r\n", MDR_ack_size);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-#endif /* TESTING_ENABLE */
-
- uint8_t MDR_req_buf[8];
- m2s_MDR_request MDR_req;
-
- if (HAL_I2C_Slave_Receive(&hi2c1, (uint8_t*)MDR_req_buf, 2, 10000) != HAL_OK) {
-#ifdef DEBUG_ENABLE
- uint8_t debug_buf[] = "Failed to get MDR req\r\n";
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
-#endif /* DEBUG_ENABLE */
- }
-
-#ifdef TESTING_ENABLE
- uint8_t bufbuf2[] = "MDR ACK buffer: ";
- HAL_UART_Transmit(&huart1, bufbuf2, sizeof(bufbuf2), 100);
- for(int x=0; x<2; x++) {
- sprintf((char*)debug_buf+x, "%x", MDR_ACK_buf[x]);
- }
- HAL_UART_Transmit(&huart1, debug_buf, MDR_enc_size, 100);
- HAL_UART_Transmit(&huart1, term, 2, 100);
- memset(debug_buf, 0, 128);
-#endif
-
- pb_istream_t MDR_req_istream = pb_istream_from_buffer(MDR_req_buf, 2);
- if(!pb_decode(&MDR_req_istream, m2s_MDR_request_fields, &MDR_req)) {
-#ifdef DEBUG_ENABLE
- uint8_t errbuf[] = "MDR request decoding error\r\n";
- HAL_UART_Transmit(&huart1, errbuf, sizeof(errbuf), 100);
-#endif /* DEBUG_ENABLE */
- }
-
-#ifdef TESTING_ENABLE
- sprintf((char*)debug_buf, "Got requested record type: %ld\r\n", MDR_req.record_type);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-#endif /* TESTING_ENABLE */
-
- HAL_GPIO_TogglePin(led_GPIO_Port, led_Pin);
-
- if (HAL_I2C_Slave_Transmit(&hi2c1, (uint8_t*)MDR_ACK_buf, s2m_MDR_req_ACK_size, 10000) != HAL_OK) {
-#ifdef DEBUG_ENABLE
- sprintf((char*)debug_buf, "Unable to send MDR ACK. I2C error: %ld\r\n", HAL_I2C_GetError(&hi2c1));
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-#endif /* DEBUG_ENABLE */
- }
-
- uint8_t MDR_CTS_buf[8];
- m2s_MDR_res_CTS MDR_CTS;
-
- if (HAL_I2C_Slave_Receive(&hi2c1, (uint8_t*)MDR_CTS_buf, 2, 10000) != HAL_OK) {
-#ifdef DEBUG_ENABLE
- sprintf((char*)debug_buf, "Failed to get MDR CTS\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-#endif /* DEBUG_ENABLE */
- }
-#ifdef TESTING_ENABLE
- uint8_t ctsbuf[] = "Got CTS buffer: ";
- for(int x=0; x<2; x++) {
- sprintf((char*)debug_buf+x, "%x", MDR_CTS_buf[x]);
- }
- HAL_UART_Transmit(&huart1, ctsbuf, sizeof(ctsbuf), 100);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- HAL_UART_Transmit(&huart1, term, 2, 100);
- memset(debug_buf, 0, 128);
-#endif /* TESTING_ENABLE */
-
- pb_istream_t MDR_CTS_istream = pb_istream_from_buffer(MDR_CTS_buf, 2);
- if (!pb_decode(&MDR_CTS_istream, m2s_MDR_res_CTS_fields, &MDR_CTS)) {
-#ifdef DEBUG_ENABLE
- sprintf((char*)debug_buf, "Failed to decode MDR CTS\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-#endif /* DEBUG_ENABLE */
- Error_Handler();
- }
-
- uint32_t MDR_timeout = MDR_CTS.timeout;
- if (HAL_I2C_Slave_Transmit(&hi2c1, (uint8_t*)MDR_buf, MDR_enc_size, 10000) !=
- HAL_OK) {
-#ifdef DEBUG_ENABLE
- sprintf((char*)debug_buf, "Unable to send MDR. I2C error: %ld\r\n",
- HAL_I2C_GetError(&hi2c1));
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
-#endif /* DEBUG_ENABLE */
- }
- else {
- sprintf((char*)debug_buf, "Successfully sent MDR\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- }
- }
-#endif /* MASTER */
-
- while (1)
- {
-
- }
-}
-
-hs_status_t handshake(uint32_t i2c_addr)
-{
-
- /* Handshake variables */
-
- uint8_t hs_sts = IDLE;
- uint8_t *MDR_req_buf, *MDR_ACK_buf, *MDR_CTS_buf, *MDR_buf;
- uint32_t AF_error_counter = 0;
- uint32_t dev_idx = GET_IDX_FROM_ADDR(i2c_addr);
- uint32_t MDR_len = 0;
-
- m2s_MDR_request MDR_req_message;
- s2m_MDR_req_ACK MDR_ACK;
- m2s_MDR_res_CTS MDR_CTS;
- s2m_MDR_response MDR_res_message;
-
-#if defined(TESTING_ENABLE) || defined(DEBUG_ENABLE)
- uint8_t debug_buf[128];
-#endif
-#ifdef TESTING_ENABLE
- uint8_t term[] = "\r\n";
- size_t MDR_req_size, MDR_CTS_size;
-#endif
-
- while (hs_sts != HS_FAILED && hs_sts != HS_REGISTERED) {
- switch (hs_sts) {
- case (IDLE):
- {
- MDR_req_buf = malloc(8);
- pb_ostream_t MDR_req_stream = pb_ostream_from_buffer(MDR_req_buf, 2);
- MDR_req_message.record_type = 7; /* Placeholder for default record type */
- if(!pb_encode(&MDR_req_stream, m2s_MDR_request_fields, &MDR_req_message)) {
- hs_sts = HS_FAILED;
-#ifdef DEBUG_ENABLE
- goto __MDR_REQ_ENC_FAIL;
- __MDR_REQ_ENC_FAIL_END:
- __asm__("nop");
-#endif
- }
- else {
-#ifdef TESTING_ENABLE
- MDR_req_size = MDR_req_stream.bytes_written;
- goto __HS_IDLE_TESTING;
- __HS_IDLE_TESTING_END:
- __asm__("nop");
-#endif
- if (HAL_I2C_Master_Transmit(&hi2c1, (uint16_t)i2c_addr, (uint8_t*)MDR_req_buf,
- MDR_req_buf_len, 10000) != HAL_OK) {
- hs_sts = HS_FAILED;
-#ifdef DEBUG_ENABLE
- goto __HS_MDR_REQ_I2C_ERROR;
- __HS_MDR_REQ_I2C_ERROR_END:
- __asm__("nop");
-#endif
- }
- else {
- hs_sts = HS_MDR_ACK;
- }
- free(MDR_req_buf);
- break;
- }
- }
- case (HS_MDR_ACK):
- {
- MDR_ACK_buf = malloc(8);
- AF_error_counter = 0;
- while (HAL_I2C_Master_Receive(&hi2c1, (uint16_t)i2c_addr, (uint8_t*)MDR_ACK_buf,
- s2m_MDR_req_ACK_size, 100) != HAL_OK) {
- if (HAL_I2C_GetError(&hi2c1) != HAL_I2C_ERROR_AF) {
- hs_sts = HS_FAILED;
- }
- if (++AF_error_counter > 1500) {
- hs_sts = HS_FAILED;
- }
- if (hs_sts == HS_FAILED) {
-#ifdef DEBUG_ENABLE
- goto __HS_MDR_ACK_I2C_ERROR;
- __HS_MDR_ACK_I2C_ERROR_END:
- __asm__("nop");
-#endif
- break;
- }
- }
- if (hs_sts != HS_FAILED) {
- pb_istream_t MDR_ACK_istream = pb_istream_from_buffer(MDR_ACK_buf, 2);
- if (!pb_decode(&MDR_ACK_istream, s2m_MDR_req_ACK_fields, &MDR_ACK)) {
- hs_sts = HS_FAILED;
-#ifdef DEBUG_ENABLE
- goto __MDR_ACK_DEC_ERROR;
- __MDR_ACK_DEC_ERROR_END:
- __asm__("nop");
-#endif
- }
- else {
- MDR_len = MDR_ACK.MDR_res_length;
- hs_sts = HS_MDR_CTS;
-#ifdef TESTING_ENABLE
- goto __HS_MDR_ACK_TESTING;
- __HS_MDR_ACK_TESTING_END:
- __asm__("nop");
-#endif
- }
- free(MDR_ACK_buf);
- }
- break;
- }
- case (HS_MDR_CTS):
- {
- MDR_CTS_buf = (uint8_t*)malloc(8);
- pb_ostream_t MDR_CTS_ostream = pb_ostream_from_buffer(MDR_CTS_buf, sizeof(MDR_CTS_buf));
- MDR_CTS.timeout = 100;
- if (!pb_encode(&MDR_CTS_ostream, m2s_MDR_res_CTS_fields, &MDR_CTS)) {
- hs_sts = HS_FAILED;
-#ifdef DEBUG_ENABLE
- goto __MDR_CTS_ENC_ERROR;
- __MDR_CTS_ENC_ERROR_END:
- __asm__("nop");
-#endif
- }
- else {
-#ifdef TESTING_ENABLE
- MDR_CTS_size = MDR_CTS_ostream.bytes_written;
- goto __HS_MDR_CTS_TESTING;
- __HS_MDR_CTS_TESTING_END:
- __asm__("nop");
-#endif
- if (HAL_I2C_Master_Transmit(&hi2c1, (uint16_t)i2c_addr,
- (uint8_t*)MDR_CTS_buf, 2, 10000) != HAL_OK) {
- hs_sts = HS_FAILED;
-#ifdef DEBUG_ENABLE
- goto __HS_CTS_I2C_ERROR;
- __HS_CTS_I2C_ERROR_END:
- __asm__("nop");
-#endif
- }
- else {
- hs_sts = HS_MDR_MDR;
- free(MDR_CTS_buf);
- }
- }
- break;
- }
- case (HS_MDR_MDR):
- {
- MDR_buf = (uint8_t*)malloc(MDR_len);
- AF_error_counter = 0;
- while (HAL_I2C_Master_Receive(&hi2c1, (uint16_t)i2c_addr,
- (uint8_t*)MDR_buf, MDR_len, 1000) != HAL_OK) {
- if (HAL_I2C_GetError(&hi2c1) != HAL_I2C_ERROR_AF) {
- hs_sts = HS_FAILED;
-#ifdef DEBUG_ENABLE
- goto __HS_MDR_I2C_ERROR;
- __HS_MDR_I2C_ERROR_END:
- __asm__("nop");
-#endif
- break;
- }
- else if (++AF_error_counter > 1500) {
- hs_sts = HS_FAILED;
- break;
- }
- }
- if (hs_sts != HS_FAILED) {
-#ifdef TESTING_ENABLE
- goto __HS_MDR_MDR_TESTING;
- __HS_MDR_MDR_TESTING_END:
- __asm__("nop");
-#endif
- MDR_res_message.subscriptions.funcs.decode = decode_subscriptions_callback;
- MDR_res_message.subscriptions.arg = (void*)dev_idx;
- pb_istream_t MDR_res_stream = pb_istream_from_buffer(MDR_buf, MDR_len);
- if (!pb_decode(&MDR_res_stream, s2m_MDR_response_fields, &MDR_res_message)) {
-#ifdef DEBUG_ENABLE
- goto __HS_MDR_DEC_ERROR;
- __HS_MDR_DEC_ERROR_END:
- __asm__("nop");
-#endif
- }
- else {
-#ifdef TESTING_ENABLE
- goto __MDR_DEC_TESTING;
- __MDR_DEC_TESTING_END:
- __asm__("nop");
-#endif
- hs_sts = HS_REGISTERED;
- }
- }
- break;
- }
- }
-
- }
-
-#ifdef TESTING_ENABLE
- {
- goto __TESTING_BLOCK_END;
- __HS_IDLE_TESTING:
- sprintf((char*)debug_buf, "MDR req length: %d\r\n", MDR_req_size);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- uint8_t bufbuf[] = "MDR req buffer: ";
- HAL_UART_Transmit(&huart1, bufbuf, sizeof(bufbuf), 100);
- for(int x=0; x<MDR_req_size; x++) {
- sprintf((char*)debug_buf+x, "%x", MDR_req_buf[x]);
- }
- HAL_UART_Transmit(&huart1, debug_buf, MDR_req_size, 100);
- HAL_UART_Transmit(&huart1, term, 2, 100);
- memset(debug_buf, 0, 128);
- goto __HS_IDLE_TESTING_END;
- __HS_MDR_ACK_TESTING:
- sprintf((char*)debug_buf, "Got MDR message length: %ld\r\n", MDR_ACK.MDR_res_length);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_ACK_TESTING_END;
- __HS_MDR_CTS_TESTING:
- sprintf((char*)debug_buf, "CTS size: %d\r\n", MDR_CTS_size);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- uint8_t ctsbuf[] = "\tCTS buffer: ";
- for(int x=0; x<2; x++) {
- sprintf((char*)debug_buf+x, "%x", MDR_CTS_buf[x]);
- }
- HAL_UART_Transmit(&huart1, ctsbuf, sizeof(ctsbuf), 100);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- HAL_UART_Transmit(&huart1, term, 2, 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_CTS_TESTING_END;
- __HS_MDR_MDR_TESTING:
- for (int x=0; x<MDR_len; x++) {
- sprintf((char*)debug_buf+x, "%x", MDR_buf[x]);
- }
- uint8_t mdrbuf[] = "Got MDR: ";
- HAL_UART_Transmit(&huart1, mdrbuf, sizeof(mdrbuf), 100);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- HAL_UART_Transmit(&huart1, term, 2, 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_MDR_TESTING_END;
- __MDR_DEC_TESTING:
- sprintf((char*)debug_buf, "MDR Decode success\r\n\tFirst subscibed module: %d\r\n",
- subs_info[dev_idx]->module_ids[1]);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __MDR_DEC_TESTING_END;
- }
-__TESTING_BLOCK_END:
- __asm__("nop");
-#endif
-
-#ifdef DEBUG_ENABLE
- {
- goto __DEBUG_BLOCK_END;
- __MDR_REQ_ENC_FAIL:
- sprintf((char*)debug_buf, "MDR reqest encoding error\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __MDR_REQ_ENC_FAIL_END;
- __HS_MDR_REQ_I2C_ERROR:
- sprintf((char*)debug_buf, "Unable to send MDR request. I2C error: %ld\r\n", HAL_I2C_GetError(&hi2c1));
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_REQ_I2C_ERROR_END;
- __HS_MDR_ACK_I2C_ERROR:
- sprintf((char*)debug_buf, "Unable to get MDR ACK. I2C error: %ld\r\n", HAL_I2C_GetError(&hi2c1));
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_ACK_I2C_ERROR_END;
- __MDR_ACK_DEC_ERROR:
- sprintf((char*)debug_buf, "MDR ACK decoding error\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __MDR_ACK_DEC_ERROR_END;
- __MDR_CTS_ENC_ERROR:
- sprintf((char*)debug_buf, "MDR encoding error\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __MDR_CTS_ENC_ERROR_END;
- __HS_CTS_I2C_ERROR:
- sprintf((char*)debug_buf, "Unable to send MDR CTS. I2C error: %ld\r\n", HAL_I2C_GetError(&hi2c1));
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __HS_CTS_I2C_ERROR_END;
- __HS_MDR_I2C_ERROR:
- sprintf((char*)debug_buf, "Unable to get MDR. I2C error: %ld\n\tError counter: %ld\r\n", HAL_I2C_GetError(&hi2c1), AF_error_counter);
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_I2C_ERROR_END;
- }
-__HS_MDR_DEC_ERROR:
- sprintf((char*)debug_buf, "MDR decode error\r\n");
- HAL_UART_Transmit(&huart1, debug_buf, sizeof(debug_buf), 100);
- memset(debug_buf, 0, 128);
- goto __HS_MDR_DEC_ERROR_END;
-__DEBUG_BLOCK_END:
- __asm__("nop");
-#endif
-
- return hs_sts;
-}
-
-bool decode_subscriptions_callback(pb_istream_t *istream, const pb_field_t *field, void **args)
-{
- _subscriptions subs;
- int *subs_idx = (int*)args;
-
- /* Check is storage is allocated; if not, allocate it */
- if ((GET_BIT_FROM_IDX(allocated, *subs_idx)) == 0) {
- subs_info[*subs_idx] = (subscription_info_t*)malloc(sizeof(subscription_info_t));
- SET_BIT_FROM_IDX(allocated, *subs_idx);
- subs_info[*subs_idx]->mod_idx = subs_info[*subs_idx]->entity_idx =
- subs_info[*subs_idx]->class_idx = subs_info[*subs_idx]->i2c_idx = 0;
- }
-
- if(!pb_decode(istream, _subscriptions_fields, &subs))
- return false;
-
- /* Parse all fields if they're included */
- if (subs.has_module_id)
- subs_info[*subs_idx]->module_ids[subs_info[*subs_idx]->mod_idx++] =
- subs.module_id;
- if (subs.has_entity_id)
- subs_info[*subs_idx]->entity_ids[subs_info[*subs_idx]->entity_idx++] =
- subs.entity_id;
- if (subs.has_module_class)
- subs_info[*subs_idx]->module_class[subs_info[*subs_idx]->class_idx++] =
- subs.module_class;
- if (subs.has_i2c_address)
- subs_info[*subs_idx]->i2c_address[subs_info[*subs_idx]->i2c_idx++] =
- subs.i2c_address;
- return true;
-}
-
-bool todo_hs_or_not_todo_hs(uint8_t i2c_addr)
-{
- uint8_t device_idx = GET_IDX_FROM_ADDR(i2c_addr);
- state_t device_curr_state = dev_sts[device_idx];
- bool do_hs = false;
- switch(device_curr_state) {
- case NO_HS:
- case CONNECTED:
- case FAILED:
- case OFFLINE:
- do_hs = true;
- break;
- case REGISTERED:
- case NO_DATA:
- do_hs = false;
- break;
- }
- return do_hs;
-}
-
-state_t get_state_from_hs_status(uint16_t device_addr, hs_status_t hs_status)
-{
- state_t device_state = OFFLINE;
- switch(hs_status) {
- case IDLE:
- case HS_FAILED:
- device_state = OFFLINE;
- break;
- case HS_MDR_ACK:
- case HS_MDR_CTS:
- case HS_MDR_MDR:
- device_state = FAILED;
- break;
- case HS_REGISTERED:
- device_state = REGISTERED;
- break;
- }
- return device_state;
-}
-
-bool encode_subscription_callback(pb_ostream_t *ostream, const pb_field_t *field, void * const *arg)
-{
- if(ostream!=NULL && field->tag == s2m_MDR_response_subscriptions_tag) {
- for (int x=0; x<2; x++) {
- _subscriptions subs;
- subs.module_id = x+10*x;
- subs.i2c_address = x+1;
- subs.has_entity_id=false;
- subs.has_module_class=false;
- subs.has_module_id=true;
- subs.has_i2c_address=true;
- if(!pb_encode_tag_for_field(ostream, field)){
- printf("ERR1\n");
- return false;
- }
- if(!pb_encode_submessage(ostream, _subscriptions_fields, &subs)){
- printf("ERR2\n");
- return false;
- }
- }
- }
- else{
- return false;
- }
- return true;
-}
-
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void)
-{
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-
- /** Configure the main internal regulator output voltage
- */
- __HAL_RCC_PWR_CLK_ENABLE();
- __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- Error_Handler();
- }
- /** Initializes the CPU, AHB and APB busses clocks
- */
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- {
- Error_Handler();
- }
-}
-
-/**
- * @brief I2C1 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_I2C1_Init(void)
-{
- hi2c1.Instance = I2C1;
- hi2c1.Init.ClockSpeed = 100000;
- hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
- hi2c1.Init.OwnAddress1 = I2C_ADDRESS;
- hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
- hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
- hi2c1.Init.OwnAddress2 = 0xFF;
- hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
- hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
- if (HAL_I2C_Init(&hi2c1) != HAL_OK)
- {
- Error_Handler();
- }
-
-}
-
-/**
- * @brief USART1 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_USART1_UART_Init(void)
-{
- huart1.Instance = USART1;
- huart1.Init.BaudRate = 9600;
- huart1.Init.WordLength = UART_WORDLENGTH_8B;
- huart1.Init.StopBits = UART_STOPBITS_1;
- huart1.Init.Parity = UART_PARITY_NONE;
- huart1.Init.Mode = UART_MODE_TX_RX;
- huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- huart1.Init.OverSampling = UART_OVERSAMPLING_16;
- if (HAL_UART_Init(&huart1) != HAL_OK)
- {
- Error_Handler();
- }
-
-}
-
-/**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void)
-{
- GPIO_InitTypeDef GPIO_InitStruct = {0};
-
- /* GPIO Ports Clock Enable */
- __HAL_RCC_GPIOC_CLK_ENABLE();
- __HAL_RCC_GPIOH_CLK_ENABLE();
- __HAL_RCC_GPIOA_CLK_ENABLE();
- __HAL_RCC_GPIOB_CLK_ENABLE();
-
- /*Configure GPIO pin Output Level */
- HAL_GPIO_WritePin(led_GPIO_Port, led_Pin, GPIO_PIN_RESET);
-
- /*Configure GPIO pin : led_Pin */
- GPIO_InitStruct.Pin = led_Pin;
- GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- HAL_GPIO_Init(led_GPIO_Port, &GPIO_InitStruct);
-
-}
-
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void)
-{
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
- while (1) {
- HAL_GPIO_TogglePin(led_GPIO_Port, led_Pin);
- HAL_Delay(1000);
- }
- /* USER CODE END Error_Handler_Debug */
-}
-
-#ifdef USE_FULL_ASSERT
-/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
-void assert_failed(uint8_t *file, uint32_t line)
-{
- /* USER CODE BEGIN 6 */
- /* User can add his own implementation to report the file name and line number,
- tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
- /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
diff --git a/src/main.h b/src/main.h
index 5d4be41..6579484 100644
--- a/src/main.h
+++ b/src/main.h
@@ -28,7 +28,7 @@ extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
+#include "port.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
diff --git a/src/main-master.c b/src/master.c
index c627a45..c627a45 100644
--- a/src/main-master.c
+++ b/src/master.c
diff --git a/src/main-slave.c b/src/slave.c
index e2364e3..4722c51 100644
--- a/src/main-slave.c
+++ b/src/slave.c
@@ -32,7 +32,7 @@
#define SET_BIT_FROM_IDX(a, b) a[b>>5]|=(1<<(b%32))
#define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
-#define I2C_ADDRESS 0x05<<1
+#define I2C_ADDRESS 0x07<<1
#define BUS_DEVICE_LIMIT 128
/* Macro to toggle between master and slave firmware */
@@ -190,7 +190,7 @@ bool handshake(void)
size_t MDR_enc_size;
s2m_MDR_response res;
res.MDR_version = 0.1;
- res.module_id = 1;
+ res.module_id = 4;
res.module_class = 2;
res.entity_id=1;
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 08:37:20 +0000