path: root/test/refchip/Top.fir

; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
;CHECK: Done!

circuit Top : 
  module HTIF : 
    output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}
    input cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1]
    output mem__ : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}
    
    wire cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1]
    cpu[0] := T_165479
    wire T_165480 : UInt<3>[3]
    T_165480[0] := UInt<3>(0)
    T_165480[1] := UInt<3>(1)
    T_165480[2] := UInt<3>(2)
    wire T_165481 : UInt<2>[2]
    T_165481[0] := UInt<2>(0)
    T_165481[1] := UInt<2>(1)
    wire T_165482 : UInt<2>[3]
    T_165482[0] := UInt<2>(1)
    T_165482[1] := UInt<2>(2)
    T_165482[2] := UInt<2>(3)
    wire T_165483 : UInt<2>[2]
    T_165483[0] := UInt<2>(2)
    T_165483[1] := UInt<2>(3)
    wire T_165484 : UInt<2>[1]
    T_165484[0] := UInt<2>(3)
    wire T_165485 : UInt<3>[3]
    T_165485[0] := UInt<3>(0)
    T_165485[1] := UInt<3>(1)
    T_165485[2] := UInt<3>(2)
    wire T_165486 : UInt<2>[2]
    T_165486[0] := UInt<2>(0)
    T_165486[1] := UInt<2>(1)
    wire T_165487 : UInt<2>[3]
    T_165487[0] := UInt<2>(1)
    T_165487[1] := UInt<2>(2)
    T_165487[2] := UInt<2>(3)
    wire T_165488 : UInt<2>[2]
    T_165488[0] := UInt<2>(2)
    T_165488[1] := UInt<2>(3)
    wire T_165489 : UInt<2>[1]
    T_165489[0] := UInt<2>(3)
    wire T_165490 : UInt<3>[3]
    T_165490[0] := UInt<3>(0)
    T_165490[1] := UInt<3>(1)
    T_165490[2] := UInt<3>(2)
    wire T_165491 : UInt<2>[2]
    T_165491[0] := UInt<2>(0)
    T_165491[1] := UInt<2>(1)
    wire T_165492 : UInt<2>[3]
    T_165492[0] := UInt<2>(1)
    T_165492[1] := UInt<2>(2)
    T_165492[2] := UInt<2>(3)
    wire T_165493 : UInt<2>[2]
    T_165493[0] := UInt<2>(2)
    T_165493[1] := UInt<2>(3)
    wire T_165494 : UInt<2>[1]
    T_165494[0] := UInt<2>(3)
    wire T_165495 : UInt<3>[3]
    T_165495[0] := UInt<3>(0)
    T_165495[1] := UInt<3>(1)
    T_165495[2] := UInt<3>(2)
    wire T_165496 : UInt<2>[2]
    T_165496[0] := UInt<2>(0)
    T_165496[1] := UInt<2>(1)
    wire T_165497 : UInt<2>[3]
    T_165497[0] := UInt<2>(1)
    T_165497[1] := UInt<2>(2)
    T_165497[2] := UInt<2>(3)
    wire T_165498 : UInt<2>[2]
    T_165498[0] := UInt<2>(2)
    T_165498[1] := UInt<2>(3)
    wire T_165499 : UInt<2>[1]
    T_165499[0] := UInt<2>(3)
    wire T_165500 : UInt<3>[3]
    T_165500[0] := UInt<3>(0)
    T_165500[1] := UInt<3>(1)
    T_165500[2] := UInt<3>(2)
    wire T_165501 : UInt<2>[2]
    T_165501[0] := UInt<2>(0)
    T_165501[1] := UInt<2>(1)
    wire T_165502 : UInt<2>[3]
    T_165502[0] := UInt<2>(1)
    T_165502[1] := UInt<2>(2)
    T_165502[2] := UInt<2>(3)
    wire T_165503 : UInt<2>[2]
    T_165503[0] := UInt<2>(2)
    T_165503[1] := UInt<2>(3)
    wire T_165504 : UInt<2>[1]
    T_165504[0] := UInt<2>(3)
    wire rdata : UInt<64>[64]
    scr.rdata[0] := T_165505
    scr.rdata[1] := T_165506
    scr.rdata[2] := T_165507
    scr.rdata[3] := T_165508
    scr.rdata[4] := T_165509
    scr.rdata[5] := T_165510
    scr.rdata[6] := T_165511
    scr.rdata[7] := T_165512
    scr.rdata[8] := T_165513
    scr.rdata[9] := T_165514
    scr.rdata[10] := T_165515
    scr.rdata[11] := T_165516
    scr.rdata[12] := T_165517
    scr.rdata[13] := T_165518
    scr.rdata[14] := T_165519
    scr.rdata[15] := T_165520
    scr.rdata[16] := T_165521
    scr.rdata[17] := T_165522
    scr.rdata[18] := T_165523
    scr.rdata[19] := T_165524
    scr.rdata[20] := T_165525
    scr.rdata[21] := T_165526
    scr.rdata[22] := T_165527
    scr.rdata[23] := T_165528
    scr.rdata[24] := T_165529
    scr.rdata[25] := T_165530
    scr.rdata[26] := T_165531
    scr.rdata[27] := T_165532
    scr.rdata[28] := T_165533
    scr.rdata[29] := T_165534
    scr.rdata[30] := T_165535
    scr.rdata[31] := T_165536
    scr.rdata[32] := T_165537
    scr.rdata[33] := T_165538
    scr.rdata[34] := T_165539
    scr.rdata[35] := T_165540
    scr.rdata[36] := T_165541
    scr.rdata[37] := T_165542
    scr.rdata[38] := T_165543
    scr.rdata[39] := T_165544
    scr.rdata[40] := T_165545
    scr.rdata[41] := T_165546
    scr.rdata[42] := T_165547
    scr.rdata[43] := T_165548
    scr.rdata[44] := T_165549
    scr.rdata[45] := T_165550
    scr.rdata[46] := T_165551
    scr.rdata[47] := T_165552
    scr.rdata[48] := T_165553
    scr.rdata[49] := T_165554
    scr.rdata[50] := T_165555
    scr.rdata[51] := T_165556
    scr.rdata[52] := T_165557
    scr.rdata[53] := T_165558
    scr.rdata[54] := T_165559
    scr.rdata[55] := T_165560
    scr.rdata[56] := T_165561
    scr.rdata[57] := T_165562
    scr.rdata[58] := T_165563
    scr.rdata[59] := T_165564
    scr.rdata[60] := T_165565
    scr.rdata[61] := T_165566
    scr.rdata[62] := T_165567
    scr.rdata[63] := T_165568
    host.debug_stats_pcr := cpu[0].debug_stats_pcr
    reg rx_count : UInt<15>
    onreset rx_count := UInt<15>(0)
    reg rx_shifter : UInt<64>
    node T_165569 = bits(rx_shifter, 63, 16)
    node rx_shifter_in = cat(host.in.bits, T_165569)
    node next_cmd = bits(rx_shifter_in, 3, 0)
    reg cmd : UInt
    reg size : UInt
    reg pos : UInt
    reg seqno : UInt
    reg addr : UInt
    
    node T_165570 = and(host.in.valid, host.in.ready)
    when T_165570 : 
      rx_shifter := rx_shifter_in
      node T_165571 = addw(rx_count, UInt<1>(1))
      rx_count := T_165571
      
      node T_165572 = eq(rx_count, UInt<2>(3))
      when T_165572 : 
        cmd := next_cmd
        node T_165573 = bits(rx_shifter_in, 15, 4)
        size := T_165573
        node T_165574 = bits(rx_shifter_in, 15, 7)
        pos := T_165574
        node T_165575 = bits(rx_shifter_in, 23, 16)
        seqno := T_165575
        node T_165576 = bits(rx_shifter_in, 63, 24)
        addr := T_165576
    node rx_word_count = dshr(rx_count, UInt<2>(2))
    node T_165577 = bits(rx_count, 1, 0)
    node T_165578 = eq(T_165577, UInt<1>(-1))
    node rx_word_done = and(host.in.valid, T_165578)
    cmem packet_ram : UInt<64>[8]
    
    node T_165579 = and(rx_word_done, host.in.ready)
    when T_165579 : 
      node T_165580 = bits(rx_word_count, 2, 0)
      node T_165581 = subw(T_165580, UInt<1>(1))
      accessor T_165582 = packet_ram[T_165581]
      T_165582 := rx_shifter_in
    node pcr_addr = bits(addr, 11, 0)
    node pcr_coreid = bits(addr, 21, 20)
    accessor pcr_wdata = packet_ram[UInt<1>(0)]
    node T_165583 = bits(size, 2, 0)
    node T_165584 = eq(T_165583, UInt<1>(0))
    node T_165585 = eq(T_165584, UInt<1>(0))
    node T_165586 = bits(addr, 2, 0)
    node T_165587 = eq(T_165586, UInt<1>(0))
    node T_165588 = eq(T_165587, UInt<1>(0))
    node bad_mem_packet = or(T_165585, T_165588)
    node T_165589 = eq(cmd, UInt<3>(0))
    node T_165590 = eq(cmd, UInt<3>(1))
    node T_165591 = or(T_165589, T_165590)
    node T_165592 = eq(cmd, UInt<3>(2))
    node T_165593 = eq(cmd, UInt<3>(3))
    node T_165594 = or(T_165592, T_165593)
    node T_165595 = neq(size, UInt<1>(1))
    wire T_165596 : UInt<1>
    T_165596 := UInt<1>(1)
    when T_165594 : T_165596 := T_165595
    wire nack : UInt<1>
    nack := T_165596
    when T_165591 : nack := bad_mem_packet
    reg tx_count : UInt<15>
    onreset tx_count := UInt<15>(0)
    node tx_subword_count = bits(tx_count, 1, 0)
    node tx_word_count = bits(tx_count, 14, 2)
    node T_165597 = bits(tx_word_count, 2, 0)
    node packet_ram_raddr = subw(T_165597, UInt<1>(1))
    
    node T_165598 = and(host.out.valid, host.out.ready)
    when T_165598 : 
      node T_165599 = addw(tx_count, UInt<1>(1))
      tx_count := T_165599
    node T_165600 = eq(rx_word_count, UInt<1>(0))
    node T_165601 = neq(next_cmd, UInt<3>(1))
    node T_165602 = neq(next_cmd, UInt<3>(3))
    node T_165603 = and(T_165601, T_165602)
    node T_165604 = eq(rx_word_count, size)
    node T_165605 = bits(rx_word_count, 2, 0)
    node T_165606 = eq(T_165605, UInt<1>(0))
    node T_165607 = or(T_165604, T_165606)
    wire T_165608 : UInt<1>
    T_165608 := T_165607
    when T_165600 : T_165608 := T_165603
    node rx_done = and(rx_word_done, T_165608)
    node T_165609 = eq(nack, UInt<1>(0))
    node T_165610 = eq(cmd, UInt<3>(0))
    node T_165611 = eq(cmd, UInt<3>(2))
    node T_165612 = or(T_165610, T_165611)
    node T_165613 = eq(cmd, UInt<3>(3))
    node T_165614 = or(T_165612, T_165613)
    node T_165615 = and(T_165609, T_165614)
    wire tx_size : UInt<1>
    tx_size := UInt<1>(0)
    when T_165615 : tx_size := size
    node T_165616 = eq(tx_subword_count, UInt<1>(-1))
    node T_165617 = and(host.out.ready, T_165616)
    node T_165618 = eq(tx_word_count, tx_size)
    node T_165619 = gt(tx_word_count, UInt<1>(0))
    node T_165620 = eq(packet_ram_raddr, UInt<1>(-1))
    node T_165621 = and(T_165619, T_165620)
    node T_165622 = or(T_165618, T_165621)
    node tx_done = and(T_165617, T_165622)
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    node T_165623 = eq(state, UInt<3>(4))
    node T_165624 = and(T_165623, mem__.acquire.ready)
    node T_165625 = eq(state, UInt<3>(5))
    node T_165626 = and(T_165625, mem__.grant.valid)
    node T_165627 = or(T_165624, T_165626)
    reg cnt : UInt<2>
    onreset cnt := UInt<2>(0)
    when T_165627 : 
      node T_165628 = eq(cnt, UInt<2>(3))
      node T_165629 = and(UInt<1>(0), T_165628)
      node T_165630 = addw(cnt, UInt<1>(1))
      wire T_165631 : UInt<2>
      T_165631 := T_165630
      when T_165629 : T_165631 := UInt<1>(0)
      cnt := T_165631
    node cnt_done = and(T_165627, T_165628)
    node T_165632 = eq(rx_word_count, UInt<1>(0))
    wire rx_cmd : UInt
    rx_cmd := cmd
    when T_165632 : rx_cmd := next_cmd
    
    
    node T_165633 = eq(state, UInt<3>(0))
    node T_165634 = and(T_165633, rx_done)
    when T_165634 : 
      node T_165635 = eq(rx_cmd, UInt<3>(0))
      node T_165636 = eq(rx_cmd, UInt<3>(1))
      node T_165637 = eq(rx_cmd, UInt<3>(2))
      node T_165638 = eq(rx_cmd, UInt<3>(3))
      node T_165639 = or(T_165637, T_165638)
      wire T_165640 : UInt<3>
      T_165640 := UInt<3>(7)
      when T_165639 : T_165640 := UInt<3>(1)
      wire T_165641 : UInt<3>
      T_165641 := T_165640
      when T_165636 : T_165641 := UInt<3>(4)
      wire T_165642 : UInt<3>
      T_165642 := T_165641
      when T_165635 : T_165642 := UInt<3>(3)
      state := T_165642
    
    node T_165643 = eq(state, UInt<3>(4))
    when T_165643 : when cnt_done : state := UInt<3>(6)
    
    node T_165644 = eq(state, UInt<3>(3))
    when T_165644 : when mem__.acquire.ready : state := UInt<3>(5)
    
    
    node T_165645 = eq(state, UInt<3>(6))
    node T_165646 = and(T_165645, mem__.grant.valid)
    when T_165646 : 
      node T_165647 = eq(cmd, UInt<3>(0))
      node T_165648 = eq(pos, UInt<1>(1))
      node T_165649 = or(T_165647, T_165648)
      wire T_165650 : UInt<3>
      T_165650 := UInt<3>(0)
      when T_165649 : T_165650 := UInt<3>(7)
      state := T_165650
      node T_165651 = subw(pos, UInt<1>(1))
      pos := T_165651
      node T_165652 = addw(addr, UInt<4>(8))
      addr := T_165652
    
    
    node T_165653 = eq(state, UInt<3>(5))
    node T_165654 = and(T_165653, cnt_done)
    when T_165654 : 
      node T_165655 = eq(cmd, UInt<3>(0))
      node T_165656 = eq(pos, UInt<1>(1))
      node T_165657 = or(T_165655, T_165656)
      wire T_165658 : UInt<3>
      T_165658 := UInt<3>(0)
      when T_165657 : T_165658 := UInt<3>(7)
      state := T_165658
      node T_165659 = subw(pos, UInt<1>(1))
      pos := T_165659
      node T_165660 = addw(addr, UInt<4>(8))
      addr := T_165660
    
    
    node T_165661 = eq(state, UInt<3>(7))
    node T_165662 = and(T_165661, tx_done)
    when T_165662 : 
      
      node T_165663 = eq(tx_word_count, tx_size)
      when T_165663 : 
        rx_count := UInt<1>(0)
        tx_count := UInt<1>(0)
      node T_165664 = eq(cmd, UInt<3>(0))
      node T_165665 = neq(pos, UInt<1>(0))
      node T_165666 = and(T_165664, T_165665)
      wire T_165667 : UInt<3>
      T_165667 := UInt<3>(0)
      when T_165666 : T_165667 := UInt<3>(3)
      state := T_165667
    
    
    node T_165668 = eq(state, UInt<3>(5))
    node T_165669 = and(T_165668, mem__.grant.valid)
    when T_165669 : 
      node T_165670 = cat(mem__.grant.bits.addr_beat, UInt<1>(0))
      accessor T_165671 = packet_ram[T_165670]
      node T_165672 = bits(mem__.grant.bits.data, 63, 0)
      T_165671 := T_165672
    node T_165673 = cat(cnt, UInt<1>(0))
    accessor T_165674 = packet_ram[T_165673]
    
    
    node T_165675 = eq(state, UInt<3>(5))
    node T_165676 = and(T_165675, mem__.grant.valid)
    when T_165676 : 
      node T_165677 = cat(mem__.grant.bits.addr_beat, UInt<1>(1))
      accessor T_165678 = packet_ram[T_165677]
      node T_165679 = bits(mem__.grant.bits.data, 127, 64)
      T_165678 := T_165679
    node T_165680 = cat(cnt, UInt<1>(1))
    accessor T_165681 = packet_ram[T_165680]
    node mem_req_data = cat(T_165681, T_165674)
    node init_addr = dshr(addr, UInt<2>(3))
    node T_165682 = eq(state, UInt<3>(3))
    node T_165683 = eq(state, UInt<3>(4))
    node T_165684 = or(T_165682, T_165683)
    mem__.acquire.valid := T_165684
    node T_165685 = eq(cmd, UInt<3>(1))
    wire T_165686 : UInt<3>[3]
    T_165686[0] := UInt<3>(0)
    T_165686[1] := UInt<3>(1)
    T_165686[2] := UInt<3>(2)
    wire T_165687 : UInt<2>[2]
    T_165687[0] := UInt<2>(0)
    T_165687[1] := UInt<2>(1)
    wire T_165688 : UInt<2>[3]
    T_165688[0] := UInt<2>(1)
    T_165688[1] := UInt<2>(2)
    T_165688[2] := UInt<2>(3)
    wire T_165689 : UInt<2>[2]
    T_165689[0] := UInt<2>(2)
    T_165689[1] := UInt<2>(3)
    wire T_165690 : UInt<2>[1]
    T_165690[0] := UInt<2>(3)
    node T_165691 = asUInt(SInt<16>(-1))
    node T_165692 = cat(T_165691, UInt<1>(1))
    wire T_165693 : UInt<3>[3]
    T_165693[0] := UInt<3>(0)
    T_165693[1] := UInt<3>(1)
    T_165693[2] := UInt<3>(2)
    wire T_165694 : UInt<2>[2]
    T_165694[0] := UInt<2>(0)
    T_165694[1] := UInt<2>(1)
    wire T_165695 : UInt<2>[3]
    T_165695[0] := UInt<2>(1)
    T_165695[1] := UInt<2>(2)
    T_165695[2] := UInt<2>(3)
    wire T_165696 : UInt<2>[2]
    T_165696[0] := UInt<2>(2)
    T_165696[1] := UInt<2>(3)
    wire T_165697 : UInt<2>[1]
    T_165697[0] := UInt<2>(3)
    wire T_165698 : UInt<3>[3]
    T_165698[0] := UInt<3>(0)
    T_165698[1] := UInt<3>(1)
    T_165698[2] := UInt<3>(2)
    wire T_165699 : UInt<2>[2]
    T_165699[0] := UInt<2>(0)
    T_165699[1] := UInt<2>(1)
    wire T_165700 : UInt<2>[3]
    T_165700[0] := UInt<2>(1)
    T_165700[1] := UInt<2>(2)
    T_165700[2] := UInt<2>(3)
    wire T_165701 : UInt<2>[2]
    T_165701[0] := UInt<2>(2)
    T_165701[1] := UInt<2>(3)
    wire T_165702 : UInt<2>[1]
    T_165702[0] := UInt<2>(3)
    wire T_165703 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_165703.is_builtin_type := UInt<1>(1)
    T_165703.a_type := UInt<3>(3)
    T_165703.client_xact_id := UInt<1>(0)
    T_165703.addr_block := init_addr
    T_165703.addr_beat := cnt
    T_165703.data := mem_req_data
    T_165703.union := T_165692
    wire T_165704 : UInt<3>[3]
    T_165704[0] := UInt<3>(0)
    T_165704[1] := UInt<3>(1)
    T_165704[2] := UInt<3>(2)
    wire T_165705 : UInt<2>[2]
    T_165705[0] := UInt<2>(0)
    T_165705[1] := UInt<2>(1)
    wire T_165706 : UInt<2>[3]
    T_165706[0] := UInt<2>(1)
    T_165706[1] := UInt<2>(2)
    T_165706[2] := UInt<2>(3)
    wire T_165707 : UInt<2>[2]
    T_165707[0] := UInt<2>(2)
    T_165707[1] := UInt<2>(3)
    wire T_165708 : UInt<2>[1]
    T_165708[0] := UInt<2>(3)
    wire T_165709 : UInt<3>[3]
    T_165709[0] := UInt<3>(0)
    T_165709[1] := UInt<3>(1)
    T_165709[2] := UInt<3>(2)
    wire T_165710 : UInt<2>[2]
    T_165710[0] := UInt<2>(0)
    T_165710[1] := UInt<2>(1)
    wire T_165711 : UInt<2>[3]
    T_165711[0] := UInt<2>(1)
    T_165711[1] := UInt<2>(2)
    T_165711[2] := UInt<2>(3)
    wire T_165712 : UInt<2>[2]
    T_165712[0] := UInt<2>(2)
    T_165712[1] := UInt<2>(3)
    wire T_165713 : UInt<2>[1]
    T_165713[0] := UInt<2>(3)
    wire T_165714 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_165714.is_builtin_type := UInt<1>(1)
    T_165714.a_type := UInt<3>(1)
    T_165714.client_xact_id := UInt<1>(0)
    T_165714.addr_block := init_addr
    T_165714.addr_beat := UInt<1>(0)
    T_165714.data := UInt<1>(0)
    T_165714.union := UInt<9>(449)
    wire T_165715 : UInt<3>[3]
    T_165715[0] := UInt<3>(0)
    T_165715[1] := UInt<3>(1)
    T_165715[2] := UInt<3>(2)
    wire T_165716 : UInt<2>[2]
    T_165716[0] := UInt<2>(0)
    T_165716[1] := UInt<2>(1)
    wire T_165717 : UInt<2>[3]
    T_165717[0] := UInt<2>(1)
    T_165717[1] := UInt<2>(2)
    T_165717[2] := UInt<2>(3)
    wire T_165718 : UInt<2>[2]
    T_165718[0] := UInt<2>(2)
    T_165718[1] := UInt<2>(3)
    wire T_165719 : UInt<2>[1]
    T_165719[0] := UInt<2>(3)
    wire T_165720 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_165720 := T_165714
    when T_165685 : T_165720 := T_165703
    mem__.acquire.bits := T_165720
    mem__.grant.ready := UInt<1>(1)
    reg rtc : UInt<64>
    onreset rtc := UInt<64>(0)
    reg T_165721 : UInt<7>
    onreset T_165721 := UInt<7>(0)
    node rtc_tick = eq(T_165721, UInt<7>(99))
    node T_165722 = and(UInt<1>(1), rtc_tick)
    node T_165723 = addw(T_165721, UInt<1>(1))
    wire T_165724 : UInt<7>
    T_165724 := T_165723
    when T_165722 : T_165724 := UInt<1>(0)
    T_165721 := T_165724
    when rtc_tick : 
      node T_165725 = addw(rtc, UInt<1>(1))
      rtc := T_165725
    reg pcrReadData : UInt<64>
    reg T_165726 : UInt<1>
    onreset T_165726 := UInt<1>(1)
    reg T_165727 : UInt<1>
    onreset T_165727 := UInt<1>(0)
    node T_165728 = eq(pcr_coreid, UInt<1>(0))
    node T_165729 = eq(state, UInt<3>(1))
    node T_165730 = and(T_165729, T_165728)
    node T_165731 = neq(pcr_addr, UInt<11>(1922))
    node T_165732 = and(T_165730, T_165731)
    cpu[0].pcr_req.valid := T_165732
    node T_165733 = eq(cmd, UInt<3>(3))
    cpu[0].pcr_req.bits.rw := T_165733
    cpu[0].pcr_req.bits.addr := pcr_addr
    cpu[0].pcr_req.bits.data := pcr_wdata
    cpu[0].reset := T_165726
    reg T_165734 : UInt<1>
    onreset T_165734 := UInt<1>(0)
    reg T_165735 : UInt<1>
    onreset T_165735 := UInt<1>(0)
    when rtc_tick : T_165734 := UInt<1>(0)
    when cpu[0].pcr_rep.valid : T_165735 := UInt<1>(0)
    when T_165735 : cpu[0].pcr_req.valid := UInt<1>(0)
    
    
    node T_165736 = neq(state, UInt<3>(1))
    node T_165737 = neq(state, UInt<3>(2))
    node T_165738 = and(T_165736, T_165737)
    node T_165739 = eq(T_165734, UInt<1>(0))
    node T_165740 = and(T_165738, T_165739)
    node T_165741 = eq(T_165735, UInt<1>(0))
    node T_165742 = and(T_165740, T_165741)
    when T_165742 : 
      cpu[0].pcr_req.valid := UInt<1>(1)
      cpu[0].pcr_req.bits.rw := UInt<1>(1)
      cpu[0].pcr_req.bits.addr := UInt<11>(1922)
      cpu[0].pcr_req.bits.data := rtc
      T_165734 := cpu[0].pcr_req.ready
      T_165735 := cpu[0].pcr_req.ready
    when cpu[0].ipi_rep.ready : T_165727 := UInt<1>(0)
    cpu[0].ipi_rep.valid := T_165727
    cpu[0].ipi_req.ready := UInt<1>(1)
    
    
    node T_165743 = eq(cpu[0].ipi_req.bits, UInt<1>(0))
    node T_165744 = and(cpu[0].ipi_req.valid, T_165743)
    when T_165744 : T_165727 := UInt<1>(1)
    
    
    node T_165745 = eq(state, UInt<3>(1))
    node T_165746 = and(cpu[0].pcr_req.ready, cpu[0].pcr_req.valid)
    node T_165747 = and(T_165745, T_165746)
    when T_165747 : state := UInt<3>(2)
    
    
    node T_165748 = eq(state, UInt<3>(1))
    node T_165749 = and(T_165748, T_165728)
    node T_165750 = eq(pcr_addr, UInt<11>(1922))
    node T_165751 = and(T_165749, T_165750)
    when T_165751 : 
      
      node T_165752 = eq(cmd, UInt<3>(3))
      when T_165752 : 
        node T_165753 = bit(pcr_wdata, 0)
        T_165726 := T_165753
      pcrReadData := T_165726
      state := UInt<3>(7)
    cpu[0].pcr_rep.ready := UInt<1>(1)
    
    
    node T_165754 = eq(state, UInt<3>(2))
    node T_165755 = and(T_165754, cpu[0].pcr_rep.valid)
    when T_165755 : 
      pcrReadData := cpu[0].pcr_rep.bits
      state := UInt<3>(7)
    node scr_addr = bits(addr, 5, 0)
    wire scr_rdata : UInt<64>[64]
    scr_rdata[0] := scr.rdata[0]
    scr_rdata[1] := scr.rdata[1]
    scr_rdata[2] := scr.rdata[2]
    scr_rdata[3] := scr.rdata[3]
    scr_rdata[4] := scr.rdata[4]
    scr_rdata[5] := scr.rdata[5]
    scr_rdata[6] := scr.rdata[6]
    scr_rdata[7] := scr.rdata[7]
    scr_rdata[8] := scr.rdata[8]
    scr_rdata[9] := scr.rdata[9]
    scr_rdata[10] := scr.rdata[10]
    scr_rdata[11] := scr.rdata[11]
    scr_rdata[12] := scr.rdata[12]
    scr_rdata[13] := scr.rdata[13]
    scr_rdata[14] := scr.rdata[14]
    scr_rdata[15] := scr.rdata[15]
    scr_rdata[16] := scr.rdata[16]
    scr_rdata[17] := scr.rdata[17]
    scr_rdata[18] := scr.rdata[18]
    scr_rdata[19] := scr.rdata[19]
    scr_rdata[20] := scr.rdata[20]
    scr_rdata[21] := scr.rdata[21]
    scr_rdata[22] := scr.rdata[22]
    scr_rdata[23] := scr.rdata[23]
    scr_rdata[24] := scr.rdata[24]
    scr_rdata[25] := scr.rdata[25]
    scr_rdata[26] := scr.rdata[26]
    scr_rdata[27] := scr.rdata[27]
    scr_rdata[28] := scr.rdata[28]
    scr_rdata[29] := scr.rdata[29]
    scr_rdata[30] := scr.rdata[30]
    scr_rdata[31] := scr.rdata[31]
    scr_rdata[32] := scr.rdata[32]
    scr_rdata[33] := scr.rdata[33]
    scr_rdata[34] := scr.rdata[34]
    scr_rdata[35] := scr.rdata[35]
    scr_rdata[36] := scr.rdata[36]
    scr_rdata[37] := scr.rdata[37]
    scr_rdata[38] := scr.rdata[38]
    scr_rdata[39] := scr.rdata[39]
    scr_rdata[40] := scr.rdata[40]
    scr_rdata[41] := scr.rdata[41]
    scr_rdata[42] := scr.rdata[42]
    scr_rdata[43] := scr.rdata[43]
    scr_rdata[44] := scr.rdata[44]
    scr_rdata[45] := scr.rdata[45]
    scr_rdata[46] := scr.rdata[46]
    scr_rdata[47] := scr.rdata[47]
    scr_rdata[48] := scr.rdata[48]
    scr_rdata[49] := scr.rdata[49]
    scr_rdata[50] := scr.rdata[50]
    scr_rdata[51] := scr.rdata[51]
    scr_rdata[52] := scr.rdata[52]
    scr_rdata[53] := scr.rdata[53]
    scr_rdata[54] := scr.rdata[54]
    scr_rdata[55] := scr.rdata[55]
    scr_rdata[56] := scr.rdata[56]
    scr_rdata[57] := scr.rdata[57]
    scr_rdata[58] := scr.rdata[58]
    scr_rdata[59] := scr.rdata[59]
    scr_rdata[60] := scr.rdata[60]
    scr_rdata[61] := scr.rdata[61]
    scr_rdata[62] := scr.rdata[62]
    scr_rdata[63] := scr.rdata[63]
    scr_rdata[0] := UInt<1>(1)
    scr_rdata[1] := UInt<13>(4096)
    scr.wen := UInt<1>(0)
    scr.wdata := pcr_wdata
    scr.waddr := scr_addr
    
    
    node T_165756 = eq(state, UInt<3>(1))
    node T_165757 = eq(pcr_coreid, SInt<1>(-1))
    node T_165758 = and(T_165756, T_165757)
    when T_165758 : 
      node T_165759 = eq(cmd, UInt<3>(3))
      scr.wen := T_165759
      accessor T_165760 = scr_rdata[scr_addr]
      pcrReadData := T_165760
      state := UInt<3>(7)
    wire tx_cmd : UInt<3>
    tx_cmd := UInt<3>(4)
    when nack : tx_cmd := UInt<3>(5)
    node tx_cmd_ext = cat(UInt<1>(0), tx_cmd)
    node T_165761 = cat(addr, seqno)
    node T_165762 = cat(tx_size, tx_cmd_ext)
    node tx_header = cat(T_165761, T_165762)
    node T_165763 = eq(tx_word_count, UInt<1>(0))
    node T_165764 = eq(cmd, UInt<3>(2))
    node T_165765 = eq(cmd, UInt<3>(3))
    node T_165766 = or(T_165764, T_165765)
    accessor T_165767 = packet_ram[packet_ram_raddr]
    wire T_165768 : UInt<64>
    T_165768 := T_165767
    when T_165766 : T_165768 := pcrReadData
    wire tx_data : UInt<64>
    tx_data := T_165768
    when T_165763 : tx_data := tx_header
    node T_165769 = eq(state, UInt<3>(0))
    host.in.ready := T_165769
    node T_165770 = eq(state, UInt<3>(7))
    host.out.valid := T_165770
    node T_165771 = bits(tx_count, 1, 0)
    node T_165772 = cat(T_165771, UInt<4>(0))
    node T_165773 = dshr(tx_data, T_165772)
    host.out.bits := T_165773
  module ClientTileLinkIOWrapper : 
    input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    
    wire T_165774 : UInt<3>[3]
    T_165774[0] := UInt<3>(0)
    T_165774[1] := UInt<3>(1)
    T_165774[2] := UInt<3>(2)
    wire T_165775 : UInt<2>[2]
    T_165775[0] := UInt<2>(0)
    T_165775[1] := UInt<2>(1)
    wire T_165776 : UInt<2>[3]
    T_165776[0] := UInt<2>(1)
    T_165776[1] := UInt<2>(2)
    T_165776[2] := UInt<2>(3)
    wire T_165777 : UInt<2>[2]
    T_165777[0] := UInt<2>(2)
    T_165777[1] := UInt<2>(3)
    wire T_165778 : UInt<2>[1]
    T_165778[0] := UInt<2>(3)
    wire T_165779 : UInt<3>[3]
    T_165779[0] := UInt<3>(0)
    T_165779[1] := UInt<3>(1)
    T_165779[2] := UInt<3>(2)
    wire T_165780 : UInt<2>[2]
    T_165780[0] := UInt<2>(0)
    T_165780[1] := UInt<2>(1)
    wire T_165781 : UInt<2>[3]
    T_165781[0] := UInt<2>(1)
    T_165781[1] := UInt<2>(2)
    T_165781[2] := UInt<2>(3)
    wire T_165782 : UInt<2>[2]
    T_165782[0] := UInt<2>(2)
    T_165782[1] := UInt<2>(3)
    wire T_165783 : UInt<2>[1]
    T_165783[0] := UInt<2>(3)
    wire T_165784 : UInt<3>[3]
    T_165784[0] := UInt<3>(0)
    T_165784[1] := UInt<3>(1)
    T_165784[2] := UInt<3>(2)
    wire T_165785 : UInt<2>[2]
    T_165785[0] := UInt<2>(0)
    T_165785[1] := UInt<2>(1)
    wire T_165786 : UInt<2>[3]
    T_165786[0] := UInt<2>(1)
    T_165786[1] := UInt<2>(2)
    T_165786[2] := UInt<2>(3)
    wire T_165787 : UInt<2>[2]
    T_165787[0] := UInt<2>(2)
    T_165787[1] := UInt<2>(3)
    wire T_165788 : UInt<2>[1]
    T_165788[0] := UInt<2>(3)
    wire T_165789 : UInt<3>[3]
    T_165789[0] := UInt<3>(0)
    T_165789[1] := UInt<3>(1)
    T_165789[2] := UInt<3>(2)
    wire T_165790 : UInt<2>[2]
    T_165790[0] := UInt<2>(0)
    T_165790[1] := UInt<2>(1)
    wire T_165791 : UInt<2>[3]
    T_165791[0] := UInt<2>(1)
    T_165791[1] := UInt<2>(2)
    T_165791[2] := UInt<2>(3)
    wire T_165792 : UInt<2>[2]
    T_165792[0] := UInt<2>(2)
    T_165792[1] := UInt<2>(3)
    wire T_165793 : UInt<2>[1]
    T_165793[0] := UInt<2>(3)
    wire T_165794 : UInt<3>[3]
    T_165794[0] := UInt<3>(0)
    T_165794[1] := UInt<3>(1)
    T_165794[2] := UInt<3>(2)
    wire T_165795 : UInt<2>[2]
    T_165795[0] := UInt<2>(0)
    T_165795[1] := UInt<2>(1)
    wire T_165796 : UInt<2>[3]
    T_165796[0] := UInt<2>(1)
    T_165796[1] := UInt<2>(2)
    T_165796[2] := UInt<2>(3)
    wire T_165797 : UInt<2>[2]
    T_165797[0] := UInt<2>(2)
    T_165797[1] := UInt<2>(3)
    wire T_165798 : UInt<2>[1]
    T_165798[0] := UInt<2>(3)
    wire T_165799 : UInt<3>[3]
    T_165799[0] := UInt<3>(0)
    T_165799[1] := UInt<3>(1)
    T_165799[2] := UInt<3>(2)
    wire T_165800 : UInt<2>[2]
    T_165800[0] := UInt<2>(0)
    T_165800[1] := UInt<2>(1)
    wire T_165801 : UInt<2>[3]
    T_165801[0] := UInt<2>(1)
    T_165801[1] := UInt<2>(2)
    T_165801[2] := UInt<2>(3)
    wire T_165802 : UInt<2>[2]
    T_165802[0] := UInt<2>(2)
    T_165802[1] := UInt<2>(3)
    wire T_165803 : UInt<2>[1]
    T_165803[0] := UInt<2>(3)
    wire T_165804 : UInt<3>[3]
    T_165804[0] := UInt<3>(0)
    T_165804[1] := UInt<3>(1)
    T_165804[2] := UInt<3>(2)
    wire T_165805 : UInt<2>[2]
    T_165805[0] := UInt<2>(0)
    T_165805[1] := UInt<2>(1)
    wire T_165806 : UInt<2>[3]
    T_165806[0] := UInt<2>(1)
    T_165806[1] := UInt<2>(2)
    T_165806[2] := UInt<2>(3)
    wire T_165807 : UInt<2>[2]
    T_165807[0] := UInt<2>(2)
    T_165807[1] := UInt<2>(3)
    wire T_165808 : UInt<2>[1]
    T_165808[0] := UInt<2>(3)
    wire T_165809 : UInt<3>[3]
    T_165809[0] := UInt<3>(0)
    T_165809[1] := UInt<3>(1)
    T_165809[2] := UInt<3>(2)
    wire T_165810 : UInt<2>[2]
    T_165810[0] := UInt<2>(0)
    T_165810[1] := UInt<2>(1)
    wire T_165811 : UInt<2>[3]
    T_165811[0] := UInt<2>(1)
    T_165811[1] := UInt<2>(2)
    T_165811[2] := UInt<2>(3)
    wire T_165812 : UInt<2>[2]
    T_165812[0] := UInt<2>(2)
    T_165812[1] := UInt<2>(3)
    wire T_165813 : UInt<2>[1]
    T_165813[0] := UInt<2>(3)
    wire T_165814 : UInt<3>[3]
    T_165814[0] := UInt<3>(0)
    T_165814[1] := UInt<3>(1)
    T_165814[2] := UInt<3>(2)
    wire T_165815 : UInt<2>[2]
    T_165815[0] := UInt<2>(0)
    T_165815[1] := UInt<2>(1)
    wire T_165816 : UInt<2>[3]
    T_165816[0] := UInt<2>(1)
    T_165816[1] := UInt<2>(2)
    T_165816[2] := UInt<2>(3)
    wire T_165817 : UInt<2>[2]
    T_165817[0] := UInt<2>(2)
    T_165817[1] := UInt<2>(3)
    wire T_165818 : UInt<2>[1]
    T_165818[0] := UInt<2>(3)
    wire T_165819 : UInt<3>[3]
    T_165819[0] := UInt<3>(0)
    T_165819[1] := UInt<3>(1)
    T_165819[2] := UInt<3>(2)
    wire T_165820 : UInt<2>[2]
    T_165820[0] := UInt<2>(0)
    T_165820[1] := UInt<2>(1)
    wire T_165821 : UInt<2>[3]
    T_165821[0] := UInt<2>(1)
    T_165821[1] := UInt<2>(2)
    T_165821[2] := UInt<2>(3)
    wire T_165822 : UInt<2>[2]
    T_165822[0] := UInt<2>(2)
    T_165822[1] := UInt<2>(3)
    wire T_165823 : UInt<2>[1]
    T_165823[0] := UInt<2>(3)
    wire T_165824 : UInt<3>[3]
    T_165824[0] := UInt<3>(0)
    T_165824[1] := UInt<3>(1)
    T_165824[2] := UInt<3>(2)
    wire T_165825 : UInt<2>[2]
    T_165825[0] := UInt<2>(0)
    T_165825[1] := UInt<2>(1)
    wire T_165826 : UInt<2>[3]
    T_165826[0] := UInt<2>(1)
    T_165826[1] := UInt<2>(2)
    T_165826[2] := UInt<2>(3)
    wire T_165827 : UInt<2>[2]
    T_165827[0] := UInt<2>(2)
    T_165827[1] := UInt<2>(3)
    wire T_165828 : UInt<2>[1]
    T_165828[0] := UInt<2>(3)
    wire T_165829 : UInt<3>[3]
    T_165829[0] := UInt<3>(0)
    T_165829[1] := UInt<3>(1)
    T_165829[2] := UInt<3>(2)
    wire T_165830 : UInt<2>[2]
    T_165830[0] := UInt<2>(0)
    T_165830[1] := UInt<2>(1)
    wire T_165831 : UInt<2>[3]
    T_165831[0] := UInt<2>(1)
    T_165831[1] := UInt<2>(2)
    T_165831[2] := UInt<2>(3)
    wire T_165832 : UInt<2>[2]
    T_165832[0] := UInt<2>(2)
    T_165832[1] := UInt<2>(3)
    wire T_165833 : UInt<2>[1]
    T_165833[0] := UInt<2>(3)
    wire T_165834 : UInt<3>[3]
    T_165834[0] := UInt<3>(0)
    T_165834[1] := UInt<3>(1)
    T_165834[2] := UInt<3>(2)
    wire T_165835 : UInt<2>[2]
    T_165835[0] := UInt<2>(0)
    T_165835[1] := UInt<2>(1)
    wire T_165836 : UInt<2>[3]
    T_165836[0] := UInt<2>(1)
    T_165836[1] := UInt<2>(2)
    T_165836[2] := UInt<2>(3)
    wire T_165837 : UInt<2>[2]
    T_165837[0] := UInt<2>(2)
    T_165837[1] := UInt<2>(3)
    wire T_165838 : UInt<2>[1]
    T_165838[0] := UInt<2>(3)
    wire T_165839 : UInt<3>[3]
    T_165839[0] := UInt<3>(0)
    T_165839[1] := UInt<3>(1)
    T_165839[2] := UInt<3>(2)
    wire T_165840 : UInt<2>[2]
    T_165840[0] := UInt<2>(0)
    T_165840[1] := UInt<2>(1)
    wire T_165841 : UInt<2>[3]
    T_165841[0] := UInt<2>(1)
    T_165841[1] := UInt<2>(2)
    T_165841[2] := UInt<2>(3)
    wire T_165842 : UInt<2>[2]
    T_165842[0] := UInt<2>(2)
    T_165842[1] := UInt<2>(3)
    wire T_165843 : UInt<2>[1]
    T_165843[0] := UInt<2>(3)
    wire T_165844 : UInt<3>[3]
    T_165844[0] := UInt<3>(0)
    T_165844[1] := UInt<3>(1)
    T_165844[2] := UInt<3>(2)
    wire T_165845 : UInt<2>[2]
    T_165845[0] := UInt<2>(0)
    T_165845[1] := UInt<2>(1)
    wire T_165846 : UInt<2>[3]
    T_165846[0] := UInt<2>(1)
    T_165846[1] := UInt<2>(2)
    T_165846[2] := UInt<2>(3)
    wire T_165847 : UInt<2>[2]
    T_165847[0] := UInt<2>(2)
    T_165847[1] := UInt<2>(3)
    wire T_165848 : UInt<2>[1]
    T_165848[0] := UInt<2>(3)
    out.acquire <> in.acquire
    out.grant <> in.grant
    out.probe.ready := UInt<1>(1)
    out.release.valid := UInt<1>(0)
  module ClientTileLinkIOWrapper_7600 : 
    input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    
    wire T_165849 : UInt<3>[3]
    T_165849[0] := UInt<3>(0)
    T_165849[1] := UInt<3>(1)
    T_165849[2] := UInt<3>(2)
    wire T_165850 : UInt<2>[2]
    T_165850[0] := UInt<2>(0)
    T_165850[1] := UInt<2>(1)
    wire T_165851 : UInt<2>[3]
    T_165851[0] := UInt<2>(1)
    T_165851[1] := UInt<2>(2)
    T_165851[2] := UInt<2>(3)
    wire T_165852 : UInt<2>[2]
    T_165852[0] := UInt<2>(2)
    T_165852[1] := UInt<2>(3)
    wire T_165853 : UInt<2>[1]
    T_165853[0] := UInt<2>(3)
    wire T_165854 : UInt<3>[3]
    T_165854[0] := UInt<3>(0)
    T_165854[1] := UInt<3>(1)
    T_165854[2] := UInt<3>(2)
    wire T_165855 : UInt<2>[2]
    T_165855[0] := UInt<2>(0)
    T_165855[1] := UInt<2>(1)
    wire T_165856 : UInt<2>[3]
    T_165856[0] := UInt<2>(1)
    T_165856[1] := UInt<2>(2)
    T_165856[2] := UInt<2>(3)
    wire T_165857 : UInt<2>[2]
    T_165857[0] := UInt<2>(2)
    T_165857[1] := UInt<2>(3)
    wire T_165858 : UInt<2>[1]
    T_165858[0] := UInt<2>(3)
    wire T_165859 : UInt<3>[3]
    T_165859[0] := UInt<3>(0)
    T_165859[1] := UInt<3>(1)
    T_165859[2] := UInt<3>(2)
    wire T_165860 : UInt<2>[2]
    T_165860[0] := UInt<2>(0)
    T_165860[1] := UInt<2>(1)
    wire T_165861 : UInt<2>[3]
    T_165861[0] := UInt<2>(1)
    T_165861[1] := UInt<2>(2)
    T_165861[2] := UInt<2>(3)
    wire T_165862 : UInt<2>[2]
    T_165862[0] := UInt<2>(2)
    T_165862[1] := UInt<2>(3)
    wire T_165863 : UInt<2>[1]
    T_165863[0] := UInt<2>(3)
    wire T_165864 : UInt<3>[3]
    T_165864[0] := UInt<3>(0)
    T_165864[1] := UInt<3>(1)
    T_165864[2] := UInt<3>(2)
    wire T_165865 : UInt<2>[2]
    T_165865[0] := UInt<2>(0)
    T_165865[1] := UInt<2>(1)
    wire T_165866 : UInt<2>[3]
    T_165866[0] := UInt<2>(1)
    T_165866[1] := UInt<2>(2)
    T_165866[2] := UInt<2>(3)
    wire T_165867 : UInt<2>[2]
    T_165867[0] := UInt<2>(2)
    T_165867[1] := UInt<2>(3)
    wire T_165868 : UInt<2>[1]
    T_165868[0] := UInt<2>(3)
    wire T_165869 : UInt<3>[3]
    T_165869[0] := UInt<3>(0)
    T_165869[1] := UInt<3>(1)
    T_165869[2] := UInt<3>(2)
    wire T_165870 : UInt<2>[2]
    T_165870[0] := UInt<2>(0)
    T_165870[1] := UInt<2>(1)
    wire T_165871 : UInt<2>[3]
    T_165871[0] := UInt<2>(1)
    T_165871[1] := UInt<2>(2)
    T_165871[2] := UInt<2>(3)
    wire T_165872 : UInt<2>[2]
    T_165872[0] := UInt<2>(2)
    T_165872[1] := UInt<2>(3)
    wire T_165873 : UInt<2>[1]
    T_165873[0] := UInt<2>(3)
    wire T_165874 : UInt<3>[3]
    T_165874[0] := UInt<3>(0)
    T_165874[1] := UInt<3>(1)
    T_165874[2] := UInt<3>(2)
    wire T_165875 : UInt<2>[2]
    T_165875[0] := UInt<2>(0)
    T_165875[1] := UInt<2>(1)
    wire T_165876 : UInt<2>[3]
    T_165876[0] := UInt<2>(1)
    T_165876[1] := UInt<2>(2)
    T_165876[2] := UInt<2>(3)
    wire T_165877 : UInt<2>[2]
    T_165877[0] := UInt<2>(2)
    T_165877[1] := UInt<2>(3)
    wire T_165878 : UInt<2>[1]
    T_165878[0] := UInt<2>(3)
    wire T_165879 : UInt<3>[3]
    T_165879[0] := UInt<3>(0)
    T_165879[1] := UInt<3>(1)
    T_165879[2] := UInt<3>(2)
    wire T_165880 : UInt<2>[2]
    T_165880[0] := UInt<2>(0)
    T_165880[1] := UInt<2>(1)
    wire T_165881 : UInt<2>[3]
    T_165881[0] := UInt<2>(1)
    T_165881[1] := UInt<2>(2)
    T_165881[2] := UInt<2>(3)
    wire T_165882 : UInt<2>[2]
    T_165882[0] := UInt<2>(2)
    T_165882[1] := UInt<2>(3)
    wire T_165883 : UInt<2>[1]
    T_165883[0] := UInt<2>(3)
    wire T_165884 : UInt<3>[3]
    T_165884[0] := UInt<3>(0)
    T_165884[1] := UInt<3>(1)
    T_165884[2] := UInt<3>(2)
    wire T_165885 : UInt<2>[2]
    T_165885[0] := UInt<2>(0)
    T_165885[1] := UInt<2>(1)
    wire T_165886 : UInt<2>[3]
    T_165886[0] := UInt<2>(1)
    T_165886[1] := UInt<2>(2)
    T_165886[2] := UInt<2>(3)
    wire T_165887 : UInt<2>[2]
    T_165887[0] := UInt<2>(2)
    T_165887[1] := UInt<2>(3)
    wire T_165888 : UInt<2>[1]
    T_165888[0] := UInt<2>(3)
    wire T_165889 : UInt<3>[3]
    T_165889[0] := UInt<3>(0)
    T_165889[1] := UInt<3>(1)
    T_165889[2] := UInt<3>(2)
    wire T_165890 : UInt<2>[2]
    T_165890[0] := UInt<2>(0)
    T_165890[1] := UInt<2>(1)
    wire T_165891 : UInt<2>[3]
    T_165891[0] := UInt<2>(1)
    T_165891[1] := UInt<2>(2)
    T_165891[2] := UInt<2>(3)
    wire T_165892 : UInt<2>[2]
    T_165892[0] := UInt<2>(2)
    T_165892[1] := UInt<2>(3)
    wire T_165893 : UInt<2>[1]
    T_165893[0] := UInt<2>(3)
    wire T_165894 : UInt<3>[3]
    T_165894[0] := UInt<3>(0)
    T_165894[1] := UInt<3>(1)
    T_165894[2] := UInt<3>(2)
    wire T_165895 : UInt<2>[2]
    T_165895[0] := UInt<2>(0)
    T_165895[1] := UInt<2>(1)
    wire T_165896 : UInt<2>[3]
    T_165896[0] := UInt<2>(1)
    T_165896[1] := UInt<2>(2)
    T_165896[2] := UInt<2>(3)
    wire T_165897 : UInt<2>[2]
    T_165897[0] := UInt<2>(2)
    T_165897[1] := UInt<2>(3)
    wire T_165898 : UInt<2>[1]
    T_165898[0] := UInt<2>(3)
    wire T_165899 : UInt<3>[3]
    T_165899[0] := UInt<3>(0)
    T_165899[1] := UInt<3>(1)
    T_165899[2] := UInt<3>(2)
    wire T_165900 : UInt<2>[2]
    T_165900[0] := UInt<2>(0)
    T_165900[1] := UInt<2>(1)
    wire T_165901 : UInt<2>[3]
    T_165901[0] := UInt<2>(1)
    T_165901[1] := UInt<2>(2)
    T_165901[2] := UInt<2>(3)
    wire T_165902 : UInt<2>[2]
    T_165902[0] := UInt<2>(2)
    T_165902[1] := UInt<2>(3)
    wire T_165903 : UInt<2>[1]
    T_165903[0] := UInt<2>(3)
    wire T_165904 : UInt<3>[3]
    T_165904[0] := UInt<3>(0)
    T_165904[1] := UInt<3>(1)
    T_165904[2] := UInt<3>(2)
    wire T_165905 : UInt<2>[2]
    T_165905[0] := UInt<2>(0)
    T_165905[1] := UInt<2>(1)
    wire T_165906 : UInt<2>[3]
    T_165906[0] := UInt<2>(1)
    T_165906[1] := UInt<2>(2)
    T_165906[2] := UInt<2>(3)
    wire T_165907 : UInt<2>[2]
    T_165907[0] := UInt<2>(2)
    T_165907[1] := UInt<2>(3)
    wire T_165908 : UInt<2>[1]
    T_165908[0] := UInt<2>(3)
    wire T_165909 : UInt<3>[3]
    T_165909[0] := UInt<3>(0)
    T_165909[1] := UInt<3>(1)
    T_165909[2] := UInt<3>(2)
    wire T_165910 : UInt<2>[2]
    T_165910[0] := UInt<2>(0)
    T_165910[1] := UInt<2>(1)
    wire T_165911 : UInt<2>[3]
    T_165911[0] := UInt<2>(1)
    T_165911[1] := UInt<2>(2)
    T_165911[2] := UInt<2>(3)
    wire T_165912 : UInt<2>[2]
    T_165912[0] := UInt<2>(2)
    T_165912[1] := UInt<2>(3)
    wire T_165913 : UInt<2>[1]
    T_165913[0] := UInt<2>(3)
    wire T_165914 : UInt<3>[3]
    T_165914[0] := UInt<3>(0)
    T_165914[1] := UInt<3>(1)
    T_165914[2] := UInt<3>(2)
    wire T_165915 : UInt<2>[2]
    T_165915[0] := UInt<2>(0)
    T_165915[1] := UInt<2>(1)
    wire T_165916 : UInt<2>[3]
    T_165916[0] := UInt<2>(1)
    T_165916[1] := UInt<2>(2)
    T_165916[2] := UInt<2>(3)
    wire T_165917 : UInt<2>[2]
    T_165917[0] := UInt<2>(2)
    T_165917[1] := UInt<2>(3)
    wire T_165918 : UInt<2>[1]
    T_165918[0] := UInt<2>(3)
    wire T_165919 : UInt<3>[3]
    T_165919[0] := UInt<3>(0)
    T_165919[1] := UInt<3>(1)
    T_165919[2] := UInt<3>(2)
    wire T_165920 : UInt<2>[2]
    T_165920[0] := UInt<2>(0)
    T_165920[1] := UInt<2>(1)
    wire T_165921 : UInt<2>[3]
    T_165921[0] := UInt<2>(1)
    T_165921[1] := UInt<2>(2)
    T_165921[2] := UInt<2>(3)
    wire T_165922 : UInt<2>[2]
    T_165922[0] := UInt<2>(2)
    T_165922[1] := UInt<2>(3)
    wire T_165923 : UInt<2>[1]
    T_165923[0] := UInt<2>(3)
    out.acquire <> in.acquire
    out.grant <> in.grant
    out.probe.ready := UInt<1>(1)
    out.release.valid := UInt<1>(0)
  module FinishQueue : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}}
    output count : UInt<2>
    
    wire T_165924 : UInt<3>[3]
    T_165924[0] := UInt<3>(0)
    T_165924[1] := UInt<3>(1)
    T_165924[2] := UInt<3>(2)
    wire T_165925 : UInt<2>[2]
    T_165925[0] := UInt<2>(0)
    T_165925[1] := UInt<2>(1)
    wire T_165926 : UInt<2>[3]
    T_165926[0] := UInt<2>(1)
    T_165926[1] := UInt<2>(2)
    T_165926[2] := UInt<2>(3)
    wire T_165927 : UInt<2>[2]
    T_165927[0] := UInt<2>(2)
    T_165927[1] := UInt<2>(3)
    wire T_165928 : UInt<2>[1]
    T_165928[0] := UInt<2>(3)
    wire T_165929 : UInt<3>[3]
    T_165929[0] := UInt<3>(0)
    T_165929[1] := UInt<3>(1)
    T_165929[2] := UInt<3>(2)
    wire T_165930 : UInt<2>[2]
    T_165930[0] := UInt<2>(0)
    T_165930[1] := UInt<2>(1)
    wire T_165931 : UInt<2>[3]
    T_165931[0] := UInt<2>(1)
    T_165931[1] := UInt<2>(2)
    T_165931[2] := UInt<2>(3)
    wire T_165932 : UInt<2>[2]
    T_165932[0] := UInt<2>(2)
    T_165932[1] := UInt<2>(3)
    wire T_165933 : UInt<2>[1]
    T_165933[0] := UInt<2>(3)
    wire T_165934 : UInt<3>[3]
    T_165934[0] := UInt<3>(0)
    T_165934[1] := UInt<3>(1)
    T_165934[2] := UInt<3>(2)
    wire T_165935 : UInt<2>[2]
    T_165935[0] := UInt<2>(0)
    T_165935[1] := UInt<2>(1)
    wire T_165936 : UInt<2>[3]
    T_165936[0] := UInt<2>(1)
    T_165936[1] := UInt<2>(2)
    T_165936[2] := UInt<2>(3)
    wire T_165937 : UInt<2>[2]
    T_165937[0] := UInt<2>(2)
    T_165937[1] := UInt<2>(3)
    wire T_165938 : UInt<2>[1]
    T_165938[0] := UInt<2>(3)
    wire T_165939 : UInt<3>[3]
    T_165939[0] := UInt<3>(0)
    T_165939[1] := UInt<3>(1)
    T_165939[2] := UInt<3>(2)
    wire T_165940 : UInt<2>[2]
    T_165940[0] := UInt<2>(0)
    T_165940[1] := UInt<2>(1)
    wire T_165941 : UInt<2>[3]
    T_165941[0] := UInt<2>(1)
    T_165941[1] := UInt<2>(2)
    T_165941[2] := UInt<2>(3)
    wire T_165942 : UInt<2>[2]
    T_165942[0] := UInt<2>(2)
    T_165942[1] := UInt<2>(3)
    wire T_165943 : UInt<2>[1]
    T_165943[0] := UInt<2>(3)
    wire T_165944 : UInt<3>[3]
    T_165944[0] := UInt<3>(0)
    T_165944[1] := UInt<3>(1)
    T_165944[2] := UInt<3>(2)
    wire T_165945 : UInt<2>[2]
    T_165945[0] := UInt<2>(0)
    T_165945[1] := UInt<2>(1)
    wire T_165946 : UInt<2>[3]
    T_165946[0] := UInt<2>(1)
    T_165946[1] := UInt<2>(2)
    T_165946[2] := UInt<2>(3)
    wire T_165947 : UInt<2>[2]
    T_165947[0] := UInt<2>(2)
    T_165947[1] := UInt<2>(3)
    wire T_165948 : UInt<2>[1]
    T_165948[0] := UInt<2>(3)
    wire T_165949 : UInt<3>[3]
    T_165949[0] := UInt<3>(0)
    T_165949[1] := UInt<3>(1)
    T_165949[2] := UInt<3>(2)
    wire T_165950 : UInt<2>[2]
    T_165950[0] := UInt<2>(0)
    T_165950[1] := UInt<2>(1)
    wire T_165951 : UInt<2>[3]
    T_165951[0] := UInt<2>(1)
    T_165951[1] := UInt<2>(2)
    T_165951[2] := UInt<2>(3)
    wire T_165952 : UInt<2>[2]
    T_165952[0] := UInt<2>(2)
    T_165952[1] := UInt<2>(3)
    wire T_165953 : UInt<2>[1]
    T_165953[0] := UInt<2>(3)
    wire T_165954 : UInt<3>[3]
    T_165954[0] := UInt<3>(0)
    T_165954[1] := UInt<3>(1)
    T_165954[2] := UInt<3>(2)
    wire T_165955 : UInt<2>[2]
    T_165955[0] := UInt<2>(0)
    T_165955[1] := UInt<2>(1)
    wire T_165956 : UInt<2>[3]
    T_165956[0] := UInt<2>(1)
    T_165956[1] := UInt<2>(2)
    T_165956[2] := UInt<2>(3)
    wire T_165957 : UInt<2>[2]
    T_165957[0] := UInt<2>(2)
    T_165957[1] := UInt<2>(3)
    wire T_165958 : UInt<2>[1]
    T_165958[0] := UInt<2>(3)
    wire T_165959 : UInt<3>[3]
    T_165959[0] := UInt<3>(0)
    T_165959[1] := UInt<3>(1)
    T_165959[2] := UInt<3>(2)
    wire T_165960 : UInt<2>[2]
    T_165960[0] := UInt<2>(0)
    T_165960[1] := UInt<2>(1)
    wire T_165961 : UInt<2>[3]
    T_165961[0] := UInt<2>(1)
    T_165961[1] := UInt<2>(2)
    T_165961[2] := UInt<2>(3)
    wire T_165962 : UInt<2>[2]
    T_165962[0] := UInt<2>(2)
    T_165962[1] := UInt<2>(3)
    wire T_165963 : UInt<2>[1]
    T_165963[0] := UInt<2>(3)
    wire T_165964 : UInt<3>[3]
    T_165964[0] := UInt<3>(0)
    T_165964[1] := UInt<3>(1)
    T_165964[2] := UInt<3>(2)
    wire T_165965 : UInt<2>[2]
    T_165965[0] := UInt<2>(0)
    T_165965[1] := UInt<2>(1)
    wire T_165966 : UInt<2>[3]
    T_165966[0] := UInt<2>(1)
    T_165966[1] := UInt<2>(2)
    T_165966[2] := UInt<2>(3)
    wire T_165967 : UInt<2>[2]
    T_165967[0] := UInt<2>(2)
    T_165967[1] := UInt<2>(3)
    wire T_165968 : UInt<2>[1]
    T_165968[0] := UInt<2>(3)
    wire T_165969 : UInt<3>[3]
    T_165969[0] := UInt<3>(0)
    T_165969[1] := UInt<3>(1)
    T_165969[2] := UInt<3>(2)
    wire T_165970 : UInt<2>[2]
    T_165970[0] := UInt<2>(0)
    T_165970[1] := UInt<2>(1)
    wire T_165971 : UInt<2>[3]
    T_165971[0] := UInt<2>(1)
    T_165971[1] := UInt<2>(2)
    T_165971[2] := UInt<2>(3)
    wire T_165972 : UInt<2>[2]
    T_165972[0] := UInt<2>(2)
    T_165972[1] := UInt<2>(3)
    wire T_165973 : UInt<2>[1]
    T_165973[0] := UInt<2>(3)
    cmem T_165974 : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}[2]
    reg T_165975 : UInt<1>
    onreset T_165975 := UInt<1>(0)
    reg T_165976 : UInt<1>
    onreset T_165976 := UInt<1>(0)
    reg T_165977 : UInt<1>
    onreset T_165977 := UInt<1>(0)
    node T_165978 = eq(T_165975, T_165976)
    node T_165979 = eq(T_165977, UInt<1>(0))
    node T_165980 = and(T_165978, T_165979)
    node T_165981 = and(T_165978, T_165977)
    node T_165982 = and(UInt<1>(0), T_165980)
    node T_165983 = and(T_165982, deq.ready)
    node T_165984 = and(enq.ready, enq.valid)
    node T_165985 = eq(T_165983, UInt<1>(0))
    node T_165986 = and(T_165984, T_165985)
    node T_165987 = and(deq.ready, deq.valid)
    node T_165988 = eq(T_165983, UInt<1>(0))
    node T_165989 = and(T_165987, T_165988)
    when T_165986 : 
      wire T_165990 : UInt<3>[3]
      T_165990[0] := UInt<3>(0)
      T_165990[1] := UInt<3>(1)
      T_165990[2] := UInt<3>(2)
      wire T_165991 : UInt<2>[2]
      T_165991[0] := UInt<2>(0)
      T_165991[1] := UInt<2>(1)
      wire T_165992 : UInt<2>[3]
      T_165992[0] := UInt<2>(1)
      T_165992[1] := UInt<2>(2)
      T_165992[2] := UInt<2>(3)
      wire T_165993 : UInt<2>[2]
      T_165993[0] := UInt<2>(2)
      T_165993[1] := UInt<2>(3)
      wire T_165994 : UInt<2>[1]
      T_165994[0] := UInt<2>(3)
      wire T_165995 : UInt<3>[3]
      T_165995[0] := UInt<3>(0)
      T_165995[1] := UInt<3>(1)
      T_165995[2] := UInt<3>(2)
      wire T_165996 : UInt<2>[2]
      T_165996[0] := UInt<2>(0)
      T_165996[1] := UInt<2>(1)
      wire T_165997 : UInt<2>[3]
      T_165997[0] := UInt<2>(1)
      T_165997[1] := UInt<2>(2)
      T_165997[2] := UInt<2>(3)
      wire T_165998 : UInt<2>[2]
      T_165998[0] := UInt<2>(2)
      T_165998[1] := UInt<2>(3)
      wire T_165999 : UInt<2>[1]
      T_165999[0] := UInt<2>(3)
      accessor T_166000 = T_165974[T_165975]
      T_166000 := enq.bits
      node T_166001 = eq(T_165975, UInt<1>(1))
      node T_166002 = and(UInt<1>(0), T_166001)
      node T_166003 = addw(T_165975, UInt<1>(1))
      wire T_166004 : UInt<1>
      T_166004 := T_166003
      when T_166002 : T_166004 := UInt<1>(0)
      T_165975 := T_166004
    when T_165989 : 
      node T_166005 = eq(T_165976, UInt<1>(1))
      node T_166006 = and(UInt<1>(0), T_166005)
      node T_166007 = addw(T_165976, UInt<1>(1))
      wire T_166008 : UInt<1>
      T_166008 := T_166007
      when T_166006 : T_166008 := UInt<1>(0)
      T_165976 := T_166008
    
    node T_166009 = neq(T_165986, T_165989)
    when T_166009 : T_165977 := T_165986
    node T_166010 = eq(T_165980, UInt<1>(0))
    node T_166011 = and(UInt<1>(0), enq.valid)
    node T_166012 = or(T_166010, T_166011)
    deq.valid := T_166012
    node T_166013 = eq(T_165981, UInt<1>(0))
    node T_166014 = and(UInt<1>(0), deq.ready)
    node T_166015 = or(T_166013, T_166014)
    enq.ready := T_166015
    wire T_166016 : UInt<3>[3]
    T_166016[0] := UInt<3>(0)
    T_166016[1] := UInt<3>(1)
    T_166016[2] := UInt<3>(2)
    wire T_166017 : UInt<2>[2]
    T_166017[0] := UInt<2>(0)
    T_166017[1] := UInt<2>(1)
    wire T_166018 : UInt<2>[3]
    T_166018[0] := UInt<2>(1)
    T_166018[1] := UInt<2>(2)
    T_166018[2] := UInt<2>(3)
    wire T_166019 : UInt<2>[2]
    T_166019[0] := UInt<2>(2)
    T_166019[1] := UInt<2>(3)
    wire T_166020 : UInt<2>[1]
    T_166020[0] := UInt<2>(3)
    wire T_166021 : UInt<3>[3]
    T_166021[0] := UInt<3>(0)
    T_166021[1] := UInt<3>(1)
    T_166021[2] := UInt<3>(2)
    wire T_166022 : UInt<2>[2]
    T_166022[0] := UInt<2>(0)
    T_166022[1] := UInt<2>(1)
    wire T_166023 : UInt<2>[3]
    T_166023[0] := UInt<2>(1)
    T_166023[1] := UInt<2>(2)
    T_166023[2] := UInt<2>(3)
    wire T_166024 : UInt<2>[2]
    T_166024[0] := UInt<2>(2)
    T_166024[1] := UInt<2>(3)
    wire T_166025 : UInt<2>[1]
    T_166025[0] := UInt<2>(3)
    accessor T_166026 = T_165974[T_165976]
    wire T_166027 : UInt<3>[3]
    T_166027[0] := UInt<3>(0)
    T_166027[1] := UInt<3>(1)
    T_166027[2] := UInt<3>(2)
    wire T_166028 : UInt<2>[2]
    T_166028[0] := UInt<2>(0)
    T_166028[1] := UInt<2>(1)
    wire T_166029 : UInt<2>[3]
    T_166029[0] := UInt<2>(1)
    T_166029[1] := UInt<2>(2)
    T_166029[2] := UInt<2>(3)
    wire T_166030 : UInt<2>[2]
    T_166030[0] := UInt<2>(2)
    T_166030[1] := UInt<2>(3)
    wire T_166031 : UInt<2>[1]
    T_166031[0] := UInt<2>(3)
    wire T_166032 : UInt<3>[3]
    T_166032[0] := UInt<3>(0)
    T_166032[1] := UInt<3>(1)
    T_166032[2] := UInt<3>(2)
    wire T_166033 : UInt<2>[2]
    T_166033[0] := UInt<2>(0)
    T_166033[1] := UInt<2>(1)
    wire T_166034 : UInt<2>[3]
    T_166034[0] := UInt<2>(1)
    T_166034[1] := UInt<2>(2)
    T_166034[2] := UInt<2>(3)
    wire T_166035 : UInt<2>[2]
    T_166035[0] := UInt<2>(2)
    T_166035[1] := UInt<2>(3)
    wire T_166036 : UInt<2>[1]
    T_166036[0] := UInt<2>(3)
    wire T_166037 : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}
    T_166037 := T_166026
    when T_165982 : T_166037 := enq.bits
    deq.bits := T_166037
    node T_166038 = subw(T_165975, T_165976)
    node T_166039 = and(T_165977, T_165978)
    node T_166040 = cat(T_166039, T_166038)
    count := T_166040
  module FinishUnit : 
    input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output ready : UInt<1>
    
    wire T_166041 : UInt<3>[3]
    T_166041[0] := UInt<3>(0)
    T_166041[1] := UInt<3>(1)
    T_166041[2] := UInt<3>(2)
    wire T_166042 : UInt<2>[2]
    T_166042[0] := UInt<2>(0)
    T_166042[1] := UInt<2>(1)
    wire T_166043 : UInt<2>[3]
    T_166043[0] := UInt<2>(1)
    T_166043[1] := UInt<2>(2)
    T_166043[2] := UInt<2>(3)
    wire T_166044 : UInt<2>[2]
    T_166044[0] := UInt<2>(2)
    T_166044[1] := UInt<2>(3)
    wire T_166045 : UInt<2>[1]
    T_166045[0] := UInt<2>(3)
    wire T_166046 : UInt<3>[3]
    T_166046[0] := UInt<3>(0)
    T_166046[1] := UInt<3>(1)
    T_166046[2] := UInt<3>(2)
    wire T_166047 : UInt<2>[2]
    T_166047[0] := UInt<2>(0)
    T_166047[1] := UInt<2>(1)
    wire T_166048 : UInt<2>[3]
    T_166048[0] := UInt<2>(1)
    T_166048[1] := UInt<2>(2)
    T_166048[2] := UInt<2>(3)
    wire T_166049 : UInt<2>[2]
    T_166049[0] := UInt<2>(2)
    T_166049[1] := UInt<2>(3)
    wire T_166050 : UInt<2>[1]
    T_166050[0] := UInt<2>(3)
    wire T_166051 : UInt<3>[3]
    T_166051[0] := UInt<3>(0)
    T_166051[1] := UInt<3>(1)
    T_166051[2] := UInt<3>(2)
    wire T_166052 : UInt<2>[2]
    T_166052[0] := UInt<2>(0)
    T_166052[1] := UInt<2>(1)
    wire T_166053 : UInt<2>[3]
    T_166053[0] := UInt<2>(1)
    T_166053[1] := UInt<2>(2)
    T_166053[2] := UInt<2>(3)
    wire T_166054 : UInt<2>[2]
    T_166054[0] := UInt<2>(2)
    T_166054[1] := UInt<2>(3)
    wire T_166055 : UInt<2>[1]
    T_166055[0] := UInt<2>(3)
    wire T_166056 : UInt<3>[3]
    T_166056[0] := UInt<3>(0)
    T_166056[1] := UInt<3>(1)
    T_166056[2] := UInt<3>(2)
    wire T_166057 : UInt<2>[2]
    T_166057[0] := UInt<2>(0)
    T_166057[1] := UInt<2>(1)
    wire T_166058 : UInt<2>[3]
    T_166058[0] := UInt<2>(1)
    T_166058[1] := UInt<2>(2)
    T_166058[2] := UInt<2>(3)
    wire T_166059 : UInt<2>[2]
    T_166059[0] := UInt<2>(2)
    T_166059[1] := UInt<2>(3)
    wire T_166060 : UInt<2>[1]
    T_166060[0] := UInt<2>(3)
    wire T_166061 : UInt<3>[3]
    T_166061[0] := UInt<3>(0)
    T_166061[1] := UInt<3>(1)
    T_166061[2] := UInt<3>(2)
    wire T_166062 : UInt<2>[2]
    T_166062[0] := UInt<2>(0)
    T_166062[1] := UInt<2>(1)
    wire T_166063 : UInt<2>[3]
    T_166063[0] := UInt<2>(1)
    T_166063[1] := UInt<2>(2)
    T_166063[2] := UInt<2>(3)
    wire T_166064 : UInt<2>[2]
    T_166064[0] := UInt<2>(2)
    T_166064[1] := UInt<2>(3)
    wire T_166065 : UInt<2>[1]
    T_166065[0] := UInt<2>(3)
    wire T_166066 : UInt<3>[3]
    T_166066[0] := UInt<3>(0)
    T_166066[1] := UInt<3>(1)
    T_166066[2] := UInt<3>(2)
    wire T_166067 : UInt<2>[2]
    T_166067[0] := UInt<2>(0)
    T_166067[1] := UInt<2>(1)
    wire T_166068 : UInt<2>[3]
    T_166068[0] := UInt<2>(1)
    T_166068[1] := UInt<2>(2)
    T_166068[2] := UInt<2>(3)
    wire T_166069 : UInt<2>[2]
    T_166069[0] := UInt<2>(2)
    T_166069[1] := UInt<2>(3)
    wire T_166070 : UInt<2>[1]
    T_166070[0] := UInt<2>(3)
    wire T_166071 : UInt<3>[3]
    T_166071[0] := UInt<3>(0)
    T_166071[1] := UInt<3>(1)
    T_166071[2] := UInt<3>(2)
    wire T_166072 : UInt<2>[2]
    T_166072[0] := UInt<2>(0)
    T_166072[1] := UInt<2>(1)
    wire T_166073 : UInt<2>[3]
    T_166073[0] := UInt<2>(1)
    T_166073[1] := UInt<2>(2)
    T_166073[2] := UInt<2>(3)
    wire T_166074 : UInt<2>[2]
    T_166074[0] := UInt<2>(2)
    T_166074[1] := UInt<2>(3)
    wire T_166075 : UInt<2>[1]
    T_166075[0] := UInt<2>(3)
    wire T_166076 : UInt<3>[3]
    T_166076[0] := UInt<3>(0)
    T_166076[1] := UInt<3>(1)
    T_166076[2] := UInt<3>(2)
    wire T_166077 : UInt<2>[2]
    T_166077[0] := UInt<2>(0)
    T_166077[1] := UInt<2>(1)
    wire T_166078 : UInt<2>[3]
    T_166078[0] := UInt<2>(1)
    T_166078[1] := UInt<2>(2)
    T_166078[2] := UInt<2>(3)
    wire T_166079 : UInt<2>[2]
    T_166079[0] := UInt<2>(2)
    T_166079[1] := UInt<2>(3)
    wire T_166080 : UInt<2>[1]
    T_166080[0] := UInt<2>(3)
    wire T_166081 : UInt<3>[3]
    T_166081[0] := UInt<3>(0)
    T_166081[1] := UInt<3>(1)
    T_166081[2] := UInt<3>(2)
    wire T_166082 : UInt<2>[2]
    T_166082[0] := UInt<2>(0)
    T_166082[1] := UInt<2>(1)
    wire T_166083 : UInt<2>[3]
    T_166083[0] := UInt<2>(1)
    T_166083[1] := UInt<2>(2)
    T_166083[2] := UInt<2>(3)
    wire T_166084 : UInt<2>[2]
    T_166084[0] := UInt<2>(2)
    T_166084[1] := UInt<2>(3)
    wire T_166085 : UInt<2>[1]
    T_166085[0] := UInt<2>(3)
    node T_166086 = and(grant.ready, grant.valid)
    wire T_166087 : UInt<3>[1]
    T_166087[0] := UInt<3>(5)
    node T_166088 = eq(T_166087[0], grant.bits.payload.g_type)
    node T_166089 = or(UInt<1>(0), T_166088)
    node T_166090 = eq(T_166057[0], grant.bits.payload.g_type)
    node T_166091 = eq(T_166057[1], grant.bits.payload.g_type)
    node T_166092 = or(UInt<1>(0), T_166090)
    node T_166093 = or(T_166092, T_166091)
    wire T_166094 : UInt<1>
    T_166094 := T_166093
    when grant.bits.payload.is_builtin_type : T_166094 := T_166089
    node T_166095 = and(UInt<1>(1), T_166094)
    node T_166096 = and(T_166086, T_166095)
    reg T_166097 : UInt<2>
    onreset T_166097 := UInt<2>(0)
    when T_166096 : 
      node T_166098 = eq(T_166097, UInt<2>(3))
      node T_166099 = and(UInt<1>(0), T_166098)
      node T_166100 = addw(T_166097, UInt<1>(1))
      wire T_166101 : UInt<2>
      T_166101 := T_166100
      when T_166099 : T_166101 := UInt<1>(0)
      T_166097 := T_166101
    node T_166102 = and(T_166096, T_166098)
    wire T_166103 : UInt<1>
    T_166103 := UInt<1>(0)
    when T_166095 : T_166103 := T_166097
    wire T_166104 : UInt<1>
    T_166104 := T_166086
    when T_166095 : T_166104 := T_166102
    wire T_166105 : UInt<3>[3]
    T_166105[0] := UInt<3>(0)
    T_166105[1] := UInt<3>(1)
    T_166105[2] := UInt<3>(2)
    wire T_166106 : UInt<2>[2]
    T_166106[0] := UInt<2>(0)
    T_166106[1] := UInt<2>(1)
    wire T_166107 : UInt<2>[3]
    T_166107[0] := UInt<2>(1)
    T_166107[1] := UInt<2>(2)
    T_166107[2] := UInt<2>(3)
    wire T_166108 : UInt<2>[2]
    T_166108[0] := UInt<2>(2)
    T_166108[1] := UInt<2>(3)
    wire T_166109 : UInt<2>[1]
    T_166109[0] := UInt<2>(3)
    wire T_166110 : UInt<3>[3]
    T_166110[0] := UInt<3>(0)
    T_166110[1] := UInt<3>(1)
    T_166110[2] := UInt<3>(2)
    wire T_166111 : UInt<2>[2]
    T_166111[0] := UInt<2>(0)
    T_166111[1] := UInt<2>(1)
    wire T_166112 : UInt<2>[3]
    T_166112[0] := UInt<2>(1)
    T_166112[1] := UInt<2>(2)
    T_166112[2] := UInt<2>(3)
    wire T_166113 : UInt<2>[2]
    T_166113[0] := UInt<2>(2)
    T_166113[1] := UInt<2>(3)
    wire T_166114 : UInt<2>[1]
    T_166114[0] := UInt<2>(3)
    inst T_166115 of FinishQueue
    node T_166116 = and(grant.ready, grant.valid)
    node T_166117 = eq(UInt<1>(0), UInt<1>(0))
    node T_166118 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_166119 = and(grant.bits.payload.is_builtin_type, T_166118)
    node T_166120 = eq(T_166119, UInt<1>(0))
    node T_166121 = and(T_166117, T_166120)
    node T_166122 = and(T_166116, T_166121)
    wire T_166123 : UInt<3>[1]
    T_166123[0] := UInt<3>(5)
    node T_166124 = eq(T_166123[0], grant.bits.payload.g_type)
    node T_166125 = or(UInt<1>(0), T_166124)
    node T_166126 = eq(T_166057[0], grant.bits.payload.g_type)
    node T_166127 = eq(T_166057[1], grant.bits.payload.g_type)
    node T_166128 = or(UInt<1>(0), T_166126)
    node T_166129 = or(T_166128, T_166127)
    wire T_166130 : UInt<1>
    T_166130 := T_166129
    when grant.bits.payload.is_builtin_type : T_166130 := T_166125
    node T_166131 = and(UInt<1>(1), T_166130)
    node T_166132 = eq(T_166131, UInt<1>(0))
    node T_166133 = or(T_166132, T_166104)
    node T_166134 = and(T_166122, T_166133)
    T_166115.enq.valid := T_166134
    wire T_166135 : UInt<3>[3]
    T_166135[0] := UInt<3>(0)
    T_166135[1] := UInt<3>(1)
    T_166135[2] := UInt<3>(2)
    wire T_166136 : UInt<2>[2]
    T_166136[0] := UInt<2>(0)
    T_166136[1] := UInt<2>(1)
    wire T_166137 : UInt<2>[3]
    T_166137[0] := UInt<2>(1)
    T_166137[1] := UInt<2>(2)
    T_166137[2] := UInt<2>(3)
    wire T_166138 : UInt<2>[2]
    T_166138[0] := UInt<2>(2)
    T_166138[1] := UInt<2>(3)
    wire T_166139 : UInt<2>[1]
    T_166139[0] := UInt<2>(3)
    wire T_166140 : UInt<3>[3]
    T_166140[0] := UInt<3>(0)
    T_166140[1] := UInt<3>(1)
    T_166140[2] := UInt<3>(2)
    wire T_166141 : UInt<2>[2]
    T_166141[0] := UInt<2>(0)
    T_166141[1] := UInt<2>(1)
    wire T_166142 : UInt<2>[3]
    T_166142[0] := UInt<2>(1)
    T_166142[1] := UInt<2>(2)
    T_166142[2] := UInt<2>(3)
    wire T_166143 : UInt<2>[2]
    T_166143[0] := UInt<2>(2)
    T_166143[1] := UInt<2>(3)
    wire T_166144 : UInt<2>[1]
    T_166144[0] := UInt<2>(3)
    wire T_166145 : {manager_xact_id : UInt<2>}
    T_166145.manager_xact_id := grant.bits.payload.manager_xact_id
    T_166115.enq.bits.fin := T_166145
    T_166115.enq.bits.dst := grant.bits.header.src
    finish.bits.header.src := UInt<1>(0)
    finish.bits.header.dst := T_166115.deq.bits.dst
    finish.bits.payload := T_166115.deq.bits.fin
    finish.valid := T_166115.deq.valid
    T_166115.deq.ready := finish.ready
    refill.valid := grant.valid
    refill.bits := grant.bits.payload
    node T_166146 = eq(UInt<1>(0), UInt<1>(0))
    node T_166147 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_166148 = and(grant.bits.payload.is_builtin_type, T_166147)
    node T_166149 = eq(T_166148, UInt<1>(0))
    node T_166150 = and(T_166146, T_166149)
    node T_166151 = eq(T_166150, UInt<1>(0))
    node T_166152 = or(T_166115.enq.ready, T_166151)
    node T_166153 = and(T_166152, refill.ready)
    grant.ready := T_166153
    ready := T_166115.enq.ready
  module ClientTileLinkNetworkPort : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_166154 : UInt<3>[3]
    T_166154[0] := UInt<3>(0)
    T_166154[1] := UInt<3>(1)
    T_166154[2] := UInt<3>(2)
    wire T_166155 : UInt<2>[2]
    T_166155[0] := UInt<2>(0)
    T_166155[1] := UInt<2>(1)
    wire T_166156 : UInt<2>[3]
    T_166156[0] := UInt<2>(1)
    T_166156[1] := UInt<2>(2)
    T_166156[2] := UInt<2>(3)
    wire T_166157 : UInt<2>[2]
    T_166157[0] := UInt<2>(2)
    T_166157[1] := UInt<2>(3)
    wire T_166158 : UInt<2>[1]
    T_166158[0] := UInt<2>(3)
    wire T_166159 : UInt<3>[3]
    T_166159[0] := UInt<3>(0)
    T_166159[1] := UInt<3>(1)
    T_166159[2] := UInt<3>(2)
    wire T_166160 : UInt<2>[2]
    T_166160[0] := UInt<2>(0)
    T_166160[1] := UInt<2>(1)
    wire T_166161 : UInt<2>[3]
    T_166161[0] := UInt<2>(1)
    T_166161[1] := UInt<2>(2)
    T_166161[2] := UInt<2>(3)
    wire T_166162 : UInt<2>[2]
    T_166162[0] := UInt<2>(2)
    T_166162[1] := UInt<2>(3)
    wire T_166163 : UInt<2>[1]
    T_166163[0] := UInt<2>(3)
    wire T_166164 : UInt<3>[3]
    T_166164[0] := UInt<3>(0)
    T_166164[1] := UInt<3>(1)
    T_166164[2] := UInt<3>(2)
    wire T_166165 : UInt<2>[2]
    T_166165[0] := UInt<2>(0)
    T_166165[1] := UInt<2>(1)
    wire T_166166 : UInt<2>[3]
    T_166166[0] := UInt<2>(1)
    T_166166[1] := UInt<2>(2)
    T_166166[2] := UInt<2>(3)
    wire T_166167 : UInt<2>[2]
    T_166167[0] := UInt<2>(2)
    T_166167[1] := UInt<2>(3)
    wire T_166168 : UInt<2>[1]
    T_166168[0] := UInt<2>(3)
    wire T_166169 : UInt<3>[3]
    T_166169[0] := UInt<3>(0)
    T_166169[1] := UInt<3>(1)
    T_166169[2] := UInt<3>(2)
    wire T_166170 : UInt<2>[2]
    T_166170[0] := UInt<2>(0)
    T_166170[1] := UInt<2>(1)
    wire T_166171 : UInt<2>[3]
    T_166171[0] := UInt<2>(1)
    T_166171[1] := UInt<2>(2)
    T_166171[2] := UInt<2>(3)
    wire T_166172 : UInt<2>[2]
    T_166172[0] := UInt<2>(2)
    T_166172[1] := UInt<2>(3)
    wire T_166173 : UInt<2>[1]
    T_166173[0] := UInt<2>(3)
    wire T_166174 : UInt<3>[3]
    T_166174[0] := UInt<3>(0)
    T_166174[1] := UInt<3>(1)
    T_166174[2] := UInt<3>(2)
    wire T_166175 : UInt<2>[2]
    T_166175[0] := UInt<2>(0)
    T_166175[1] := UInt<2>(1)
    wire T_166176 : UInt<2>[3]
    T_166176[0] := UInt<2>(1)
    T_166176[1] := UInt<2>(2)
    T_166176[2] := UInt<2>(3)
    wire T_166177 : UInt<2>[2]
    T_166177[0] := UInt<2>(2)
    T_166177[1] := UInt<2>(3)
    wire T_166178 : UInt<2>[1]
    T_166178[0] := UInt<2>(3)
    wire T_166179 : UInt<3>[3]
    T_166179[0] := UInt<3>(0)
    T_166179[1] := UInt<3>(1)
    T_166179[2] := UInt<3>(2)
    wire T_166180 : UInt<2>[2]
    T_166180[0] := UInt<2>(0)
    T_166180[1] := UInt<2>(1)
    wire T_166181 : UInt<2>[3]
    T_166181[0] := UInt<2>(1)
    T_166181[1] := UInt<2>(2)
    T_166181[2] := UInt<2>(3)
    wire T_166182 : UInt<2>[2]
    T_166182[0] := UInt<2>(2)
    T_166182[1] := UInt<2>(3)
    wire T_166183 : UInt<2>[1]
    T_166183[0] := UInt<2>(3)
    wire T_166184 : UInt<3>[3]
    T_166184[0] := UInt<3>(0)
    T_166184[1] := UInt<3>(1)
    T_166184[2] := UInt<3>(2)
    wire T_166185 : UInt<2>[2]
    T_166185[0] := UInt<2>(0)
    T_166185[1] := UInt<2>(1)
    wire T_166186 : UInt<2>[3]
    T_166186[0] := UInt<2>(1)
    T_166186[1] := UInt<2>(2)
    T_166186[2] := UInt<2>(3)
    wire T_166187 : UInt<2>[2]
    T_166187[0] := UInt<2>(2)
    T_166187[1] := UInt<2>(3)
    wire T_166188 : UInt<2>[1]
    T_166188[0] := UInt<2>(3)
    wire T_166189 : UInt<3>[3]
    T_166189[0] := UInt<3>(0)
    T_166189[1] := UInt<3>(1)
    T_166189[2] := UInt<3>(2)
    wire T_166190 : UInt<2>[2]
    T_166190[0] := UInt<2>(0)
    T_166190[1] := UInt<2>(1)
    wire T_166191 : UInt<2>[3]
    T_166191[0] := UInt<2>(1)
    T_166191[1] := UInt<2>(2)
    T_166191[2] := UInt<2>(3)
    wire T_166192 : UInt<2>[2]
    T_166192[0] := UInt<2>(2)
    T_166192[1] := UInt<2>(3)
    wire T_166193 : UInt<2>[1]
    T_166193[0] := UInt<2>(3)
    wire T_166194 : UInt<3>[3]
    T_166194[0] := UInt<3>(0)
    T_166194[1] := UInt<3>(1)
    T_166194[2] := UInt<3>(2)
    wire T_166195 : UInt<2>[2]
    T_166195[0] := UInt<2>(0)
    T_166195[1] := UInt<2>(1)
    wire T_166196 : UInt<2>[3]
    T_166196[0] := UInt<2>(1)
    T_166196[1] := UInt<2>(2)
    T_166196[2] := UInt<2>(3)
    wire T_166197 : UInt<2>[2]
    T_166197[0] := UInt<2>(2)
    T_166197[1] := UInt<2>(3)
    wire T_166198 : UInt<2>[1]
    T_166198[0] := UInt<2>(3)
    wire T_166199 : UInt<3>[3]
    T_166199[0] := UInt<3>(0)
    T_166199[1] := UInt<3>(1)
    T_166199[2] := UInt<3>(2)
    wire T_166200 : UInt<2>[2]
    T_166200[0] := UInt<2>(0)
    T_166200[1] := UInt<2>(1)
    wire T_166201 : UInt<2>[3]
    T_166201[0] := UInt<2>(1)
    T_166201[1] := UInt<2>(2)
    T_166201[2] := UInt<2>(3)
    wire T_166202 : UInt<2>[2]
    T_166202[0] := UInt<2>(2)
    T_166202[1] := UInt<2>(3)
    wire T_166203 : UInt<2>[1]
    T_166203[0] := UInt<2>(3)
    wire T_166204 : UInt<3>[3]
    T_166204[0] := UInt<3>(0)
    T_166204[1] := UInt<3>(1)
    T_166204[2] := UInt<3>(2)
    wire T_166205 : UInt<2>[2]
    T_166205[0] := UInt<2>(0)
    T_166205[1] := UInt<2>(1)
    wire T_166206 : UInt<2>[3]
    T_166206[0] := UInt<2>(1)
    T_166206[1] := UInt<2>(2)
    T_166206[2] := UInt<2>(3)
    wire T_166207 : UInt<2>[2]
    T_166207[0] := UInt<2>(2)
    T_166207[1] := UInt<2>(3)
    wire T_166208 : UInt<2>[1]
    T_166208[0] := UInt<2>(3)
    wire T_166209 : UInt<3>[3]
    T_166209[0] := UInt<3>(0)
    T_166209[1] := UInt<3>(1)
    T_166209[2] := UInt<3>(2)
    wire T_166210 : UInt<2>[2]
    T_166210[0] := UInt<2>(0)
    T_166210[1] := UInt<2>(1)
    wire T_166211 : UInt<2>[3]
    T_166211[0] := UInt<2>(1)
    T_166211[1] := UInt<2>(2)
    T_166211[2] := UInt<2>(3)
    wire T_166212 : UInt<2>[2]
    T_166212[0] := UInt<2>(2)
    T_166212[1] := UInt<2>(3)
    wire T_166213 : UInt<2>[1]
    T_166213[0] := UInt<2>(3)
    wire T_166214 : UInt<3>[3]
    T_166214[0] := UInt<3>(0)
    T_166214[1] := UInt<3>(1)
    T_166214[2] := UInt<3>(2)
    wire T_166215 : UInt<2>[2]
    T_166215[0] := UInt<2>(0)
    T_166215[1] := UInt<2>(1)
    wire T_166216 : UInt<2>[3]
    T_166216[0] := UInt<2>(1)
    T_166216[1] := UInt<2>(2)
    T_166216[2] := UInt<2>(3)
    wire T_166217 : UInt<2>[2]
    T_166217[0] := UInt<2>(2)
    T_166217[1] := UInt<2>(3)
    wire T_166218 : UInt<2>[1]
    T_166218[0] := UInt<2>(3)
    wire T_166219 : UInt<3>[3]
    T_166219[0] := UInt<3>(0)
    T_166219[1] := UInt<3>(1)
    T_166219[2] := UInt<3>(2)
    wire T_166220 : UInt<2>[2]
    T_166220[0] := UInt<2>(0)
    T_166220[1] := UInt<2>(1)
    wire T_166221 : UInt<2>[3]
    T_166221[0] := UInt<2>(1)
    T_166221[1] := UInt<2>(2)
    T_166221[2] := UInt<2>(3)
    wire T_166222 : UInt<2>[2]
    T_166222[0] := UInt<2>(2)
    T_166222[1] := UInt<2>(3)
    wire T_166223 : UInt<2>[1]
    T_166223[0] := UInt<2>(3)
    wire T_166224 : UInt<3>[3]
    T_166224[0] := UInt<3>(0)
    T_166224[1] := UInt<3>(1)
    T_166224[2] := UInt<3>(2)
    wire T_166225 : UInt<2>[2]
    T_166225[0] := UInt<2>(0)
    T_166225[1] := UInt<2>(1)
    wire T_166226 : UInt<2>[3]
    T_166226[0] := UInt<2>(1)
    T_166226[1] := UInt<2>(2)
    T_166226[2] := UInt<2>(3)
    wire T_166227 : UInt<2>[2]
    T_166227[0] := UInt<2>(2)
    T_166227[1] := UInt<2>(3)
    wire T_166228 : UInt<2>[1]
    T_166228[0] := UInt<2>(3)
    wire T_166229 : UInt<3>[3]
    T_166229[0] := UInt<3>(0)
    T_166229[1] := UInt<3>(1)
    T_166229[2] := UInt<3>(2)
    wire T_166230 : UInt<2>[2]
    T_166230[0] := UInt<2>(0)
    T_166230[1] := UInt<2>(1)
    wire T_166231 : UInt<2>[3]
    T_166231[0] := UInt<2>(1)
    T_166231[1] := UInt<2>(2)
    T_166231[2] := UInt<2>(3)
    wire T_166232 : UInt<2>[2]
    T_166232[0] := UInt<2>(2)
    T_166232[1] := UInt<2>(3)
    wire T_166233 : UInt<2>[1]
    T_166233[0] := UInt<2>(3)
    wire T_166234 : UInt<3>[3]
    T_166234[0] := UInt<3>(0)
    T_166234[1] := UInt<3>(1)
    T_166234[2] := UInt<3>(2)
    wire T_166235 : UInt<2>[2]
    T_166235[0] := UInt<2>(0)
    T_166235[1] := UInt<2>(1)
    wire T_166236 : UInt<2>[3]
    T_166236[0] := UInt<2>(1)
    T_166236[1] := UInt<2>(2)
    T_166236[2] := UInt<2>(3)
    wire T_166237 : UInt<2>[2]
    T_166237[0] := UInt<2>(2)
    T_166237[1] := UInt<2>(3)
    wire T_166238 : UInt<2>[1]
    T_166238[0] := UInt<2>(3)
    wire T_166239 : UInt<3>[3]
    T_166239[0] := UInt<3>(0)
    T_166239[1] := UInt<3>(1)
    T_166239[2] := UInt<3>(2)
    wire T_166240 : UInt<2>[2]
    T_166240[0] := UInt<2>(0)
    T_166240[1] := UInt<2>(1)
    wire T_166241 : UInt<2>[3]
    T_166241[0] := UInt<2>(1)
    T_166241[1] := UInt<2>(2)
    T_166241[2] := UInt<2>(3)
    wire T_166242 : UInt<2>[2]
    T_166242[0] := UInt<2>(2)
    T_166242[1] := UInt<2>(3)
    wire T_166243 : UInt<2>[1]
    T_166243[0] := UInt<2>(3)
    wire T_166244 : UInt<3>[3]
    T_166244[0] := UInt<3>(0)
    T_166244[1] := UInt<3>(1)
    T_166244[2] := UInt<3>(2)
    wire T_166245 : UInt<2>[2]
    T_166245[0] := UInt<2>(0)
    T_166245[1] := UInt<2>(1)
    wire T_166246 : UInt<2>[3]
    T_166246[0] := UInt<2>(1)
    T_166246[1] := UInt<2>(2)
    T_166246[2] := UInt<2>(3)
    wire T_166247 : UInt<2>[2]
    T_166247[0] := UInt<2>(2)
    T_166247[1] := UInt<2>(3)
    wire T_166248 : UInt<2>[1]
    T_166248[0] := UInt<2>(3)
    wire T_166249 : UInt<3>[3]
    T_166249[0] := UInt<3>(0)
    T_166249[1] := UInt<3>(1)
    T_166249[2] := UInt<3>(2)
    wire T_166250 : UInt<2>[2]
    T_166250[0] := UInt<2>(0)
    T_166250[1] := UInt<2>(1)
    wire T_166251 : UInt<2>[3]
    T_166251[0] := UInt<2>(1)
    T_166251[1] := UInt<2>(2)
    T_166251[2] := UInt<2>(3)
    wire T_166252 : UInt<2>[2]
    T_166252[0] := UInt<2>(2)
    T_166252[1] := UInt<2>(3)
    wire T_166253 : UInt<2>[1]
    T_166253[0] := UInt<2>(3)
    wire T_166254 : UInt<3>[3]
    T_166254[0] := UInt<3>(0)
    T_166254[1] := UInt<3>(1)
    T_166254[2] := UInt<3>(2)
    wire T_166255 : UInt<2>[2]
    T_166255[0] := UInt<2>(0)
    T_166255[1] := UInt<2>(1)
    wire T_166256 : UInt<2>[3]
    T_166256[0] := UInt<2>(1)
    T_166256[1] := UInt<2>(2)
    T_166256[2] := UInt<2>(3)
    wire T_166257 : UInt<2>[2]
    T_166257[0] := UInt<2>(2)
    T_166257[1] := UInt<2>(3)
    wire T_166258 : UInt<2>[1]
    T_166258[0] := UInt<2>(3)
    wire T_166259 : UInt<3>[3]
    T_166259[0] := UInt<3>(0)
    T_166259[1] := UInt<3>(1)
    T_166259[2] := UInt<3>(2)
    wire T_166260 : UInt<2>[2]
    T_166260[0] := UInt<2>(0)
    T_166260[1] := UInt<2>(1)
    wire T_166261 : UInt<2>[3]
    T_166261[0] := UInt<2>(1)
    T_166261[1] := UInt<2>(2)
    T_166261[2] := UInt<2>(3)
    wire T_166262 : UInt<2>[2]
    T_166262[0] := UInt<2>(2)
    T_166262[1] := UInt<2>(3)
    wire T_166263 : UInt<2>[1]
    T_166263[0] := UInt<2>(3)
    wire T_166264 : UInt<3>[3]
    T_166264[0] := UInt<3>(0)
    T_166264[1] := UInt<3>(1)
    T_166264[2] := UInt<3>(2)
    wire T_166265 : UInt<2>[2]
    T_166265[0] := UInt<2>(0)
    T_166265[1] := UInt<2>(1)
    wire T_166266 : UInt<2>[3]
    T_166266[0] := UInt<2>(1)
    T_166266[1] := UInt<2>(2)
    T_166266[2] := UInt<2>(3)
    wire T_166267 : UInt<2>[2]
    T_166267[0] := UInt<2>(2)
    T_166267[1] := UInt<2>(3)
    wire T_166268 : UInt<2>[1]
    T_166268[0] := UInt<2>(3)
    wire T_166269 : UInt<3>[3]
    T_166269[0] := UInt<3>(0)
    T_166269[1] := UInt<3>(1)
    T_166269[2] := UInt<3>(2)
    wire T_166270 : UInt<2>[2]
    T_166270[0] := UInt<2>(0)
    T_166270[1] := UInt<2>(1)
    wire T_166271 : UInt<2>[3]
    T_166271[0] := UInt<2>(1)
    T_166271[1] := UInt<2>(2)
    T_166271[2] := UInt<2>(3)
    wire T_166272 : UInt<2>[2]
    T_166272[0] := UInt<2>(2)
    T_166272[1] := UInt<2>(3)
    wire T_166273 : UInt<2>[1]
    T_166273[0] := UInt<2>(3)
    wire T_166274 : UInt<3>[3]
    T_166274[0] := UInt<3>(0)
    T_166274[1] := UInt<3>(1)
    T_166274[2] := UInt<3>(2)
    wire T_166275 : UInt<2>[2]
    T_166275[0] := UInt<2>(0)
    T_166275[1] := UInt<2>(1)
    wire T_166276 : UInt<2>[3]
    T_166276[0] := UInt<2>(1)
    T_166276[1] := UInt<2>(2)
    T_166276[2] := UInt<2>(3)
    wire T_166277 : UInt<2>[2]
    T_166277[0] := UInt<2>(2)
    T_166277[1] := UInt<2>(3)
    wire T_166278 : UInt<2>[1]
    T_166278[0] := UInt<2>(3)
    wire T_166279 : UInt<3>[3]
    T_166279[0] := UInt<3>(0)
    T_166279[1] := UInt<3>(1)
    T_166279[2] := UInt<3>(2)
    wire T_166280 : UInt<2>[2]
    T_166280[0] := UInt<2>(0)
    T_166280[1] := UInt<2>(1)
    wire T_166281 : UInt<2>[3]
    T_166281[0] := UInt<2>(1)
    T_166281[1] := UInt<2>(2)
    T_166281[2] := UInt<2>(3)
    wire T_166282 : UInt<2>[2]
    T_166282[0] := UInt<2>(2)
    T_166282[1] := UInt<2>(3)
    wire T_166283 : UInt<2>[1]
    T_166283[0] := UInt<2>(3)
    inst finisher of FinishUnit
    finisher.grant <> network.grant
    network.finish <> finisher.finish
    wire T_166284 : UInt<3>[3]
    T_166284[0] := UInt<3>(0)
    T_166284[1] := UInt<3>(1)
    T_166284[2] := UInt<3>(2)
    wire T_166285 : UInt<2>[2]
    T_166285[0] := UInt<2>(0)
    T_166285[1] := UInt<2>(1)
    wire T_166286 : UInt<2>[3]
    T_166286[0] := UInt<2>(1)
    T_166286[1] := UInt<2>(2)
    T_166286[2] := UInt<2>(3)
    wire T_166287 : UInt<2>[2]
    T_166287[0] := UInt<2>(2)
    T_166287[1] := UInt<2>(3)
    wire T_166288 : UInt<2>[1]
    T_166288[0] := UInt<2>(3)
    wire T_166289 : UInt<3>[3]
    T_166289[0] := UInt<3>(0)
    T_166289[1] := UInt<3>(1)
    T_166289[2] := UInt<3>(2)
    wire T_166290 : UInt<2>[2]
    T_166290[0] := UInt<2>(0)
    T_166290[1] := UInt<2>(1)
    wire T_166291 : UInt<2>[3]
    T_166291[0] := UInt<2>(1)
    T_166291[1] := UInt<2>(2)
    T_166291[2] := UInt<2>(3)
    wire T_166292 : UInt<2>[2]
    T_166292[0] := UInt<2>(2)
    T_166292[1] := UInt<2>(3)
    wire T_166293 : UInt<2>[1]
    T_166293[0] := UInt<2>(3)
    wire T_166294 : UInt<3>[3]
    T_166294[0] := UInt<3>(0)
    T_166294[1] := UInt<3>(1)
    T_166294[2] := UInt<3>(2)
    wire T_166295 : UInt<2>[2]
    T_166295[0] := UInt<2>(0)
    T_166295[1] := UInt<2>(1)
    wire T_166296 : UInt<2>[3]
    T_166296[0] := UInt<2>(1)
    T_166296[1] := UInt<2>(2)
    T_166296[2] := UInt<2>(3)
    wire T_166297 : UInt<2>[2]
    T_166297[0] := UInt<2>(2)
    T_166297[1] := UInt<2>(3)
    wire T_166298 : UInt<2>[1]
    T_166298[0] := UInt<2>(3)
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    acq_with_header.bits.payload := client.acquire.bits
    acq_with_header.bits.header.src := UInt<1>(0)
    acq_with_header.bits.header.dst := UInt<1>(0)
    acq_with_header.valid := client.acquire.valid
    client.acquire.ready := acq_with_header.ready
    wire T_166299 : UInt<3>[3]
    T_166299[0] := UInt<3>(0)
    T_166299[1] := UInt<3>(1)
    T_166299[2] := UInt<3>(2)
    wire T_166300 : UInt<2>[2]
    T_166300[0] := UInt<2>(0)
    T_166300[1] := UInt<2>(1)
    wire T_166301 : UInt<2>[3]
    T_166301[0] := UInt<2>(1)
    T_166301[1] := UInt<2>(2)
    T_166301[2] := UInt<2>(3)
    wire T_166302 : UInt<2>[2]
    T_166302[0] := UInt<2>(2)
    T_166302[1] := UInt<2>(3)
    wire T_166303 : UInt<2>[1]
    T_166303[0] := UInt<2>(3)
    wire T_166304 : UInt<3>[3]
    T_166304[0] := UInt<3>(0)
    T_166304[1] := UInt<3>(1)
    T_166304[2] := UInt<3>(2)
    wire T_166305 : UInt<2>[2]
    T_166305[0] := UInt<2>(0)
    T_166305[1] := UInt<2>(1)
    wire T_166306 : UInt<2>[3]
    T_166306[0] := UInt<2>(1)
    T_166306[1] := UInt<2>(2)
    T_166306[2] := UInt<2>(3)
    wire T_166307 : UInt<2>[2]
    T_166307[0] := UInt<2>(2)
    T_166307[1] := UInt<2>(3)
    wire T_166308 : UInt<2>[1]
    T_166308[0] := UInt<2>(3)
    wire T_166309 : UInt<3>[3]
    T_166309[0] := UInt<3>(0)
    T_166309[1] := UInt<3>(1)
    T_166309[2] := UInt<3>(2)
    wire T_166310 : UInt<2>[2]
    T_166310[0] := UInt<2>(0)
    T_166310[1] := UInt<2>(1)
    wire T_166311 : UInt<2>[3]
    T_166311[0] := UInt<2>(1)
    T_166311[1] := UInt<2>(2)
    T_166311[2] := UInt<2>(3)
    wire T_166312 : UInt<2>[2]
    T_166312[0] := UInt<2>(2)
    T_166312[1] := UInt<2>(3)
    wire T_166313 : UInt<2>[1]
    T_166313[0] := UInt<2>(3)
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    rel_with_header.bits.payload := client.release.bits
    rel_with_header.bits.header.src := UInt<1>(0)
    rel_with_header.bits.header.dst := UInt<1>(0)
    rel_with_header.valid := client.release.valid
    client.release.ready := rel_with_header.ready
    wire T_166314 : UInt<3>[3]
    T_166314[0] := UInt<3>(0)
    T_166314[1] := UInt<3>(1)
    T_166314[2] := UInt<3>(2)
    wire T_166315 : UInt<2>[2]
    T_166315[0] := UInt<2>(0)
    T_166315[1] := UInt<2>(1)
    wire T_166316 : UInt<2>[3]
    T_166316[0] := UInt<2>(1)
    T_166316[1] := UInt<2>(2)
    T_166316[2] := UInt<2>(3)
    wire T_166317 : UInt<2>[2]
    T_166317[0] := UInt<2>(2)
    T_166317[1] := UInt<2>(3)
    wire T_166318 : UInt<2>[1]
    T_166318[0] := UInt<2>(3)
    wire T_166319 : UInt<3>[3]
    T_166319[0] := UInt<3>(0)
    T_166319[1] := UInt<3>(1)
    T_166319[2] := UInt<3>(2)
    wire T_166320 : UInt<2>[2]
    T_166320[0] := UInt<2>(0)
    T_166320[1] := UInt<2>(1)
    wire T_166321 : UInt<2>[3]
    T_166321[0] := UInt<2>(1)
    T_166321[1] := UInt<2>(2)
    T_166321[2] := UInt<2>(3)
    wire T_166322 : UInt<2>[2]
    T_166322[0] := UInt<2>(2)
    T_166322[1] := UInt<2>(3)
    wire T_166323 : UInt<2>[1]
    T_166323[0] := UInt<2>(3)
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header.valid := network.probe.valid
    prb_without_header.bits := network.probe.bits.payload
    network.probe.ready := prb_without_header.ready
    network.acquire.bits := acq_with_header.bits
    node T_166324 = and(acq_with_header.valid, finisher.ready)
    network.acquire.valid := T_166324
    node T_166325 = and(network.acquire.ready, finisher.ready)
    acq_with_header.ready := T_166325
    network.release <> rel_with_header
    client.probe <> prb_without_header
    client.grant <> finisher.refill
  module Queue : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output count : UInt<2>
    
    wire T_166326 : UInt<3>[3]
    T_166326[0] := UInt<3>(0)
    T_166326[1] := UInt<3>(1)
    T_166326[2] := UInt<3>(2)
    wire T_166327 : UInt<2>[2]
    T_166327[0] := UInt<2>(0)
    T_166327[1] := UInt<2>(1)
    wire T_166328 : UInt<2>[3]
    T_166328[0] := UInt<2>(1)
    T_166328[1] := UInt<2>(2)
    T_166328[2] := UInt<2>(3)
    wire T_166329 : UInt<2>[2]
    T_166329[0] := UInt<2>(2)
    T_166329[1] := UInt<2>(3)
    wire T_166330 : UInt<2>[1]
    T_166330[0] := UInt<2>(3)
    wire T_166331 : UInt<3>[3]
    T_166331[0] := UInt<3>(0)
    T_166331[1] := UInt<3>(1)
    T_166331[2] := UInt<3>(2)
    wire T_166332 : UInt<2>[2]
    T_166332[0] := UInt<2>(0)
    T_166332[1] := UInt<2>(1)
    wire T_166333 : UInt<2>[3]
    T_166333[0] := UInt<2>(1)
    T_166333[1] := UInt<2>(2)
    T_166333[2] := UInt<2>(3)
    wire T_166334 : UInt<2>[2]
    T_166334[0] := UInt<2>(2)
    T_166334[1] := UInt<2>(3)
    wire T_166335 : UInt<2>[1]
    T_166335[0] := UInt<2>(3)
    wire T_166336 : UInt<3>[3]
    T_166336[0] := UInt<3>(0)
    T_166336[1] := UInt<3>(1)
    T_166336[2] := UInt<3>(2)
    wire T_166337 : UInt<2>[2]
    T_166337[0] := UInt<2>(0)
    T_166337[1] := UInt<2>(1)
    wire T_166338 : UInt<2>[3]
    T_166338[0] := UInt<2>(1)
    T_166338[1] := UInt<2>(2)
    T_166338[2] := UInt<2>(3)
    wire T_166339 : UInt<2>[2]
    T_166339[0] := UInt<2>(2)
    T_166339[1] := UInt<2>(3)
    wire T_166340 : UInt<2>[1]
    T_166340[0] := UInt<2>(3)
    wire T_166341 : UInt<3>[3]
    T_166341[0] := UInt<3>(0)
    T_166341[1] := UInt<3>(1)
    T_166341[2] := UInt<3>(2)
    wire T_166342 : UInt<2>[2]
    T_166342[0] := UInt<2>(0)
    T_166342[1] := UInt<2>(1)
    wire T_166343 : UInt<2>[3]
    T_166343[0] := UInt<2>(1)
    T_166343[1] := UInt<2>(2)
    T_166343[2] := UInt<2>(3)
    wire T_166344 : UInt<2>[2]
    T_166344[0] := UInt<2>(2)
    T_166344[1] := UInt<2>(3)
    wire T_166345 : UInt<2>[1]
    T_166345[0] := UInt<2>(3)
    wire T_166346 : UInt<3>[3]
    T_166346[0] := UInt<3>(0)
    T_166346[1] := UInt<3>(1)
    T_166346[2] := UInt<3>(2)
    wire T_166347 : UInt<2>[2]
    T_166347[0] := UInt<2>(0)
    T_166347[1] := UInt<2>(1)
    wire T_166348 : UInt<2>[3]
    T_166348[0] := UInt<2>(1)
    T_166348[1] := UInt<2>(2)
    T_166348[2] := UInt<2>(3)
    wire T_166349 : UInt<2>[2]
    T_166349[0] := UInt<2>(2)
    T_166349[1] := UInt<2>(3)
    wire T_166350 : UInt<2>[1]
    T_166350[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2]
    reg T_166351 : UInt<1>
    onreset T_166351 := UInt<1>(0)
    reg T_166352 : UInt<1>
    onreset T_166352 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_166351, T_166352)
    node T_166353 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_166353)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_166354 = and(enq.ready, enq.valid)
    node T_166355 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_166354, T_166355)
    node T_166356 = and(deq.ready, deq.valid)
    node T_166357 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_166356, T_166357)
    when do_enq : 
      wire T_166358 : UInt<3>[3]
      T_166358[0] := UInt<3>(0)
      T_166358[1] := UInt<3>(1)
      T_166358[2] := UInt<3>(2)
      wire T_166359 : UInt<2>[2]
      T_166359[0] := UInt<2>(0)
      T_166359[1] := UInt<2>(1)
      wire T_166360 : UInt<2>[3]
      T_166360[0] := UInt<2>(1)
      T_166360[1] := UInt<2>(2)
      T_166360[2] := UInt<2>(3)
      wire T_166361 : UInt<2>[2]
      T_166361[0] := UInt<2>(2)
      T_166361[1] := UInt<2>(3)
      wire T_166362 : UInt<2>[1]
      T_166362[0] := UInt<2>(3)
      accessor T_166363 = ram[T_166351]
      T_166363 := enq.bits
      node T_166364 = eq(T_166351, UInt<1>(1))
      node T_166365 = and(UInt<1>(0), T_166364)
      node T_166366 = addw(T_166351, UInt<1>(1))
      wire T_166367 : UInt<1>
      T_166367 := T_166366
      when T_166365 : T_166367 := UInt<1>(0)
      T_166351 := T_166367
    when do_deq : 
      node T_166368 = eq(T_166352, UInt<1>(1))
      node T_166369 = and(UInt<1>(0), T_166368)
      node T_166370 = addw(T_166352, UInt<1>(1))
      wire T_166371 : UInt<1>
      T_166371 := T_166370
      when T_166369 : T_166371 := UInt<1>(0)
      T_166352 := T_166371
    
    node T_166372 = neq(do_enq, do_deq)
    when T_166372 : maybe_full := do_enq
    node T_166373 = eq(empty, UInt<1>(0))
    node T_166374 = and(UInt<1>(0), enq.valid)
    node T_166375 = or(T_166373, T_166374)
    deq.valid := T_166375
    node T_166376 = eq(full, UInt<1>(0))
    node T_166377 = and(UInt<1>(0), deq.ready)
    node T_166378 = or(T_166376, T_166377)
    enq.ready := T_166378
    wire T_166379 : UInt<3>[3]
    T_166379[0] := UInt<3>(0)
    T_166379[1] := UInt<3>(1)
    T_166379[2] := UInt<3>(2)
    wire T_166380 : UInt<2>[2]
    T_166380[0] := UInt<2>(0)
    T_166380[1] := UInt<2>(1)
    wire T_166381 : UInt<2>[3]
    T_166381[0] := UInt<2>(1)
    T_166381[1] := UInt<2>(2)
    T_166381[2] := UInt<2>(3)
    wire T_166382 : UInt<2>[2]
    T_166382[0] := UInt<2>(2)
    T_166382[1] := UInt<2>(3)
    wire T_166383 : UInt<2>[1]
    T_166383[0] := UInt<2>(3)
    accessor T_166384 = ram[T_166352]
    wire T_166385 : UInt<3>[3]
    T_166385[0] := UInt<3>(0)
    T_166385[1] := UInt<3>(1)
    T_166385[2] := UInt<3>(2)
    wire T_166386 : UInt<2>[2]
    T_166386[0] := UInt<2>(0)
    T_166386[1] := UInt<2>(1)
    wire T_166387 : UInt<2>[3]
    T_166387[0] := UInt<2>(1)
    T_166387[1] := UInt<2>(2)
    T_166387[2] := UInt<2>(3)
    wire T_166388 : UInt<2>[2]
    T_166388[0] := UInt<2>(2)
    T_166388[1] := UInt<2>(3)
    wire T_166389 : UInt<2>[1]
    T_166389[0] := UInt<2>(3)
    wire T_166390 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    T_166390 := T_166384
    when maybe_flow : T_166390 := enq.bits
    deq.bits := T_166390
    node ptr_diff = subw(T_166351, T_166352)
    node T_166391 = and(maybe_full, ptr_match)
    node T_166392 = cat(T_166391, ptr_diff)
    count := T_166392
  module Queue_20089 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}
    output count : UInt<2>
    
    wire T_166393 : UInt<3>[3]
    T_166393[0] := UInt<3>(0)
    T_166393[1] := UInt<3>(1)
    T_166393[2] := UInt<3>(2)
    wire T_166394 : UInt<2>[2]
    T_166394[0] := UInt<2>(0)
    T_166394[1] := UInt<2>(1)
    wire T_166395 : UInt<2>[3]
    T_166395[0] := UInt<2>(1)
    T_166395[1] := UInt<2>(2)
    T_166395[2] := UInt<2>(3)
    wire T_166396 : UInt<2>[2]
    T_166396[0] := UInt<2>(2)
    T_166396[1] := UInt<2>(3)
    wire T_166397 : UInt<2>[1]
    T_166397[0] := UInt<2>(3)
    wire T_166398 : UInt<3>[3]
    T_166398[0] := UInt<3>(0)
    T_166398[1] := UInt<3>(1)
    T_166398[2] := UInt<3>(2)
    wire T_166399 : UInt<2>[2]
    T_166399[0] := UInt<2>(0)
    T_166399[1] := UInt<2>(1)
    wire T_166400 : UInt<2>[3]
    T_166400[0] := UInt<2>(1)
    T_166400[1] := UInt<2>(2)
    T_166400[2] := UInt<2>(3)
    wire T_166401 : UInt<2>[2]
    T_166401[0] := UInt<2>(2)
    T_166401[1] := UInt<2>(3)
    wire T_166402 : UInt<2>[1]
    T_166402[0] := UInt<2>(3)
    wire T_166403 : UInt<3>[3]
    T_166403[0] := UInt<3>(0)
    T_166403[1] := UInt<3>(1)
    T_166403[2] := UInt<3>(2)
    wire T_166404 : UInt<2>[2]
    T_166404[0] := UInt<2>(0)
    T_166404[1] := UInt<2>(1)
    wire T_166405 : UInt<2>[3]
    T_166405[0] := UInt<2>(1)
    T_166405[1] := UInt<2>(2)
    T_166405[2] := UInt<2>(3)
    wire T_166406 : UInt<2>[2]
    T_166406[0] := UInt<2>(2)
    T_166406[1] := UInt<2>(3)
    wire T_166407 : UInt<2>[1]
    T_166407[0] := UInt<2>(3)
    wire T_166408 : UInt<3>[3]
    T_166408[0] := UInt<3>(0)
    T_166408[1] := UInt<3>(1)
    T_166408[2] := UInt<3>(2)
    wire T_166409 : UInt<2>[2]
    T_166409[0] := UInt<2>(0)
    T_166409[1] := UInt<2>(1)
    wire T_166410 : UInt<2>[3]
    T_166410[0] := UInt<2>(1)
    T_166410[1] := UInt<2>(2)
    T_166410[2] := UInt<2>(3)
    wire T_166411 : UInt<2>[2]
    T_166411[0] := UInt<2>(2)
    T_166411[1] := UInt<2>(3)
    wire T_166412 : UInt<2>[1]
    T_166412[0] := UInt<2>(3)
    wire T_166413 : UInt<3>[3]
    T_166413[0] := UInt<3>(0)
    T_166413[1] := UInt<3>(1)
    T_166413[2] := UInt<3>(2)
    wire T_166414 : UInt<2>[2]
    T_166414[0] := UInt<2>(0)
    T_166414[1] := UInt<2>(1)
    wire T_166415 : UInt<2>[3]
    T_166415[0] := UInt<2>(1)
    T_166415[1] := UInt<2>(2)
    T_166415[2] := UInt<2>(3)
    wire T_166416 : UInt<2>[2]
    T_166416[0] := UInt<2>(2)
    T_166416[1] := UInt<2>(3)
    wire T_166417 : UInt<2>[1]
    T_166417[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2]
    reg T_166418 : UInt<1>
    onreset T_166418 := UInt<1>(0)
    reg T_166419 : UInt<1>
    onreset T_166419 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_166418, T_166419)
    node T_166420 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_166420)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_166421 = and(enq.ready, enq.valid)
    node T_166422 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_166421, T_166422)
    node T_166423 = and(deq.ready, deq.valid)
    node T_166424 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_166423, T_166424)
    when do_enq : 
      wire T_166425 : UInt<3>[3]
      T_166425[0] := UInt<3>(0)
      T_166425[1] := UInt<3>(1)
      T_166425[2] := UInt<3>(2)
      wire T_166426 : UInt<2>[2]
      T_166426[0] := UInt<2>(0)
      T_166426[1] := UInt<2>(1)
      wire T_166427 : UInt<2>[3]
      T_166427[0] := UInt<2>(1)
      T_166427[1] := UInt<2>(2)
      T_166427[2] := UInt<2>(3)
      wire T_166428 : UInt<2>[2]
      T_166428[0] := UInt<2>(2)
      T_166428[1] := UInt<2>(3)
      wire T_166429 : UInt<2>[1]
      T_166429[0] := UInt<2>(3)
      accessor T_166430 = ram[T_166418]
      T_166430 := enq.bits
      node T_166431 = eq(T_166418, UInt<1>(1))
      node T_166432 = and(UInt<1>(0), T_166431)
      node T_166433 = addw(T_166418, UInt<1>(1))
      wire T_166434 : UInt<1>
      T_166434 := T_166433
      when T_166432 : T_166434 := UInt<1>(0)
      T_166418 := T_166434
    when do_deq : 
      node T_166435 = eq(T_166419, UInt<1>(1))
      node T_166436 = and(UInt<1>(0), T_166435)
      node T_166437 = addw(T_166419, UInt<1>(1))
      wire T_166438 : UInt<1>
      T_166438 := T_166437
      when T_166436 : T_166438 := UInt<1>(0)
      T_166419 := T_166438
    
    node T_166439 = neq(do_enq, do_deq)
    when T_166439 : maybe_full := do_enq
    node T_166440 = eq(empty, UInt<1>(0))
    node T_166441 = and(UInt<1>(0), enq.valid)
    node T_166442 = or(T_166440, T_166441)
    deq.valid := T_166442
    node T_166443 = eq(full, UInt<1>(0))
    node T_166444 = and(UInt<1>(0), deq.ready)
    node T_166445 = or(T_166443, T_166444)
    enq.ready := T_166445
    wire T_166446 : UInt<3>[3]
    T_166446[0] := UInt<3>(0)
    T_166446[1] := UInt<3>(1)
    T_166446[2] := UInt<3>(2)
    wire T_166447 : UInt<2>[2]
    T_166447[0] := UInt<2>(0)
    T_166447[1] := UInt<2>(1)
    wire T_166448 : UInt<2>[3]
    T_166448[0] := UInt<2>(1)
    T_166448[1] := UInt<2>(2)
    T_166448[2] := UInt<2>(3)
    wire T_166449 : UInt<2>[2]
    T_166449[0] := UInt<2>(2)
    T_166449[1] := UInt<2>(3)
    wire T_166450 : UInt<2>[1]
    T_166450[0] := UInt<2>(3)
    accessor T_166451 = ram[T_166419]
    wire T_166452 : UInt<3>[3]
    T_166452[0] := UInt<3>(0)
    T_166452[1] := UInt<3>(1)
    T_166452[2] := UInt<3>(2)
    wire T_166453 : UInt<2>[2]
    T_166453[0] := UInt<2>(0)
    T_166453[1] := UInt<2>(1)
    wire T_166454 : UInt<2>[3]
    T_166454[0] := UInt<2>(1)
    T_166454[1] := UInt<2>(2)
    T_166454[2] := UInt<2>(3)
    wire T_166455 : UInt<2>[2]
    T_166455[0] := UInt<2>(2)
    T_166455[1] := UInt<2>(3)
    wire T_166456 : UInt<2>[1]
    T_166456[0] := UInt<2>(3)
    wire T_166457 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}
    T_166457 := T_166451
    when maybe_flow : T_166457 := enq.bits
    deq.bits := T_166457
    node ptr_diff = subw(T_166418, T_166419)
    node T_166458 = and(maybe_full, ptr_match)
    node T_166459 = cat(T_166458, ptr_diff)
    count := T_166459
  module Queue_20764 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output count : UInt<2>
    
    wire T_166460 : UInt<3>[3]
    T_166460[0] := UInt<3>(0)
    T_166460[1] := UInt<3>(1)
    T_166460[2] := UInt<3>(2)
    wire T_166461 : UInt<2>[2]
    T_166461[0] := UInt<2>(0)
    T_166461[1] := UInt<2>(1)
    wire T_166462 : UInt<2>[3]
    T_166462[0] := UInt<2>(1)
    T_166462[1] := UInt<2>(2)
    T_166462[2] := UInt<2>(3)
    wire T_166463 : UInt<2>[2]
    T_166463[0] := UInt<2>(2)
    T_166463[1] := UInt<2>(3)
    wire T_166464 : UInt<2>[1]
    T_166464[0] := UInt<2>(3)
    wire T_166465 : UInt<3>[3]
    T_166465[0] := UInt<3>(0)
    T_166465[1] := UInt<3>(1)
    T_166465[2] := UInt<3>(2)
    wire T_166466 : UInt<2>[2]
    T_166466[0] := UInt<2>(0)
    T_166466[1] := UInt<2>(1)
    wire T_166467 : UInt<2>[3]
    T_166467[0] := UInt<2>(1)
    T_166467[1] := UInt<2>(2)
    T_166467[2] := UInt<2>(3)
    wire T_166468 : UInt<2>[2]
    T_166468[0] := UInt<2>(2)
    T_166468[1] := UInt<2>(3)
    wire T_166469 : UInt<2>[1]
    T_166469[0] := UInt<2>(3)
    wire T_166470 : UInt<3>[3]
    T_166470[0] := UInt<3>(0)
    T_166470[1] := UInt<3>(1)
    T_166470[2] := UInt<3>(2)
    wire T_166471 : UInt<2>[2]
    T_166471[0] := UInt<2>(0)
    T_166471[1] := UInt<2>(1)
    wire T_166472 : UInt<2>[3]
    T_166472[0] := UInt<2>(1)
    T_166472[1] := UInt<2>(2)
    T_166472[2] := UInt<2>(3)
    wire T_166473 : UInt<2>[2]
    T_166473[0] := UInt<2>(2)
    T_166473[1] := UInt<2>(3)
    wire T_166474 : UInt<2>[1]
    T_166474[0] := UInt<2>(3)
    wire T_166475 : UInt<3>[3]
    T_166475[0] := UInt<3>(0)
    T_166475[1] := UInt<3>(1)
    T_166475[2] := UInt<3>(2)
    wire T_166476 : UInt<2>[2]
    T_166476[0] := UInt<2>(0)
    T_166476[1] := UInt<2>(1)
    wire T_166477 : UInt<2>[3]
    T_166477[0] := UInt<2>(1)
    T_166477[1] := UInt<2>(2)
    T_166477[2] := UInt<2>(3)
    wire T_166478 : UInt<2>[2]
    T_166478[0] := UInt<2>(2)
    T_166478[1] := UInt<2>(3)
    wire T_166479 : UInt<2>[1]
    T_166479[0] := UInt<2>(3)
    wire T_166480 : UInt<3>[3]
    T_166480[0] := UInt<3>(0)
    T_166480[1] := UInt<3>(1)
    T_166480[2] := UInt<3>(2)
    wire T_166481 : UInt<2>[2]
    T_166481[0] := UInt<2>(0)
    T_166481[1] := UInt<2>(1)
    wire T_166482 : UInt<2>[3]
    T_166482[0] := UInt<2>(1)
    T_166482[1] := UInt<2>(2)
    T_166482[2] := UInt<2>(3)
    wire T_166483 : UInt<2>[2]
    T_166483[0] := UInt<2>(2)
    T_166483[1] := UInt<2>(3)
    wire T_166484 : UInt<2>[1]
    T_166484[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2]
    reg T_166485 : UInt<1>
    onreset T_166485 := UInt<1>(0)
    reg T_166486 : UInt<1>
    onreset T_166486 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_166485, T_166486)
    node T_166487 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_166487)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_166488 = and(enq.ready, enq.valid)
    node T_166489 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_166488, T_166489)
    node T_166490 = and(deq.ready, deq.valid)
    node T_166491 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_166490, T_166491)
    when do_enq : 
      wire T_166492 : UInt<3>[3]
      T_166492[0] := UInt<3>(0)
      T_166492[1] := UInt<3>(1)
      T_166492[2] := UInt<3>(2)
      wire T_166493 : UInt<2>[2]
      T_166493[0] := UInt<2>(0)
      T_166493[1] := UInt<2>(1)
      wire T_166494 : UInt<2>[3]
      T_166494[0] := UInt<2>(1)
      T_166494[1] := UInt<2>(2)
      T_166494[2] := UInt<2>(3)
      wire T_166495 : UInt<2>[2]
      T_166495[0] := UInt<2>(2)
      T_166495[1] := UInt<2>(3)
      wire T_166496 : UInt<2>[1]
      T_166496[0] := UInt<2>(3)
      accessor T_166497 = ram[T_166485]
      T_166497 := enq.bits
      node T_166498 = eq(T_166485, UInt<1>(1))
      node T_166499 = and(UInt<1>(0), T_166498)
      node T_166500 = addw(T_166485, UInt<1>(1))
      wire T_166501 : UInt<1>
      T_166501 := T_166500
      when T_166499 : T_166501 := UInt<1>(0)
      T_166485 := T_166501
    when do_deq : 
      node T_166502 = eq(T_166486, UInt<1>(1))
      node T_166503 = and(UInt<1>(0), T_166502)
      node T_166504 = addw(T_166486, UInt<1>(1))
      wire T_166505 : UInt<1>
      T_166505 := T_166504
      when T_166503 : T_166505 := UInt<1>(0)
      T_166486 := T_166505
    
    node T_166506 = neq(do_enq, do_deq)
    when T_166506 : maybe_full := do_enq
    node T_166507 = eq(empty, UInt<1>(0))
    node T_166508 = and(UInt<1>(0), enq.valid)
    node T_166509 = or(T_166507, T_166508)
    deq.valid := T_166509
    node T_166510 = eq(full, UInt<1>(0))
    node T_166511 = and(UInt<1>(0), deq.ready)
    node T_166512 = or(T_166510, T_166511)
    enq.ready := T_166512
    wire T_166513 : UInt<3>[3]
    T_166513[0] := UInt<3>(0)
    T_166513[1] := UInt<3>(1)
    T_166513[2] := UInt<3>(2)
    wire T_166514 : UInt<2>[2]
    T_166514[0] := UInt<2>(0)
    T_166514[1] := UInt<2>(1)
    wire T_166515 : UInt<2>[3]
    T_166515[0] := UInt<2>(1)
    T_166515[1] := UInt<2>(2)
    T_166515[2] := UInt<2>(3)
    wire T_166516 : UInt<2>[2]
    T_166516[0] := UInt<2>(2)
    T_166516[1] := UInt<2>(3)
    wire T_166517 : UInt<2>[1]
    T_166517[0] := UInt<2>(3)
    accessor T_166518 = ram[T_166486]
    wire T_166519 : UInt<3>[3]
    T_166519[0] := UInt<3>(0)
    T_166519[1] := UInt<3>(1)
    T_166519[2] := UInt<3>(2)
    wire T_166520 : UInt<2>[2]
    T_166520[0] := UInt<2>(0)
    T_166520[1] := UInt<2>(1)
    wire T_166521 : UInt<2>[3]
    T_166521[0] := UInt<2>(1)
    T_166521[1] := UInt<2>(2)
    T_166521[2] := UInt<2>(3)
    wire T_166522 : UInt<2>[2]
    T_166522[0] := UInt<2>(2)
    T_166522[1] := UInt<2>(3)
    wire T_166523 : UInt<2>[1]
    T_166523[0] := UInt<2>(3)
    wire T_166524 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    T_166524 := T_166518
    when maybe_flow : T_166524 := enq.bits
    deq.bits := T_166524
    node ptr_diff = subw(T_166485, T_166486)
    node T_166525 = and(maybe_full, ptr_match)
    node T_166526 = cat(T_166525, ptr_diff)
    count := T_166526
  module Queue_21439 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output count : UInt<2>
    
    wire T_166527 : UInt<3>[3]
    T_166527[0] := UInt<3>(0)
    T_166527[1] := UInt<3>(1)
    T_166527[2] := UInt<3>(2)
    wire T_166528 : UInt<2>[2]
    T_166528[0] := UInt<2>(0)
    T_166528[1] := UInt<2>(1)
    wire T_166529 : UInt<2>[3]
    T_166529[0] := UInt<2>(1)
    T_166529[1] := UInt<2>(2)
    T_166529[2] := UInt<2>(3)
    wire T_166530 : UInt<2>[2]
    T_166530[0] := UInt<2>(2)
    T_166530[1] := UInt<2>(3)
    wire T_166531 : UInt<2>[1]
    T_166531[0] := UInt<2>(3)
    wire T_166532 : UInt<3>[3]
    T_166532[0] := UInt<3>(0)
    T_166532[1] := UInt<3>(1)
    T_166532[2] := UInt<3>(2)
    wire T_166533 : UInt<2>[2]
    T_166533[0] := UInt<2>(0)
    T_166533[1] := UInt<2>(1)
    wire T_166534 : UInt<2>[3]
    T_166534[0] := UInt<2>(1)
    T_166534[1] := UInt<2>(2)
    T_166534[2] := UInt<2>(3)
    wire T_166535 : UInt<2>[2]
    T_166535[0] := UInt<2>(2)
    T_166535[1] := UInt<2>(3)
    wire T_166536 : UInt<2>[1]
    T_166536[0] := UInt<2>(3)
    wire T_166537 : UInt<3>[3]
    T_166537[0] := UInt<3>(0)
    T_166537[1] := UInt<3>(1)
    T_166537[2] := UInt<3>(2)
    wire T_166538 : UInt<2>[2]
    T_166538[0] := UInt<2>(0)
    T_166538[1] := UInt<2>(1)
    wire T_166539 : UInt<2>[3]
    T_166539[0] := UInt<2>(1)
    T_166539[1] := UInt<2>(2)
    T_166539[2] := UInt<2>(3)
    wire T_166540 : UInt<2>[2]
    T_166540[0] := UInt<2>(2)
    T_166540[1] := UInt<2>(3)
    wire T_166541 : UInt<2>[1]
    T_166541[0] := UInt<2>(3)
    wire T_166542 : UInt<3>[3]
    T_166542[0] := UInt<3>(0)
    T_166542[1] := UInt<3>(1)
    T_166542[2] := UInt<3>(2)
    wire T_166543 : UInt<2>[2]
    T_166543[0] := UInt<2>(0)
    T_166543[1] := UInt<2>(1)
    wire T_166544 : UInt<2>[3]
    T_166544[0] := UInt<2>(1)
    T_166544[1] := UInt<2>(2)
    T_166544[2] := UInt<2>(3)
    wire T_166545 : UInt<2>[2]
    T_166545[0] := UInt<2>(2)
    T_166545[1] := UInt<2>(3)
    wire T_166546 : UInt<2>[1]
    T_166546[0] := UInt<2>(3)
    wire T_166547 : UInt<3>[3]
    T_166547[0] := UInt<3>(0)
    T_166547[1] := UInt<3>(1)
    T_166547[2] := UInt<3>(2)
    wire T_166548 : UInt<2>[2]
    T_166548[0] := UInt<2>(0)
    T_166548[1] := UInt<2>(1)
    wire T_166549 : UInt<2>[3]
    T_166549[0] := UInt<2>(1)
    T_166549[1] := UInt<2>(2)
    T_166549[2] := UInt<2>(3)
    wire T_166550 : UInt<2>[2]
    T_166550[0] := UInt<2>(2)
    T_166550[1] := UInt<2>(3)
    wire T_166551 : UInt<2>[1]
    T_166551[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}[2]
    reg T_166552 : UInt<1>
    onreset T_166552 := UInt<1>(0)
    reg T_166553 : UInt<1>
    onreset T_166553 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_166552, T_166553)
    node T_166554 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_166554)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_166555 = and(enq.ready, enq.valid)
    node T_166556 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_166555, T_166556)
    node T_166557 = and(deq.ready, deq.valid)
    node T_166558 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_166557, T_166558)
    when do_enq : 
      wire T_166559 : UInt<3>[3]
      T_166559[0] := UInt<3>(0)
      T_166559[1] := UInt<3>(1)
      T_166559[2] := UInt<3>(2)
      wire T_166560 : UInt<2>[2]
      T_166560[0] := UInt<2>(0)
      T_166560[1] := UInt<2>(1)
      wire T_166561 : UInt<2>[3]
      T_166561[0] := UInt<2>(1)
      T_166561[1] := UInt<2>(2)
      T_166561[2] := UInt<2>(3)
      wire T_166562 : UInt<2>[2]
      T_166562[0] := UInt<2>(2)
      T_166562[1] := UInt<2>(3)
      wire T_166563 : UInt<2>[1]
      T_166563[0] := UInt<2>(3)
      accessor T_166564 = ram[T_166552]
      T_166564 := enq.bits
      node T_166565 = eq(T_166552, UInt<1>(1))
      node T_166566 = and(UInt<1>(0), T_166565)
      node T_166567 = addw(T_166552, UInt<1>(1))
      wire T_166568 : UInt<1>
      T_166568 := T_166567
      when T_166566 : T_166568 := UInt<1>(0)
      T_166552 := T_166568
    when do_deq : 
      node T_166569 = eq(T_166553, UInt<1>(1))
      node T_166570 = and(UInt<1>(0), T_166569)
      node T_166571 = addw(T_166553, UInt<1>(1))
      wire T_166572 : UInt<1>
      T_166572 := T_166571
      when T_166570 : T_166572 := UInt<1>(0)
      T_166553 := T_166572
    
    node T_166573 = neq(do_enq, do_deq)
    when T_166573 : maybe_full := do_enq
    node T_166574 = eq(empty, UInt<1>(0))
    node T_166575 = and(UInt<1>(0), enq.valid)
    node T_166576 = or(T_166574, T_166575)
    deq.valid := T_166576
    node T_166577 = eq(full, UInt<1>(0))
    node T_166578 = and(UInt<1>(0), deq.ready)
    node T_166579 = or(T_166577, T_166578)
    enq.ready := T_166579
    wire T_166580 : UInt<3>[3]
    T_166580[0] := UInt<3>(0)
    T_166580[1] := UInt<3>(1)
    T_166580[2] := UInt<3>(2)
    wire T_166581 : UInt<2>[2]
    T_166581[0] := UInt<2>(0)
    T_166581[1] := UInt<2>(1)
    wire T_166582 : UInt<2>[3]
    T_166582[0] := UInt<2>(1)
    T_166582[1] := UInt<2>(2)
    T_166582[2] := UInt<2>(3)
    wire T_166583 : UInt<2>[2]
    T_166583[0] := UInt<2>(2)
    T_166583[1] := UInt<2>(3)
    wire T_166584 : UInt<2>[1]
    T_166584[0] := UInt<2>(3)
    accessor T_166585 = ram[T_166553]
    wire T_166586 : UInt<3>[3]
    T_166586[0] := UInt<3>(0)
    T_166586[1] := UInt<3>(1)
    T_166586[2] := UInt<3>(2)
    wire T_166587 : UInt<2>[2]
    T_166587[0] := UInt<2>(0)
    T_166587[1] := UInt<2>(1)
    wire T_166588 : UInt<2>[3]
    T_166588[0] := UInt<2>(1)
    T_166588[1] := UInt<2>(2)
    T_166588[2] := UInt<2>(3)
    wire T_166589 : UInt<2>[2]
    T_166589[0] := UInt<2>(2)
    T_166589[1] := UInt<2>(3)
    wire T_166590 : UInt<2>[1]
    T_166590[0] := UInt<2>(3)
    wire T_166591 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    T_166591 := T_166585
    when maybe_flow : T_166591 := enq.bits
    deq.bits := T_166591
    node ptr_diff = subw(T_166552, T_166553)
    node T_166592 = and(maybe_full, ptr_match)
    node T_166593 = cat(T_166592, ptr_diff)
    count := T_166593
  module Queue_22069 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output count : UInt<2>
    
    wire T_166594 : UInt<3>[3]
    T_166594[0] := UInt<3>(0)
    T_166594[1] := UInt<3>(1)
    T_166594[2] := UInt<3>(2)
    wire T_166595 : UInt<2>[2]
    T_166595[0] := UInt<2>(0)
    T_166595[1] := UInt<2>(1)
    wire T_166596 : UInt<2>[3]
    T_166596[0] := UInt<2>(1)
    T_166596[1] := UInt<2>(2)
    T_166596[2] := UInt<2>(3)
    wire T_166597 : UInt<2>[2]
    T_166597[0] := UInt<2>(2)
    T_166597[1] := UInt<2>(3)
    wire T_166598 : UInt<2>[1]
    T_166598[0] := UInt<2>(3)
    wire T_166599 : UInt<3>[3]
    T_166599[0] := UInt<3>(0)
    T_166599[1] := UInt<3>(1)
    T_166599[2] := UInt<3>(2)
    wire T_166600 : UInt<2>[2]
    T_166600[0] := UInt<2>(0)
    T_166600[1] := UInt<2>(1)
    wire T_166601 : UInt<2>[3]
    T_166601[0] := UInt<2>(1)
    T_166601[1] := UInt<2>(2)
    T_166601[2] := UInt<2>(3)
    wire T_166602 : UInt<2>[2]
    T_166602[0] := UInt<2>(2)
    T_166602[1] := UInt<2>(3)
    wire T_166603 : UInt<2>[1]
    T_166603[0] := UInt<2>(3)
    wire T_166604 : UInt<3>[3]
    T_166604[0] := UInt<3>(0)
    T_166604[1] := UInt<3>(1)
    T_166604[2] := UInt<3>(2)
    wire T_166605 : UInt<2>[2]
    T_166605[0] := UInt<2>(0)
    T_166605[1] := UInt<2>(1)
    wire T_166606 : UInt<2>[3]
    T_166606[0] := UInt<2>(1)
    T_166606[1] := UInt<2>(2)
    T_166606[2] := UInt<2>(3)
    wire T_166607 : UInt<2>[2]
    T_166607[0] := UInt<2>(2)
    T_166607[1] := UInt<2>(3)
    wire T_166608 : UInt<2>[1]
    T_166608[0] := UInt<2>(3)
    wire T_166609 : UInt<3>[3]
    T_166609[0] := UInt<3>(0)
    T_166609[1] := UInt<3>(1)
    T_166609[2] := UInt<3>(2)
    wire T_166610 : UInt<2>[2]
    T_166610[0] := UInt<2>(0)
    T_166610[1] := UInt<2>(1)
    wire T_166611 : UInt<2>[3]
    T_166611[0] := UInt<2>(1)
    T_166611[1] := UInt<2>(2)
    T_166611[2] := UInt<2>(3)
    wire T_166612 : UInt<2>[2]
    T_166612[0] := UInt<2>(2)
    T_166612[1] := UInt<2>(3)
    wire T_166613 : UInt<2>[1]
    T_166613[0] := UInt<2>(3)
    wire T_166614 : UInt<3>[3]
    T_166614[0] := UInt<3>(0)
    T_166614[1] := UInt<3>(1)
    T_166614[2] := UInt<3>(2)
    wire T_166615 : UInt<2>[2]
    T_166615[0] := UInt<2>(0)
    T_166615[1] := UInt<2>(1)
    wire T_166616 : UInt<2>[3]
    T_166616[0] := UInt<2>(1)
    T_166616[1] := UInt<2>(2)
    T_166616[2] := UInt<2>(3)
    wire T_166617 : UInt<2>[2]
    T_166617[0] := UInt<2>(2)
    T_166617[1] := UInt<2>(3)
    wire T_166618 : UInt<2>[1]
    T_166618[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}[2]
    reg T_166619 : UInt<1>
    onreset T_166619 := UInt<1>(0)
    reg T_166620 : UInt<1>
    onreset T_166620 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_166619, T_166620)
    node T_166621 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_166621)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_166622 = and(enq.ready, enq.valid)
    node T_166623 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_166622, T_166623)
    node T_166624 = and(deq.ready, deq.valid)
    node T_166625 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_166624, T_166625)
    when do_enq : 
      wire T_166626 : UInt<3>[3]
      T_166626[0] := UInt<3>(0)
      T_166626[1] := UInt<3>(1)
      T_166626[2] := UInt<3>(2)
      wire T_166627 : UInt<2>[2]
      T_166627[0] := UInt<2>(0)
      T_166627[1] := UInt<2>(1)
      wire T_166628 : UInt<2>[3]
      T_166628[0] := UInt<2>(1)
      T_166628[1] := UInt<2>(2)
      T_166628[2] := UInt<2>(3)
      wire T_166629 : UInt<2>[2]
      T_166629[0] := UInt<2>(2)
      T_166629[1] := UInt<2>(3)
      wire T_166630 : UInt<2>[1]
      T_166630[0] := UInt<2>(3)
      accessor T_166631 = ram[T_166619]
      T_166631 := enq.bits
      node T_166632 = eq(T_166619, UInt<1>(1))
      node T_166633 = and(UInt<1>(0), T_166632)
      node T_166634 = addw(T_166619, UInt<1>(1))
      wire T_166635 : UInt<1>
      T_166635 := T_166634
      when T_166633 : T_166635 := UInt<1>(0)
      T_166619 := T_166635
    when do_deq : 
      node T_166636 = eq(T_166620, UInt<1>(1))
      node T_166637 = and(UInt<1>(0), T_166636)
      node T_166638 = addw(T_166620, UInt<1>(1))
      wire T_166639 : UInt<1>
      T_166639 := T_166638
      when T_166637 : T_166639 := UInt<1>(0)
      T_166620 := T_166639
    
    node T_166640 = neq(do_enq, do_deq)
    when T_166640 : maybe_full := do_enq
    node T_166641 = eq(empty, UInt<1>(0))
    node T_166642 = and(UInt<1>(0), enq.valid)
    node T_166643 = or(T_166641, T_166642)
    deq.valid := T_166643
    node T_166644 = eq(full, UInt<1>(0))
    node T_166645 = and(UInt<1>(0), deq.ready)
    node T_166646 = or(T_166644, T_166645)
    enq.ready := T_166646
    wire T_166647 : UInt<3>[3]
    T_166647[0] := UInt<3>(0)
    T_166647[1] := UInt<3>(1)
    T_166647[2] := UInt<3>(2)
    wire T_166648 : UInt<2>[2]
    T_166648[0] := UInt<2>(0)
    T_166648[1] := UInt<2>(1)
    wire T_166649 : UInt<2>[3]
    T_166649[0] := UInt<2>(1)
    T_166649[1] := UInt<2>(2)
    T_166649[2] := UInt<2>(3)
    wire T_166650 : UInt<2>[2]
    T_166650[0] := UInt<2>(2)
    T_166650[1] := UInt<2>(3)
    wire T_166651 : UInt<2>[1]
    T_166651[0] := UInt<2>(3)
    accessor T_166652 = ram[T_166620]
    wire T_166653 : UInt<3>[3]
    T_166653[0] := UInt<3>(0)
    T_166653[1] := UInt<3>(1)
    T_166653[2] := UInt<3>(2)
    wire T_166654 : UInt<2>[2]
    T_166654[0] := UInt<2>(0)
    T_166654[1] := UInt<2>(1)
    wire T_166655 : UInt<2>[3]
    T_166655[0] := UInt<2>(1)
    T_166655[1] := UInt<2>(2)
    T_166655[2] := UInt<2>(3)
    wire T_166656 : UInt<2>[2]
    T_166656[0] := UInt<2>(2)
    T_166656[1] := UInt<2>(3)
    wire T_166657 : UInt<2>[1]
    T_166657[0] := UInt<2>(3)
    wire T_166658 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}
    T_166658 := T_166652
    when maybe_flow : T_166658 := enq.bits
    deq.bits := T_166658
    node ptr_diff = subw(T_166619, T_166620)
    node T_166659 = and(maybe_full, ptr_match)
    node T_166660 = cat(T_166659, ptr_diff)
    count := T_166660
  module TileLinkEnqueuer : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_166661 : UInt<3>[3]
    T_166661[0] := UInt<3>(0)
    T_166661[1] := UInt<3>(1)
    T_166661[2] := UInt<3>(2)
    wire T_166662 : UInt<2>[2]
    T_166662[0] := UInt<2>(0)
    T_166662[1] := UInt<2>(1)
    wire T_166663 : UInt<2>[3]
    T_166663[0] := UInt<2>(1)
    T_166663[1] := UInt<2>(2)
    T_166663[2] := UInt<2>(3)
    wire T_166664 : UInt<2>[2]
    T_166664[0] := UInt<2>(2)
    T_166664[1] := UInt<2>(3)
    wire T_166665 : UInt<2>[1]
    T_166665[0] := UInt<2>(3)
    wire T_166666 : UInt<3>[3]
    T_166666[0] := UInt<3>(0)
    T_166666[1] := UInt<3>(1)
    T_166666[2] := UInt<3>(2)
    wire T_166667 : UInt<2>[2]
    T_166667[0] := UInt<2>(0)
    T_166667[1] := UInt<2>(1)
    wire T_166668 : UInt<2>[3]
    T_166668[0] := UInt<2>(1)
    T_166668[1] := UInt<2>(2)
    T_166668[2] := UInt<2>(3)
    wire T_166669 : UInt<2>[2]
    T_166669[0] := UInt<2>(2)
    T_166669[1] := UInt<2>(3)
    wire T_166670 : UInt<2>[1]
    T_166670[0] := UInt<2>(3)
    wire T_166671 : UInt<3>[3]
    T_166671[0] := UInt<3>(0)
    T_166671[1] := UInt<3>(1)
    T_166671[2] := UInt<3>(2)
    wire T_166672 : UInt<2>[2]
    T_166672[0] := UInt<2>(0)
    T_166672[1] := UInt<2>(1)
    wire T_166673 : UInt<2>[3]
    T_166673[0] := UInt<2>(1)
    T_166673[1] := UInt<2>(2)
    T_166673[2] := UInt<2>(3)
    wire T_166674 : UInt<2>[2]
    T_166674[0] := UInt<2>(2)
    T_166674[1] := UInt<2>(3)
    wire T_166675 : UInt<2>[1]
    T_166675[0] := UInt<2>(3)
    wire T_166676 : UInt<3>[3]
    T_166676[0] := UInt<3>(0)
    T_166676[1] := UInt<3>(1)
    T_166676[2] := UInt<3>(2)
    wire T_166677 : UInt<2>[2]
    T_166677[0] := UInt<2>(0)
    T_166677[1] := UInt<2>(1)
    wire T_166678 : UInt<2>[3]
    T_166678[0] := UInt<2>(1)
    T_166678[1] := UInt<2>(2)
    T_166678[2] := UInt<2>(3)
    wire T_166679 : UInt<2>[2]
    T_166679[0] := UInt<2>(2)
    T_166679[1] := UInt<2>(3)
    wire T_166680 : UInt<2>[1]
    T_166680[0] := UInt<2>(3)
    wire T_166681 : UInt<3>[3]
    T_166681[0] := UInt<3>(0)
    T_166681[1] := UInt<3>(1)
    T_166681[2] := UInt<3>(2)
    wire T_166682 : UInt<2>[2]
    T_166682[0] := UInt<2>(0)
    T_166682[1] := UInt<2>(1)
    wire T_166683 : UInt<2>[3]
    T_166683[0] := UInt<2>(1)
    T_166683[1] := UInt<2>(2)
    T_166683[2] := UInt<2>(3)
    wire T_166684 : UInt<2>[2]
    T_166684[0] := UInt<2>(2)
    T_166684[1] := UInt<2>(3)
    wire T_166685 : UInt<2>[1]
    T_166685[0] := UInt<2>(3)
    wire T_166686 : UInt<3>[3]
    T_166686[0] := UInt<3>(0)
    T_166686[1] := UInt<3>(1)
    T_166686[2] := UInt<3>(2)
    wire T_166687 : UInt<2>[2]
    T_166687[0] := UInt<2>(0)
    T_166687[1] := UInt<2>(1)
    wire T_166688 : UInt<2>[3]
    T_166688[0] := UInt<2>(1)
    T_166688[1] := UInt<2>(2)
    T_166688[2] := UInt<2>(3)
    wire T_166689 : UInt<2>[2]
    T_166689[0] := UInt<2>(2)
    T_166689[1] := UInt<2>(3)
    wire T_166690 : UInt<2>[1]
    T_166690[0] := UInt<2>(3)
    wire T_166691 : UInt<3>[3]
    T_166691[0] := UInt<3>(0)
    T_166691[1] := UInt<3>(1)
    T_166691[2] := UInt<3>(2)
    wire T_166692 : UInt<2>[2]
    T_166692[0] := UInt<2>(0)
    T_166692[1] := UInt<2>(1)
    wire T_166693 : UInt<2>[3]
    T_166693[0] := UInt<2>(1)
    T_166693[1] := UInt<2>(2)
    T_166693[2] := UInt<2>(3)
    wire T_166694 : UInt<2>[2]
    T_166694[0] := UInt<2>(2)
    T_166694[1] := UInt<2>(3)
    wire T_166695 : UInt<2>[1]
    T_166695[0] := UInt<2>(3)
    wire T_166696 : UInt<3>[3]
    T_166696[0] := UInt<3>(0)
    T_166696[1] := UInt<3>(1)
    T_166696[2] := UInt<3>(2)
    wire T_166697 : UInt<2>[2]
    T_166697[0] := UInt<2>(0)
    T_166697[1] := UInt<2>(1)
    wire T_166698 : UInt<2>[3]
    T_166698[0] := UInt<2>(1)
    T_166698[1] := UInt<2>(2)
    T_166698[2] := UInt<2>(3)
    wire T_166699 : UInt<2>[2]
    T_166699[0] := UInt<2>(2)
    T_166699[1] := UInt<2>(3)
    wire T_166700 : UInt<2>[1]
    T_166700[0] := UInt<2>(3)
    wire T_166701 : UInt<3>[3]
    T_166701[0] := UInt<3>(0)
    T_166701[1] := UInt<3>(1)
    T_166701[2] := UInt<3>(2)
    wire T_166702 : UInt<2>[2]
    T_166702[0] := UInt<2>(0)
    T_166702[1] := UInt<2>(1)
    wire T_166703 : UInt<2>[3]
    T_166703[0] := UInt<2>(1)
    T_166703[1] := UInt<2>(2)
    T_166703[2] := UInt<2>(3)
    wire T_166704 : UInt<2>[2]
    T_166704[0] := UInt<2>(2)
    T_166704[1] := UInt<2>(3)
    wire T_166705 : UInt<2>[1]
    T_166705[0] := UInt<2>(3)
    wire T_166706 : UInt<3>[3]
    T_166706[0] := UInt<3>(0)
    T_166706[1] := UInt<3>(1)
    T_166706[2] := UInt<3>(2)
    wire T_166707 : UInt<2>[2]
    T_166707[0] := UInt<2>(0)
    T_166707[1] := UInt<2>(1)
    wire T_166708 : UInt<2>[3]
    T_166708[0] := UInt<2>(1)
    T_166708[1] := UInt<2>(2)
    T_166708[2] := UInt<2>(3)
    wire T_166709 : UInt<2>[2]
    T_166709[0] := UInt<2>(2)
    T_166709[1] := UInt<2>(3)
    wire T_166710 : UInt<2>[1]
    T_166710[0] := UInt<2>(3)
    wire T_166711 : UInt<3>[3]
    T_166711[0] := UInt<3>(0)
    T_166711[1] := UInt<3>(1)
    T_166711[2] := UInt<3>(2)
    wire T_166712 : UInt<2>[2]
    T_166712[0] := UInt<2>(0)
    T_166712[1] := UInt<2>(1)
    wire T_166713 : UInt<2>[3]
    T_166713[0] := UInt<2>(1)
    T_166713[1] := UInt<2>(2)
    T_166713[2] := UInt<2>(3)
    wire T_166714 : UInt<2>[2]
    T_166714[0] := UInt<2>(2)
    T_166714[1] := UInt<2>(3)
    wire T_166715 : UInt<2>[1]
    T_166715[0] := UInt<2>(3)
    wire T_166716 : UInt<3>[3]
    T_166716[0] := UInt<3>(0)
    T_166716[1] := UInt<3>(1)
    T_166716[2] := UInt<3>(2)
    wire T_166717 : UInt<2>[2]
    T_166717[0] := UInt<2>(0)
    T_166717[1] := UInt<2>(1)
    wire T_166718 : UInt<2>[3]
    T_166718[0] := UInt<2>(1)
    T_166718[1] := UInt<2>(2)
    T_166718[2] := UInt<2>(3)
    wire T_166719 : UInt<2>[2]
    T_166719[0] := UInt<2>(2)
    T_166719[1] := UInt<2>(3)
    wire T_166720 : UInt<2>[1]
    T_166720[0] := UInt<2>(3)
    wire T_166721 : UInt<3>[3]
    T_166721[0] := UInt<3>(0)
    T_166721[1] := UInt<3>(1)
    T_166721[2] := UInt<3>(2)
    wire T_166722 : UInt<2>[2]
    T_166722[0] := UInt<2>(0)
    T_166722[1] := UInt<2>(1)
    wire T_166723 : UInt<2>[3]
    T_166723[0] := UInt<2>(1)
    T_166723[1] := UInt<2>(2)
    T_166723[2] := UInt<2>(3)
    wire T_166724 : UInt<2>[2]
    T_166724[0] := UInt<2>(2)
    T_166724[1] := UInt<2>(3)
    wire T_166725 : UInt<2>[1]
    T_166725[0] := UInt<2>(3)
    wire T_166726 : UInt<3>[3]
    T_166726[0] := UInt<3>(0)
    T_166726[1] := UInt<3>(1)
    T_166726[2] := UInt<3>(2)
    wire T_166727 : UInt<2>[2]
    T_166727[0] := UInt<2>(0)
    T_166727[1] := UInt<2>(1)
    wire T_166728 : UInt<2>[3]
    T_166728[0] := UInt<2>(1)
    T_166728[1] := UInt<2>(2)
    T_166728[2] := UInt<2>(3)
    wire T_166729 : UInt<2>[2]
    T_166729[0] := UInt<2>(2)
    T_166729[1] := UInt<2>(3)
    wire T_166730 : UInt<2>[1]
    T_166730[0] := UInt<2>(3)
    wire T_166731 : UInt<3>[3]
    T_166731[0] := UInt<3>(0)
    T_166731[1] := UInt<3>(1)
    T_166731[2] := UInt<3>(2)
    wire T_166732 : UInt<2>[2]
    T_166732[0] := UInt<2>(0)
    T_166732[1] := UInt<2>(1)
    wire T_166733 : UInt<2>[3]
    T_166733[0] := UInt<2>(1)
    T_166733[1] := UInt<2>(2)
    T_166733[2] := UInt<2>(3)
    wire T_166734 : UInt<2>[2]
    T_166734[0] := UInt<2>(2)
    T_166734[1] := UInt<2>(3)
    wire T_166735 : UInt<2>[1]
    T_166735[0] := UInt<2>(3)
    wire T_166736 : UInt<3>[3]
    T_166736[0] := UInt<3>(0)
    T_166736[1] := UInt<3>(1)
    T_166736[2] := UInt<3>(2)
    wire T_166737 : UInt<2>[2]
    T_166737[0] := UInt<2>(0)
    T_166737[1] := UInt<2>(1)
    wire T_166738 : UInt<2>[3]
    T_166738[0] := UInt<2>(1)
    T_166738[1] := UInt<2>(2)
    T_166738[2] := UInt<2>(3)
    wire T_166739 : UInt<2>[2]
    T_166739[0] := UInt<2>(2)
    T_166739[1] := UInt<2>(3)
    wire T_166740 : UInt<2>[1]
    T_166740[0] := UInt<2>(3)
    wire T_166741 : UInt<3>[3]
    T_166741[0] := UInt<3>(0)
    T_166741[1] := UInt<3>(1)
    T_166741[2] := UInt<3>(2)
    wire T_166742 : UInt<2>[2]
    T_166742[0] := UInt<2>(0)
    T_166742[1] := UInt<2>(1)
    wire T_166743 : UInt<2>[3]
    T_166743[0] := UInt<2>(1)
    T_166743[1] := UInt<2>(2)
    T_166743[2] := UInt<2>(3)
    wire T_166744 : UInt<2>[2]
    T_166744[0] := UInt<2>(2)
    T_166744[1] := UInt<2>(3)
    wire T_166745 : UInt<2>[1]
    T_166745[0] := UInt<2>(3)
    wire T_166746 : UInt<3>[3]
    T_166746[0] := UInt<3>(0)
    T_166746[1] := UInt<3>(1)
    T_166746[2] := UInt<3>(2)
    wire T_166747 : UInt<2>[2]
    T_166747[0] := UInt<2>(0)
    T_166747[1] := UInt<2>(1)
    wire T_166748 : UInt<2>[3]
    T_166748[0] := UInt<2>(1)
    T_166748[1] := UInt<2>(2)
    T_166748[2] := UInt<2>(3)
    wire T_166749 : UInt<2>[2]
    T_166749[0] := UInt<2>(2)
    T_166749[1] := UInt<2>(3)
    wire T_166750 : UInt<2>[1]
    T_166750[0] := UInt<2>(3)
    wire T_166751 : UInt<3>[3]
    T_166751[0] := UInt<3>(0)
    T_166751[1] := UInt<3>(1)
    T_166751[2] := UInt<3>(2)
    wire T_166752 : UInt<2>[2]
    T_166752[0] := UInt<2>(0)
    T_166752[1] := UInt<2>(1)
    wire T_166753 : UInt<2>[3]
    T_166753[0] := UInt<2>(1)
    T_166753[1] := UInt<2>(2)
    T_166753[2] := UInt<2>(3)
    wire T_166754 : UInt<2>[2]
    T_166754[0] := UInt<2>(2)
    T_166754[1] := UInt<2>(3)
    wire T_166755 : UInt<2>[1]
    T_166755[0] := UInt<2>(3)
    wire T_166756 : UInt<3>[3]
    T_166756[0] := UInt<3>(0)
    T_166756[1] := UInt<3>(1)
    T_166756[2] := UInt<3>(2)
    wire T_166757 : UInt<2>[2]
    T_166757[0] := UInt<2>(0)
    T_166757[1] := UInt<2>(1)
    wire T_166758 : UInt<2>[3]
    T_166758[0] := UInt<2>(1)
    T_166758[1] := UInt<2>(2)
    T_166758[2] := UInt<2>(3)
    wire T_166759 : UInt<2>[2]
    T_166759[0] := UInt<2>(2)
    T_166759[1] := UInt<2>(3)
    wire T_166760 : UInt<2>[1]
    T_166760[0] := UInt<2>(3)
    wire T_166761 : UInt<3>[3]
    T_166761[0] := UInt<3>(0)
    T_166761[1] := UInt<3>(1)
    T_166761[2] := UInt<3>(2)
    wire T_166762 : UInt<2>[2]
    T_166762[0] := UInt<2>(0)
    T_166762[1] := UInt<2>(1)
    wire T_166763 : UInt<2>[3]
    T_166763[0] := UInt<2>(1)
    T_166763[1] := UInt<2>(2)
    T_166763[2] := UInt<2>(3)
    wire T_166764 : UInt<2>[2]
    T_166764[0] := UInt<2>(2)
    T_166764[1] := UInt<2>(3)
    wire T_166765 : UInt<2>[1]
    T_166765[0] := UInt<2>(3)
    wire T_166766 : UInt<3>[3]
    T_166766[0] := UInt<3>(0)
    T_166766[1] := UInt<3>(1)
    T_166766[2] := UInt<3>(2)
    wire T_166767 : UInt<2>[2]
    T_166767[0] := UInt<2>(0)
    T_166767[1] := UInt<2>(1)
    wire T_166768 : UInt<2>[3]
    T_166768[0] := UInt<2>(1)
    T_166768[1] := UInt<2>(2)
    T_166768[2] := UInt<2>(3)
    wire T_166769 : UInt<2>[2]
    T_166769[0] := UInt<2>(2)
    T_166769[1] := UInt<2>(3)
    wire T_166770 : UInt<2>[1]
    T_166770[0] := UInt<2>(3)
    wire T_166771 : UInt<3>[3]
    T_166771[0] := UInt<3>(0)
    T_166771[1] := UInt<3>(1)
    T_166771[2] := UInt<3>(2)
    wire T_166772 : UInt<2>[2]
    T_166772[0] := UInt<2>(0)
    T_166772[1] := UInt<2>(1)
    wire T_166773 : UInt<2>[3]
    T_166773[0] := UInt<2>(1)
    T_166773[1] := UInt<2>(2)
    T_166773[2] := UInt<2>(3)
    wire T_166774 : UInt<2>[2]
    T_166774[0] := UInt<2>(2)
    T_166774[1] := UInt<2>(3)
    wire T_166775 : UInt<2>[1]
    T_166775[0] := UInt<2>(3)
    wire T_166776 : UInt<3>[3]
    T_166776[0] := UInt<3>(0)
    T_166776[1] := UInt<3>(1)
    T_166776[2] := UInt<3>(2)
    wire T_166777 : UInt<2>[2]
    T_166777[0] := UInt<2>(0)
    T_166777[1] := UInt<2>(1)
    wire T_166778 : UInt<2>[3]
    T_166778[0] := UInt<2>(1)
    T_166778[1] := UInt<2>(2)
    T_166778[2] := UInt<2>(3)
    wire T_166779 : UInt<2>[2]
    T_166779[0] := UInt<2>(2)
    T_166779[1] := UInt<2>(3)
    wire T_166780 : UInt<2>[1]
    T_166780[0] := UInt<2>(3)
    wire T_166781 : UInt<3>[3]
    T_166781[0] := UInt<3>(0)
    T_166781[1] := UInt<3>(1)
    T_166781[2] := UInt<3>(2)
    wire T_166782 : UInt<2>[2]
    T_166782[0] := UInt<2>(0)
    T_166782[1] := UInt<2>(1)
    wire T_166783 : UInt<2>[3]
    T_166783[0] := UInt<2>(1)
    T_166783[1] := UInt<2>(2)
    T_166783[2] := UInt<2>(3)
    wire T_166784 : UInt<2>[2]
    T_166784[0] := UInt<2>(2)
    T_166784[1] := UInt<2>(3)
    wire T_166785 : UInt<2>[1]
    T_166785[0] := UInt<2>(3)
    wire T_166786 : UInt<3>[3]
    T_166786[0] := UInt<3>(0)
    T_166786[1] := UInt<3>(1)
    T_166786[2] := UInt<3>(2)
    wire T_166787 : UInt<2>[2]
    T_166787[0] := UInt<2>(0)
    T_166787[1] := UInt<2>(1)
    wire T_166788 : UInt<2>[3]
    T_166788[0] := UInt<2>(1)
    T_166788[1] := UInt<2>(2)
    T_166788[2] := UInt<2>(3)
    wire T_166789 : UInt<2>[2]
    T_166789[0] := UInt<2>(2)
    T_166789[1] := UInt<2>(3)
    wire T_166790 : UInt<2>[1]
    T_166790[0] := UInt<2>(3)
    wire T_166791 : UInt<3>[3]
    T_166791[0] := UInt<3>(0)
    T_166791[1] := UInt<3>(1)
    T_166791[2] := UInt<3>(2)
    wire T_166792 : UInt<2>[2]
    T_166792[0] := UInt<2>(0)
    T_166792[1] := UInt<2>(1)
    wire T_166793 : UInt<2>[3]
    T_166793[0] := UInt<2>(1)
    T_166793[1] := UInt<2>(2)
    T_166793[2] := UInt<2>(3)
    wire T_166794 : UInt<2>[2]
    T_166794[0] := UInt<2>(2)
    T_166794[1] := UInt<2>(3)
    wire T_166795 : UInt<2>[1]
    T_166795[0] := UInt<2>(3)
    wire T_166796 : UInt<3>[3]
    T_166796[0] := UInt<3>(0)
    T_166796[1] := UInt<3>(1)
    T_166796[2] := UInt<3>(2)
    wire T_166797 : UInt<2>[2]
    T_166797[0] := UInt<2>(0)
    T_166797[1] := UInt<2>(1)
    wire T_166798 : UInt<2>[3]
    T_166798[0] := UInt<2>(1)
    T_166798[1] := UInt<2>(2)
    T_166798[2] := UInt<2>(3)
    wire T_166799 : UInt<2>[2]
    T_166799[0] := UInt<2>(2)
    T_166799[1] := UInt<2>(3)
    wire T_166800 : UInt<2>[1]
    T_166800[0] := UInt<2>(3)
    wire T_166801 : UInt<3>[3]
    T_166801[0] := UInt<3>(0)
    T_166801[1] := UInt<3>(1)
    T_166801[2] := UInt<3>(2)
    wire T_166802 : UInt<2>[2]
    T_166802[0] := UInt<2>(0)
    T_166802[1] := UInt<2>(1)
    wire T_166803 : UInt<2>[3]
    T_166803[0] := UInt<2>(1)
    T_166803[1] := UInt<2>(2)
    T_166803[2] := UInt<2>(3)
    wire T_166804 : UInt<2>[2]
    T_166804[0] := UInt<2>(2)
    T_166804[1] := UInt<2>(3)
    wire T_166805 : UInt<2>[1]
    T_166805[0] := UInt<2>(3)
    wire T_166806 : UInt<3>[3]
    T_166806[0] := UInt<3>(0)
    T_166806[1] := UInt<3>(1)
    T_166806[2] := UInt<3>(2)
    wire T_166807 : UInt<2>[2]
    T_166807[0] := UInt<2>(0)
    T_166807[1] := UInt<2>(1)
    wire T_166808 : UInt<2>[3]
    T_166808[0] := UInt<2>(1)
    T_166808[1] := UInt<2>(2)
    T_166808[2] := UInt<2>(3)
    wire T_166809 : UInt<2>[2]
    T_166809[0] := UInt<2>(2)
    T_166809[1] := UInt<2>(3)
    wire T_166810 : UInt<2>[1]
    T_166810[0] := UInt<2>(3)
    wire T_166811 : UInt<3>[3]
    T_166811[0] := UInt<3>(0)
    T_166811[1] := UInt<3>(1)
    T_166811[2] := UInt<3>(2)
    wire T_166812 : UInt<2>[2]
    T_166812[0] := UInt<2>(0)
    T_166812[1] := UInt<2>(1)
    wire T_166813 : UInt<2>[3]
    T_166813[0] := UInt<2>(1)
    T_166813[1] := UInt<2>(2)
    T_166813[2] := UInt<2>(3)
    wire T_166814 : UInt<2>[2]
    T_166814[0] := UInt<2>(2)
    T_166814[1] := UInt<2>(3)
    wire T_166815 : UInt<2>[1]
    T_166815[0] := UInt<2>(3)
    wire T_166816 : UInt<3>[3]
    T_166816[0] := UInt<3>(0)
    T_166816[1] := UInt<3>(1)
    T_166816[2] := UInt<3>(2)
    wire T_166817 : UInt<2>[2]
    T_166817[0] := UInt<2>(0)
    T_166817[1] := UInt<2>(1)
    wire T_166818 : UInt<2>[3]
    T_166818[0] := UInt<2>(1)
    T_166818[1] := UInt<2>(2)
    T_166818[2] := UInt<2>(3)
    wire T_166819 : UInt<2>[2]
    T_166819[0] := UInt<2>(2)
    T_166819[1] := UInt<2>(3)
    wire T_166820 : UInt<2>[1]
    T_166820[0] := UInt<2>(3)
    wire T_166821 : UInt<3>[3]
    T_166821[0] := UInt<3>(0)
    T_166821[1] := UInt<3>(1)
    T_166821[2] := UInt<3>(2)
    wire T_166822 : UInt<2>[2]
    T_166822[0] := UInt<2>(0)
    T_166822[1] := UInt<2>(1)
    wire T_166823 : UInt<2>[3]
    T_166823[0] := UInt<2>(1)
    T_166823[1] := UInt<2>(2)
    T_166823[2] := UInt<2>(3)
    wire T_166824 : UInt<2>[2]
    T_166824[0] := UInt<2>(2)
    T_166824[1] := UInt<2>(3)
    wire T_166825 : UInt<2>[1]
    T_166825[0] := UInt<2>(3)
    inst T_166826 of Queue
    T_166826.enq.valid := client.acquire.valid
    T_166826.enq.bits := client.acquire.bits
    client.acquire.ready := T_166826.enq.ready
    manager.acquire <> T_166826.deq
    wire T_166827 : UInt<3>[3]
    T_166827[0] := UInt<3>(0)
    T_166827[1] := UInt<3>(1)
    T_166827[2] := UInt<3>(2)
    wire T_166828 : UInt<2>[2]
    T_166828[0] := UInt<2>(0)
    T_166828[1] := UInt<2>(1)
    wire T_166829 : UInt<2>[3]
    T_166829[0] := UInt<2>(1)
    T_166829[1] := UInt<2>(2)
    T_166829[2] := UInt<2>(3)
    wire T_166830 : UInt<2>[2]
    T_166830[0] := UInt<2>(2)
    T_166830[1] := UInt<2>(3)
    wire T_166831 : UInt<2>[1]
    T_166831[0] := UInt<2>(3)
    inst T_166832 of Queue_20089
    T_166832.enq.valid := manager.probe.valid
    T_166832.enq.bits := manager.probe.bits
    manager.probe.ready := T_166832.enq.ready
    client.probe <> T_166832.deq
    wire T_166833 : UInt<3>[3]
    T_166833[0] := UInt<3>(0)
    T_166833[1] := UInt<3>(1)
    T_166833[2] := UInt<3>(2)
    wire T_166834 : UInt<2>[2]
    T_166834[0] := UInt<2>(0)
    T_166834[1] := UInt<2>(1)
    wire T_166835 : UInt<2>[3]
    T_166835[0] := UInt<2>(1)
    T_166835[1] := UInt<2>(2)
    T_166835[2] := UInt<2>(3)
    wire T_166836 : UInt<2>[2]
    T_166836[0] := UInt<2>(2)
    T_166836[1] := UInt<2>(3)
    wire T_166837 : UInt<2>[1]
    T_166837[0] := UInt<2>(3)
    inst T_166838 of Queue_20764
    T_166838.enq.valid := client.release.valid
    T_166838.enq.bits := client.release.bits
    client.release.ready := T_166838.enq.ready
    manager.release <> T_166838.deq
    wire T_166839 : UInt<3>[3]
    T_166839[0] := UInt<3>(0)
    T_166839[1] := UInt<3>(1)
    T_166839[2] := UInt<3>(2)
    wire T_166840 : UInt<2>[2]
    T_166840[0] := UInt<2>(0)
    T_166840[1] := UInt<2>(1)
    wire T_166841 : UInt<2>[3]
    T_166841[0] := UInt<2>(1)
    T_166841[1] := UInt<2>(2)
    T_166841[2] := UInt<2>(3)
    wire T_166842 : UInt<2>[2]
    T_166842[0] := UInt<2>(2)
    T_166842[1] := UInt<2>(3)
    wire T_166843 : UInt<2>[1]
    T_166843[0] := UInt<2>(3)
    inst T_166844 of Queue_21439
    T_166844.enq.valid := manager.grant.valid
    T_166844.enq.bits := manager.grant.bits
    manager.grant.ready := T_166844.enq.ready
    client.grant <> T_166844.deq
    wire T_166845 : UInt<3>[3]
    T_166845[0] := UInt<3>(0)
    T_166845[1] := UInt<3>(1)
    T_166845[2] := UInt<3>(2)
    wire T_166846 : UInt<2>[2]
    T_166846[0] := UInt<2>(0)
    T_166846[1] := UInt<2>(1)
    wire T_166847 : UInt<2>[3]
    T_166847[0] := UInt<2>(1)
    T_166847[1] := UInt<2>(2)
    T_166847[2] := UInt<2>(3)
    wire T_166848 : UInt<2>[2]
    T_166848[0] := UInt<2>(2)
    T_166848[1] := UInt<2>(3)
    wire T_166849 : UInt<2>[1]
    T_166849[0] := UInt<2>(3)
    inst T_166850 of Queue_22069
    T_166850.enq.valid := client.finish.valid
    T_166850.enq.bits := client.finish.bits
    client.finish.ready := T_166850.enq.ready
    manager.finish <> T_166850.deq
  module FinishQueue_25492 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}}
    output count : UInt<2>
    
    wire T_166851 : UInt<3>[3]
    T_166851[0] := UInt<3>(0)
    T_166851[1] := UInt<3>(1)
    T_166851[2] := UInt<3>(2)
    wire T_166852 : UInt<2>[2]
    T_166852[0] := UInt<2>(0)
    T_166852[1] := UInt<2>(1)
    wire T_166853 : UInt<2>[3]
    T_166853[0] := UInt<2>(1)
    T_166853[1] := UInt<2>(2)
    T_166853[2] := UInt<2>(3)
    wire T_166854 : UInt<2>[2]
    T_166854[0] := UInt<2>(2)
    T_166854[1] := UInt<2>(3)
    wire T_166855 : UInt<2>[1]
    T_166855[0] := UInt<2>(3)
    wire T_166856 : UInt<3>[3]
    T_166856[0] := UInt<3>(0)
    T_166856[1] := UInt<3>(1)
    T_166856[2] := UInt<3>(2)
    wire T_166857 : UInt<2>[2]
    T_166857[0] := UInt<2>(0)
    T_166857[1] := UInt<2>(1)
    wire T_166858 : UInt<2>[3]
    T_166858[0] := UInt<2>(1)
    T_166858[1] := UInt<2>(2)
    T_166858[2] := UInt<2>(3)
    wire T_166859 : UInt<2>[2]
    T_166859[0] := UInt<2>(2)
    T_166859[1] := UInt<2>(3)
    wire T_166860 : UInt<2>[1]
    T_166860[0] := UInt<2>(3)
    wire T_166861 : UInt<3>[3]
    T_166861[0] := UInt<3>(0)
    T_166861[1] := UInt<3>(1)
    T_166861[2] := UInt<3>(2)
    wire T_166862 : UInt<2>[2]
    T_166862[0] := UInt<2>(0)
    T_166862[1] := UInt<2>(1)
    wire T_166863 : UInt<2>[3]
    T_166863[0] := UInt<2>(1)
    T_166863[1] := UInt<2>(2)
    T_166863[2] := UInt<2>(3)
    wire T_166864 : UInt<2>[2]
    T_166864[0] := UInt<2>(2)
    T_166864[1] := UInt<2>(3)
    wire T_166865 : UInt<2>[1]
    T_166865[0] := UInt<2>(3)
    wire T_166866 : UInt<3>[3]
    T_166866[0] := UInt<3>(0)
    T_166866[1] := UInt<3>(1)
    T_166866[2] := UInt<3>(2)
    wire T_166867 : UInt<2>[2]
    T_166867[0] := UInt<2>(0)
    T_166867[1] := UInt<2>(1)
    wire T_166868 : UInt<2>[3]
    T_166868[0] := UInt<2>(1)
    T_166868[1] := UInt<2>(2)
    T_166868[2] := UInt<2>(3)
    wire T_166869 : UInt<2>[2]
    T_166869[0] := UInt<2>(2)
    T_166869[1] := UInt<2>(3)
    wire T_166870 : UInt<2>[1]
    T_166870[0] := UInt<2>(3)
    wire T_166871 : UInt<3>[3]
    T_166871[0] := UInt<3>(0)
    T_166871[1] := UInt<3>(1)
    T_166871[2] := UInt<3>(2)
    wire T_166872 : UInt<2>[2]
    T_166872[0] := UInt<2>(0)
    T_166872[1] := UInt<2>(1)
    wire T_166873 : UInt<2>[3]
    T_166873[0] := UInt<2>(1)
    T_166873[1] := UInt<2>(2)
    T_166873[2] := UInt<2>(3)
    wire T_166874 : UInt<2>[2]
    T_166874[0] := UInt<2>(2)
    T_166874[1] := UInt<2>(3)
    wire T_166875 : UInt<2>[1]
    T_166875[0] := UInt<2>(3)
    wire T_166876 : UInt<3>[3]
    T_166876[0] := UInt<3>(0)
    T_166876[1] := UInt<3>(1)
    T_166876[2] := UInt<3>(2)
    wire T_166877 : UInt<2>[2]
    T_166877[0] := UInt<2>(0)
    T_166877[1] := UInt<2>(1)
    wire T_166878 : UInt<2>[3]
    T_166878[0] := UInt<2>(1)
    T_166878[1] := UInt<2>(2)
    T_166878[2] := UInt<2>(3)
    wire T_166879 : UInt<2>[2]
    T_166879[0] := UInt<2>(2)
    T_166879[1] := UInt<2>(3)
    wire T_166880 : UInt<2>[1]
    T_166880[0] := UInt<2>(3)
    wire T_166881 : UInt<3>[3]
    T_166881[0] := UInt<3>(0)
    T_166881[1] := UInt<3>(1)
    T_166881[2] := UInt<3>(2)
    wire T_166882 : UInt<2>[2]
    T_166882[0] := UInt<2>(0)
    T_166882[1] := UInt<2>(1)
    wire T_166883 : UInt<2>[3]
    T_166883[0] := UInt<2>(1)
    T_166883[1] := UInt<2>(2)
    T_166883[2] := UInt<2>(3)
    wire T_166884 : UInt<2>[2]
    T_166884[0] := UInt<2>(2)
    T_166884[1] := UInt<2>(3)
    wire T_166885 : UInt<2>[1]
    T_166885[0] := UInt<2>(3)
    wire T_166886 : UInt<3>[3]
    T_166886[0] := UInt<3>(0)
    T_166886[1] := UInt<3>(1)
    T_166886[2] := UInt<3>(2)
    wire T_166887 : UInt<2>[2]
    T_166887[0] := UInt<2>(0)
    T_166887[1] := UInt<2>(1)
    wire T_166888 : UInt<2>[3]
    T_166888[0] := UInt<2>(1)
    T_166888[1] := UInt<2>(2)
    T_166888[2] := UInt<2>(3)
    wire T_166889 : UInt<2>[2]
    T_166889[0] := UInt<2>(2)
    T_166889[1] := UInt<2>(3)
    wire T_166890 : UInt<2>[1]
    T_166890[0] := UInt<2>(3)
    wire T_166891 : UInt<3>[3]
    T_166891[0] := UInt<3>(0)
    T_166891[1] := UInt<3>(1)
    T_166891[2] := UInt<3>(2)
    wire T_166892 : UInt<2>[2]
    T_166892[0] := UInt<2>(0)
    T_166892[1] := UInt<2>(1)
    wire T_166893 : UInt<2>[3]
    T_166893[0] := UInt<2>(1)
    T_166893[1] := UInt<2>(2)
    T_166893[2] := UInt<2>(3)
    wire T_166894 : UInt<2>[2]
    T_166894[0] := UInt<2>(2)
    T_166894[1] := UInt<2>(3)
    wire T_166895 : UInt<2>[1]
    T_166895[0] := UInt<2>(3)
    wire T_166896 : UInt<3>[3]
    T_166896[0] := UInt<3>(0)
    T_166896[1] := UInt<3>(1)
    T_166896[2] := UInt<3>(2)
    wire T_166897 : UInt<2>[2]
    T_166897[0] := UInt<2>(0)
    T_166897[1] := UInt<2>(1)
    wire T_166898 : UInt<2>[3]
    T_166898[0] := UInt<2>(1)
    T_166898[1] := UInt<2>(2)
    T_166898[2] := UInt<2>(3)
    wire T_166899 : UInt<2>[2]
    T_166899[0] := UInt<2>(2)
    T_166899[1] := UInt<2>(3)
    wire T_166900 : UInt<2>[1]
    T_166900[0] := UInt<2>(3)
    cmem T_166901 : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}[2]
    reg T_166902 : UInt<1>
    onreset T_166902 := UInt<1>(0)
    reg T_166903 : UInt<1>
    onreset T_166903 := UInt<1>(0)
    reg T_166904 : UInt<1>
    onreset T_166904 := UInt<1>(0)
    node T_166905 = eq(T_166902, T_166903)
    node T_166906 = eq(T_166904, UInt<1>(0))
    node T_166907 = and(T_166905, T_166906)
    node T_166908 = and(T_166905, T_166904)
    node T_166909 = and(UInt<1>(0), T_166907)
    node T_166910 = and(T_166909, deq.ready)
    node T_166911 = and(enq.ready, enq.valid)
    node T_166912 = eq(T_166910, UInt<1>(0))
    node T_166913 = and(T_166911, T_166912)
    node T_166914 = and(deq.ready, deq.valid)
    node T_166915 = eq(T_166910, UInt<1>(0))
    node T_166916 = and(T_166914, T_166915)
    when T_166913 : 
      wire T_166917 : UInt<3>[3]
      T_166917[0] := UInt<3>(0)
      T_166917[1] := UInt<3>(1)
      T_166917[2] := UInt<3>(2)
      wire T_166918 : UInt<2>[2]
      T_166918[0] := UInt<2>(0)
      T_166918[1] := UInt<2>(1)
      wire T_166919 : UInt<2>[3]
      T_166919[0] := UInt<2>(1)
      T_166919[1] := UInt<2>(2)
      T_166919[2] := UInt<2>(3)
      wire T_166920 : UInt<2>[2]
      T_166920[0] := UInt<2>(2)
      T_166920[1] := UInt<2>(3)
      wire T_166921 : UInt<2>[1]
      T_166921[0] := UInt<2>(3)
      wire T_166922 : UInt<3>[3]
      T_166922[0] := UInt<3>(0)
      T_166922[1] := UInt<3>(1)
      T_166922[2] := UInt<3>(2)
      wire T_166923 : UInt<2>[2]
      T_166923[0] := UInt<2>(0)
      T_166923[1] := UInt<2>(1)
      wire T_166924 : UInt<2>[3]
      T_166924[0] := UInt<2>(1)
      T_166924[1] := UInt<2>(2)
      T_166924[2] := UInt<2>(3)
      wire T_166925 : UInt<2>[2]
      T_166925[0] := UInt<2>(2)
      T_166925[1] := UInt<2>(3)
      wire T_166926 : UInt<2>[1]
      T_166926[0] := UInt<2>(3)
      accessor T_166927 = T_166901[T_166902]
      T_166927 := enq.bits
      node T_166928 = eq(T_166902, UInt<1>(1))
      node T_166929 = and(UInt<1>(0), T_166928)
      node T_166930 = addw(T_166902, UInt<1>(1))
      wire T_166931 : UInt<1>
      T_166931 := T_166930
      when T_166929 : T_166931 := UInt<1>(0)
      T_166902 := T_166931
    when T_166916 : 
      node T_166932 = eq(T_166903, UInt<1>(1))
      node T_166933 = and(UInt<1>(0), T_166932)
      node T_166934 = addw(T_166903, UInt<1>(1))
      wire T_166935 : UInt<1>
      T_166935 := T_166934
      when T_166933 : T_166935 := UInt<1>(0)
      T_166903 := T_166935
    
    node T_166936 = neq(T_166913, T_166916)
    when T_166936 : T_166904 := T_166913
    node T_166937 = eq(T_166907, UInt<1>(0))
    node T_166938 = and(UInt<1>(0), enq.valid)
    node T_166939 = or(T_166937, T_166938)
    deq.valid := T_166939
    node T_166940 = eq(T_166908, UInt<1>(0))
    node T_166941 = and(UInt<1>(0), deq.ready)
    node T_166942 = or(T_166940, T_166941)
    enq.ready := T_166942
    wire T_166943 : UInt<3>[3]
    T_166943[0] := UInt<3>(0)
    T_166943[1] := UInt<3>(1)
    T_166943[2] := UInt<3>(2)
    wire T_166944 : UInt<2>[2]
    T_166944[0] := UInt<2>(0)
    T_166944[1] := UInt<2>(1)
    wire T_166945 : UInt<2>[3]
    T_166945[0] := UInt<2>(1)
    T_166945[1] := UInt<2>(2)
    T_166945[2] := UInt<2>(3)
    wire T_166946 : UInt<2>[2]
    T_166946[0] := UInt<2>(2)
    T_166946[1] := UInt<2>(3)
    wire T_166947 : UInt<2>[1]
    T_166947[0] := UInt<2>(3)
    wire T_166948 : UInt<3>[3]
    T_166948[0] := UInt<3>(0)
    T_166948[1] := UInt<3>(1)
    T_166948[2] := UInt<3>(2)
    wire T_166949 : UInt<2>[2]
    T_166949[0] := UInt<2>(0)
    T_166949[1] := UInt<2>(1)
    wire T_166950 : UInt<2>[3]
    T_166950[0] := UInt<2>(1)
    T_166950[1] := UInt<2>(2)
    T_166950[2] := UInt<2>(3)
    wire T_166951 : UInt<2>[2]
    T_166951[0] := UInt<2>(2)
    T_166951[1] := UInt<2>(3)
    wire T_166952 : UInt<2>[1]
    T_166952[0] := UInt<2>(3)
    accessor T_166953 = T_166901[T_166903]
    wire T_166954 : UInt<3>[3]
    T_166954[0] := UInt<3>(0)
    T_166954[1] := UInt<3>(1)
    T_166954[2] := UInt<3>(2)
    wire T_166955 : UInt<2>[2]
    T_166955[0] := UInt<2>(0)
    T_166955[1] := UInt<2>(1)
    wire T_166956 : UInt<2>[3]
    T_166956[0] := UInt<2>(1)
    T_166956[1] := UInt<2>(2)
    T_166956[2] := UInt<2>(3)
    wire T_166957 : UInt<2>[2]
    T_166957[0] := UInt<2>(2)
    T_166957[1] := UInt<2>(3)
    wire T_166958 : UInt<2>[1]
    T_166958[0] := UInt<2>(3)
    wire T_166959 : UInt<3>[3]
    T_166959[0] := UInt<3>(0)
    T_166959[1] := UInt<3>(1)
    T_166959[2] := UInt<3>(2)
    wire T_166960 : UInt<2>[2]
    T_166960[0] := UInt<2>(0)
    T_166960[1] := UInt<2>(1)
    wire T_166961 : UInt<2>[3]
    T_166961[0] := UInt<2>(1)
    T_166961[1] := UInt<2>(2)
    T_166961[2] := UInt<2>(3)
    wire T_166962 : UInt<2>[2]
    T_166962[0] := UInt<2>(2)
    T_166962[1] := UInt<2>(3)
    wire T_166963 : UInt<2>[1]
    T_166963[0] := UInt<2>(3)
    wire T_166964 : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}
    T_166964 := T_166953
    when T_166909 : T_166964 := enq.bits
    deq.bits := T_166964
    node T_166965 = subw(T_166902, T_166903)
    node T_166966 = and(T_166904, T_166905)
    node T_166967 = cat(T_166966, T_166965)
    count := T_166967
  module FinishUnit_25654 : 
    input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output ready : UInt<1>
    
    wire T_166968 : UInt<3>[3]
    T_166968[0] := UInt<3>(0)
    T_166968[1] := UInt<3>(1)
    T_166968[2] := UInt<3>(2)
    wire T_166969 : UInt<2>[2]
    T_166969[0] := UInt<2>(0)
    T_166969[1] := UInt<2>(1)
    wire T_166970 : UInt<2>[3]
    T_166970[0] := UInt<2>(1)
    T_166970[1] := UInt<2>(2)
    T_166970[2] := UInt<2>(3)
    wire T_166971 : UInt<2>[2]
    T_166971[0] := UInt<2>(2)
    T_166971[1] := UInt<2>(3)
    wire T_166972 : UInt<2>[1]
    T_166972[0] := UInt<2>(3)
    wire T_166973 : UInt<3>[3]
    T_166973[0] := UInt<3>(0)
    T_166973[1] := UInt<3>(1)
    T_166973[2] := UInt<3>(2)
    wire T_166974 : UInt<2>[2]
    T_166974[0] := UInt<2>(0)
    T_166974[1] := UInt<2>(1)
    wire T_166975 : UInt<2>[3]
    T_166975[0] := UInt<2>(1)
    T_166975[1] := UInt<2>(2)
    T_166975[2] := UInt<2>(3)
    wire T_166976 : UInt<2>[2]
    T_166976[0] := UInt<2>(2)
    T_166976[1] := UInt<2>(3)
    wire T_166977 : UInt<2>[1]
    T_166977[0] := UInt<2>(3)
    wire T_166978 : UInt<3>[3]
    T_166978[0] := UInt<3>(0)
    T_166978[1] := UInt<3>(1)
    T_166978[2] := UInt<3>(2)
    wire T_166979 : UInt<2>[2]
    T_166979[0] := UInt<2>(0)
    T_166979[1] := UInt<2>(1)
    wire T_166980 : UInt<2>[3]
    T_166980[0] := UInt<2>(1)
    T_166980[1] := UInt<2>(2)
    T_166980[2] := UInt<2>(3)
    wire T_166981 : UInt<2>[2]
    T_166981[0] := UInt<2>(2)
    T_166981[1] := UInt<2>(3)
    wire T_166982 : UInt<2>[1]
    T_166982[0] := UInt<2>(3)
    wire T_166983 : UInt<3>[3]
    T_166983[0] := UInt<3>(0)
    T_166983[1] := UInt<3>(1)
    T_166983[2] := UInt<3>(2)
    wire T_166984 : UInt<2>[2]
    T_166984[0] := UInt<2>(0)
    T_166984[1] := UInt<2>(1)
    wire T_166985 : UInt<2>[3]
    T_166985[0] := UInt<2>(1)
    T_166985[1] := UInt<2>(2)
    T_166985[2] := UInt<2>(3)
    wire T_166986 : UInt<2>[2]
    T_166986[0] := UInt<2>(2)
    T_166986[1] := UInt<2>(3)
    wire T_166987 : UInt<2>[1]
    T_166987[0] := UInt<2>(3)
    wire T_166988 : UInt<3>[3]
    T_166988[0] := UInt<3>(0)
    T_166988[1] := UInt<3>(1)
    T_166988[2] := UInt<3>(2)
    wire T_166989 : UInt<2>[2]
    T_166989[0] := UInt<2>(0)
    T_166989[1] := UInt<2>(1)
    wire T_166990 : UInt<2>[3]
    T_166990[0] := UInt<2>(1)
    T_166990[1] := UInt<2>(2)
    T_166990[2] := UInt<2>(3)
    wire T_166991 : UInt<2>[2]
    T_166991[0] := UInt<2>(2)
    T_166991[1] := UInt<2>(3)
    wire T_166992 : UInt<2>[1]
    T_166992[0] := UInt<2>(3)
    wire T_166993 : UInt<3>[3]
    T_166993[0] := UInt<3>(0)
    T_166993[1] := UInt<3>(1)
    T_166993[2] := UInt<3>(2)
    wire T_166994 : UInt<2>[2]
    T_166994[0] := UInt<2>(0)
    T_166994[1] := UInt<2>(1)
    wire T_166995 : UInt<2>[3]
    T_166995[0] := UInt<2>(1)
    T_166995[1] := UInt<2>(2)
    T_166995[2] := UInt<2>(3)
    wire T_166996 : UInt<2>[2]
    T_166996[0] := UInt<2>(2)
    T_166996[1] := UInt<2>(3)
    wire T_166997 : UInt<2>[1]
    T_166997[0] := UInt<2>(3)
    wire T_166998 : UInt<3>[3]
    T_166998[0] := UInt<3>(0)
    T_166998[1] := UInt<3>(1)
    T_166998[2] := UInt<3>(2)
    wire T_166999 : UInt<2>[2]
    T_166999[0] := UInt<2>(0)
    T_166999[1] := UInt<2>(1)
    wire T_167000 : UInt<2>[3]
    T_167000[0] := UInt<2>(1)
    T_167000[1] := UInt<2>(2)
    T_167000[2] := UInt<2>(3)
    wire T_167001 : UInt<2>[2]
    T_167001[0] := UInt<2>(2)
    T_167001[1] := UInt<2>(3)
    wire T_167002 : UInt<2>[1]
    T_167002[0] := UInt<2>(3)
    wire T_167003 : UInt<3>[3]
    T_167003[0] := UInt<3>(0)
    T_167003[1] := UInt<3>(1)
    T_167003[2] := UInt<3>(2)
    wire T_167004 : UInt<2>[2]
    T_167004[0] := UInt<2>(0)
    T_167004[1] := UInt<2>(1)
    wire T_167005 : UInt<2>[3]
    T_167005[0] := UInt<2>(1)
    T_167005[1] := UInt<2>(2)
    T_167005[2] := UInt<2>(3)
    wire T_167006 : UInt<2>[2]
    T_167006[0] := UInt<2>(2)
    T_167006[1] := UInt<2>(3)
    wire T_167007 : UInt<2>[1]
    T_167007[0] := UInt<2>(3)
    wire T_167008 : UInt<3>[3]
    T_167008[0] := UInt<3>(0)
    T_167008[1] := UInt<3>(1)
    T_167008[2] := UInt<3>(2)
    wire T_167009 : UInt<2>[2]
    T_167009[0] := UInt<2>(0)
    T_167009[1] := UInt<2>(1)
    wire T_167010 : UInt<2>[3]
    T_167010[0] := UInt<2>(1)
    T_167010[1] := UInt<2>(2)
    T_167010[2] := UInt<2>(3)
    wire T_167011 : UInt<2>[2]
    T_167011[0] := UInt<2>(2)
    T_167011[1] := UInt<2>(3)
    wire T_167012 : UInt<2>[1]
    T_167012[0] := UInt<2>(3)
    node T_167013 = and(grant.ready, grant.valid)
    wire T_167014 : UInt<3>[1]
    T_167014[0] := UInt<3>(5)
    node T_167015 = eq(T_167014[0], grant.bits.payload.g_type)
    node T_167016 = or(UInt<1>(0), T_167015)
    node T_167017 = eq(T_166984[0], grant.bits.payload.g_type)
    node T_167018 = eq(T_166984[1], grant.bits.payload.g_type)
    node T_167019 = or(UInt<1>(0), T_167017)
    node T_167020 = or(T_167019, T_167018)
    wire T_167021 : UInt<1>
    T_167021 := T_167020
    when grant.bits.payload.is_builtin_type : T_167021 := T_167016
    node T_167022 = and(UInt<1>(1), T_167021)
    node T_167023 = and(T_167013, T_167022)
    reg T_167024 : UInt<2>
    onreset T_167024 := UInt<2>(0)
    when T_167023 : 
      node T_167025 = eq(T_167024, UInt<2>(3))
      node T_167026 = and(UInt<1>(0), T_167025)
      node T_167027 = addw(T_167024, UInt<1>(1))
      wire T_167028 : UInt<2>
      T_167028 := T_167027
      when T_167026 : T_167028 := UInt<1>(0)
      T_167024 := T_167028
    node T_167029 = and(T_167023, T_167025)
    wire T_167030 : UInt<1>
    T_167030 := UInt<1>(0)
    when T_167022 : T_167030 := T_167024
    wire T_167031 : UInt<1>
    T_167031 := T_167013
    when T_167022 : T_167031 := T_167029
    wire T_167032 : UInt<3>[3]
    T_167032[0] := UInt<3>(0)
    T_167032[1] := UInt<3>(1)
    T_167032[2] := UInt<3>(2)
    wire T_167033 : UInt<2>[2]
    T_167033[0] := UInt<2>(0)
    T_167033[1] := UInt<2>(1)
    wire T_167034 : UInt<2>[3]
    T_167034[0] := UInt<2>(1)
    T_167034[1] := UInt<2>(2)
    T_167034[2] := UInt<2>(3)
    wire T_167035 : UInt<2>[2]
    T_167035[0] := UInt<2>(2)
    T_167035[1] := UInt<2>(3)
    wire T_167036 : UInt<2>[1]
    T_167036[0] := UInt<2>(3)
    wire T_167037 : UInt<3>[3]
    T_167037[0] := UInt<3>(0)
    T_167037[1] := UInt<3>(1)
    T_167037[2] := UInt<3>(2)
    wire T_167038 : UInt<2>[2]
    T_167038[0] := UInt<2>(0)
    T_167038[1] := UInt<2>(1)
    wire T_167039 : UInt<2>[3]
    T_167039[0] := UInt<2>(1)
    T_167039[1] := UInt<2>(2)
    T_167039[2] := UInt<2>(3)
    wire T_167040 : UInt<2>[2]
    T_167040[0] := UInt<2>(2)
    T_167040[1] := UInt<2>(3)
    wire T_167041 : UInt<2>[1]
    T_167041[0] := UInt<2>(3)
    inst T_167042 of FinishQueue_25492
    node T_167043 = and(grant.ready, grant.valid)
    node T_167044 = eq(UInt<1>(0), UInt<1>(0))
    node T_167045 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_167046 = and(grant.bits.payload.is_builtin_type, T_167045)
    node T_167047 = eq(T_167046, UInt<1>(0))
    node T_167048 = and(T_167044, T_167047)
    node T_167049 = and(T_167043, T_167048)
    wire T_167050 : UInt<3>[1]
    T_167050[0] := UInt<3>(5)
    node T_167051 = eq(T_167050[0], grant.bits.payload.g_type)
    node T_167052 = or(UInt<1>(0), T_167051)
    node T_167053 = eq(T_166984[0], grant.bits.payload.g_type)
    node T_167054 = eq(T_166984[1], grant.bits.payload.g_type)
    node T_167055 = or(UInt<1>(0), T_167053)
    node T_167056 = or(T_167055, T_167054)
    wire T_167057 : UInt<1>
    T_167057 := T_167056
    when grant.bits.payload.is_builtin_type : T_167057 := T_167052
    node T_167058 = and(UInt<1>(1), T_167057)
    node T_167059 = eq(T_167058, UInt<1>(0))
    node T_167060 = or(T_167059, T_167031)
    node T_167061 = and(T_167049, T_167060)
    T_167042.enq.valid := T_167061
    wire T_167062 : UInt<3>[3]
    T_167062[0] := UInt<3>(0)
    T_167062[1] := UInt<3>(1)
    T_167062[2] := UInt<3>(2)
    wire T_167063 : UInt<2>[2]
    T_167063[0] := UInt<2>(0)
    T_167063[1] := UInt<2>(1)
    wire T_167064 : UInt<2>[3]
    T_167064[0] := UInt<2>(1)
    T_167064[1] := UInt<2>(2)
    T_167064[2] := UInt<2>(3)
    wire T_167065 : UInt<2>[2]
    T_167065[0] := UInt<2>(2)
    T_167065[1] := UInt<2>(3)
    wire T_167066 : UInt<2>[1]
    T_167066[0] := UInt<2>(3)
    wire T_167067 : UInt<3>[3]
    T_167067[0] := UInt<3>(0)
    T_167067[1] := UInt<3>(1)
    T_167067[2] := UInt<3>(2)
    wire T_167068 : UInt<2>[2]
    T_167068[0] := UInt<2>(0)
    T_167068[1] := UInt<2>(1)
    wire T_167069 : UInt<2>[3]
    T_167069[0] := UInt<2>(1)
    T_167069[1] := UInt<2>(2)
    T_167069[2] := UInt<2>(3)
    wire T_167070 : UInt<2>[2]
    T_167070[0] := UInt<2>(2)
    T_167070[1] := UInt<2>(3)
    wire T_167071 : UInt<2>[1]
    T_167071[0] := UInt<2>(3)
    wire T_167072 : {manager_xact_id : UInt<2>}
    T_167072.manager_xact_id := grant.bits.payload.manager_xact_id
    T_167042.enq.bits.fin := T_167072
    T_167042.enq.bits.dst := grant.bits.header.src
    finish.bits.header.src := UInt<1>(1)
    finish.bits.header.dst := T_167042.deq.bits.dst
    finish.bits.payload := T_167042.deq.bits.fin
    finish.valid := T_167042.deq.valid
    T_167042.deq.ready := finish.ready
    refill.valid := grant.valid
    refill.bits := grant.bits.payload
    node T_167073 = eq(UInt<1>(0), UInt<1>(0))
    node T_167074 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_167075 = and(grant.bits.payload.is_builtin_type, T_167074)
    node T_167076 = eq(T_167075, UInt<1>(0))
    node T_167077 = and(T_167073, T_167076)
    node T_167078 = eq(T_167077, UInt<1>(0))
    node T_167079 = or(T_167042.enq.ready, T_167078)
    node T_167080 = and(T_167079, refill.ready)
    grant.ready := T_167080
    ready := T_167042.enq.ready
  module ClientTileLinkNetworkPort_26210 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_167081 : UInt<3>[3]
    T_167081[0] := UInt<3>(0)
    T_167081[1] := UInt<3>(1)
    T_167081[2] := UInt<3>(2)
    wire T_167082 : UInt<2>[2]
    T_167082[0] := UInt<2>(0)
    T_167082[1] := UInt<2>(1)
    wire T_167083 : UInt<2>[3]
    T_167083[0] := UInt<2>(1)
    T_167083[1] := UInt<2>(2)
    T_167083[2] := UInt<2>(3)
    wire T_167084 : UInt<2>[2]
    T_167084[0] := UInt<2>(2)
    T_167084[1] := UInt<2>(3)
    wire T_167085 : UInt<2>[1]
    T_167085[0] := UInt<2>(3)
    wire T_167086 : UInt<3>[3]
    T_167086[0] := UInt<3>(0)
    T_167086[1] := UInt<3>(1)
    T_167086[2] := UInt<3>(2)
    wire T_167087 : UInt<2>[2]
    T_167087[0] := UInt<2>(0)
    T_167087[1] := UInt<2>(1)
    wire T_167088 : UInt<2>[3]
    T_167088[0] := UInt<2>(1)
    T_167088[1] := UInt<2>(2)
    T_167088[2] := UInt<2>(3)
    wire T_167089 : UInt<2>[2]
    T_167089[0] := UInt<2>(2)
    T_167089[1] := UInt<2>(3)
    wire T_167090 : UInt<2>[1]
    T_167090[0] := UInt<2>(3)
    wire T_167091 : UInt<3>[3]
    T_167091[0] := UInt<3>(0)
    T_167091[1] := UInt<3>(1)
    T_167091[2] := UInt<3>(2)
    wire T_167092 : UInt<2>[2]
    T_167092[0] := UInt<2>(0)
    T_167092[1] := UInt<2>(1)
    wire T_167093 : UInt<2>[3]
    T_167093[0] := UInt<2>(1)
    T_167093[1] := UInt<2>(2)
    T_167093[2] := UInt<2>(3)
    wire T_167094 : UInt<2>[2]
    T_167094[0] := UInt<2>(2)
    T_167094[1] := UInt<2>(3)
    wire T_167095 : UInt<2>[1]
    T_167095[0] := UInt<2>(3)
    wire T_167096 : UInt<3>[3]
    T_167096[0] := UInt<3>(0)
    T_167096[1] := UInt<3>(1)
    T_167096[2] := UInt<3>(2)
    wire T_167097 : UInt<2>[2]
    T_167097[0] := UInt<2>(0)
    T_167097[1] := UInt<2>(1)
    wire T_167098 : UInt<2>[3]
    T_167098[0] := UInt<2>(1)
    T_167098[1] := UInt<2>(2)
    T_167098[2] := UInt<2>(3)
    wire T_167099 : UInt<2>[2]
    T_167099[0] := UInt<2>(2)
    T_167099[1] := UInt<2>(3)
    wire T_167100 : UInt<2>[1]
    T_167100[0] := UInt<2>(3)
    wire T_167101 : UInt<3>[3]
    T_167101[0] := UInt<3>(0)
    T_167101[1] := UInt<3>(1)
    T_167101[2] := UInt<3>(2)
    wire T_167102 : UInt<2>[2]
    T_167102[0] := UInt<2>(0)
    T_167102[1] := UInt<2>(1)
    wire T_167103 : UInt<2>[3]
    T_167103[0] := UInt<2>(1)
    T_167103[1] := UInt<2>(2)
    T_167103[2] := UInt<2>(3)
    wire T_167104 : UInt<2>[2]
    T_167104[0] := UInt<2>(2)
    T_167104[1] := UInt<2>(3)
    wire T_167105 : UInt<2>[1]
    T_167105[0] := UInt<2>(3)
    wire T_167106 : UInt<3>[3]
    T_167106[0] := UInt<3>(0)
    T_167106[1] := UInt<3>(1)
    T_167106[2] := UInt<3>(2)
    wire T_167107 : UInt<2>[2]
    T_167107[0] := UInt<2>(0)
    T_167107[1] := UInt<2>(1)
    wire T_167108 : UInt<2>[3]
    T_167108[0] := UInt<2>(1)
    T_167108[1] := UInt<2>(2)
    T_167108[2] := UInt<2>(3)
    wire T_167109 : UInt<2>[2]
    T_167109[0] := UInt<2>(2)
    T_167109[1] := UInt<2>(3)
    wire T_167110 : UInt<2>[1]
    T_167110[0] := UInt<2>(3)
    wire T_167111 : UInt<3>[3]
    T_167111[0] := UInt<3>(0)
    T_167111[1] := UInt<3>(1)
    T_167111[2] := UInt<3>(2)
    wire T_167112 : UInt<2>[2]
    T_167112[0] := UInt<2>(0)
    T_167112[1] := UInt<2>(1)
    wire T_167113 : UInt<2>[3]
    T_167113[0] := UInt<2>(1)
    T_167113[1] := UInt<2>(2)
    T_167113[2] := UInt<2>(3)
    wire T_167114 : UInt<2>[2]
    T_167114[0] := UInt<2>(2)
    T_167114[1] := UInt<2>(3)
    wire T_167115 : UInt<2>[1]
    T_167115[0] := UInt<2>(3)
    wire T_167116 : UInt<3>[3]
    T_167116[0] := UInt<3>(0)
    T_167116[1] := UInt<3>(1)
    T_167116[2] := UInt<3>(2)
    wire T_167117 : UInt<2>[2]
    T_167117[0] := UInt<2>(0)
    T_167117[1] := UInt<2>(1)
    wire T_167118 : UInt<2>[3]
    T_167118[0] := UInt<2>(1)
    T_167118[1] := UInt<2>(2)
    T_167118[2] := UInt<2>(3)
    wire T_167119 : UInt<2>[2]
    T_167119[0] := UInt<2>(2)
    T_167119[1] := UInt<2>(3)
    wire T_167120 : UInt<2>[1]
    T_167120[0] := UInt<2>(3)
    wire T_167121 : UInt<3>[3]
    T_167121[0] := UInt<3>(0)
    T_167121[1] := UInt<3>(1)
    T_167121[2] := UInt<3>(2)
    wire T_167122 : UInt<2>[2]
    T_167122[0] := UInt<2>(0)
    T_167122[1] := UInt<2>(1)
    wire T_167123 : UInt<2>[3]
    T_167123[0] := UInt<2>(1)
    T_167123[1] := UInt<2>(2)
    T_167123[2] := UInt<2>(3)
    wire T_167124 : UInt<2>[2]
    T_167124[0] := UInt<2>(2)
    T_167124[1] := UInt<2>(3)
    wire T_167125 : UInt<2>[1]
    T_167125[0] := UInt<2>(3)
    wire T_167126 : UInt<3>[3]
    T_167126[0] := UInt<3>(0)
    T_167126[1] := UInt<3>(1)
    T_167126[2] := UInt<3>(2)
    wire T_167127 : UInt<2>[2]
    T_167127[0] := UInt<2>(0)
    T_167127[1] := UInt<2>(1)
    wire T_167128 : UInt<2>[3]
    T_167128[0] := UInt<2>(1)
    T_167128[1] := UInt<2>(2)
    T_167128[2] := UInt<2>(3)
    wire T_167129 : UInt<2>[2]
    T_167129[0] := UInt<2>(2)
    T_167129[1] := UInt<2>(3)
    wire T_167130 : UInt<2>[1]
    T_167130[0] := UInt<2>(3)
    wire T_167131 : UInt<3>[3]
    T_167131[0] := UInt<3>(0)
    T_167131[1] := UInt<3>(1)
    T_167131[2] := UInt<3>(2)
    wire T_167132 : UInt<2>[2]
    T_167132[0] := UInt<2>(0)
    T_167132[1] := UInt<2>(1)
    wire T_167133 : UInt<2>[3]
    T_167133[0] := UInt<2>(1)
    T_167133[1] := UInt<2>(2)
    T_167133[2] := UInt<2>(3)
    wire T_167134 : UInt<2>[2]
    T_167134[0] := UInt<2>(2)
    T_167134[1] := UInt<2>(3)
    wire T_167135 : UInt<2>[1]
    T_167135[0] := UInt<2>(3)
    wire T_167136 : UInt<3>[3]
    T_167136[0] := UInt<3>(0)
    T_167136[1] := UInt<3>(1)
    T_167136[2] := UInt<3>(2)
    wire T_167137 : UInt<2>[2]
    T_167137[0] := UInt<2>(0)
    T_167137[1] := UInt<2>(1)
    wire T_167138 : UInt<2>[3]
    T_167138[0] := UInt<2>(1)
    T_167138[1] := UInt<2>(2)
    T_167138[2] := UInt<2>(3)
    wire T_167139 : UInt<2>[2]
    T_167139[0] := UInt<2>(2)
    T_167139[1] := UInt<2>(3)
    wire T_167140 : UInt<2>[1]
    T_167140[0] := UInt<2>(3)
    wire T_167141 : UInt<3>[3]
    T_167141[0] := UInt<3>(0)
    T_167141[1] := UInt<3>(1)
    T_167141[2] := UInt<3>(2)
    wire T_167142 : UInt<2>[2]
    T_167142[0] := UInt<2>(0)
    T_167142[1] := UInt<2>(1)
    wire T_167143 : UInt<2>[3]
    T_167143[0] := UInt<2>(1)
    T_167143[1] := UInt<2>(2)
    T_167143[2] := UInt<2>(3)
    wire T_167144 : UInt<2>[2]
    T_167144[0] := UInt<2>(2)
    T_167144[1] := UInt<2>(3)
    wire T_167145 : UInt<2>[1]
    T_167145[0] := UInt<2>(3)
    wire T_167146 : UInt<3>[3]
    T_167146[0] := UInt<3>(0)
    T_167146[1] := UInt<3>(1)
    T_167146[2] := UInt<3>(2)
    wire T_167147 : UInt<2>[2]
    T_167147[0] := UInt<2>(0)
    T_167147[1] := UInt<2>(1)
    wire T_167148 : UInt<2>[3]
    T_167148[0] := UInt<2>(1)
    T_167148[1] := UInt<2>(2)
    T_167148[2] := UInt<2>(3)
    wire T_167149 : UInt<2>[2]
    T_167149[0] := UInt<2>(2)
    T_167149[1] := UInt<2>(3)
    wire T_167150 : UInt<2>[1]
    T_167150[0] := UInt<2>(3)
    wire T_167151 : UInt<3>[3]
    T_167151[0] := UInt<3>(0)
    T_167151[1] := UInt<3>(1)
    T_167151[2] := UInt<3>(2)
    wire T_167152 : UInt<2>[2]
    T_167152[0] := UInt<2>(0)
    T_167152[1] := UInt<2>(1)
    wire T_167153 : UInt<2>[3]
    T_167153[0] := UInt<2>(1)
    T_167153[1] := UInt<2>(2)
    T_167153[2] := UInt<2>(3)
    wire T_167154 : UInt<2>[2]
    T_167154[0] := UInt<2>(2)
    T_167154[1] := UInt<2>(3)
    wire T_167155 : UInt<2>[1]
    T_167155[0] := UInt<2>(3)
    wire T_167156 : UInt<3>[3]
    T_167156[0] := UInt<3>(0)
    T_167156[1] := UInt<3>(1)
    T_167156[2] := UInt<3>(2)
    wire T_167157 : UInt<2>[2]
    T_167157[0] := UInt<2>(0)
    T_167157[1] := UInt<2>(1)
    wire T_167158 : UInt<2>[3]
    T_167158[0] := UInt<2>(1)
    T_167158[1] := UInt<2>(2)
    T_167158[2] := UInt<2>(3)
    wire T_167159 : UInt<2>[2]
    T_167159[0] := UInt<2>(2)
    T_167159[1] := UInt<2>(3)
    wire T_167160 : UInt<2>[1]
    T_167160[0] := UInt<2>(3)
    wire T_167161 : UInt<3>[3]
    T_167161[0] := UInt<3>(0)
    T_167161[1] := UInt<3>(1)
    T_167161[2] := UInt<3>(2)
    wire T_167162 : UInt<2>[2]
    T_167162[0] := UInt<2>(0)
    T_167162[1] := UInt<2>(1)
    wire T_167163 : UInt<2>[3]
    T_167163[0] := UInt<2>(1)
    T_167163[1] := UInt<2>(2)
    T_167163[2] := UInt<2>(3)
    wire T_167164 : UInt<2>[2]
    T_167164[0] := UInt<2>(2)
    T_167164[1] := UInt<2>(3)
    wire T_167165 : UInt<2>[1]
    T_167165[0] := UInt<2>(3)
    wire T_167166 : UInt<3>[3]
    T_167166[0] := UInt<3>(0)
    T_167166[1] := UInt<3>(1)
    T_167166[2] := UInt<3>(2)
    wire T_167167 : UInt<2>[2]
    T_167167[0] := UInt<2>(0)
    T_167167[1] := UInt<2>(1)
    wire T_167168 : UInt<2>[3]
    T_167168[0] := UInt<2>(1)
    T_167168[1] := UInt<2>(2)
    T_167168[2] := UInt<2>(3)
    wire T_167169 : UInt<2>[2]
    T_167169[0] := UInt<2>(2)
    T_167169[1] := UInt<2>(3)
    wire T_167170 : UInt<2>[1]
    T_167170[0] := UInt<2>(3)
    wire T_167171 : UInt<3>[3]
    T_167171[0] := UInt<3>(0)
    T_167171[1] := UInt<3>(1)
    T_167171[2] := UInt<3>(2)
    wire T_167172 : UInt<2>[2]
    T_167172[0] := UInt<2>(0)
    T_167172[1] := UInt<2>(1)
    wire T_167173 : UInt<2>[3]
    T_167173[0] := UInt<2>(1)
    T_167173[1] := UInt<2>(2)
    T_167173[2] := UInt<2>(3)
    wire T_167174 : UInt<2>[2]
    T_167174[0] := UInt<2>(2)
    T_167174[1] := UInt<2>(3)
    wire T_167175 : UInt<2>[1]
    T_167175[0] := UInt<2>(3)
    wire T_167176 : UInt<3>[3]
    T_167176[0] := UInt<3>(0)
    T_167176[1] := UInt<3>(1)
    T_167176[2] := UInt<3>(2)
    wire T_167177 : UInt<2>[2]
    T_167177[0] := UInt<2>(0)
    T_167177[1] := UInt<2>(1)
    wire T_167178 : UInt<2>[3]
    T_167178[0] := UInt<2>(1)
    T_167178[1] := UInt<2>(2)
    T_167178[2] := UInt<2>(3)
    wire T_167179 : UInt<2>[2]
    T_167179[0] := UInt<2>(2)
    T_167179[1] := UInt<2>(3)
    wire T_167180 : UInt<2>[1]
    T_167180[0] := UInt<2>(3)
    wire T_167181 : UInt<3>[3]
    T_167181[0] := UInt<3>(0)
    T_167181[1] := UInt<3>(1)
    T_167181[2] := UInt<3>(2)
    wire T_167182 : UInt<2>[2]
    T_167182[0] := UInt<2>(0)
    T_167182[1] := UInt<2>(1)
    wire T_167183 : UInt<2>[3]
    T_167183[0] := UInt<2>(1)
    T_167183[1] := UInt<2>(2)
    T_167183[2] := UInt<2>(3)
    wire T_167184 : UInt<2>[2]
    T_167184[0] := UInt<2>(2)
    T_167184[1] := UInt<2>(3)
    wire T_167185 : UInt<2>[1]
    T_167185[0] := UInt<2>(3)
    wire T_167186 : UInt<3>[3]
    T_167186[0] := UInt<3>(0)
    T_167186[1] := UInt<3>(1)
    T_167186[2] := UInt<3>(2)
    wire T_167187 : UInt<2>[2]
    T_167187[0] := UInt<2>(0)
    T_167187[1] := UInt<2>(1)
    wire T_167188 : UInt<2>[3]
    T_167188[0] := UInt<2>(1)
    T_167188[1] := UInt<2>(2)
    T_167188[2] := UInt<2>(3)
    wire T_167189 : UInt<2>[2]
    T_167189[0] := UInt<2>(2)
    T_167189[1] := UInt<2>(3)
    wire T_167190 : UInt<2>[1]
    T_167190[0] := UInt<2>(3)
    wire T_167191 : UInt<3>[3]
    T_167191[0] := UInt<3>(0)
    T_167191[1] := UInt<3>(1)
    T_167191[2] := UInt<3>(2)
    wire T_167192 : UInt<2>[2]
    T_167192[0] := UInt<2>(0)
    T_167192[1] := UInt<2>(1)
    wire T_167193 : UInt<2>[3]
    T_167193[0] := UInt<2>(1)
    T_167193[1] := UInt<2>(2)
    T_167193[2] := UInt<2>(3)
    wire T_167194 : UInt<2>[2]
    T_167194[0] := UInt<2>(2)
    T_167194[1] := UInt<2>(3)
    wire T_167195 : UInt<2>[1]
    T_167195[0] := UInt<2>(3)
    wire T_167196 : UInt<3>[3]
    T_167196[0] := UInt<3>(0)
    T_167196[1] := UInt<3>(1)
    T_167196[2] := UInt<3>(2)
    wire T_167197 : UInt<2>[2]
    T_167197[0] := UInt<2>(0)
    T_167197[1] := UInt<2>(1)
    wire T_167198 : UInt<2>[3]
    T_167198[0] := UInt<2>(1)
    T_167198[1] := UInt<2>(2)
    T_167198[2] := UInt<2>(3)
    wire T_167199 : UInt<2>[2]
    T_167199[0] := UInt<2>(2)
    T_167199[1] := UInt<2>(3)
    wire T_167200 : UInt<2>[1]
    T_167200[0] := UInt<2>(3)
    wire T_167201 : UInt<3>[3]
    T_167201[0] := UInt<3>(0)
    T_167201[1] := UInt<3>(1)
    T_167201[2] := UInt<3>(2)
    wire T_167202 : UInt<2>[2]
    T_167202[0] := UInt<2>(0)
    T_167202[1] := UInt<2>(1)
    wire T_167203 : UInt<2>[3]
    T_167203[0] := UInt<2>(1)
    T_167203[1] := UInt<2>(2)
    T_167203[2] := UInt<2>(3)
    wire T_167204 : UInt<2>[2]
    T_167204[0] := UInt<2>(2)
    T_167204[1] := UInt<2>(3)
    wire T_167205 : UInt<2>[1]
    T_167205[0] := UInt<2>(3)
    wire T_167206 : UInt<3>[3]
    T_167206[0] := UInt<3>(0)
    T_167206[1] := UInt<3>(1)
    T_167206[2] := UInt<3>(2)
    wire T_167207 : UInt<2>[2]
    T_167207[0] := UInt<2>(0)
    T_167207[1] := UInt<2>(1)
    wire T_167208 : UInt<2>[3]
    T_167208[0] := UInt<2>(1)
    T_167208[1] := UInt<2>(2)
    T_167208[2] := UInt<2>(3)
    wire T_167209 : UInt<2>[2]
    T_167209[0] := UInt<2>(2)
    T_167209[1] := UInt<2>(3)
    wire T_167210 : UInt<2>[1]
    T_167210[0] := UInt<2>(3)
    inst finisher of FinishUnit_25654
    finisher.grant <> network.grant
    network.finish <> finisher.finish
    wire T_167211 : UInt<3>[3]
    T_167211[0] := UInt<3>(0)
    T_167211[1] := UInt<3>(1)
    T_167211[2] := UInt<3>(2)
    wire T_167212 : UInt<2>[2]
    T_167212[0] := UInt<2>(0)
    T_167212[1] := UInt<2>(1)
    wire T_167213 : UInt<2>[3]
    T_167213[0] := UInt<2>(1)
    T_167213[1] := UInt<2>(2)
    T_167213[2] := UInt<2>(3)
    wire T_167214 : UInt<2>[2]
    T_167214[0] := UInt<2>(2)
    T_167214[1] := UInt<2>(3)
    wire T_167215 : UInt<2>[1]
    T_167215[0] := UInt<2>(3)
    wire T_167216 : UInt<3>[3]
    T_167216[0] := UInt<3>(0)
    T_167216[1] := UInt<3>(1)
    T_167216[2] := UInt<3>(2)
    wire T_167217 : UInt<2>[2]
    T_167217[0] := UInt<2>(0)
    T_167217[1] := UInt<2>(1)
    wire T_167218 : UInt<2>[3]
    T_167218[0] := UInt<2>(1)
    T_167218[1] := UInt<2>(2)
    T_167218[2] := UInt<2>(3)
    wire T_167219 : UInt<2>[2]
    T_167219[0] := UInt<2>(2)
    T_167219[1] := UInt<2>(3)
    wire T_167220 : UInt<2>[1]
    T_167220[0] := UInt<2>(3)
    wire T_167221 : UInt<3>[3]
    T_167221[0] := UInt<3>(0)
    T_167221[1] := UInt<3>(1)
    T_167221[2] := UInt<3>(2)
    wire T_167222 : UInt<2>[2]
    T_167222[0] := UInt<2>(0)
    T_167222[1] := UInt<2>(1)
    wire T_167223 : UInt<2>[3]
    T_167223[0] := UInt<2>(1)
    T_167223[1] := UInt<2>(2)
    T_167223[2] := UInt<2>(3)
    wire T_167224 : UInt<2>[2]
    T_167224[0] := UInt<2>(2)
    T_167224[1] := UInt<2>(3)
    wire T_167225 : UInt<2>[1]
    T_167225[0] := UInt<2>(3)
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    acq_with_header.bits.payload := client.acquire.bits
    acq_with_header.bits.header.src := UInt<1>(1)
    acq_with_header.bits.header.dst := UInt<1>(0)
    acq_with_header.valid := client.acquire.valid
    client.acquire.ready := acq_with_header.ready
    wire T_167226 : UInt<3>[3]
    T_167226[0] := UInt<3>(0)
    T_167226[1] := UInt<3>(1)
    T_167226[2] := UInt<3>(2)
    wire T_167227 : UInt<2>[2]
    T_167227[0] := UInt<2>(0)
    T_167227[1] := UInt<2>(1)
    wire T_167228 : UInt<2>[3]
    T_167228[0] := UInt<2>(1)
    T_167228[1] := UInt<2>(2)
    T_167228[2] := UInt<2>(3)
    wire T_167229 : UInt<2>[2]
    T_167229[0] := UInt<2>(2)
    T_167229[1] := UInt<2>(3)
    wire T_167230 : UInt<2>[1]
    T_167230[0] := UInt<2>(3)
    wire T_167231 : UInt<3>[3]
    T_167231[0] := UInt<3>(0)
    T_167231[1] := UInt<3>(1)
    T_167231[2] := UInt<3>(2)
    wire T_167232 : UInt<2>[2]
    T_167232[0] := UInt<2>(0)
    T_167232[1] := UInt<2>(1)
    wire T_167233 : UInt<2>[3]
    T_167233[0] := UInt<2>(1)
    T_167233[1] := UInt<2>(2)
    T_167233[2] := UInt<2>(3)
    wire T_167234 : UInt<2>[2]
    T_167234[0] := UInt<2>(2)
    T_167234[1] := UInt<2>(3)
    wire T_167235 : UInt<2>[1]
    T_167235[0] := UInt<2>(3)
    wire T_167236 : UInt<3>[3]
    T_167236[0] := UInt<3>(0)
    T_167236[1] := UInt<3>(1)
    T_167236[2] := UInt<3>(2)
    wire T_167237 : UInt<2>[2]
    T_167237[0] := UInt<2>(0)
    T_167237[1] := UInt<2>(1)
    wire T_167238 : UInt<2>[3]
    T_167238[0] := UInt<2>(1)
    T_167238[1] := UInt<2>(2)
    T_167238[2] := UInt<2>(3)
    wire T_167239 : UInt<2>[2]
    T_167239[0] := UInt<2>(2)
    T_167239[1] := UInt<2>(3)
    wire T_167240 : UInt<2>[1]
    T_167240[0] := UInt<2>(3)
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    rel_with_header.bits.payload := client.release.bits
    rel_with_header.bits.header.src := UInt<1>(1)
    rel_with_header.bits.header.dst := UInt<1>(0)
    rel_with_header.valid := client.release.valid
    client.release.ready := rel_with_header.ready
    wire T_167241 : UInt<3>[3]
    T_167241[0] := UInt<3>(0)
    T_167241[1] := UInt<3>(1)
    T_167241[2] := UInt<3>(2)
    wire T_167242 : UInt<2>[2]
    T_167242[0] := UInt<2>(0)
    T_167242[1] := UInt<2>(1)
    wire T_167243 : UInt<2>[3]
    T_167243[0] := UInt<2>(1)
    T_167243[1] := UInt<2>(2)
    T_167243[2] := UInt<2>(3)
    wire T_167244 : UInt<2>[2]
    T_167244[0] := UInt<2>(2)
    T_167244[1] := UInt<2>(3)
    wire T_167245 : UInt<2>[1]
    T_167245[0] := UInt<2>(3)
    wire T_167246 : UInt<3>[3]
    T_167246[0] := UInt<3>(0)
    T_167246[1] := UInt<3>(1)
    T_167246[2] := UInt<3>(2)
    wire T_167247 : UInt<2>[2]
    T_167247[0] := UInt<2>(0)
    T_167247[1] := UInt<2>(1)
    wire T_167248 : UInt<2>[3]
    T_167248[0] := UInt<2>(1)
    T_167248[1] := UInt<2>(2)
    T_167248[2] := UInt<2>(3)
    wire T_167249 : UInt<2>[2]
    T_167249[0] := UInt<2>(2)
    T_167249[1] := UInt<2>(3)
    wire T_167250 : UInt<2>[1]
    T_167250[0] := UInt<2>(3)
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header.valid := network.probe.valid
    prb_without_header.bits := network.probe.bits.payload
    network.probe.ready := prb_without_header.ready
    network.acquire.bits := acq_with_header.bits
    node T_167251 = and(acq_with_header.valid, finisher.ready)
    network.acquire.valid := T_167251
    node T_167252 = and(network.acquire.ready, finisher.ready)
    acq_with_header.ready := T_167252
    network.release <> rel_with_header
    client.probe <> prb_without_header
    client.grant <> finisher.refill
  module Queue_28995 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output count : UInt<2>
    
    wire T_167253 : UInt<3>[3]
    T_167253[0] := UInt<3>(0)
    T_167253[1] := UInt<3>(1)
    T_167253[2] := UInt<3>(2)
    wire T_167254 : UInt<2>[2]
    T_167254[0] := UInt<2>(0)
    T_167254[1] := UInt<2>(1)
    wire T_167255 : UInt<2>[3]
    T_167255[0] := UInt<2>(1)
    T_167255[1] := UInt<2>(2)
    T_167255[2] := UInt<2>(3)
    wire T_167256 : UInt<2>[2]
    T_167256[0] := UInt<2>(2)
    T_167256[1] := UInt<2>(3)
    wire T_167257 : UInt<2>[1]
    T_167257[0] := UInt<2>(3)
    wire T_167258 : UInt<3>[3]
    T_167258[0] := UInt<3>(0)
    T_167258[1] := UInt<3>(1)
    T_167258[2] := UInt<3>(2)
    wire T_167259 : UInt<2>[2]
    T_167259[0] := UInt<2>(0)
    T_167259[1] := UInt<2>(1)
    wire T_167260 : UInt<2>[3]
    T_167260[0] := UInt<2>(1)
    T_167260[1] := UInt<2>(2)
    T_167260[2] := UInt<2>(3)
    wire T_167261 : UInt<2>[2]
    T_167261[0] := UInt<2>(2)
    T_167261[1] := UInt<2>(3)
    wire T_167262 : UInt<2>[1]
    T_167262[0] := UInt<2>(3)
    wire T_167263 : UInt<3>[3]
    T_167263[0] := UInt<3>(0)
    T_167263[1] := UInt<3>(1)
    T_167263[2] := UInt<3>(2)
    wire T_167264 : UInt<2>[2]
    T_167264[0] := UInt<2>(0)
    T_167264[1] := UInt<2>(1)
    wire T_167265 : UInt<2>[3]
    T_167265[0] := UInt<2>(1)
    T_167265[1] := UInt<2>(2)
    T_167265[2] := UInt<2>(3)
    wire T_167266 : UInt<2>[2]
    T_167266[0] := UInt<2>(2)
    T_167266[1] := UInt<2>(3)
    wire T_167267 : UInt<2>[1]
    T_167267[0] := UInt<2>(3)
    wire T_167268 : UInt<3>[3]
    T_167268[0] := UInt<3>(0)
    T_167268[1] := UInt<3>(1)
    T_167268[2] := UInt<3>(2)
    wire T_167269 : UInt<2>[2]
    T_167269[0] := UInt<2>(0)
    T_167269[1] := UInt<2>(1)
    wire T_167270 : UInt<2>[3]
    T_167270[0] := UInt<2>(1)
    T_167270[1] := UInt<2>(2)
    T_167270[2] := UInt<2>(3)
    wire T_167271 : UInt<2>[2]
    T_167271[0] := UInt<2>(2)
    T_167271[1] := UInt<2>(3)
    wire T_167272 : UInt<2>[1]
    T_167272[0] := UInt<2>(3)
    wire T_167273 : UInt<3>[3]
    T_167273[0] := UInt<3>(0)
    T_167273[1] := UInt<3>(1)
    T_167273[2] := UInt<3>(2)
    wire T_167274 : UInt<2>[2]
    T_167274[0] := UInt<2>(0)
    T_167274[1] := UInt<2>(1)
    wire T_167275 : UInt<2>[3]
    T_167275[0] := UInt<2>(1)
    T_167275[1] := UInt<2>(2)
    T_167275[2] := UInt<2>(3)
    wire T_167276 : UInt<2>[2]
    T_167276[0] := UInt<2>(2)
    T_167276[1] := UInt<2>(3)
    wire T_167277 : UInt<2>[1]
    T_167277[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2]
    reg T_167278 : UInt<1>
    onreset T_167278 := UInt<1>(0)
    reg T_167279 : UInt<1>
    onreset T_167279 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_167278, T_167279)
    node T_167280 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_167280)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_167281 = and(enq.ready, enq.valid)
    node T_167282 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_167281, T_167282)
    node T_167283 = and(deq.ready, deq.valid)
    node T_167284 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_167283, T_167284)
    when do_enq : 
      wire T_167285 : UInt<3>[3]
      T_167285[0] := UInt<3>(0)
      T_167285[1] := UInt<3>(1)
      T_167285[2] := UInt<3>(2)
      wire T_167286 : UInt<2>[2]
      T_167286[0] := UInt<2>(0)
      T_167286[1] := UInt<2>(1)
      wire T_167287 : UInt<2>[3]
      T_167287[0] := UInt<2>(1)
      T_167287[1] := UInt<2>(2)
      T_167287[2] := UInt<2>(3)
      wire T_167288 : UInt<2>[2]
      T_167288[0] := UInt<2>(2)
      T_167288[1] := UInt<2>(3)
      wire T_167289 : UInt<2>[1]
      T_167289[0] := UInt<2>(3)
      accessor T_167290 = ram[T_167278]
      T_167290 := enq.bits
      node T_167291 = eq(T_167278, UInt<1>(1))
      node T_167292 = and(UInt<1>(0), T_167291)
      node T_167293 = addw(T_167278, UInt<1>(1))
      wire T_167294 : UInt<1>
      T_167294 := T_167293
      when T_167292 : T_167294 := UInt<1>(0)
      T_167278 := T_167294
    when do_deq : 
      node T_167295 = eq(T_167279, UInt<1>(1))
      node T_167296 = and(UInt<1>(0), T_167295)
      node T_167297 = addw(T_167279, UInt<1>(1))
      wire T_167298 : UInt<1>
      T_167298 := T_167297
      when T_167296 : T_167298 := UInt<1>(0)
      T_167279 := T_167298
    
    node T_167299 = neq(do_enq, do_deq)
    when T_167299 : maybe_full := do_enq
    node T_167300 = eq(empty, UInt<1>(0))
    node T_167301 = and(UInt<1>(0), enq.valid)
    node T_167302 = or(T_167300, T_167301)
    deq.valid := T_167302
    node T_167303 = eq(full, UInt<1>(0))
    node T_167304 = and(UInt<1>(0), deq.ready)
    node T_167305 = or(T_167303, T_167304)
    enq.ready := T_167305
    wire T_167306 : UInt<3>[3]
    T_167306[0] := UInt<3>(0)
    T_167306[1] := UInt<3>(1)
    T_167306[2] := UInt<3>(2)
    wire T_167307 : UInt<2>[2]
    T_167307[0] := UInt<2>(0)
    T_167307[1] := UInt<2>(1)
    wire T_167308 : UInt<2>[3]
    T_167308[0] := UInt<2>(1)
    T_167308[1] := UInt<2>(2)
    T_167308[2] := UInt<2>(3)
    wire T_167309 : UInt<2>[2]
    T_167309[0] := UInt<2>(2)
    T_167309[1] := UInt<2>(3)
    wire T_167310 : UInt<2>[1]
    T_167310[0] := UInt<2>(3)
    accessor T_167311 = ram[T_167279]
    wire T_167312 : UInt<3>[3]
    T_167312[0] := UInt<3>(0)
    T_167312[1] := UInt<3>(1)
    T_167312[2] := UInt<3>(2)
    wire T_167313 : UInt<2>[2]
    T_167313[0] := UInt<2>(0)
    T_167313[1] := UInt<2>(1)
    wire T_167314 : UInt<2>[3]
    T_167314[0] := UInt<2>(1)
    T_167314[1] := UInt<2>(2)
    T_167314[2] := UInt<2>(3)
    wire T_167315 : UInt<2>[2]
    T_167315[0] := UInt<2>(2)
    T_167315[1] := UInt<2>(3)
    wire T_167316 : UInt<2>[1]
    T_167316[0] := UInt<2>(3)
    wire T_167317 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    T_167317 := T_167311
    when maybe_flow : T_167317 := enq.bits
    deq.bits := T_167317
    node ptr_diff = subw(T_167278, T_167279)
    node T_167318 = and(maybe_full, ptr_match)
    node T_167319 = cat(T_167318, ptr_diff)
    count := T_167319
  module Queue_29634 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}
    output count : UInt<2>
    
    wire T_167320 : UInt<3>[3]
    T_167320[0] := UInt<3>(0)
    T_167320[1] := UInt<3>(1)
    T_167320[2] := UInt<3>(2)
    wire T_167321 : UInt<2>[2]
    T_167321[0] := UInt<2>(0)
    T_167321[1] := UInt<2>(1)
    wire T_167322 : UInt<2>[3]
    T_167322[0] := UInt<2>(1)
    T_167322[1] := UInt<2>(2)
    T_167322[2] := UInt<2>(3)
    wire T_167323 : UInt<2>[2]
    T_167323[0] := UInt<2>(2)
    T_167323[1] := UInt<2>(3)
    wire T_167324 : UInt<2>[1]
    T_167324[0] := UInt<2>(3)
    wire T_167325 : UInt<3>[3]
    T_167325[0] := UInt<3>(0)
    T_167325[1] := UInt<3>(1)
    T_167325[2] := UInt<3>(2)
    wire T_167326 : UInt<2>[2]
    T_167326[0] := UInt<2>(0)
    T_167326[1] := UInt<2>(1)
    wire T_167327 : UInt<2>[3]
    T_167327[0] := UInt<2>(1)
    T_167327[1] := UInt<2>(2)
    T_167327[2] := UInt<2>(3)
    wire T_167328 : UInt<2>[2]
    T_167328[0] := UInt<2>(2)
    T_167328[1] := UInt<2>(3)
    wire T_167329 : UInt<2>[1]
    T_167329[0] := UInt<2>(3)
    wire T_167330 : UInt<3>[3]
    T_167330[0] := UInt<3>(0)
    T_167330[1] := UInt<3>(1)
    T_167330[2] := UInt<3>(2)
    wire T_167331 : UInt<2>[2]
    T_167331[0] := UInt<2>(0)
    T_167331[1] := UInt<2>(1)
    wire T_167332 : UInt<2>[3]
    T_167332[0] := UInt<2>(1)
    T_167332[1] := UInt<2>(2)
    T_167332[2] := UInt<2>(3)
    wire T_167333 : UInt<2>[2]
    T_167333[0] := UInt<2>(2)
    T_167333[1] := UInt<2>(3)
    wire T_167334 : UInt<2>[1]
    T_167334[0] := UInt<2>(3)
    wire T_167335 : UInt<3>[3]
    T_167335[0] := UInt<3>(0)
    T_167335[1] := UInt<3>(1)
    T_167335[2] := UInt<3>(2)
    wire T_167336 : UInt<2>[2]
    T_167336[0] := UInt<2>(0)
    T_167336[1] := UInt<2>(1)
    wire T_167337 : UInt<2>[3]
    T_167337[0] := UInt<2>(1)
    T_167337[1] := UInt<2>(2)
    T_167337[2] := UInt<2>(3)
    wire T_167338 : UInt<2>[2]
    T_167338[0] := UInt<2>(2)
    T_167338[1] := UInt<2>(3)
    wire T_167339 : UInt<2>[1]
    T_167339[0] := UInt<2>(3)
    wire T_167340 : UInt<3>[3]
    T_167340[0] := UInt<3>(0)
    T_167340[1] := UInt<3>(1)
    T_167340[2] := UInt<3>(2)
    wire T_167341 : UInt<2>[2]
    T_167341[0] := UInt<2>(0)
    T_167341[1] := UInt<2>(1)
    wire T_167342 : UInt<2>[3]
    T_167342[0] := UInt<2>(1)
    T_167342[1] := UInt<2>(2)
    T_167342[2] := UInt<2>(3)
    wire T_167343 : UInt<2>[2]
    T_167343[0] := UInt<2>(2)
    T_167343[1] := UInt<2>(3)
    wire T_167344 : UInt<2>[1]
    T_167344[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2]
    reg T_167345 : UInt<1>
    onreset T_167345 := UInt<1>(0)
    reg T_167346 : UInt<1>
    onreset T_167346 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_167345, T_167346)
    node T_167347 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_167347)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_167348 = and(enq.ready, enq.valid)
    node T_167349 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_167348, T_167349)
    node T_167350 = and(deq.ready, deq.valid)
    node T_167351 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_167350, T_167351)
    when do_enq : 
      wire T_167352 : UInt<3>[3]
      T_167352[0] := UInt<3>(0)
      T_167352[1] := UInt<3>(1)
      T_167352[2] := UInt<3>(2)
      wire T_167353 : UInt<2>[2]
      T_167353[0] := UInt<2>(0)
      T_167353[1] := UInt<2>(1)
      wire T_167354 : UInt<2>[3]
      T_167354[0] := UInt<2>(1)
      T_167354[1] := UInt<2>(2)
      T_167354[2] := UInt<2>(3)
      wire T_167355 : UInt<2>[2]
      T_167355[0] := UInt<2>(2)
      T_167355[1] := UInt<2>(3)
      wire T_167356 : UInt<2>[1]
      T_167356[0] := UInt<2>(3)
      accessor T_167357 = ram[T_167345]
      T_167357 := enq.bits
      node T_167358 = eq(T_167345, UInt<1>(1))
      node T_167359 = and(UInt<1>(0), T_167358)
      node T_167360 = addw(T_167345, UInt<1>(1))
      wire T_167361 : UInt<1>
      T_167361 := T_167360
      when T_167359 : T_167361 := UInt<1>(0)
      T_167345 := T_167361
    when do_deq : 
      node T_167362 = eq(T_167346, UInt<1>(1))
      node T_167363 = and(UInt<1>(0), T_167362)
      node T_167364 = addw(T_167346, UInt<1>(1))
      wire T_167365 : UInt<1>
      T_167365 := T_167364
      when T_167363 : T_167365 := UInt<1>(0)
      T_167346 := T_167365
    
    node T_167366 = neq(do_enq, do_deq)
    when T_167366 : maybe_full := do_enq
    node T_167367 = eq(empty, UInt<1>(0))
    node T_167368 = and(UInt<1>(0), enq.valid)
    node T_167369 = or(T_167367, T_167368)
    deq.valid := T_167369
    node T_167370 = eq(full, UInt<1>(0))
    node T_167371 = and(UInt<1>(0), deq.ready)
    node T_167372 = or(T_167370, T_167371)
    enq.ready := T_167372
    wire T_167373 : UInt<3>[3]
    T_167373[0] := UInt<3>(0)
    T_167373[1] := UInt<3>(1)
    T_167373[2] := UInt<3>(2)
    wire T_167374 : UInt<2>[2]
    T_167374[0] := UInt<2>(0)
    T_167374[1] := UInt<2>(1)
    wire T_167375 : UInt<2>[3]
    T_167375[0] := UInt<2>(1)
    T_167375[1] := UInt<2>(2)
    T_167375[2] := UInt<2>(3)
    wire T_167376 : UInt<2>[2]
    T_167376[0] := UInt<2>(2)
    T_167376[1] := UInt<2>(3)
    wire T_167377 : UInt<2>[1]
    T_167377[0] := UInt<2>(3)
    accessor T_167378 = ram[T_167346]
    wire T_167379 : UInt<3>[3]
    T_167379[0] := UInt<3>(0)
    T_167379[1] := UInt<3>(1)
    T_167379[2] := UInt<3>(2)
    wire T_167380 : UInt<2>[2]
    T_167380[0] := UInt<2>(0)
    T_167380[1] := UInt<2>(1)
    wire T_167381 : UInt<2>[3]
    T_167381[0] := UInt<2>(1)
    T_167381[1] := UInt<2>(2)
    T_167381[2] := UInt<2>(3)
    wire T_167382 : UInt<2>[2]
    T_167382[0] := UInt<2>(2)
    T_167382[1] := UInt<2>(3)
    wire T_167383 : UInt<2>[1]
    T_167383[0] := UInt<2>(3)
    wire T_167384 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}
    T_167384 := T_167378
    when maybe_flow : T_167384 := enq.bits
    deq.bits := T_167384
    node ptr_diff = subw(T_167345, T_167346)
    node T_167385 = and(maybe_full, ptr_match)
    node T_167386 = cat(T_167385, ptr_diff)
    count := T_167386
  module Queue_30309 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output count : UInt<2>
    
    wire T_167387 : UInt<3>[3]
    T_167387[0] := UInt<3>(0)
    T_167387[1] := UInt<3>(1)
    T_167387[2] := UInt<3>(2)
    wire T_167388 : UInt<2>[2]
    T_167388[0] := UInt<2>(0)
    T_167388[1] := UInt<2>(1)
    wire T_167389 : UInt<2>[3]
    T_167389[0] := UInt<2>(1)
    T_167389[1] := UInt<2>(2)
    T_167389[2] := UInt<2>(3)
    wire T_167390 : UInt<2>[2]
    T_167390[0] := UInt<2>(2)
    T_167390[1] := UInt<2>(3)
    wire T_167391 : UInt<2>[1]
    T_167391[0] := UInt<2>(3)
    wire T_167392 : UInt<3>[3]
    T_167392[0] := UInt<3>(0)
    T_167392[1] := UInt<3>(1)
    T_167392[2] := UInt<3>(2)
    wire T_167393 : UInt<2>[2]
    T_167393[0] := UInt<2>(0)
    T_167393[1] := UInt<2>(1)
    wire T_167394 : UInt<2>[3]
    T_167394[0] := UInt<2>(1)
    T_167394[1] := UInt<2>(2)
    T_167394[2] := UInt<2>(3)
    wire T_167395 : UInt<2>[2]
    T_167395[0] := UInt<2>(2)
    T_167395[1] := UInt<2>(3)
    wire T_167396 : UInt<2>[1]
    T_167396[0] := UInt<2>(3)
    wire T_167397 : UInt<3>[3]
    T_167397[0] := UInt<3>(0)
    T_167397[1] := UInt<3>(1)
    T_167397[2] := UInt<3>(2)
    wire T_167398 : UInt<2>[2]
    T_167398[0] := UInt<2>(0)
    T_167398[1] := UInt<2>(1)
    wire T_167399 : UInt<2>[3]
    T_167399[0] := UInt<2>(1)
    T_167399[1] := UInt<2>(2)
    T_167399[2] := UInt<2>(3)
    wire T_167400 : UInt<2>[2]
    T_167400[0] := UInt<2>(2)
    T_167400[1] := UInt<2>(3)
    wire T_167401 : UInt<2>[1]
    T_167401[0] := UInt<2>(3)
    wire T_167402 : UInt<3>[3]
    T_167402[0] := UInt<3>(0)
    T_167402[1] := UInt<3>(1)
    T_167402[2] := UInt<3>(2)
    wire T_167403 : UInt<2>[2]
    T_167403[0] := UInt<2>(0)
    T_167403[1] := UInt<2>(1)
    wire T_167404 : UInt<2>[3]
    T_167404[0] := UInt<2>(1)
    T_167404[1] := UInt<2>(2)
    T_167404[2] := UInt<2>(3)
    wire T_167405 : UInt<2>[2]
    T_167405[0] := UInt<2>(2)
    T_167405[1] := UInt<2>(3)
    wire T_167406 : UInt<2>[1]
    T_167406[0] := UInt<2>(3)
    wire T_167407 : UInt<3>[3]
    T_167407[0] := UInt<3>(0)
    T_167407[1] := UInt<3>(1)
    T_167407[2] := UInt<3>(2)
    wire T_167408 : UInt<2>[2]
    T_167408[0] := UInt<2>(0)
    T_167408[1] := UInt<2>(1)
    wire T_167409 : UInt<2>[3]
    T_167409[0] := UInt<2>(1)
    T_167409[1] := UInt<2>(2)
    T_167409[2] := UInt<2>(3)
    wire T_167410 : UInt<2>[2]
    T_167410[0] := UInt<2>(2)
    T_167410[1] := UInt<2>(3)
    wire T_167411 : UInt<2>[1]
    T_167411[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2]
    reg T_167412 : UInt<1>
    onreset T_167412 := UInt<1>(0)
    reg T_167413 : UInt<1>
    onreset T_167413 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_167412, T_167413)
    node T_167414 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_167414)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_167415 = and(enq.ready, enq.valid)
    node T_167416 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_167415, T_167416)
    node T_167417 = and(deq.ready, deq.valid)
    node T_167418 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_167417, T_167418)
    when do_enq : 
      wire T_167419 : UInt<3>[3]
      T_167419[0] := UInt<3>(0)
      T_167419[1] := UInt<3>(1)
      T_167419[2] := UInt<3>(2)
      wire T_167420 : UInt<2>[2]
      T_167420[0] := UInt<2>(0)
      T_167420[1] := UInt<2>(1)
      wire T_167421 : UInt<2>[3]
      T_167421[0] := UInt<2>(1)
      T_167421[1] := UInt<2>(2)
      T_167421[2] := UInt<2>(3)
      wire T_167422 : UInt<2>[2]
      T_167422[0] := UInt<2>(2)
      T_167422[1] := UInt<2>(3)
      wire T_167423 : UInt<2>[1]
      T_167423[0] := UInt<2>(3)
      accessor T_167424 = ram[T_167412]
      T_167424 := enq.bits
      node T_167425 = eq(T_167412, UInt<1>(1))
      node T_167426 = and(UInt<1>(0), T_167425)
      node T_167427 = addw(T_167412, UInt<1>(1))
      wire T_167428 : UInt<1>
      T_167428 := T_167427
      when T_167426 : T_167428 := UInt<1>(0)
      T_167412 := T_167428
    when do_deq : 
      node T_167429 = eq(T_167413, UInt<1>(1))
      node T_167430 = and(UInt<1>(0), T_167429)
      node T_167431 = addw(T_167413, UInt<1>(1))
      wire T_167432 : UInt<1>
      T_167432 := T_167431
      when T_167430 : T_167432 := UInt<1>(0)
      T_167413 := T_167432
    
    node T_167433 = neq(do_enq, do_deq)
    when T_167433 : maybe_full := do_enq
    node T_167434 = eq(empty, UInt<1>(0))
    node T_167435 = and(UInt<1>(0), enq.valid)
    node T_167436 = or(T_167434, T_167435)
    deq.valid := T_167436
    node T_167437 = eq(full, UInt<1>(0))
    node T_167438 = and(UInt<1>(0), deq.ready)
    node T_167439 = or(T_167437, T_167438)
    enq.ready := T_167439
    wire T_167440 : UInt<3>[3]
    T_167440[0] := UInt<3>(0)
    T_167440[1] := UInt<3>(1)
    T_167440[2] := UInt<3>(2)
    wire T_167441 : UInt<2>[2]
    T_167441[0] := UInt<2>(0)
    T_167441[1] := UInt<2>(1)
    wire T_167442 : UInt<2>[3]
    T_167442[0] := UInt<2>(1)
    T_167442[1] := UInt<2>(2)
    T_167442[2] := UInt<2>(3)
    wire T_167443 : UInt<2>[2]
    T_167443[0] := UInt<2>(2)
    T_167443[1] := UInt<2>(3)
    wire T_167444 : UInt<2>[1]
    T_167444[0] := UInt<2>(3)
    accessor T_167445 = ram[T_167413]
    wire T_167446 : UInt<3>[3]
    T_167446[0] := UInt<3>(0)
    T_167446[1] := UInt<3>(1)
    T_167446[2] := UInt<3>(2)
    wire T_167447 : UInt<2>[2]
    T_167447[0] := UInt<2>(0)
    T_167447[1] := UInt<2>(1)
    wire T_167448 : UInt<2>[3]
    T_167448[0] := UInt<2>(1)
    T_167448[1] := UInt<2>(2)
    T_167448[2] := UInt<2>(3)
    wire T_167449 : UInt<2>[2]
    T_167449[0] := UInt<2>(2)
    T_167449[1] := UInt<2>(3)
    wire T_167450 : UInt<2>[1]
    T_167450[0] := UInt<2>(3)
    wire T_167451 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    T_167451 := T_167445
    when maybe_flow : T_167451 := enq.bits
    deq.bits := T_167451
    node ptr_diff = subw(T_167412, T_167413)
    node T_167452 = and(maybe_full, ptr_match)
    node T_167453 = cat(T_167452, ptr_diff)
    count := T_167453
  module Queue_30984 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output count : UInt<2>
    
    wire T_167454 : UInt<3>[3]
    T_167454[0] := UInt<3>(0)
    T_167454[1] := UInt<3>(1)
    T_167454[2] := UInt<3>(2)
    wire T_167455 : UInt<2>[2]
    T_167455[0] := UInt<2>(0)
    T_167455[1] := UInt<2>(1)
    wire T_167456 : UInt<2>[3]
    T_167456[0] := UInt<2>(1)
    T_167456[1] := UInt<2>(2)
    T_167456[2] := UInt<2>(3)
    wire T_167457 : UInt<2>[2]
    T_167457[0] := UInt<2>(2)
    T_167457[1] := UInt<2>(3)
    wire T_167458 : UInt<2>[1]
    T_167458[0] := UInt<2>(3)
    wire T_167459 : UInt<3>[3]
    T_167459[0] := UInt<3>(0)
    T_167459[1] := UInt<3>(1)
    T_167459[2] := UInt<3>(2)
    wire T_167460 : UInt<2>[2]
    T_167460[0] := UInt<2>(0)
    T_167460[1] := UInt<2>(1)
    wire T_167461 : UInt<2>[3]
    T_167461[0] := UInt<2>(1)
    T_167461[1] := UInt<2>(2)
    T_167461[2] := UInt<2>(3)
    wire T_167462 : UInt<2>[2]
    T_167462[0] := UInt<2>(2)
    T_167462[1] := UInt<2>(3)
    wire T_167463 : UInt<2>[1]
    T_167463[0] := UInt<2>(3)
    wire T_167464 : UInt<3>[3]
    T_167464[0] := UInt<3>(0)
    T_167464[1] := UInt<3>(1)
    T_167464[2] := UInt<3>(2)
    wire T_167465 : UInt<2>[2]
    T_167465[0] := UInt<2>(0)
    T_167465[1] := UInt<2>(1)
    wire T_167466 : UInt<2>[3]
    T_167466[0] := UInt<2>(1)
    T_167466[1] := UInt<2>(2)
    T_167466[2] := UInt<2>(3)
    wire T_167467 : UInt<2>[2]
    T_167467[0] := UInt<2>(2)
    T_167467[1] := UInt<2>(3)
    wire T_167468 : UInt<2>[1]
    T_167468[0] := UInt<2>(3)
    wire T_167469 : UInt<3>[3]
    T_167469[0] := UInt<3>(0)
    T_167469[1] := UInt<3>(1)
    T_167469[2] := UInt<3>(2)
    wire T_167470 : UInt<2>[2]
    T_167470[0] := UInt<2>(0)
    T_167470[1] := UInt<2>(1)
    wire T_167471 : UInt<2>[3]
    T_167471[0] := UInt<2>(1)
    T_167471[1] := UInt<2>(2)
    T_167471[2] := UInt<2>(3)
    wire T_167472 : UInt<2>[2]
    T_167472[0] := UInt<2>(2)
    T_167472[1] := UInt<2>(3)
    wire T_167473 : UInt<2>[1]
    T_167473[0] := UInt<2>(3)
    wire T_167474 : UInt<3>[3]
    T_167474[0] := UInt<3>(0)
    T_167474[1] := UInt<3>(1)
    T_167474[2] := UInt<3>(2)
    wire T_167475 : UInt<2>[2]
    T_167475[0] := UInt<2>(0)
    T_167475[1] := UInt<2>(1)
    wire T_167476 : UInt<2>[3]
    T_167476[0] := UInt<2>(1)
    T_167476[1] := UInt<2>(2)
    T_167476[2] := UInt<2>(3)
    wire T_167477 : UInt<2>[2]
    T_167477[0] := UInt<2>(2)
    T_167477[1] := UInt<2>(3)
    wire T_167478 : UInt<2>[1]
    T_167478[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}[2]
    reg T_167479 : UInt<1>
    onreset T_167479 := UInt<1>(0)
    reg T_167480 : UInt<1>
    onreset T_167480 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_167479, T_167480)
    node T_167481 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_167481)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_167482 = and(enq.ready, enq.valid)
    node T_167483 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_167482, T_167483)
    node T_167484 = and(deq.ready, deq.valid)
    node T_167485 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_167484, T_167485)
    when do_enq : 
      wire T_167486 : UInt<3>[3]
      T_167486[0] := UInt<3>(0)
      T_167486[1] := UInt<3>(1)
      T_167486[2] := UInt<3>(2)
      wire T_167487 : UInt<2>[2]
      T_167487[0] := UInt<2>(0)
      T_167487[1] := UInt<2>(1)
      wire T_167488 : UInt<2>[3]
      T_167488[0] := UInt<2>(1)
      T_167488[1] := UInt<2>(2)
      T_167488[2] := UInt<2>(3)
      wire T_167489 : UInt<2>[2]
      T_167489[0] := UInt<2>(2)
      T_167489[1] := UInt<2>(3)
      wire T_167490 : UInt<2>[1]
      T_167490[0] := UInt<2>(3)
      accessor T_167491 = ram[T_167479]
      T_167491 := enq.bits
      node T_167492 = eq(T_167479, UInt<1>(1))
      node T_167493 = and(UInt<1>(0), T_167492)
      node T_167494 = addw(T_167479, UInt<1>(1))
      wire T_167495 : UInt<1>
      T_167495 := T_167494
      when T_167493 : T_167495 := UInt<1>(0)
      T_167479 := T_167495
    when do_deq : 
      node T_167496 = eq(T_167480, UInt<1>(1))
      node T_167497 = and(UInt<1>(0), T_167496)
      node T_167498 = addw(T_167480, UInt<1>(1))
      wire T_167499 : UInt<1>
      T_167499 := T_167498
      when T_167497 : T_167499 := UInt<1>(0)
      T_167480 := T_167499
    
    node T_167500 = neq(do_enq, do_deq)
    when T_167500 : maybe_full := do_enq
    node T_167501 = eq(empty, UInt<1>(0))
    node T_167502 = and(UInt<1>(0), enq.valid)
    node T_167503 = or(T_167501, T_167502)
    deq.valid := T_167503
    node T_167504 = eq(full, UInt<1>(0))
    node T_167505 = and(UInt<1>(0), deq.ready)
    node T_167506 = or(T_167504, T_167505)
    enq.ready := T_167506
    wire T_167507 : UInt<3>[3]
    T_167507[0] := UInt<3>(0)
    T_167507[1] := UInt<3>(1)
    T_167507[2] := UInt<3>(2)
    wire T_167508 : UInt<2>[2]
    T_167508[0] := UInt<2>(0)
    T_167508[1] := UInt<2>(1)
    wire T_167509 : UInt<2>[3]
    T_167509[0] := UInt<2>(1)
    T_167509[1] := UInt<2>(2)
    T_167509[2] := UInt<2>(3)
    wire T_167510 : UInt<2>[2]
    T_167510[0] := UInt<2>(2)
    T_167510[1] := UInt<2>(3)
    wire T_167511 : UInt<2>[1]
    T_167511[0] := UInt<2>(3)
    accessor T_167512 = ram[T_167480]
    wire T_167513 : UInt<3>[3]
    T_167513[0] := UInt<3>(0)
    T_167513[1] := UInt<3>(1)
    T_167513[2] := UInt<3>(2)
    wire T_167514 : UInt<2>[2]
    T_167514[0] := UInt<2>(0)
    T_167514[1] := UInt<2>(1)
    wire T_167515 : UInt<2>[3]
    T_167515[0] := UInt<2>(1)
    T_167515[1] := UInt<2>(2)
    T_167515[2] := UInt<2>(3)
    wire T_167516 : UInt<2>[2]
    T_167516[0] := UInt<2>(2)
    T_167516[1] := UInt<2>(3)
    wire T_167517 : UInt<2>[1]
    T_167517[0] := UInt<2>(3)
    wire T_167518 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    T_167518 := T_167512
    when maybe_flow : T_167518 := enq.bits
    deq.bits := T_167518
    node ptr_diff = subw(T_167479, T_167480)
    node T_167519 = and(maybe_full, ptr_match)
    node T_167520 = cat(T_167519, ptr_diff)
    count := T_167520
  module Queue_31614 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output count : UInt<2>
    
    wire T_167521 : UInt<3>[3]
    T_167521[0] := UInt<3>(0)
    T_167521[1] := UInt<3>(1)
    T_167521[2] := UInt<3>(2)
    wire T_167522 : UInt<2>[2]
    T_167522[0] := UInt<2>(0)
    T_167522[1] := UInt<2>(1)
    wire T_167523 : UInt<2>[3]
    T_167523[0] := UInt<2>(1)
    T_167523[1] := UInt<2>(2)
    T_167523[2] := UInt<2>(3)
    wire T_167524 : UInt<2>[2]
    T_167524[0] := UInt<2>(2)
    T_167524[1] := UInt<2>(3)
    wire T_167525 : UInt<2>[1]
    T_167525[0] := UInt<2>(3)
    wire T_167526 : UInt<3>[3]
    T_167526[0] := UInt<3>(0)
    T_167526[1] := UInt<3>(1)
    T_167526[2] := UInt<3>(2)
    wire T_167527 : UInt<2>[2]
    T_167527[0] := UInt<2>(0)
    T_167527[1] := UInt<2>(1)
    wire T_167528 : UInt<2>[3]
    T_167528[0] := UInt<2>(1)
    T_167528[1] := UInt<2>(2)
    T_167528[2] := UInt<2>(3)
    wire T_167529 : UInt<2>[2]
    T_167529[0] := UInt<2>(2)
    T_167529[1] := UInt<2>(3)
    wire T_167530 : UInt<2>[1]
    T_167530[0] := UInt<2>(3)
    wire T_167531 : UInt<3>[3]
    T_167531[0] := UInt<3>(0)
    T_167531[1] := UInt<3>(1)
    T_167531[2] := UInt<3>(2)
    wire T_167532 : UInt<2>[2]
    T_167532[0] := UInt<2>(0)
    T_167532[1] := UInt<2>(1)
    wire T_167533 : UInt<2>[3]
    T_167533[0] := UInt<2>(1)
    T_167533[1] := UInt<2>(2)
    T_167533[2] := UInt<2>(3)
    wire T_167534 : UInt<2>[2]
    T_167534[0] := UInt<2>(2)
    T_167534[1] := UInt<2>(3)
    wire T_167535 : UInt<2>[1]
    T_167535[0] := UInt<2>(3)
    wire T_167536 : UInt<3>[3]
    T_167536[0] := UInt<3>(0)
    T_167536[1] := UInt<3>(1)
    T_167536[2] := UInt<3>(2)
    wire T_167537 : UInt<2>[2]
    T_167537[0] := UInt<2>(0)
    T_167537[1] := UInt<2>(1)
    wire T_167538 : UInt<2>[3]
    T_167538[0] := UInt<2>(1)
    T_167538[1] := UInt<2>(2)
    T_167538[2] := UInt<2>(3)
    wire T_167539 : UInt<2>[2]
    T_167539[0] := UInt<2>(2)
    T_167539[1] := UInt<2>(3)
    wire T_167540 : UInt<2>[1]
    T_167540[0] := UInt<2>(3)
    wire T_167541 : UInt<3>[3]
    T_167541[0] := UInt<3>(0)
    T_167541[1] := UInt<3>(1)
    T_167541[2] := UInt<3>(2)
    wire T_167542 : UInt<2>[2]
    T_167542[0] := UInt<2>(0)
    T_167542[1] := UInt<2>(1)
    wire T_167543 : UInt<2>[3]
    T_167543[0] := UInt<2>(1)
    T_167543[1] := UInt<2>(2)
    T_167543[2] := UInt<2>(3)
    wire T_167544 : UInt<2>[2]
    T_167544[0] := UInt<2>(2)
    T_167544[1] := UInt<2>(3)
    wire T_167545 : UInt<2>[1]
    T_167545[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}[2]
    reg T_167546 : UInt<1>
    onreset T_167546 := UInt<1>(0)
    reg T_167547 : UInt<1>
    onreset T_167547 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_167546, T_167547)
    node T_167548 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_167548)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_167549 = and(enq.ready, enq.valid)
    node T_167550 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_167549, T_167550)
    node T_167551 = and(deq.ready, deq.valid)
    node T_167552 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_167551, T_167552)
    when do_enq : 
      wire T_167553 : UInt<3>[3]
      T_167553[0] := UInt<3>(0)
      T_167553[1] := UInt<3>(1)
      T_167553[2] := UInt<3>(2)
      wire T_167554 : UInt<2>[2]
      T_167554[0] := UInt<2>(0)
      T_167554[1] := UInt<2>(1)
      wire T_167555 : UInt<2>[3]
      T_167555[0] := UInt<2>(1)
      T_167555[1] := UInt<2>(2)
      T_167555[2] := UInt<2>(3)
      wire T_167556 : UInt<2>[2]
      T_167556[0] := UInt<2>(2)
      T_167556[1] := UInt<2>(3)
      wire T_167557 : UInt<2>[1]
      T_167557[0] := UInt<2>(3)
      accessor T_167558 = ram[T_167546]
      T_167558 := enq.bits
      node T_167559 = eq(T_167546, UInt<1>(1))
      node T_167560 = and(UInt<1>(0), T_167559)
      node T_167561 = addw(T_167546, UInt<1>(1))
      wire T_167562 : UInt<1>
      T_167562 := T_167561
      when T_167560 : T_167562 := UInt<1>(0)
      T_167546 := T_167562
    when do_deq : 
      node T_167563 = eq(T_167547, UInt<1>(1))
      node T_167564 = and(UInt<1>(0), T_167563)
      node T_167565 = addw(T_167547, UInt<1>(1))
      wire T_167566 : UInt<1>
      T_167566 := T_167565
      when T_167564 : T_167566 := UInt<1>(0)
      T_167547 := T_167566
    
    node T_167567 = neq(do_enq, do_deq)
    when T_167567 : maybe_full := do_enq
    node T_167568 = eq(empty, UInt<1>(0))
    node T_167569 = and(UInt<1>(0), enq.valid)
    node T_167570 = or(T_167568, T_167569)
    deq.valid := T_167570
    node T_167571 = eq(full, UInt<1>(0))
    node T_167572 = and(UInt<1>(0), deq.ready)
    node T_167573 = or(T_167571, T_167572)
    enq.ready := T_167573
    wire T_167574 : UInt<3>[3]
    T_167574[0] := UInt<3>(0)
    T_167574[1] := UInt<3>(1)
    T_167574[2] := UInt<3>(2)
    wire T_167575 : UInt<2>[2]
    T_167575[0] := UInt<2>(0)
    T_167575[1] := UInt<2>(1)
    wire T_167576 : UInt<2>[3]
    T_167576[0] := UInt<2>(1)
    T_167576[1] := UInt<2>(2)
    T_167576[2] := UInt<2>(3)
    wire T_167577 : UInt<2>[2]
    T_167577[0] := UInt<2>(2)
    T_167577[1] := UInt<2>(3)
    wire T_167578 : UInt<2>[1]
    T_167578[0] := UInt<2>(3)
    accessor T_167579 = ram[T_167547]
    wire T_167580 : UInt<3>[3]
    T_167580[0] := UInt<3>(0)
    T_167580[1] := UInt<3>(1)
    T_167580[2] := UInt<3>(2)
    wire T_167581 : UInt<2>[2]
    T_167581[0] := UInt<2>(0)
    T_167581[1] := UInt<2>(1)
    wire T_167582 : UInt<2>[3]
    T_167582[0] := UInt<2>(1)
    T_167582[1] := UInt<2>(2)
    T_167582[2] := UInt<2>(3)
    wire T_167583 : UInt<2>[2]
    T_167583[0] := UInt<2>(2)
    T_167583[1] := UInt<2>(3)
    wire T_167584 : UInt<2>[1]
    T_167584[0] := UInt<2>(3)
    wire T_167585 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}
    T_167585 := T_167579
    when maybe_flow : T_167585 := enq.bits
    deq.bits := T_167585
    node ptr_diff = subw(T_167546, T_167547)
    node T_167586 = and(maybe_full, ptr_match)
    node T_167587 = cat(T_167586, ptr_diff)
    count := T_167587
  module TileLinkEnqueuer_31615 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_167588 : UInt<3>[3]
    T_167588[0] := UInt<3>(0)
    T_167588[1] := UInt<3>(1)
    T_167588[2] := UInt<3>(2)
    wire T_167589 : UInt<2>[2]
    T_167589[0] := UInt<2>(0)
    T_167589[1] := UInt<2>(1)
    wire T_167590 : UInt<2>[3]
    T_167590[0] := UInt<2>(1)
    T_167590[1] := UInt<2>(2)
    T_167590[2] := UInt<2>(3)
    wire T_167591 : UInt<2>[2]
    T_167591[0] := UInt<2>(2)
    T_167591[1] := UInt<2>(3)
    wire T_167592 : UInt<2>[1]
    T_167592[0] := UInt<2>(3)
    wire T_167593 : UInt<3>[3]
    T_167593[0] := UInt<3>(0)
    T_167593[1] := UInt<3>(1)
    T_167593[2] := UInt<3>(2)
    wire T_167594 : UInt<2>[2]
    T_167594[0] := UInt<2>(0)
    T_167594[1] := UInt<2>(1)
    wire T_167595 : UInt<2>[3]
    T_167595[0] := UInt<2>(1)
    T_167595[1] := UInt<2>(2)
    T_167595[2] := UInt<2>(3)
    wire T_167596 : UInt<2>[2]
    T_167596[0] := UInt<2>(2)
    T_167596[1] := UInt<2>(3)
    wire T_167597 : UInt<2>[1]
    T_167597[0] := UInt<2>(3)
    wire T_167598 : UInt<3>[3]
    T_167598[0] := UInt<3>(0)
    T_167598[1] := UInt<3>(1)
    T_167598[2] := UInt<3>(2)
    wire T_167599 : UInt<2>[2]
    T_167599[0] := UInt<2>(0)
    T_167599[1] := UInt<2>(1)
    wire T_167600 : UInt<2>[3]
    T_167600[0] := UInt<2>(1)
    T_167600[1] := UInt<2>(2)
    T_167600[2] := UInt<2>(3)
    wire T_167601 : UInt<2>[2]
    T_167601[0] := UInt<2>(2)
    T_167601[1] := UInt<2>(3)
    wire T_167602 : UInt<2>[1]
    T_167602[0] := UInt<2>(3)
    wire T_167603 : UInt<3>[3]
    T_167603[0] := UInt<3>(0)
    T_167603[1] := UInt<3>(1)
    T_167603[2] := UInt<3>(2)
    wire T_167604 : UInt<2>[2]
    T_167604[0] := UInt<2>(0)
    T_167604[1] := UInt<2>(1)
    wire T_167605 : UInt<2>[3]
    T_167605[0] := UInt<2>(1)
    T_167605[1] := UInt<2>(2)
    T_167605[2] := UInt<2>(3)
    wire T_167606 : UInt<2>[2]
    T_167606[0] := UInt<2>(2)
    T_167606[1] := UInt<2>(3)
    wire T_167607 : UInt<2>[1]
    T_167607[0] := UInt<2>(3)
    wire T_167608 : UInt<3>[3]
    T_167608[0] := UInt<3>(0)
    T_167608[1] := UInt<3>(1)
    T_167608[2] := UInt<3>(2)
    wire T_167609 : UInt<2>[2]
    T_167609[0] := UInt<2>(0)
    T_167609[1] := UInt<2>(1)
    wire T_167610 : UInt<2>[3]
    T_167610[0] := UInt<2>(1)
    T_167610[1] := UInt<2>(2)
    T_167610[2] := UInt<2>(3)
    wire T_167611 : UInt<2>[2]
    T_167611[0] := UInt<2>(2)
    T_167611[1] := UInt<2>(3)
    wire T_167612 : UInt<2>[1]
    T_167612[0] := UInt<2>(3)
    wire T_167613 : UInt<3>[3]
    T_167613[0] := UInt<3>(0)
    T_167613[1] := UInt<3>(1)
    T_167613[2] := UInt<3>(2)
    wire T_167614 : UInt<2>[2]
    T_167614[0] := UInt<2>(0)
    T_167614[1] := UInt<2>(1)
    wire T_167615 : UInt<2>[3]
    T_167615[0] := UInt<2>(1)
    T_167615[1] := UInt<2>(2)
    T_167615[2] := UInt<2>(3)
    wire T_167616 : UInt<2>[2]
    T_167616[0] := UInt<2>(2)
    T_167616[1] := UInt<2>(3)
    wire T_167617 : UInt<2>[1]
    T_167617[0] := UInt<2>(3)
    wire T_167618 : UInt<3>[3]
    T_167618[0] := UInt<3>(0)
    T_167618[1] := UInt<3>(1)
    T_167618[2] := UInt<3>(2)
    wire T_167619 : UInt<2>[2]
    T_167619[0] := UInt<2>(0)
    T_167619[1] := UInt<2>(1)
    wire T_167620 : UInt<2>[3]
    T_167620[0] := UInt<2>(1)
    T_167620[1] := UInt<2>(2)
    T_167620[2] := UInt<2>(3)
    wire T_167621 : UInt<2>[2]
    T_167621[0] := UInt<2>(2)
    T_167621[1] := UInt<2>(3)
    wire T_167622 : UInt<2>[1]
    T_167622[0] := UInt<2>(3)
    wire T_167623 : UInt<3>[3]
    T_167623[0] := UInt<3>(0)
    T_167623[1] := UInt<3>(1)
    T_167623[2] := UInt<3>(2)
    wire T_167624 : UInt<2>[2]
    T_167624[0] := UInt<2>(0)
    T_167624[1] := UInt<2>(1)
    wire T_167625 : UInt<2>[3]
    T_167625[0] := UInt<2>(1)
    T_167625[1] := UInt<2>(2)
    T_167625[2] := UInt<2>(3)
    wire T_167626 : UInt<2>[2]
    T_167626[0] := UInt<2>(2)
    T_167626[1] := UInt<2>(3)
    wire T_167627 : UInt<2>[1]
    T_167627[0] := UInt<2>(3)
    wire T_167628 : UInt<3>[3]
    T_167628[0] := UInt<3>(0)
    T_167628[1] := UInt<3>(1)
    T_167628[2] := UInt<3>(2)
    wire T_167629 : UInt<2>[2]
    T_167629[0] := UInt<2>(0)
    T_167629[1] := UInt<2>(1)
    wire T_167630 : UInt<2>[3]
    T_167630[0] := UInt<2>(1)
    T_167630[1] := UInt<2>(2)
    T_167630[2] := UInt<2>(3)
    wire T_167631 : UInt<2>[2]
    T_167631[0] := UInt<2>(2)
    T_167631[1] := UInt<2>(3)
    wire T_167632 : UInt<2>[1]
    T_167632[0] := UInt<2>(3)
    wire T_167633 : UInt<3>[3]
    T_167633[0] := UInt<3>(0)
    T_167633[1] := UInt<3>(1)
    T_167633[2] := UInt<3>(2)
    wire T_167634 : UInt<2>[2]
    T_167634[0] := UInt<2>(0)
    T_167634[1] := UInt<2>(1)
    wire T_167635 : UInt<2>[3]
    T_167635[0] := UInt<2>(1)
    T_167635[1] := UInt<2>(2)
    T_167635[2] := UInt<2>(3)
    wire T_167636 : UInt<2>[2]
    T_167636[0] := UInt<2>(2)
    T_167636[1] := UInt<2>(3)
    wire T_167637 : UInt<2>[1]
    T_167637[0] := UInt<2>(3)
    wire T_167638 : UInt<3>[3]
    T_167638[0] := UInt<3>(0)
    T_167638[1] := UInt<3>(1)
    T_167638[2] := UInt<3>(2)
    wire T_167639 : UInt<2>[2]
    T_167639[0] := UInt<2>(0)
    T_167639[1] := UInt<2>(1)
    wire T_167640 : UInt<2>[3]
    T_167640[0] := UInt<2>(1)
    T_167640[1] := UInt<2>(2)
    T_167640[2] := UInt<2>(3)
    wire T_167641 : UInt<2>[2]
    T_167641[0] := UInt<2>(2)
    T_167641[1] := UInt<2>(3)
    wire T_167642 : UInt<2>[1]
    T_167642[0] := UInt<2>(3)
    wire T_167643 : UInt<3>[3]
    T_167643[0] := UInt<3>(0)
    T_167643[1] := UInt<3>(1)
    T_167643[2] := UInt<3>(2)
    wire T_167644 : UInt<2>[2]
    T_167644[0] := UInt<2>(0)
    T_167644[1] := UInt<2>(1)
    wire T_167645 : UInt<2>[3]
    T_167645[0] := UInt<2>(1)
    T_167645[1] := UInt<2>(2)
    T_167645[2] := UInt<2>(3)
    wire T_167646 : UInt<2>[2]
    T_167646[0] := UInt<2>(2)
    T_167646[1] := UInt<2>(3)
    wire T_167647 : UInt<2>[1]
    T_167647[0] := UInt<2>(3)
    wire T_167648 : UInt<3>[3]
    T_167648[0] := UInt<3>(0)
    T_167648[1] := UInt<3>(1)
    T_167648[2] := UInt<3>(2)
    wire T_167649 : UInt<2>[2]
    T_167649[0] := UInt<2>(0)
    T_167649[1] := UInt<2>(1)
    wire T_167650 : UInt<2>[3]
    T_167650[0] := UInt<2>(1)
    T_167650[1] := UInt<2>(2)
    T_167650[2] := UInt<2>(3)
    wire T_167651 : UInt<2>[2]
    T_167651[0] := UInt<2>(2)
    T_167651[1] := UInt<2>(3)
    wire T_167652 : UInt<2>[1]
    T_167652[0] := UInt<2>(3)
    wire T_167653 : UInt<3>[3]
    T_167653[0] := UInt<3>(0)
    T_167653[1] := UInt<3>(1)
    T_167653[2] := UInt<3>(2)
    wire T_167654 : UInt<2>[2]
    T_167654[0] := UInt<2>(0)
    T_167654[1] := UInt<2>(1)
    wire T_167655 : UInt<2>[3]
    T_167655[0] := UInt<2>(1)
    T_167655[1] := UInt<2>(2)
    T_167655[2] := UInt<2>(3)
    wire T_167656 : UInt<2>[2]
    T_167656[0] := UInt<2>(2)
    T_167656[1] := UInt<2>(3)
    wire T_167657 : UInt<2>[1]
    T_167657[0] := UInt<2>(3)
    wire T_167658 : UInt<3>[3]
    T_167658[0] := UInt<3>(0)
    T_167658[1] := UInt<3>(1)
    T_167658[2] := UInt<3>(2)
    wire T_167659 : UInt<2>[2]
    T_167659[0] := UInt<2>(0)
    T_167659[1] := UInt<2>(1)
    wire T_167660 : UInt<2>[3]
    T_167660[0] := UInt<2>(1)
    T_167660[1] := UInt<2>(2)
    T_167660[2] := UInt<2>(3)
    wire T_167661 : UInt<2>[2]
    T_167661[0] := UInt<2>(2)
    T_167661[1] := UInt<2>(3)
    wire T_167662 : UInt<2>[1]
    T_167662[0] := UInt<2>(3)
    wire T_167663 : UInt<3>[3]
    T_167663[0] := UInt<3>(0)
    T_167663[1] := UInt<3>(1)
    T_167663[2] := UInt<3>(2)
    wire T_167664 : UInt<2>[2]
    T_167664[0] := UInt<2>(0)
    T_167664[1] := UInt<2>(1)
    wire T_167665 : UInt<2>[3]
    T_167665[0] := UInt<2>(1)
    T_167665[1] := UInt<2>(2)
    T_167665[2] := UInt<2>(3)
    wire T_167666 : UInt<2>[2]
    T_167666[0] := UInt<2>(2)
    T_167666[1] := UInt<2>(3)
    wire T_167667 : UInt<2>[1]
    T_167667[0] := UInt<2>(3)
    wire T_167668 : UInt<3>[3]
    T_167668[0] := UInt<3>(0)
    T_167668[1] := UInt<3>(1)
    T_167668[2] := UInt<3>(2)
    wire T_167669 : UInt<2>[2]
    T_167669[0] := UInt<2>(0)
    T_167669[1] := UInt<2>(1)
    wire T_167670 : UInt<2>[3]
    T_167670[0] := UInt<2>(1)
    T_167670[1] := UInt<2>(2)
    T_167670[2] := UInt<2>(3)
    wire T_167671 : UInt<2>[2]
    T_167671[0] := UInt<2>(2)
    T_167671[1] := UInt<2>(3)
    wire T_167672 : UInt<2>[1]
    T_167672[0] := UInt<2>(3)
    wire T_167673 : UInt<3>[3]
    T_167673[0] := UInt<3>(0)
    T_167673[1] := UInt<3>(1)
    T_167673[2] := UInt<3>(2)
    wire T_167674 : UInt<2>[2]
    T_167674[0] := UInt<2>(0)
    T_167674[1] := UInt<2>(1)
    wire T_167675 : UInt<2>[3]
    T_167675[0] := UInt<2>(1)
    T_167675[1] := UInt<2>(2)
    T_167675[2] := UInt<2>(3)
    wire T_167676 : UInt<2>[2]
    T_167676[0] := UInt<2>(2)
    T_167676[1] := UInt<2>(3)
    wire T_167677 : UInt<2>[1]
    T_167677[0] := UInt<2>(3)
    wire T_167678 : UInt<3>[3]
    T_167678[0] := UInt<3>(0)
    T_167678[1] := UInt<3>(1)
    T_167678[2] := UInt<3>(2)
    wire T_167679 : UInt<2>[2]
    T_167679[0] := UInt<2>(0)
    T_167679[1] := UInt<2>(1)
    wire T_167680 : UInt<2>[3]
    T_167680[0] := UInt<2>(1)
    T_167680[1] := UInt<2>(2)
    T_167680[2] := UInt<2>(3)
    wire T_167681 : UInt<2>[2]
    T_167681[0] := UInt<2>(2)
    T_167681[1] := UInt<2>(3)
    wire T_167682 : UInt<2>[1]
    T_167682[0] := UInt<2>(3)
    wire T_167683 : UInt<3>[3]
    T_167683[0] := UInt<3>(0)
    T_167683[1] := UInt<3>(1)
    T_167683[2] := UInt<3>(2)
    wire T_167684 : UInt<2>[2]
    T_167684[0] := UInt<2>(0)
    T_167684[1] := UInt<2>(1)
    wire T_167685 : UInt<2>[3]
    T_167685[0] := UInt<2>(1)
    T_167685[1] := UInt<2>(2)
    T_167685[2] := UInt<2>(3)
    wire T_167686 : UInt<2>[2]
    T_167686[0] := UInt<2>(2)
    T_167686[1] := UInt<2>(3)
    wire T_167687 : UInt<2>[1]
    T_167687[0] := UInt<2>(3)
    wire T_167688 : UInt<3>[3]
    T_167688[0] := UInt<3>(0)
    T_167688[1] := UInt<3>(1)
    T_167688[2] := UInt<3>(2)
    wire T_167689 : UInt<2>[2]
    T_167689[0] := UInt<2>(0)
    T_167689[1] := UInt<2>(1)
    wire T_167690 : UInt<2>[3]
    T_167690[0] := UInt<2>(1)
    T_167690[1] := UInt<2>(2)
    T_167690[2] := UInt<2>(3)
    wire T_167691 : UInt<2>[2]
    T_167691[0] := UInt<2>(2)
    T_167691[1] := UInt<2>(3)
    wire T_167692 : UInt<2>[1]
    T_167692[0] := UInt<2>(3)
    wire T_167693 : UInt<3>[3]
    T_167693[0] := UInt<3>(0)
    T_167693[1] := UInt<3>(1)
    T_167693[2] := UInt<3>(2)
    wire T_167694 : UInt<2>[2]
    T_167694[0] := UInt<2>(0)
    T_167694[1] := UInt<2>(1)
    wire T_167695 : UInt<2>[3]
    T_167695[0] := UInt<2>(1)
    T_167695[1] := UInt<2>(2)
    T_167695[2] := UInt<2>(3)
    wire T_167696 : UInt<2>[2]
    T_167696[0] := UInt<2>(2)
    T_167696[1] := UInt<2>(3)
    wire T_167697 : UInt<2>[1]
    T_167697[0] := UInt<2>(3)
    wire T_167698 : UInt<3>[3]
    T_167698[0] := UInt<3>(0)
    T_167698[1] := UInt<3>(1)
    T_167698[2] := UInt<3>(2)
    wire T_167699 : UInt<2>[2]
    T_167699[0] := UInt<2>(0)
    T_167699[1] := UInt<2>(1)
    wire T_167700 : UInt<2>[3]
    T_167700[0] := UInt<2>(1)
    T_167700[1] := UInt<2>(2)
    T_167700[2] := UInt<2>(3)
    wire T_167701 : UInt<2>[2]
    T_167701[0] := UInt<2>(2)
    T_167701[1] := UInt<2>(3)
    wire T_167702 : UInt<2>[1]
    T_167702[0] := UInt<2>(3)
    wire T_167703 : UInt<3>[3]
    T_167703[0] := UInt<3>(0)
    T_167703[1] := UInt<3>(1)
    T_167703[2] := UInt<3>(2)
    wire T_167704 : UInt<2>[2]
    T_167704[0] := UInt<2>(0)
    T_167704[1] := UInt<2>(1)
    wire T_167705 : UInt<2>[3]
    T_167705[0] := UInt<2>(1)
    T_167705[1] := UInt<2>(2)
    T_167705[2] := UInt<2>(3)
    wire T_167706 : UInt<2>[2]
    T_167706[0] := UInt<2>(2)
    T_167706[1] := UInt<2>(3)
    wire T_167707 : UInt<2>[1]
    T_167707[0] := UInt<2>(3)
    wire T_167708 : UInt<3>[3]
    T_167708[0] := UInt<3>(0)
    T_167708[1] := UInt<3>(1)
    T_167708[2] := UInt<3>(2)
    wire T_167709 : UInt<2>[2]
    T_167709[0] := UInt<2>(0)
    T_167709[1] := UInt<2>(1)
    wire T_167710 : UInt<2>[3]
    T_167710[0] := UInt<2>(1)
    T_167710[1] := UInt<2>(2)
    T_167710[2] := UInt<2>(3)
    wire T_167711 : UInt<2>[2]
    T_167711[0] := UInt<2>(2)
    T_167711[1] := UInt<2>(3)
    wire T_167712 : UInt<2>[1]
    T_167712[0] := UInt<2>(3)
    wire T_167713 : UInt<3>[3]
    T_167713[0] := UInt<3>(0)
    T_167713[1] := UInt<3>(1)
    T_167713[2] := UInt<3>(2)
    wire T_167714 : UInt<2>[2]
    T_167714[0] := UInt<2>(0)
    T_167714[1] := UInt<2>(1)
    wire T_167715 : UInt<2>[3]
    T_167715[0] := UInt<2>(1)
    T_167715[1] := UInt<2>(2)
    T_167715[2] := UInt<2>(3)
    wire T_167716 : UInt<2>[2]
    T_167716[0] := UInt<2>(2)
    T_167716[1] := UInt<2>(3)
    wire T_167717 : UInt<2>[1]
    T_167717[0] := UInt<2>(3)
    wire T_167718 : UInt<3>[3]
    T_167718[0] := UInt<3>(0)
    T_167718[1] := UInt<3>(1)
    T_167718[2] := UInt<3>(2)
    wire T_167719 : UInt<2>[2]
    T_167719[0] := UInt<2>(0)
    T_167719[1] := UInt<2>(1)
    wire T_167720 : UInt<2>[3]
    T_167720[0] := UInt<2>(1)
    T_167720[1] := UInt<2>(2)
    T_167720[2] := UInt<2>(3)
    wire T_167721 : UInt<2>[2]
    T_167721[0] := UInt<2>(2)
    T_167721[1] := UInt<2>(3)
    wire T_167722 : UInt<2>[1]
    T_167722[0] := UInt<2>(3)
    wire T_167723 : UInt<3>[3]
    T_167723[0] := UInt<3>(0)
    T_167723[1] := UInt<3>(1)
    T_167723[2] := UInt<3>(2)
    wire T_167724 : UInt<2>[2]
    T_167724[0] := UInt<2>(0)
    T_167724[1] := UInt<2>(1)
    wire T_167725 : UInt<2>[3]
    T_167725[0] := UInt<2>(1)
    T_167725[1] := UInt<2>(2)
    T_167725[2] := UInt<2>(3)
    wire T_167726 : UInt<2>[2]
    T_167726[0] := UInt<2>(2)
    T_167726[1] := UInt<2>(3)
    wire T_167727 : UInt<2>[1]
    T_167727[0] := UInt<2>(3)
    wire T_167728 : UInt<3>[3]
    T_167728[0] := UInt<3>(0)
    T_167728[1] := UInt<3>(1)
    T_167728[2] := UInt<3>(2)
    wire T_167729 : UInt<2>[2]
    T_167729[0] := UInt<2>(0)
    T_167729[1] := UInt<2>(1)
    wire T_167730 : UInt<2>[3]
    T_167730[0] := UInt<2>(1)
    T_167730[1] := UInt<2>(2)
    T_167730[2] := UInt<2>(3)
    wire T_167731 : UInt<2>[2]
    T_167731[0] := UInt<2>(2)
    T_167731[1] := UInt<2>(3)
    wire T_167732 : UInt<2>[1]
    T_167732[0] := UInt<2>(3)
    wire T_167733 : UInt<3>[3]
    T_167733[0] := UInt<3>(0)
    T_167733[1] := UInt<3>(1)
    T_167733[2] := UInt<3>(2)
    wire T_167734 : UInt<2>[2]
    T_167734[0] := UInt<2>(0)
    T_167734[1] := UInt<2>(1)
    wire T_167735 : UInt<2>[3]
    T_167735[0] := UInt<2>(1)
    T_167735[1] := UInt<2>(2)
    T_167735[2] := UInt<2>(3)
    wire T_167736 : UInt<2>[2]
    T_167736[0] := UInt<2>(2)
    T_167736[1] := UInt<2>(3)
    wire T_167737 : UInt<2>[1]
    T_167737[0] := UInt<2>(3)
    wire T_167738 : UInt<3>[3]
    T_167738[0] := UInt<3>(0)
    T_167738[1] := UInt<3>(1)
    T_167738[2] := UInt<3>(2)
    wire T_167739 : UInt<2>[2]
    T_167739[0] := UInt<2>(0)
    T_167739[1] := UInt<2>(1)
    wire T_167740 : UInt<2>[3]
    T_167740[0] := UInt<2>(1)
    T_167740[1] := UInt<2>(2)
    T_167740[2] := UInt<2>(3)
    wire T_167741 : UInt<2>[2]
    T_167741[0] := UInt<2>(2)
    T_167741[1] := UInt<2>(3)
    wire T_167742 : UInt<2>[1]
    T_167742[0] := UInt<2>(3)
    wire T_167743 : UInt<3>[3]
    T_167743[0] := UInt<3>(0)
    T_167743[1] := UInt<3>(1)
    T_167743[2] := UInt<3>(2)
    wire T_167744 : UInt<2>[2]
    T_167744[0] := UInt<2>(0)
    T_167744[1] := UInt<2>(1)
    wire T_167745 : UInt<2>[3]
    T_167745[0] := UInt<2>(1)
    T_167745[1] := UInt<2>(2)
    T_167745[2] := UInt<2>(3)
    wire T_167746 : UInt<2>[2]
    T_167746[0] := UInt<2>(2)
    T_167746[1] := UInt<2>(3)
    wire T_167747 : UInt<2>[1]
    T_167747[0] := UInt<2>(3)
    wire T_167748 : UInt<3>[3]
    T_167748[0] := UInt<3>(0)
    T_167748[1] := UInt<3>(1)
    T_167748[2] := UInt<3>(2)
    wire T_167749 : UInt<2>[2]
    T_167749[0] := UInt<2>(0)
    T_167749[1] := UInt<2>(1)
    wire T_167750 : UInt<2>[3]
    T_167750[0] := UInt<2>(1)
    T_167750[1] := UInt<2>(2)
    T_167750[2] := UInt<2>(3)
    wire T_167751 : UInt<2>[2]
    T_167751[0] := UInt<2>(2)
    T_167751[1] := UInt<2>(3)
    wire T_167752 : UInt<2>[1]
    T_167752[0] := UInt<2>(3)
    inst T_167753 of Queue_28995
    T_167753.enq.valid := client.acquire.valid
    T_167753.enq.bits := client.acquire.bits
    client.acquire.ready := T_167753.enq.ready
    manager.acquire <> T_167753.deq
    wire T_167754 : UInt<3>[3]
    T_167754[0] := UInt<3>(0)
    T_167754[1] := UInt<3>(1)
    T_167754[2] := UInt<3>(2)
    wire T_167755 : UInt<2>[2]
    T_167755[0] := UInt<2>(0)
    T_167755[1] := UInt<2>(1)
    wire T_167756 : UInt<2>[3]
    T_167756[0] := UInt<2>(1)
    T_167756[1] := UInt<2>(2)
    T_167756[2] := UInt<2>(3)
    wire T_167757 : UInt<2>[2]
    T_167757[0] := UInt<2>(2)
    T_167757[1] := UInt<2>(3)
    wire T_167758 : UInt<2>[1]
    T_167758[0] := UInt<2>(3)
    inst T_167759 of Queue_29634
    T_167759.enq.valid := manager.probe.valid
    T_167759.enq.bits := manager.probe.bits
    manager.probe.ready := T_167759.enq.ready
    client.probe <> T_167759.deq
    wire T_167760 : UInt<3>[3]
    T_167760[0] := UInt<3>(0)
    T_167760[1] := UInt<3>(1)
    T_167760[2] := UInt<3>(2)
    wire T_167761 : UInt<2>[2]
    T_167761[0] := UInt<2>(0)
    T_167761[1] := UInt<2>(1)
    wire T_167762 : UInt<2>[3]
    T_167762[0] := UInt<2>(1)
    T_167762[1] := UInt<2>(2)
    T_167762[2] := UInt<2>(3)
    wire T_167763 : UInt<2>[2]
    T_167763[0] := UInt<2>(2)
    T_167763[1] := UInt<2>(3)
    wire T_167764 : UInt<2>[1]
    T_167764[0] := UInt<2>(3)
    inst T_167765 of Queue_30309
    T_167765.enq.valid := client.release.valid
    T_167765.enq.bits := client.release.bits
    client.release.ready := T_167765.enq.ready
    manager.release <> T_167765.deq
    wire T_167766 : UInt<3>[3]
    T_167766[0] := UInt<3>(0)
    T_167766[1] := UInt<3>(1)
    T_167766[2] := UInt<3>(2)
    wire T_167767 : UInt<2>[2]
    T_167767[0] := UInt<2>(0)
    T_167767[1] := UInt<2>(1)
    wire T_167768 : UInt<2>[3]
    T_167768[0] := UInt<2>(1)
    T_167768[1] := UInt<2>(2)
    T_167768[2] := UInt<2>(3)
    wire T_167769 : UInt<2>[2]
    T_167769[0] := UInt<2>(2)
    T_167769[1] := UInt<2>(3)
    wire T_167770 : UInt<2>[1]
    T_167770[0] := UInt<2>(3)
    inst T_167771 of Queue_30984
    T_167771.enq.valid := manager.grant.valid
    T_167771.enq.bits := manager.grant.bits
    manager.grant.ready := T_167771.enq.ready
    client.grant <> T_167771.deq
    wire T_167772 : UInt<3>[3]
    T_167772[0] := UInt<3>(0)
    T_167772[1] := UInt<3>(1)
    T_167772[2] := UInt<3>(2)
    wire T_167773 : UInt<2>[2]
    T_167773[0] := UInt<2>(0)
    T_167773[1] := UInt<2>(1)
    wire T_167774 : UInt<2>[3]
    T_167774[0] := UInt<2>(1)
    T_167774[1] := UInt<2>(2)
    T_167774[2] := UInt<2>(3)
    wire T_167775 : UInt<2>[2]
    T_167775[0] := UInt<2>(2)
    T_167775[1] := UInt<2>(3)
    wire T_167776 : UInt<2>[1]
    T_167776[0] := UInt<2>(3)
    inst T_167777 of Queue_31614
    T_167777.enq.valid := client.finish.valid
    T_167777.enq.bits := client.finish.bits
    client.finish.ready := T_167777.enq.ready
    manager.finish <> T_167777.deq
  module FinishQueue_35038 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}}
    output count : UInt<2>
    
    wire T_167778 : UInt<3>[3]
    T_167778[0] := UInt<3>(0)
    T_167778[1] := UInt<3>(1)
    T_167778[2] := UInt<3>(2)
    wire T_167779 : UInt<2>[2]
    T_167779[0] := UInt<2>(0)
    T_167779[1] := UInt<2>(1)
    wire T_167780 : UInt<2>[3]
    T_167780[0] := UInt<2>(1)
    T_167780[1] := UInt<2>(2)
    T_167780[2] := UInt<2>(3)
    wire T_167781 : UInt<2>[2]
    T_167781[0] := UInt<2>(2)
    T_167781[1] := UInt<2>(3)
    wire T_167782 : UInt<2>[1]
    T_167782[0] := UInt<2>(3)
    wire T_167783 : UInt<3>[3]
    T_167783[0] := UInt<3>(0)
    T_167783[1] := UInt<3>(1)
    T_167783[2] := UInt<3>(2)
    wire T_167784 : UInt<2>[2]
    T_167784[0] := UInt<2>(0)
    T_167784[1] := UInt<2>(1)
    wire T_167785 : UInt<2>[3]
    T_167785[0] := UInt<2>(1)
    T_167785[1] := UInt<2>(2)
    T_167785[2] := UInt<2>(3)
    wire T_167786 : UInt<2>[2]
    T_167786[0] := UInt<2>(2)
    T_167786[1] := UInt<2>(3)
    wire T_167787 : UInt<2>[1]
    T_167787[0] := UInt<2>(3)
    wire T_167788 : UInt<3>[3]
    T_167788[0] := UInt<3>(0)
    T_167788[1] := UInt<3>(1)
    T_167788[2] := UInt<3>(2)
    wire T_167789 : UInt<2>[2]
    T_167789[0] := UInt<2>(0)
    T_167789[1] := UInt<2>(1)
    wire T_167790 : UInt<2>[3]
    T_167790[0] := UInt<2>(1)
    T_167790[1] := UInt<2>(2)
    T_167790[2] := UInt<2>(3)
    wire T_167791 : UInt<2>[2]
    T_167791[0] := UInt<2>(2)
    T_167791[1] := UInt<2>(3)
    wire T_167792 : UInt<2>[1]
    T_167792[0] := UInt<2>(3)
    wire T_167793 : UInt<3>[3]
    T_167793[0] := UInt<3>(0)
    T_167793[1] := UInt<3>(1)
    T_167793[2] := UInt<3>(2)
    wire T_167794 : UInt<2>[2]
    T_167794[0] := UInt<2>(0)
    T_167794[1] := UInt<2>(1)
    wire T_167795 : UInt<2>[3]
    T_167795[0] := UInt<2>(1)
    T_167795[1] := UInt<2>(2)
    T_167795[2] := UInt<2>(3)
    wire T_167796 : UInt<2>[2]
    T_167796[0] := UInt<2>(2)
    T_167796[1] := UInt<2>(3)
    wire T_167797 : UInt<2>[1]
    T_167797[0] := UInt<2>(3)
    wire T_167798 : UInt<3>[3]
    T_167798[0] := UInt<3>(0)
    T_167798[1] := UInt<3>(1)
    T_167798[2] := UInt<3>(2)
    wire T_167799 : UInt<2>[2]
    T_167799[0] := UInt<2>(0)
    T_167799[1] := UInt<2>(1)
    wire T_167800 : UInt<2>[3]
    T_167800[0] := UInt<2>(1)
    T_167800[1] := UInt<2>(2)
    T_167800[2] := UInt<2>(3)
    wire T_167801 : UInt<2>[2]
    T_167801[0] := UInt<2>(2)
    T_167801[1] := UInt<2>(3)
    wire T_167802 : UInt<2>[1]
    T_167802[0] := UInt<2>(3)
    wire T_167803 : UInt<3>[3]
    T_167803[0] := UInt<3>(0)
    T_167803[1] := UInt<3>(1)
    T_167803[2] := UInt<3>(2)
    wire T_167804 : UInt<2>[2]
    T_167804[0] := UInt<2>(0)
    T_167804[1] := UInt<2>(1)
    wire T_167805 : UInt<2>[3]
    T_167805[0] := UInt<2>(1)
    T_167805[1] := UInt<2>(2)
    T_167805[2] := UInt<2>(3)
    wire T_167806 : UInt<2>[2]
    T_167806[0] := UInt<2>(2)
    T_167806[1] := UInt<2>(3)
    wire T_167807 : UInt<2>[1]
    T_167807[0] := UInt<2>(3)
    wire T_167808 : UInt<3>[3]
    T_167808[0] := UInt<3>(0)
    T_167808[1] := UInt<3>(1)
    T_167808[2] := UInt<3>(2)
    wire T_167809 : UInt<2>[2]
    T_167809[0] := UInt<2>(0)
    T_167809[1] := UInt<2>(1)
    wire T_167810 : UInt<2>[3]
    T_167810[0] := UInt<2>(1)
    T_167810[1] := UInt<2>(2)
    T_167810[2] := UInt<2>(3)
    wire T_167811 : UInt<2>[2]
    T_167811[0] := UInt<2>(2)
    T_167811[1] := UInt<2>(3)
    wire T_167812 : UInt<2>[1]
    T_167812[0] := UInt<2>(3)
    wire T_167813 : UInt<3>[3]
    T_167813[0] := UInt<3>(0)
    T_167813[1] := UInt<3>(1)
    T_167813[2] := UInt<3>(2)
    wire T_167814 : UInt<2>[2]
    T_167814[0] := UInt<2>(0)
    T_167814[1] := UInt<2>(1)
    wire T_167815 : UInt<2>[3]
    T_167815[0] := UInt<2>(1)
    T_167815[1] := UInt<2>(2)
    T_167815[2] := UInt<2>(3)
    wire T_167816 : UInt<2>[2]
    T_167816[0] := UInt<2>(2)
    T_167816[1] := UInt<2>(3)
    wire T_167817 : UInt<2>[1]
    T_167817[0] := UInt<2>(3)
    wire T_167818 : UInt<3>[3]
    T_167818[0] := UInt<3>(0)
    T_167818[1] := UInt<3>(1)
    T_167818[2] := UInt<3>(2)
    wire T_167819 : UInt<2>[2]
    T_167819[0] := UInt<2>(0)
    T_167819[1] := UInt<2>(1)
    wire T_167820 : UInt<2>[3]
    T_167820[0] := UInt<2>(1)
    T_167820[1] := UInt<2>(2)
    T_167820[2] := UInt<2>(3)
    wire T_167821 : UInt<2>[2]
    T_167821[0] := UInt<2>(2)
    T_167821[1] := UInt<2>(3)
    wire T_167822 : UInt<2>[1]
    T_167822[0] := UInt<2>(3)
    wire T_167823 : UInt<3>[3]
    T_167823[0] := UInt<3>(0)
    T_167823[1] := UInt<3>(1)
    T_167823[2] := UInt<3>(2)
    wire T_167824 : UInt<2>[2]
    T_167824[0] := UInt<2>(0)
    T_167824[1] := UInt<2>(1)
    wire T_167825 : UInt<2>[3]
    T_167825[0] := UInt<2>(1)
    T_167825[1] := UInt<2>(2)
    T_167825[2] := UInt<2>(3)
    wire T_167826 : UInt<2>[2]
    T_167826[0] := UInt<2>(2)
    T_167826[1] := UInt<2>(3)
    wire T_167827 : UInt<2>[1]
    T_167827[0] := UInt<2>(3)
    cmem T_167828 : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}[2]
    reg T_167829 : UInt<1>
    onreset T_167829 := UInt<1>(0)
    reg T_167830 : UInt<1>
    onreset T_167830 := UInt<1>(0)
    reg T_167831 : UInt<1>
    onreset T_167831 := UInt<1>(0)
    node T_167832 = eq(T_167829, T_167830)
    node T_167833 = eq(T_167831, UInt<1>(0))
    node T_167834 = and(T_167832, T_167833)
    node T_167835 = and(T_167832, T_167831)
    node T_167836 = and(UInt<1>(0), T_167834)
    node T_167837 = and(T_167836, deq.ready)
    node T_167838 = and(enq.ready, enq.valid)
    node T_167839 = eq(T_167837, UInt<1>(0))
    node T_167840 = and(T_167838, T_167839)
    node T_167841 = and(deq.ready, deq.valid)
    node T_167842 = eq(T_167837, UInt<1>(0))
    node T_167843 = and(T_167841, T_167842)
    when T_167840 : 
      wire T_167844 : UInt<3>[3]
      T_167844[0] := UInt<3>(0)
      T_167844[1] := UInt<3>(1)
      T_167844[2] := UInt<3>(2)
      wire T_167845 : UInt<2>[2]
      T_167845[0] := UInt<2>(0)
      T_167845[1] := UInt<2>(1)
      wire T_167846 : UInt<2>[3]
      T_167846[0] := UInt<2>(1)
      T_167846[1] := UInt<2>(2)
      T_167846[2] := UInt<2>(3)
      wire T_167847 : UInt<2>[2]
      T_167847[0] := UInt<2>(2)
      T_167847[1] := UInt<2>(3)
      wire T_167848 : UInt<2>[1]
      T_167848[0] := UInt<2>(3)
      wire T_167849 : UInt<3>[3]
      T_167849[0] := UInt<3>(0)
      T_167849[1] := UInt<3>(1)
      T_167849[2] := UInt<3>(2)
      wire T_167850 : UInt<2>[2]
      T_167850[0] := UInt<2>(0)
      T_167850[1] := UInt<2>(1)
      wire T_167851 : UInt<2>[3]
      T_167851[0] := UInt<2>(1)
      T_167851[1] := UInt<2>(2)
      T_167851[2] := UInt<2>(3)
      wire T_167852 : UInt<2>[2]
      T_167852[0] := UInt<2>(2)
      T_167852[1] := UInt<2>(3)
      wire T_167853 : UInt<2>[1]
      T_167853[0] := UInt<2>(3)
      accessor T_167854 = T_167828[T_167829]
      T_167854 := enq.bits
      node T_167855 = eq(T_167829, UInt<1>(1))
      node T_167856 = and(UInt<1>(0), T_167855)
      node T_167857 = addw(T_167829, UInt<1>(1))
      wire T_167858 : UInt<1>
      T_167858 := T_167857
      when T_167856 : T_167858 := UInt<1>(0)
      T_167829 := T_167858
    when T_167843 : 
      node T_167859 = eq(T_167830, UInt<1>(1))
      node T_167860 = and(UInt<1>(0), T_167859)
      node T_167861 = addw(T_167830, UInt<1>(1))
      wire T_167862 : UInt<1>
      T_167862 := T_167861
      when T_167860 : T_167862 := UInt<1>(0)
      T_167830 := T_167862
    
    node T_167863 = neq(T_167840, T_167843)
    when T_167863 : T_167831 := T_167840
    node T_167864 = eq(T_167834, UInt<1>(0))
    node T_167865 = and(UInt<1>(0), enq.valid)
    node T_167866 = or(T_167864, T_167865)
    deq.valid := T_167866
    node T_167867 = eq(T_167835, UInt<1>(0))
    node T_167868 = and(UInt<1>(0), deq.ready)
    node T_167869 = or(T_167867, T_167868)
    enq.ready := T_167869
    wire T_167870 : UInt<3>[3]
    T_167870[0] := UInt<3>(0)
    T_167870[1] := UInt<3>(1)
    T_167870[2] := UInt<3>(2)
    wire T_167871 : UInt<2>[2]
    T_167871[0] := UInt<2>(0)
    T_167871[1] := UInt<2>(1)
    wire T_167872 : UInt<2>[3]
    T_167872[0] := UInt<2>(1)
    T_167872[1] := UInt<2>(2)
    T_167872[2] := UInt<2>(3)
    wire T_167873 : UInt<2>[2]
    T_167873[0] := UInt<2>(2)
    T_167873[1] := UInt<2>(3)
    wire T_167874 : UInt<2>[1]
    T_167874[0] := UInt<2>(3)
    wire T_167875 : UInt<3>[3]
    T_167875[0] := UInt<3>(0)
    T_167875[1] := UInt<3>(1)
    T_167875[2] := UInt<3>(2)
    wire T_167876 : UInt<2>[2]
    T_167876[0] := UInt<2>(0)
    T_167876[1] := UInt<2>(1)
    wire T_167877 : UInt<2>[3]
    T_167877[0] := UInt<2>(1)
    T_167877[1] := UInt<2>(2)
    T_167877[2] := UInt<2>(3)
    wire T_167878 : UInt<2>[2]
    T_167878[0] := UInt<2>(2)
    T_167878[1] := UInt<2>(3)
    wire T_167879 : UInt<2>[1]
    T_167879[0] := UInt<2>(3)
    accessor T_167880 = T_167828[T_167830]
    wire T_167881 : UInt<3>[3]
    T_167881[0] := UInt<3>(0)
    T_167881[1] := UInt<3>(1)
    T_167881[2] := UInt<3>(2)
    wire T_167882 : UInt<2>[2]
    T_167882[0] := UInt<2>(0)
    T_167882[1] := UInt<2>(1)
    wire T_167883 : UInt<2>[3]
    T_167883[0] := UInt<2>(1)
    T_167883[1] := UInt<2>(2)
    T_167883[2] := UInt<2>(3)
    wire T_167884 : UInt<2>[2]
    T_167884[0] := UInt<2>(2)
    T_167884[1] := UInt<2>(3)
    wire T_167885 : UInt<2>[1]
    T_167885[0] := UInt<2>(3)
    wire T_167886 : UInt<3>[3]
    T_167886[0] := UInt<3>(0)
    T_167886[1] := UInt<3>(1)
    T_167886[2] := UInt<3>(2)
    wire T_167887 : UInt<2>[2]
    T_167887[0] := UInt<2>(0)
    T_167887[1] := UInt<2>(1)
    wire T_167888 : UInt<2>[3]
    T_167888[0] := UInt<2>(1)
    T_167888[1] := UInt<2>(2)
    T_167888[2] := UInt<2>(3)
    wire T_167889 : UInt<2>[2]
    T_167889[0] := UInt<2>(2)
    T_167889[1] := UInt<2>(3)
    wire T_167890 : UInt<2>[1]
    T_167890[0] := UInt<2>(3)
    wire T_167891 : {fin : {manager_xact_id : UInt<2>}, dst : UInt<2>}
    T_167891 := T_167880
    when T_167836 : T_167891 := enq.bits
    deq.bits := T_167891
    node T_167892 = subw(T_167829, T_167830)
    node T_167893 = and(T_167831, T_167832)
    node T_167894 = cat(T_167893, T_167892)
    count := T_167894
  module FinishUnit_35200 : 
    input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output ready : UInt<1>
    
    wire T_167895 : UInt<3>[3]
    T_167895[0] := UInt<3>(0)
    T_167895[1] := UInt<3>(1)
    T_167895[2] := UInt<3>(2)
    wire T_167896 : UInt<2>[2]
    T_167896[0] := UInt<2>(0)
    T_167896[1] := UInt<2>(1)
    wire T_167897 : UInt<2>[3]
    T_167897[0] := UInt<2>(1)
    T_167897[1] := UInt<2>(2)
    T_167897[2] := UInt<2>(3)
    wire T_167898 : UInt<2>[2]
    T_167898[0] := UInt<2>(2)
    T_167898[1] := UInt<2>(3)
    wire T_167899 : UInt<2>[1]
    T_167899[0] := UInt<2>(3)
    wire T_167900 : UInt<3>[3]
    T_167900[0] := UInt<3>(0)
    T_167900[1] := UInt<3>(1)
    T_167900[2] := UInt<3>(2)
    wire T_167901 : UInt<2>[2]
    T_167901[0] := UInt<2>(0)
    T_167901[1] := UInt<2>(1)
    wire T_167902 : UInt<2>[3]
    T_167902[0] := UInt<2>(1)
    T_167902[1] := UInt<2>(2)
    T_167902[2] := UInt<2>(3)
    wire T_167903 : UInt<2>[2]
    T_167903[0] := UInt<2>(2)
    T_167903[1] := UInt<2>(3)
    wire T_167904 : UInt<2>[1]
    T_167904[0] := UInt<2>(3)
    wire T_167905 : UInt<3>[3]
    T_167905[0] := UInt<3>(0)
    T_167905[1] := UInt<3>(1)
    T_167905[2] := UInt<3>(2)
    wire T_167906 : UInt<2>[2]
    T_167906[0] := UInt<2>(0)
    T_167906[1] := UInt<2>(1)
    wire T_167907 : UInt<2>[3]
    T_167907[0] := UInt<2>(1)
    T_167907[1] := UInt<2>(2)
    T_167907[2] := UInt<2>(3)
    wire T_167908 : UInt<2>[2]
    T_167908[0] := UInt<2>(2)
    T_167908[1] := UInt<2>(3)
    wire T_167909 : UInt<2>[1]
    T_167909[0] := UInt<2>(3)
    wire T_167910 : UInt<3>[3]
    T_167910[0] := UInt<3>(0)
    T_167910[1] := UInt<3>(1)
    T_167910[2] := UInt<3>(2)
    wire T_167911 : UInt<2>[2]
    T_167911[0] := UInt<2>(0)
    T_167911[1] := UInt<2>(1)
    wire T_167912 : UInt<2>[3]
    T_167912[0] := UInt<2>(1)
    T_167912[1] := UInt<2>(2)
    T_167912[2] := UInt<2>(3)
    wire T_167913 : UInt<2>[2]
    T_167913[0] := UInt<2>(2)
    T_167913[1] := UInt<2>(3)
    wire T_167914 : UInt<2>[1]
    T_167914[0] := UInt<2>(3)
    wire T_167915 : UInt<3>[3]
    T_167915[0] := UInt<3>(0)
    T_167915[1] := UInt<3>(1)
    T_167915[2] := UInt<3>(2)
    wire T_167916 : UInt<2>[2]
    T_167916[0] := UInt<2>(0)
    T_167916[1] := UInt<2>(1)
    wire T_167917 : UInt<2>[3]
    T_167917[0] := UInt<2>(1)
    T_167917[1] := UInt<2>(2)
    T_167917[2] := UInt<2>(3)
    wire T_167918 : UInt<2>[2]
    T_167918[0] := UInt<2>(2)
    T_167918[1] := UInt<2>(3)
    wire T_167919 : UInt<2>[1]
    T_167919[0] := UInt<2>(3)
    wire T_167920 : UInt<3>[3]
    T_167920[0] := UInt<3>(0)
    T_167920[1] := UInt<3>(1)
    T_167920[2] := UInt<3>(2)
    wire T_167921 : UInt<2>[2]
    T_167921[0] := UInt<2>(0)
    T_167921[1] := UInt<2>(1)
    wire T_167922 : UInt<2>[3]
    T_167922[0] := UInt<2>(1)
    T_167922[1] := UInt<2>(2)
    T_167922[2] := UInt<2>(3)
    wire T_167923 : UInt<2>[2]
    T_167923[0] := UInt<2>(2)
    T_167923[1] := UInt<2>(3)
    wire T_167924 : UInt<2>[1]
    T_167924[0] := UInt<2>(3)
    wire T_167925 : UInt<3>[3]
    T_167925[0] := UInt<3>(0)
    T_167925[1] := UInt<3>(1)
    T_167925[2] := UInt<3>(2)
    wire T_167926 : UInt<2>[2]
    T_167926[0] := UInt<2>(0)
    T_167926[1] := UInt<2>(1)
    wire T_167927 : UInt<2>[3]
    T_167927[0] := UInt<2>(1)
    T_167927[1] := UInt<2>(2)
    T_167927[2] := UInt<2>(3)
    wire T_167928 : UInt<2>[2]
    T_167928[0] := UInt<2>(2)
    T_167928[1] := UInt<2>(3)
    wire T_167929 : UInt<2>[1]
    T_167929[0] := UInt<2>(3)
    wire T_167930 : UInt<3>[3]
    T_167930[0] := UInt<3>(0)
    T_167930[1] := UInt<3>(1)
    T_167930[2] := UInt<3>(2)
    wire T_167931 : UInt<2>[2]
    T_167931[0] := UInt<2>(0)
    T_167931[1] := UInt<2>(1)
    wire T_167932 : UInt<2>[3]
    T_167932[0] := UInt<2>(1)
    T_167932[1] := UInt<2>(2)
    T_167932[2] := UInt<2>(3)
    wire T_167933 : UInt<2>[2]
    T_167933[0] := UInt<2>(2)
    T_167933[1] := UInt<2>(3)
    wire T_167934 : UInt<2>[1]
    T_167934[0] := UInt<2>(3)
    wire T_167935 : UInt<3>[3]
    T_167935[0] := UInt<3>(0)
    T_167935[1] := UInt<3>(1)
    T_167935[2] := UInt<3>(2)
    wire T_167936 : UInt<2>[2]
    T_167936[0] := UInt<2>(0)
    T_167936[1] := UInt<2>(1)
    wire T_167937 : UInt<2>[3]
    T_167937[0] := UInt<2>(1)
    T_167937[1] := UInt<2>(2)
    T_167937[2] := UInt<2>(3)
    wire T_167938 : UInt<2>[2]
    T_167938[0] := UInt<2>(2)
    T_167938[1] := UInt<2>(3)
    wire T_167939 : UInt<2>[1]
    T_167939[0] := UInt<2>(3)
    node T_167940 = and(grant.ready, grant.valid)
    wire T_167941 : UInt<3>[1]
    T_167941[0] := UInt<3>(5)
    node T_167942 = eq(T_167941[0], grant.bits.payload.g_type)
    node T_167943 = or(UInt<1>(0), T_167942)
    node T_167944 = eq(T_167911[0], grant.bits.payload.g_type)
    node T_167945 = eq(T_167911[1], grant.bits.payload.g_type)
    node T_167946 = or(UInt<1>(0), T_167944)
    node T_167947 = or(T_167946, T_167945)
    wire T_167948 : UInt<1>
    T_167948 := T_167947
    when grant.bits.payload.is_builtin_type : T_167948 := T_167943
    node T_167949 = and(UInt<1>(1), T_167948)
    node T_167950 = and(T_167940, T_167949)
    reg T_167951 : UInt<2>
    onreset T_167951 := UInt<2>(0)
    when T_167950 : 
      node T_167952 = eq(T_167951, UInt<2>(3))
      node T_167953 = and(UInt<1>(0), T_167952)
      node T_167954 = addw(T_167951, UInt<1>(1))
      wire T_167955 : UInt<2>
      T_167955 := T_167954
      when T_167953 : T_167955 := UInt<1>(0)
      T_167951 := T_167955
    node T_167956 = and(T_167950, T_167952)
    wire T_167957 : UInt<1>
    T_167957 := UInt<1>(0)
    when T_167949 : T_167957 := T_167951
    wire T_167958 : UInt<1>
    T_167958 := T_167940
    when T_167949 : T_167958 := T_167956
    wire T_167959 : UInt<3>[3]
    T_167959[0] := UInt<3>(0)
    T_167959[1] := UInt<3>(1)
    T_167959[2] := UInt<3>(2)
    wire T_167960 : UInt<2>[2]
    T_167960[0] := UInt<2>(0)
    T_167960[1] := UInt<2>(1)
    wire T_167961 : UInt<2>[3]
    T_167961[0] := UInt<2>(1)
    T_167961[1] := UInt<2>(2)
    T_167961[2] := UInt<2>(3)
    wire T_167962 : UInt<2>[2]
    T_167962[0] := UInt<2>(2)
    T_167962[1] := UInt<2>(3)
    wire T_167963 : UInt<2>[1]
    T_167963[0] := UInt<2>(3)
    wire T_167964 : UInt<3>[3]
    T_167964[0] := UInt<3>(0)
    T_167964[1] := UInt<3>(1)
    T_167964[2] := UInt<3>(2)
    wire T_167965 : UInt<2>[2]
    T_167965[0] := UInt<2>(0)
    T_167965[1] := UInt<2>(1)
    wire T_167966 : UInt<2>[3]
    T_167966[0] := UInt<2>(1)
    T_167966[1] := UInt<2>(2)
    T_167966[2] := UInt<2>(3)
    wire T_167967 : UInt<2>[2]
    T_167967[0] := UInt<2>(2)
    T_167967[1] := UInt<2>(3)
    wire T_167968 : UInt<2>[1]
    T_167968[0] := UInt<2>(3)
    inst T_167969 of FinishQueue_35038
    node T_167970 = and(grant.ready, grant.valid)
    node T_167971 = eq(UInt<1>(0), UInt<1>(0))
    node T_167972 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_167973 = and(grant.bits.payload.is_builtin_type, T_167972)
    node T_167974 = eq(T_167973, UInt<1>(0))
    node T_167975 = and(T_167971, T_167974)
    node T_167976 = and(T_167970, T_167975)
    wire T_167977 : UInt<3>[1]
    T_167977[0] := UInt<3>(5)
    node T_167978 = eq(T_167977[0], grant.bits.payload.g_type)
    node T_167979 = or(UInt<1>(0), T_167978)
    node T_167980 = eq(T_167911[0], grant.bits.payload.g_type)
    node T_167981 = eq(T_167911[1], grant.bits.payload.g_type)
    node T_167982 = or(UInt<1>(0), T_167980)
    node T_167983 = or(T_167982, T_167981)
    wire T_167984 : UInt<1>
    T_167984 := T_167983
    when grant.bits.payload.is_builtin_type : T_167984 := T_167979
    node T_167985 = and(UInt<1>(1), T_167984)
    node T_167986 = eq(T_167985, UInt<1>(0))
    node T_167987 = or(T_167986, T_167958)
    node T_167988 = and(T_167976, T_167987)
    T_167969.enq.valid := T_167988
    wire T_167989 : UInt<3>[3]
    T_167989[0] := UInt<3>(0)
    T_167989[1] := UInt<3>(1)
    T_167989[2] := UInt<3>(2)
    wire T_167990 : UInt<2>[2]
    T_167990[0] := UInt<2>(0)
    T_167990[1] := UInt<2>(1)
    wire T_167991 : UInt<2>[3]
    T_167991[0] := UInt<2>(1)
    T_167991[1] := UInt<2>(2)
    T_167991[2] := UInt<2>(3)
    wire T_167992 : UInt<2>[2]
    T_167992[0] := UInt<2>(2)
    T_167992[1] := UInt<2>(3)
    wire T_167993 : UInt<2>[1]
    T_167993[0] := UInt<2>(3)
    wire T_167994 : UInt<3>[3]
    T_167994[0] := UInt<3>(0)
    T_167994[1] := UInt<3>(1)
    T_167994[2] := UInt<3>(2)
    wire T_167995 : UInt<2>[2]
    T_167995[0] := UInt<2>(0)
    T_167995[1] := UInt<2>(1)
    wire T_167996 : UInt<2>[3]
    T_167996[0] := UInt<2>(1)
    T_167996[1] := UInt<2>(2)
    T_167996[2] := UInt<2>(3)
    wire T_167997 : UInt<2>[2]
    T_167997[0] := UInt<2>(2)
    T_167997[1] := UInt<2>(3)
    wire T_167998 : UInt<2>[1]
    T_167998[0] := UInt<2>(3)
    wire T_167999 : {manager_xact_id : UInt<2>}
    T_167999.manager_xact_id := grant.bits.payload.manager_xact_id
    T_167969.enq.bits.fin := T_167999
    T_167969.enq.bits.dst := grant.bits.header.src
    finish.bits.header.src := UInt<2>(2)
    finish.bits.header.dst := T_167969.deq.bits.dst
    finish.bits.payload := T_167969.deq.bits.fin
    finish.valid := T_167969.deq.valid
    T_167969.deq.ready := finish.ready
    refill.valid := grant.valid
    refill.bits := grant.bits.payload
    node T_168000 = eq(UInt<1>(0), UInt<1>(0))
    node T_168001 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_168002 = and(grant.bits.payload.is_builtin_type, T_168001)
    node T_168003 = eq(T_168002, UInt<1>(0))
    node T_168004 = and(T_168000, T_168003)
    node T_168005 = eq(T_168004, UInt<1>(0))
    node T_168006 = or(T_167969.enq.ready, T_168005)
    node T_168007 = and(T_168006, refill.ready)
    grant.ready := T_168007
    ready := T_167969.enq.ready
  module ClientTileLinkNetworkPort_35756 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_168008 : UInt<3>[3]
    T_168008[0] := UInt<3>(0)
    T_168008[1] := UInt<3>(1)
    T_168008[2] := UInt<3>(2)
    wire T_168009 : UInt<2>[2]
    T_168009[0] := UInt<2>(0)
    T_168009[1] := UInt<2>(1)
    wire T_168010 : UInt<2>[3]
    T_168010[0] := UInt<2>(1)
    T_168010[1] := UInt<2>(2)
    T_168010[2] := UInt<2>(3)
    wire T_168011 : UInt<2>[2]
    T_168011[0] := UInt<2>(2)
    T_168011[1] := UInt<2>(3)
    wire T_168012 : UInt<2>[1]
    T_168012[0] := UInt<2>(3)
    wire T_168013 : UInt<3>[3]
    T_168013[0] := UInt<3>(0)
    T_168013[1] := UInt<3>(1)
    T_168013[2] := UInt<3>(2)
    wire T_168014 : UInt<2>[2]
    T_168014[0] := UInt<2>(0)
    T_168014[1] := UInt<2>(1)
    wire T_168015 : UInt<2>[3]
    T_168015[0] := UInt<2>(1)
    T_168015[1] := UInt<2>(2)
    T_168015[2] := UInt<2>(3)
    wire T_168016 : UInt<2>[2]
    T_168016[0] := UInt<2>(2)
    T_168016[1] := UInt<2>(3)
    wire T_168017 : UInt<2>[1]
    T_168017[0] := UInt<2>(3)
    wire T_168018 : UInt<3>[3]
    T_168018[0] := UInt<3>(0)
    T_168018[1] := UInt<3>(1)
    T_168018[2] := UInt<3>(2)
    wire T_168019 : UInt<2>[2]
    T_168019[0] := UInt<2>(0)
    T_168019[1] := UInt<2>(1)
    wire T_168020 : UInt<2>[3]
    T_168020[0] := UInt<2>(1)
    T_168020[1] := UInt<2>(2)
    T_168020[2] := UInt<2>(3)
    wire T_168021 : UInt<2>[2]
    T_168021[0] := UInt<2>(2)
    T_168021[1] := UInt<2>(3)
    wire T_168022 : UInt<2>[1]
    T_168022[0] := UInt<2>(3)
    wire T_168023 : UInt<3>[3]
    T_168023[0] := UInt<3>(0)
    T_168023[1] := UInt<3>(1)
    T_168023[2] := UInt<3>(2)
    wire T_168024 : UInt<2>[2]
    T_168024[0] := UInt<2>(0)
    T_168024[1] := UInt<2>(1)
    wire T_168025 : UInt<2>[3]
    T_168025[0] := UInt<2>(1)
    T_168025[1] := UInt<2>(2)
    T_168025[2] := UInt<2>(3)
    wire T_168026 : UInt<2>[2]
    T_168026[0] := UInt<2>(2)
    T_168026[1] := UInt<2>(3)
    wire T_168027 : UInt<2>[1]
    T_168027[0] := UInt<2>(3)
    wire T_168028 : UInt<3>[3]
    T_168028[0] := UInt<3>(0)
    T_168028[1] := UInt<3>(1)
    T_168028[2] := UInt<3>(2)
    wire T_168029 : UInt<2>[2]
    T_168029[0] := UInt<2>(0)
    T_168029[1] := UInt<2>(1)
    wire T_168030 : UInt<2>[3]
    T_168030[0] := UInt<2>(1)
    T_168030[1] := UInt<2>(2)
    T_168030[2] := UInt<2>(3)
    wire T_168031 : UInt<2>[2]
    T_168031[0] := UInt<2>(2)
    T_168031[1] := UInt<2>(3)
    wire T_168032 : UInt<2>[1]
    T_168032[0] := UInt<2>(3)
    wire T_168033 : UInt<3>[3]
    T_168033[0] := UInt<3>(0)
    T_168033[1] := UInt<3>(1)
    T_168033[2] := UInt<3>(2)
    wire T_168034 : UInt<2>[2]
    T_168034[0] := UInt<2>(0)
    T_168034[1] := UInt<2>(1)
    wire T_168035 : UInt<2>[3]
    T_168035[0] := UInt<2>(1)
    T_168035[1] := UInt<2>(2)
    T_168035[2] := UInt<2>(3)
    wire T_168036 : UInt<2>[2]
    T_168036[0] := UInt<2>(2)
    T_168036[1] := UInt<2>(3)
    wire T_168037 : UInt<2>[1]
    T_168037[0] := UInt<2>(3)
    wire T_168038 : UInt<3>[3]
    T_168038[0] := UInt<3>(0)
    T_168038[1] := UInt<3>(1)
    T_168038[2] := UInt<3>(2)
    wire T_168039 : UInt<2>[2]
    T_168039[0] := UInt<2>(0)
    T_168039[1] := UInt<2>(1)
    wire T_168040 : UInt<2>[3]
    T_168040[0] := UInt<2>(1)
    T_168040[1] := UInt<2>(2)
    T_168040[2] := UInt<2>(3)
    wire T_168041 : UInt<2>[2]
    T_168041[0] := UInt<2>(2)
    T_168041[1] := UInt<2>(3)
    wire T_168042 : UInt<2>[1]
    T_168042[0] := UInt<2>(3)
    wire T_168043 : UInt<3>[3]
    T_168043[0] := UInt<3>(0)
    T_168043[1] := UInt<3>(1)
    T_168043[2] := UInt<3>(2)
    wire T_168044 : UInt<2>[2]
    T_168044[0] := UInt<2>(0)
    T_168044[1] := UInt<2>(1)
    wire T_168045 : UInt<2>[3]
    T_168045[0] := UInt<2>(1)
    T_168045[1] := UInt<2>(2)
    T_168045[2] := UInt<2>(3)
    wire T_168046 : UInt<2>[2]
    T_168046[0] := UInt<2>(2)
    T_168046[1] := UInt<2>(3)
    wire T_168047 : UInt<2>[1]
    T_168047[0] := UInt<2>(3)
    wire T_168048 : UInt<3>[3]
    T_168048[0] := UInt<3>(0)
    T_168048[1] := UInt<3>(1)
    T_168048[2] := UInt<3>(2)
    wire T_168049 : UInt<2>[2]
    T_168049[0] := UInt<2>(0)
    T_168049[1] := UInt<2>(1)
    wire T_168050 : UInt<2>[3]
    T_168050[0] := UInt<2>(1)
    T_168050[1] := UInt<2>(2)
    T_168050[2] := UInt<2>(3)
    wire T_168051 : UInt<2>[2]
    T_168051[0] := UInt<2>(2)
    T_168051[1] := UInt<2>(3)
    wire T_168052 : UInt<2>[1]
    T_168052[0] := UInt<2>(3)
    wire T_168053 : UInt<3>[3]
    T_168053[0] := UInt<3>(0)
    T_168053[1] := UInt<3>(1)
    T_168053[2] := UInt<3>(2)
    wire T_168054 : UInt<2>[2]
    T_168054[0] := UInt<2>(0)
    T_168054[1] := UInt<2>(1)
    wire T_168055 : UInt<2>[3]
    T_168055[0] := UInt<2>(1)
    T_168055[1] := UInt<2>(2)
    T_168055[2] := UInt<2>(3)
    wire T_168056 : UInt<2>[2]
    T_168056[0] := UInt<2>(2)
    T_168056[1] := UInt<2>(3)
    wire T_168057 : UInt<2>[1]
    T_168057[0] := UInt<2>(3)
    wire T_168058 : UInt<3>[3]
    T_168058[0] := UInt<3>(0)
    T_168058[1] := UInt<3>(1)
    T_168058[2] := UInt<3>(2)
    wire T_168059 : UInt<2>[2]
    T_168059[0] := UInt<2>(0)
    T_168059[1] := UInt<2>(1)
    wire T_168060 : UInt<2>[3]
    T_168060[0] := UInt<2>(1)
    T_168060[1] := UInt<2>(2)
    T_168060[2] := UInt<2>(3)
    wire T_168061 : UInt<2>[2]
    T_168061[0] := UInt<2>(2)
    T_168061[1] := UInt<2>(3)
    wire T_168062 : UInt<2>[1]
    T_168062[0] := UInt<2>(3)
    wire T_168063 : UInt<3>[3]
    T_168063[0] := UInt<3>(0)
    T_168063[1] := UInt<3>(1)
    T_168063[2] := UInt<3>(2)
    wire T_168064 : UInt<2>[2]
    T_168064[0] := UInt<2>(0)
    T_168064[1] := UInt<2>(1)
    wire T_168065 : UInt<2>[3]
    T_168065[0] := UInt<2>(1)
    T_168065[1] := UInt<2>(2)
    T_168065[2] := UInt<2>(3)
    wire T_168066 : UInt<2>[2]
    T_168066[0] := UInt<2>(2)
    T_168066[1] := UInt<2>(3)
    wire T_168067 : UInt<2>[1]
    T_168067[0] := UInt<2>(3)
    wire T_168068 : UInt<3>[3]
    T_168068[0] := UInt<3>(0)
    T_168068[1] := UInt<3>(1)
    T_168068[2] := UInt<3>(2)
    wire T_168069 : UInt<2>[2]
    T_168069[0] := UInt<2>(0)
    T_168069[1] := UInt<2>(1)
    wire T_168070 : UInt<2>[3]
    T_168070[0] := UInt<2>(1)
    T_168070[1] := UInt<2>(2)
    T_168070[2] := UInt<2>(3)
    wire T_168071 : UInt<2>[2]
    T_168071[0] := UInt<2>(2)
    T_168071[1] := UInt<2>(3)
    wire T_168072 : UInt<2>[1]
    T_168072[0] := UInt<2>(3)
    wire T_168073 : UInt<3>[3]
    T_168073[0] := UInt<3>(0)
    T_168073[1] := UInt<3>(1)
    T_168073[2] := UInt<3>(2)
    wire T_168074 : UInt<2>[2]
    T_168074[0] := UInt<2>(0)
    T_168074[1] := UInt<2>(1)
    wire T_168075 : UInt<2>[3]
    T_168075[0] := UInt<2>(1)
    T_168075[1] := UInt<2>(2)
    T_168075[2] := UInt<2>(3)
    wire T_168076 : UInt<2>[2]
    T_168076[0] := UInt<2>(2)
    T_168076[1] := UInt<2>(3)
    wire T_168077 : UInt<2>[1]
    T_168077[0] := UInt<2>(3)
    wire T_168078 : UInt<3>[3]
    T_168078[0] := UInt<3>(0)
    T_168078[1] := UInt<3>(1)
    T_168078[2] := UInt<3>(2)
    wire T_168079 : UInt<2>[2]
    T_168079[0] := UInt<2>(0)
    T_168079[1] := UInt<2>(1)
    wire T_168080 : UInt<2>[3]
    T_168080[0] := UInt<2>(1)
    T_168080[1] := UInt<2>(2)
    T_168080[2] := UInt<2>(3)
    wire T_168081 : UInt<2>[2]
    T_168081[0] := UInt<2>(2)
    T_168081[1] := UInt<2>(3)
    wire T_168082 : UInt<2>[1]
    T_168082[0] := UInt<2>(3)
    wire T_168083 : UInt<3>[3]
    T_168083[0] := UInt<3>(0)
    T_168083[1] := UInt<3>(1)
    T_168083[2] := UInt<3>(2)
    wire T_168084 : UInt<2>[2]
    T_168084[0] := UInt<2>(0)
    T_168084[1] := UInt<2>(1)
    wire T_168085 : UInt<2>[3]
    T_168085[0] := UInt<2>(1)
    T_168085[1] := UInt<2>(2)
    T_168085[2] := UInt<2>(3)
    wire T_168086 : UInt<2>[2]
    T_168086[0] := UInt<2>(2)
    T_168086[1] := UInt<2>(3)
    wire T_168087 : UInt<2>[1]
    T_168087[0] := UInt<2>(3)
    wire T_168088 : UInt<3>[3]
    T_168088[0] := UInt<3>(0)
    T_168088[1] := UInt<3>(1)
    T_168088[2] := UInt<3>(2)
    wire T_168089 : UInt<2>[2]
    T_168089[0] := UInt<2>(0)
    T_168089[1] := UInt<2>(1)
    wire T_168090 : UInt<2>[3]
    T_168090[0] := UInt<2>(1)
    T_168090[1] := UInt<2>(2)
    T_168090[2] := UInt<2>(3)
    wire T_168091 : UInt<2>[2]
    T_168091[0] := UInt<2>(2)
    T_168091[1] := UInt<2>(3)
    wire T_168092 : UInt<2>[1]
    T_168092[0] := UInt<2>(3)
    wire T_168093 : UInt<3>[3]
    T_168093[0] := UInt<3>(0)
    T_168093[1] := UInt<3>(1)
    T_168093[2] := UInt<3>(2)
    wire T_168094 : UInt<2>[2]
    T_168094[0] := UInt<2>(0)
    T_168094[1] := UInt<2>(1)
    wire T_168095 : UInt<2>[3]
    T_168095[0] := UInt<2>(1)
    T_168095[1] := UInt<2>(2)
    T_168095[2] := UInt<2>(3)
    wire T_168096 : UInt<2>[2]
    T_168096[0] := UInt<2>(2)
    T_168096[1] := UInt<2>(3)
    wire T_168097 : UInt<2>[1]
    T_168097[0] := UInt<2>(3)
    wire T_168098 : UInt<3>[3]
    T_168098[0] := UInt<3>(0)
    T_168098[1] := UInt<3>(1)
    T_168098[2] := UInt<3>(2)
    wire T_168099 : UInt<2>[2]
    T_168099[0] := UInt<2>(0)
    T_168099[1] := UInt<2>(1)
    wire T_168100 : UInt<2>[3]
    T_168100[0] := UInt<2>(1)
    T_168100[1] := UInt<2>(2)
    T_168100[2] := UInt<2>(3)
    wire T_168101 : UInt<2>[2]
    T_168101[0] := UInt<2>(2)
    T_168101[1] := UInt<2>(3)
    wire T_168102 : UInt<2>[1]
    T_168102[0] := UInt<2>(3)
    wire T_168103 : UInt<3>[3]
    T_168103[0] := UInt<3>(0)
    T_168103[1] := UInt<3>(1)
    T_168103[2] := UInt<3>(2)
    wire T_168104 : UInt<2>[2]
    T_168104[0] := UInt<2>(0)
    T_168104[1] := UInt<2>(1)
    wire T_168105 : UInt<2>[3]
    T_168105[0] := UInt<2>(1)
    T_168105[1] := UInt<2>(2)
    T_168105[2] := UInt<2>(3)
    wire T_168106 : UInt<2>[2]
    T_168106[0] := UInt<2>(2)
    T_168106[1] := UInt<2>(3)
    wire T_168107 : UInt<2>[1]
    T_168107[0] := UInt<2>(3)
    wire T_168108 : UInt<3>[3]
    T_168108[0] := UInt<3>(0)
    T_168108[1] := UInt<3>(1)
    T_168108[2] := UInt<3>(2)
    wire T_168109 : UInt<2>[2]
    T_168109[0] := UInt<2>(0)
    T_168109[1] := UInt<2>(1)
    wire T_168110 : UInt<2>[3]
    T_168110[0] := UInt<2>(1)
    T_168110[1] := UInt<2>(2)
    T_168110[2] := UInt<2>(3)
    wire T_168111 : UInt<2>[2]
    T_168111[0] := UInt<2>(2)
    T_168111[1] := UInt<2>(3)
    wire T_168112 : UInt<2>[1]
    T_168112[0] := UInt<2>(3)
    wire T_168113 : UInt<3>[3]
    T_168113[0] := UInt<3>(0)
    T_168113[1] := UInt<3>(1)
    T_168113[2] := UInt<3>(2)
    wire T_168114 : UInt<2>[2]
    T_168114[0] := UInt<2>(0)
    T_168114[1] := UInt<2>(1)
    wire T_168115 : UInt<2>[3]
    T_168115[0] := UInt<2>(1)
    T_168115[1] := UInt<2>(2)
    T_168115[2] := UInt<2>(3)
    wire T_168116 : UInt<2>[2]
    T_168116[0] := UInt<2>(2)
    T_168116[1] := UInt<2>(3)
    wire T_168117 : UInt<2>[1]
    T_168117[0] := UInt<2>(3)
    wire T_168118 : UInt<3>[3]
    T_168118[0] := UInt<3>(0)
    T_168118[1] := UInt<3>(1)
    T_168118[2] := UInt<3>(2)
    wire T_168119 : UInt<2>[2]
    T_168119[0] := UInt<2>(0)
    T_168119[1] := UInt<2>(1)
    wire T_168120 : UInt<2>[3]
    T_168120[0] := UInt<2>(1)
    T_168120[1] := UInt<2>(2)
    T_168120[2] := UInt<2>(3)
    wire T_168121 : UInt<2>[2]
    T_168121[0] := UInt<2>(2)
    T_168121[1] := UInt<2>(3)
    wire T_168122 : UInt<2>[1]
    T_168122[0] := UInt<2>(3)
    wire T_168123 : UInt<3>[3]
    T_168123[0] := UInt<3>(0)
    T_168123[1] := UInt<3>(1)
    T_168123[2] := UInt<3>(2)
    wire T_168124 : UInt<2>[2]
    T_168124[0] := UInt<2>(0)
    T_168124[1] := UInt<2>(1)
    wire T_168125 : UInt<2>[3]
    T_168125[0] := UInt<2>(1)
    T_168125[1] := UInt<2>(2)
    T_168125[2] := UInt<2>(3)
    wire T_168126 : UInt<2>[2]
    T_168126[0] := UInt<2>(2)
    T_168126[1] := UInt<2>(3)
    wire T_168127 : UInt<2>[1]
    T_168127[0] := UInt<2>(3)
    wire T_168128 : UInt<3>[3]
    T_168128[0] := UInt<3>(0)
    T_168128[1] := UInt<3>(1)
    T_168128[2] := UInt<3>(2)
    wire T_168129 : UInt<2>[2]
    T_168129[0] := UInt<2>(0)
    T_168129[1] := UInt<2>(1)
    wire T_168130 : UInt<2>[3]
    T_168130[0] := UInt<2>(1)
    T_168130[1] := UInt<2>(2)
    T_168130[2] := UInt<2>(3)
    wire T_168131 : UInt<2>[2]
    T_168131[0] := UInt<2>(2)
    T_168131[1] := UInt<2>(3)
    wire T_168132 : UInt<2>[1]
    T_168132[0] := UInt<2>(3)
    wire T_168133 : UInt<3>[3]
    T_168133[0] := UInt<3>(0)
    T_168133[1] := UInt<3>(1)
    T_168133[2] := UInt<3>(2)
    wire T_168134 : UInt<2>[2]
    T_168134[0] := UInt<2>(0)
    T_168134[1] := UInt<2>(1)
    wire T_168135 : UInt<2>[3]
    T_168135[0] := UInt<2>(1)
    T_168135[1] := UInt<2>(2)
    T_168135[2] := UInt<2>(3)
    wire T_168136 : UInt<2>[2]
    T_168136[0] := UInt<2>(2)
    T_168136[1] := UInt<2>(3)
    wire T_168137 : UInt<2>[1]
    T_168137[0] := UInt<2>(3)
    inst finisher of FinishUnit_35200
    finisher.grant <> network.grant
    network.finish <> finisher.finish
    wire T_168138 : UInt<3>[3]
    T_168138[0] := UInt<3>(0)
    T_168138[1] := UInt<3>(1)
    T_168138[2] := UInt<3>(2)
    wire T_168139 : UInt<2>[2]
    T_168139[0] := UInt<2>(0)
    T_168139[1] := UInt<2>(1)
    wire T_168140 : UInt<2>[3]
    T_168140[0] := UInt<2>(1)
    T_168140[1] := UInt<2>(2)
    T_168140[2] := UInt<2>(3)
    wire T_168141 : UInt<2>[2]
    T_168141[0] := UInt<2>(2)
    T_168141[1] := UInt<2>(3)
    wire T_168142 : UInt<2>[1]
    T_168142[0] := UInt<2>(3)
    wire T_168143 : UInt<3>[3]
    T_168143[0] := UInt<3>(0)
    T_168143[1] := UInt<3>(1)
    T_168143[2] := UInt<3>(2)
    wire T_168144 : UInt<2>[2]
    T_168144[0] := UInt<2>(0)
    T_168144[1] := UInt<2>(1)
    wire T_168145 : UInt<2>[3]
    T_168145[0] := UInt<2>(1)
    T_168145[1] := UInt<2>(2)
    T_168145[2] := UInt<2>(3)
    wire T_168146 : UInt<2>[2]
    T_168146[0] := UInt<2>(2)
    T_168146[1] := UInt<2>(3)
    wire T_168147 : UInt<2>[1]
    T_168147[0] := UInt<2>(3)
    wire T_168148 : UInt<3>[3]
    T_168148[0] := UInt<3>(0)
    T_168148[1] := UInt<3>(1)
    T_168148[2] := UInt<3>(2)
    wire T_168149 : UInt<2>[2]
    T_168149[0] := UInt<2>(0)
    T_168149[1] := UInt<2>(1)
    wire T_168150 : UInt<2>[3]
    T_168150[0] := UInt<2>(1)
    T_168150[1] := UInt<2>(2)
    T_168150[2] := UInt<2>(3)
    wire T_168151 : UInt<2>[2]
    T_168151[0] := UInt<2>(2)
    T_168151[1] := UInt<2>(3)
    wire T_168152 : UInt<2>[1]
    T_168152[0] := UInt<2>(3)
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    acq_with_header.bits.payload := client.acquire.bits
    acq_with_header.bits.header.src := UInt<2>(2)
    acq_with_header.bits.header.dst := UInt<1>(0)
    acq_with_header.valid := client.acquire.valid
    client.acquire.ready := acq_with_header.ready
    wire T_168153 : UInt<3>[3]
    T_168153[0] := UInt<3>(0)
    T_168153[1] := UInt<3>(1)
    T_168153[2] := UInt<3>(2)
    wire T_168154 : UInt<2>[2]
    T_168154[0] := UInt<2>(0)
    T_168154[1] := UInt<2>(1)
    wire T_168155 : UInt<2>[3]
    T_168155[0] := UInt<2>(1)
    T_168155[1] := UInt<2>(2)
    T_168155[2] := UInt<2>(3)
    wire T_168156 : UInt<2>[2]
    T_168156[0] := UInt<2>(2)
    T_168156[1] := UInt<2>(3)
    wire T_168157 : UInt<2>[1]
    T_168157[0] := UInt<2>(3)
    wire T_168158 : UInt<3>[3]
    T_168158[0] := UInt<3>(0)
    T_168158[1] := UInt<3>(1)
    T_168158[2] := UInt<3>(2)
    wire T_168159 : UInt<2>[2]
    T_168159[0] := UInt<2>(0)
    T_168159[1] := UInt<2>(1)
    wire T_168160 : UInt<2>[3]
    T_168160[0] := UInt<2>(1)
    T_168160[1] := UInt<2>(2)
    T_168160[2] := UInt<2>(3)
    wire T_168161 : UInt<2>[2]
    T_168161[0] := UInt<2>(2)
    T_168161[1] := UInt<2>(3)
    wire T_168162 : UInt<2>[1]
    T_168162[0] := UInt<2>(3)
    wire T_168163 : UInt<3>[3]
    T_168163[0] := UInt<3>(0)
    T_168163[1] := UInt<3>(1)
    T_168163[2] := UInt<3>(2)
    wire T_168164 : UInt<2>[2]
    T_168164[0] := UInt<2>(0)
    T_168164[1] := UInt<2>(1)
    wire T_168165 : UInt<2>[3]
    T_168165[0] := UInt<2>(1)
    T_168165[1] := UInt<2>(2)
    T_168165[2] := UInt<2>(3)
    wire T_168166 : UInt<2>[2]
    T_168166[0] := UInt<2>(2)
    T_168166[1] := UInt<2>(3)
    wire T_168167 : UInt<2>[1]
    T_168167[0] := UInt<2>(3)
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    rel_with_header.bits.payload := client.release.bits
    rel_with_header.bits.header.src := UInt<2>(2)
    rel_with_header.bits.header.dst := UInt<1>(0)
    rel_with_header.valid := client.release.valid
    client.release.ready := rel_with_header.ready
    wire T_168168 : UInt<3>[3]
    T_168168[0] := UInt<3>(0)
    T_168168[1] := UInt<3>(1)
    T_168168[2] := UInt<3>(2)
    wire T_168169 : UInt<2>[2]
    T_168169[0] := UInt<2>(0)
    T_168169[1] := UInt<2>(1)
    wire T_168170 : UInt<2>[3]
    T_168170[0] := UInt<2>(1)
    T_168170[1] := UInt<2>(2)
    T_168170[2] := UInt<2>(3)
    wire T_168171 : UInt<2>[2]
    T_168171[0] := UInt<2>(2)
    T_168171[1] := UInt<2>(3)
    wire T_168172 : UInt<2>[1]
    T_168172[0] := UInt<2>(3)
    wire T_168173 : UInt<3>[3]
    T_168173[0] := UInt<3>(0)
    T_168173[1] := UInt<3>(1)
    T_168173[2] := UInt<3>(2)
    wire T_168174 : UInt<2>[2]
    T_168174[0] := UInt<2>(0)
    T_168174[1] := UInt<2>(1)
    wire T_168175 : UInt<2>[3]
    T_168175[0] := UInt<2>(1)
    T_168175[1] := UInt<2>(2)
    T_168175[2] := UInt<2>(3)
    wire T_168176 : UInt<2>[2]
    T_168176[0] := UInt<2>(2)
    T_168176[1] := UInt<2>(3)
    wire T_168177 : UInt<2>[1]
    T_168177[0] := UInt<2>(3)
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header.valid := network.probe.valid
    prb_without_header.bits := network.probe.bits.payload
    network.probe.ready := prb_without_header.ready
    network.acquire.bits := acq_with_header.bits
    node T_168178 = and(acq_with_header.valid, finisher.ready)
    network.acquire.valid := T_168178
    node T_168179 = and(network.acquire.ready, finisher.ready)
    acq_with_header.ready := T_168179
    network.release <> rel_with_header
    client.probe <> prb_without_header
    client.grant <> finisher.refill
  module Queue_38541 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output count : UInt<2>
    
    wire T_168180 : UInt<3>[3]
    T_168180[0] := UInt<3>(0)
    T_168180[1] := UInt<3>(1)
    T_168180[2] := UInt<3>(2)
    wire T_168181 : UInt<2>[2]
    T_168181[0] := UInt<2>(0)
    T_168181[1] := UInt<2>(1)
    wire T_168182 : UInt<2>[3]
    T_168182[0] := UInt<2>(1)
    T_168182[1] := UInt<2>(2)
    T_168182[2] := UInt<2>(3)
    wire T_168183 : UInt<2>[2]
    T_168183[0] := UInt<2>(2)
    T_168183[1] := UInt<2>(3)
    wire T_168184 : UInt<2>[1]
    T_168184[0] := UInt<2>(3)
    wire T_168185 : UInt<3>[3]
    T_168185[0] := UInt<3>(0)
    T_168185[1] := UInt<3>(1)
    T_168185[2] := UInt<3>(2)
    wire T_168186 : UInt<2>[2]
    T_168186[0] := UInt<2>(0)
    T_168186[1] := UInt<2>(1)
    wire T_168187 : UInt<2>[3]
    T_168187[0] := UInt<2>(1)
    T_168187[1] := UInt<2>(2)
    T_168187[2] := UInt<2>(3)
    wire T_168188 : UInt<2>[2]
    T_168188[0] := UInt<2>(2)
    T_168188[1] := UInt<2>(3)
    wire T_168189 : UInt<2>[1]
    T_168189[0] := UInt<2>(3)
    wire T_168190 : UInt<3>[3]
    T_168190[0] := UInt<3>(0)
    T_168190[1] := UInt<3>(1)
    T_168190[2] := UInt<3>(2)
    wire T_168191 : UInt<2>[2]
    T_168191[0] := UInt<2>(0)
    T_168191[1] := UInt<2>(1)
    wire T_168192 : UInt<2>[3]
    T_168192[0] := UInt<2>(1)
    T_168192[1] := UInt<2>(2)
    T_168192[2] := UInt<2>(3)
    wire T_168193 : UInt<2>[2]
    T_168193[0] := UInt<2>(2)
    T_168193[1] := UInt<2>(3)
    wire T_168194 : UInt<2>[1]
    T_168194[0] := UInt<2>(3)
    wire T_168195 : UInt<3>[3]
    T_168195[0] := UInt<3>(0)
    T_168195[1] := UInt<3>(1)
    T_168195[2] := UInt<3>(2)
    wire T_168196 : UInt<2>[2]
    T_168196[0] := UInt<2>(0)
    T_168196[1] := UInt<2>(1)
    wire T_168197 : UInt<2>[3]
    T_168197[0] := UInt<2>(1)
    T_168197[1] := UInt<2>(2)
    T_168197[2] := UInt<2>(3)
    wire T_168198 : UInt<2>[2]
    T_168198[0] := UInt<2>(2)
    T_168198[1] := UInt<2>(3)
    wire T_168199 : UInt<2>[1]
    T_168199[0] := UInt<2>(3)
    wire T_168200 : UInt<3>[3]
    T_168200[0] := UInt<3>(0)
    T_168200[1] := UInt<3>(1)
    T_168200[2] := UInt<3>(2)
    wire T_168201 : UInt<2>[2]
    T_168201[0] := UInt<2>(0)
    T_168201[1] := UInt<2>(1)
    wire T_168202 : UInt<2>[3]
    T_168202[0] := UInt<2>(1)
    T_168202[1] := UInt<2>(2)
    T_168202[2] := UInt<2>(3)
    wire T_168203 : UInt<2>[2]
    T_168203[0] := UInt<2>(2)
    T_168203[1] := UInt<2>(3)
    wire T_168204 : UInt<2>[1]
    T_168204[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2]
    reg T_168205 : UInt<1>
    onreset T_168205 := UInt<1>(0)
    reg T_168206 : UInt<1>
    onreset T_168206 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_168205, T_168206)
    node T_168207 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_168207)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_168208 = and(enq.ready, enq.valid)
    node T_168209 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_168208, T_168209)
    node T_168210 = and(deq.ready, deq.valid)
    node T_168211 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_168210, T_168211)
    when do_enq : 
      wire T_168212 : UInt<3>[3]
      T_168212[0] := UInt<3>(0)
      T_168212[1] := UInt<3>(1)
      T_168212[2] := UInt<3>(2)
      wire T_168213 : UInt<2>[2]
      T_168213[0] := UInt<2>(0)
      T_168213[1] := UInt<2>(1)
      wire T_168214 : UInt<2>[3]
      T_168214[0] := UInt<2>(1)
      T_168214[1] := UInt<2>(2)
      T_168214[2] := UInt<2>(3)
      wire T_168215 : UInt<2>[2]
      T_168215[0] := UInt<2>(2)
      T_168215[1] := UInt<2>(3)
      wire T_168216 : UInt<2>[1]
      T_168216[0] := UInt<2>(3)
      accessor T_168217 = ram[T_168205]
      T_168217 := enq.bits
      node T_168218 = eq(T_168205, UInt<1>(1))
      node T_168219 = and(UInt<1>(0), T_168218)
      node T_168220 = addw(T_168205, UInt<1>(1))
      wire T_168221 : UInt<1>
      T_168221 := T_168220
      when T_168219 : T_168221 := UInt<1>(0)
      T_168205 := T_168221
    when do_deq : 
      node T_168222 = eq(T_168206, UInt<1>(1))
      node T_168223 = and(UInt<1>(0), T_168222)
      node T_168224 = addw(T_168206, UInt<1>(1))
      wire T_168225 : UInt<1>
      T_168225 := T_168224
      when T_168223 : T_168225 := UInt<1>(0)
      T_168206 := T_168225
    
    node T_168226 = neq(do_enq, do_deq)
    when T_168226 : maybe_full := do_enq
    node T_168227 = eq(empty, UInt<1>(0))
    node T_168228 = and(UInt<1>(0), enq.valid)
    node T_168229 = or(T_168227, T_168228)
    deq.valid := T_168229
    node T_168230 = eq(full, UInt<1>(0))
    node T_168231 = and(UInt<1>(0), deq.ready)
    node T_168232 = or(T_168230, T_168231)
    enq.ready := T_168232
    wire T_168233 : UInt<3>[3]
    T_168233[0] := UInt<3>(0)
    T_168233[1] := UInt<3>(1)
    T_168233[2] := UInt<3>(2)
    wire T_168234 : UInt<2>[2]
    T_168234[0] := UInt<2>(0)
    T_168234[1] := UInt<2>(1)
    wire T_168235 : UInt<2>[3]
    T_168235[0] := UInt<2>(1)
    T_168235[1] := UInt<2>(2)
    T_168235[2] := UInt<2>(3)
    wire T_168236 : UInt<2>[2]
    T_168236[0] := UInt<2>(2)
    T_168236[1] := UInt<2>(3)
    wire T_168237 : UInt<2>[1]
    T_168237[0] := UInt<2>(3)
    accessor T_168238 = ram[T_168206]
    wire T_168239 : UInt<3>[3]
    T_168239[0] := UInt<3>(0)
    T_168239[1] := UInt<3>(1)
    T_168239[2] := UInt<3>(2)
    wire T_168240 : UInt<2>[2]
    T_168240[0] := UInt<2>(0)
    T_168240[1] := UInt<2>(1)
    wire T_168241 : UInt<2>[3]
    T_168241[0] := UInt<2>(1)
    T_168241[1] := UInt<2>(2)
    T_168241[2] := UInt<2>(3)
    wire T_168242 : UInt<2>[2]
    T_168242[0] := UInt<2>(2)
    T_168242[1] := UInt<2>(3)
    wire T_168243 : UInt<2>[1]
    T_168243[0] := UInt<2>(3)
    wire T_168244 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    T_168244 := T_168238
    when maybe_flow : T_168244 := enq.bits
    deq.bits := T_168244
    node ptr_diff = subw(T_168205, T_168206)
    node T_168245 = and(maybe_full, ptr_match)
    node T_168246 = cat(T_168245, ptr_diff)
    count := T_168246
  module Queue_39180 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}
    output count : UInt<2>
    
    wire T_168247 : UInt<3>[3]
    T_168247[0] := UInt<3>(0)
    T_168247[1] := UInt<3>(1)
    T_168247[2] := UInt<3>(2)
    wire T_168248 : UInt<2>[2]
    T_168248[0] := UInt<2>(0)
    T_168248[1] := UInt<2>(1)
    wire T_168249 : UInt<2>[3]
    T_168249[0] := UInt<2>(1)
    T_168249[1] := UInt<2>(2)
    T_168249[2] := UInt<2>(3)
    wire T_168250 : UInt<2>[2]
    T_168250[0] := UInt<2>(2)
    T_168250[1] := UInt<2>(3)
    wire T_168251 : UInt<2>[1]
    T_168251[0] := UInt<2>(3)
    wire T_168252 : UInt<3>[3]
    T_168252[0] := UInt<3>(0)
    T_168252[1] := UInt<3>(1)
    T_168252[2] := UInt<3>(2)
    wire T_168253 : UInt<2>[2]
    T_168253[0] := UInt<2>(0)
    T_168253[1] := UInt<2>(1)
    wire T_168254 : UInt<2>[3]
    T_168254[0] := UInt<2>(1)
    T_168254[1] := UInt<2>(2)
    T_168254[2] := UInt<2>(3)
    wire T_168255 : UInt<2>[2]
    T_168255[0] := UInt<2>(2)
    T_168255[1] := UInt<2>(3)
    wire T_168256 : UInt<2>[1]
    T_168256[0] := UInt<2>(3)
    wire T_168257 : UInt<3>[3]
    T_168257[0] := UInt<3>(0)
    T_168257[1] := UInt<3>(1)
    T_168257[2] := UInt<3>(2)
    wire T_168258 : UInt<2>[2]
    T_168258[0] := UInt<2>(0)
    T_168258[1] := UInt<2>(1)
    wire T_168259 : UInt<2>[3]
    T_168259[0] := UInt<2>(1)
    T_168259[1] := UInt<2>(2)
    T_168259[2] := UInt<2>(3)
    wire T_168260 : UInt<2>[2]
    T_168260[0] := UInt<2>(2)
    T_168260[1] := UInt<2>(3)
    wire T_168261 : UInt<2>[1]
    T_168261[0] := UInt<2>(3)
    wire T_168262 : UInt<3>[3]
    T_168262[0] := UInt<3>(0)
    T_168262[1] := UInt<3>(1)
    T_168262[2] := UInt<3>(2)
    wire T_168263 : UInt<2>[2]
    T_168263[0] := UInt<2>(0)
    T_168263[1] := UInt<2>(1)
    wire T_168264 : UInt<2>[3]
    T_168264[0] := UInt<2>(1)
    T_168264[1] := UInt<2>(2)
    T_168264[2] := UInt<2>(3)
    wire T_168265 : UInt<2>[2]
    T_168265[0] := UInt<2>(2)
    T_168265[1] := UInt<2>(3)
    wire T_168266 : UInt<2>[1]
    T_168266[0] := UInt<2>(3)
    wire T_168267 : UInt<3>[3]
    T_168267[0] := UInt<3>(0)
    T_168267[1] := UInt<3>(1)
    T_168267[2] := UInt<3>(2)
    wire T_168268 : UInt<2>[2]
    T_168268[0] := UInt<2>(0)
    T_168268[1] := UInt<2>(1)
    wire T_168269 : UInt<2>[3]
    T_168269[0] := UInt<2>(1)
    T_168269[1] := UInt<2>(2)
    T_168269[2] := UInt<2>(3)
    wire T_168270 : UInt<2>[2]
    T_168270[0] := UInt<2>(2)
    T_168270[1] := UInt<2>(3)
    wire T_168271 : UInt<2>[1]
    T_168271[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2]
    reg T_168272 : UInt<1>
    onreset T_168272 := UInt<1>(0)
    reg T_168273 : UInt<1>
    onreset T_168273 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_168272, T_168273)
    node T_168274 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_168274)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_168275 = and(enq.ready, enq.valid)
    node T_168276 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_168275, T_168276)
    node T_168277 = and(deq.ready, deq.valid)
    node T_168278 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_168277, T_168278)
    when do_enq : 
      wire T_168279 : UInt<3>[3]
      T_168279[0] := UInt<3>(0)
      T_168279[1] := UInt<3>(1)
      T_168279[2] := UInt<3>(2)
      wire T_168280 : UInt<2>[2]
      T_168280[0] := UInt<2>(0)
      T_168280[1] := UInt<2>(1)
      wire T_168281 : UInt<2>[3]
      T_168281[0] := UInt<2>(1)
      T_168281[1] := UInt<2>(2)
      T_168281[2] := UInt<2>(3)
      wire T_168282 : UInt<2>[2]
      T_168282[0] := UInt<2>(2)
      T_168282[1] := UInt<2>(3)
      wire T_168283 : UInt<2>[1]
      T_168283[0] := UInt<2>(3)
      accessor T_168284 = ram[T_168272]
      T_168284 := enq.bits
      node T_168285 = eq(T_168272, UInt<1>(1))
      node T_168286 = and(UInt<1>(0), T_168285)
      node T_168287 = addw(T_168272, UInt<1>(1))
      wire T_168288 : UInt<1>
      T_168288 := T_168287
      when T_168286 : T_168288 := UInt<1>(0)
      T_168272 := T_168288
    when do_deq : 
      node T_168289 = eq(T_168273, UInt<1>(1))
      node T_168290 = and(UInt<1>(0), T_168289)
      node T_168291 = addw(T_168273, UInt<1>(1))
      wire T_168292 : UInt<1>
      T_168292 := T_168291
      when T_168290 : T_168292 := UInt<1>(0)
      T_168273 := T_168292
    
    node T_168293 = neq(do_enq, do_deq)
    when T_168293 : maybe_full := do_enq
    node T_168294 = eq(empty, UInt<1>(0))
    node T_168295 = and(UInt<1>(0), enq.valid)
    node T_168296 = or(T_168294, T_168295)
    deq.valid := T_168296
    node T_168297 = eq(full, UInt<1>(0))
    node T_168298 = and(UInt<1>(0), deq.ready)
    node T_168299 = or(T_168297, T_168298)
    enq.ready := T_168299
    wire T_168300 : UInt<3>[3]
    T_168300[0] := UInt<3>(0)
    T_168300[1] := UInt<3>(1)
    T_168300[2] := UInt<3>(2)
    wire T_168301 : UInt<2>[2]
    T_168301[0] := UInt<2>(0)
    T_168301[1] := UInt<2>(1)
    wire T_168302 : UInt<2>[3]
    T_168302[0] := UInt<2>(1)
    T_168302[1] := UInt<2>(2)
    T_168302[2] := UInt<2>(3)
    wire T_168303 : UInt<2>[2]
    T_168303[0] := UInt<2>(2)
    T_168303[1] := UInt<2>(3)
    wire T_168304 : UInt<2>[1]
    T_168304[0] := UInt<2>(3)
    accessor T_168305 = ram[T_168273]
    wire T_168306 : UInt<3>[3]
    T_168306[0] := UInt<3>(0)
    T_168306[1] := UInt<3>(1)
    T_168306[2] := UInt<3>(2)
    wire T_168307 : UInt<2>[2]
    T_168307[0] := UInt<2>(0)
    T_168307[1] := UInt<2>(1)
    wire T_168308 : UInt<2>[3]
    T_168308[0] := UInt<2>(1)
    T_168308[1] := UInt<2>(2)
    T_168308[2] := UInt<2>(3)
    wire T_168309 : UInt<2>[2]
    T_168309[0] := UInt<2>(2)
    T_168309[1] := UInt<2>(3)
    wire T_168310 : UInt<2>[1]
    T_168310[0] := UInt<2>(3)
    wire T_168311 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}
    T_168311 := T_168305
    when maybe_flow : T_168311 := enq.bits
    deq.bits := T_168311
    node ptr_diff = subw(T_168272, T_168273)
    node T_168312 = and(maybe_full, ptr_match)
    node T_168313 = cat(T_168312, ptr_diff)
    count := T_168313
  module Queue_39855 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output count : UInt<2>
    
    wire T_168314 : UInt<3>[3]
    T_168314[0] := UInt<3>(0)
    T_168314[1] := UInt<3>(1)
    T_168314[2] := UInt<3>(2)
    wire T_168315 : UInt<2>[2]
    T_168315[0] := UInt<2>(0)
    T_168315[1] := UInt<2>(1)
    wire T_168316 : UInt<2>[3]
    T_168316[0] := UInt<2>(1)
    T_168316[1] := UInt<2>(2)
    T_168316[2] := UInt<2>(3)
    wire T_168317 : UInt<2>[2]
    T_168317[0] := UInt<2>(2)
    T_168317[1] := UInt<2>(3)
    wire T_168318 : UInt<2>[1]
    T_168318[0] := UInt<2>(3)
    wire T_168319 : UInt<3>[3]
    T_168319[0] := UInt<3>(0)
    T_168319[1] := UInt<3>(1)
    T_168319[2] := UInt<3>(2)
    wire T_168320 : UInt<2>[2]
    T_168320[0] := UInt<2>(0)
    T_168320[1] := UInt<2>(1)
    wire T_168321 : UInt<2>[3]
    T_168321[0] := UInt<2>(1)
    T_168321[1] := UInt<2>(2)
    T_168321[2] := UInt<2>(3)
    wire T_168322 : UInt<2>[2]
    T_168322[0] := UInt<2>(2)
    T_168322[1] := UInt<2>(3)
    wire T_168323 : UInt<2>[1]
    T_168323[0] := UInt<2>(3)
    wire T_168324 : UInt<3>[3]
    T_168324[0] := UInt<3>(0)
    T_168324[1] := UInt<3>(1)
    T_168324[2] := UInt<3>(2)
    wire T_168325 : UInt<2>[2]
    T_168325[0] := UInt<2>(0)
    T_168325[1] := UInt<2>(1)
    wire T_168326 : UInt<2>[3]
    T_168326[0] := UInt<2>(1)
    T_168326[1] := UInt<2>(2)
    T_168326[2] := UInt<2>(3)
    wire T_168327 : UInt<2>[2]
    T_168327[0] := UInt<2>(2)
    T_168327[1] := UInt<2>(3)
    wire T_168328 : UInt<2>[1]
    T_168328[0] := UInt<2>(3)
    wire T_168329 : UInt<3>[3]
    T_168329[0] := UInt<3>(0)
    T_168329[1] := UInt<3>(1)
    T_168329[2] := UInt<3>(2)
    wire T_168330 : UInt<2>[2]
    T_168330[0] := UInt<2>(0)
    T_168330[1] := UInt<2>(1)
    wire T_168331 : UInt<2>[3]
    T_168331[0] := UInt<2>(1)
    T_168331[1] := UInt<2>(2)
    T_168331[2] := UInt<2>(3)
    wire T_168332 : UInt<2>[2]
    T_168332[0] := UInt<2>(2)
    T_168332[1] := UInt<2>(3)
    wire T_168333 : UInt<2>[1]
    T_168333[0] := UInt<2>(3)
    wire T_168334 : UInt<3>[3]
    T_168334[0] := UInt<3>(0)
    T_168334[1] := UInt<3>(1)
    T_168334[2] := UInt<3>(2)
    wire T_168335 : UInt<2>[2]
    T_168335[0] := UInt<2>(0)
    T_168335[1] := UInt<2>(1)
    wire T_168336 : UInt<2>[3]
    T_168336[0] := UInt<2>(1)
    T_168336[1] := UInt<2>(2)
    T_168336[2] := UInt<2>(3)
    wire T_168337 : UInt<2>[2]
    T_168337[0] := UInt<2>(2)
    T_168337[1] := UInt<2>(3)
    wire T_168338 : UInt<2>[1]
    T_168338[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2]
    reg T_168339 : UInt<1>
    onreset T_168339 := UInt<1>(0)
    reg T_168340 : UInt<1>
    onreset T_168340 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_168339, T_168340)
    node T_168341 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_168341)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_168342 = and(enq.ready, enq.valid)
    node T_168343 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_168342, T_168343)
    node T_168344 = and(deq.ready, deq.valid)
    node T_168345 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_168344, T_168345)
    when do_enq : 
      wire T_168346 : UInt<3>[3]
      T_168346[0] := UInt<3>(0)
      T_168346[1] := UInt<3>(1)
      T_168346[2] := UInt<3>(2)
      wire T_168347 : UInt<2>[2]
      T_168347[0] := UInt<2>(0)
      T_168347[1] := UInt<2>(1)
      wire T_168348 : UInt<2>[3]
      T_168348[0] := UInt<2>(1)
      T_168348[1] := UInt<2>(2)
      T_168348[2] := UInt<2>(3)
      wire T_168349 : UInt<2>[2]
      T_168349[0] := UInt<2>(2)
      T_168349[1] := UInt<2>(3)
      wire T_168350 : UInt<2>[1]
      T_168350[0] := UInt<2>(3)
      accessor T_168351 = ram[T_168339]
      T_168351 := enq.bits
      node T_168352 = eq(T_168339, UInt<1>(1))
      node T_168353 = and(UInt<1>(0), T_168352)
      node T_168354 = addw(T_168339, UInt<1>(1))
      wire T_168355 : UInt<1>
      T_168355 := T_168354
      when T_168353 : T_168355 := UInt<1>(0)
      T_168339 := T_168355
    when do_deq : 
      node T_168356 = eq(T_168340, UInt<1>(1))
      node T_168357 = and(UInt<1>(0), T_168356)
      node T_168358 = addw(T_168340, UInt<1>(1))
      wire T_168359 : UInt<1>
      T_168359 := T_168358
      when T_168357 : T_168359 := UInt<1>(0)
      T_168340 := T_168359
    
    node T_168360 = neq(do_enq, do_deq)
    when T_168360 : maybe_full := do_enq
    node T_168361 = eq(empty, UInt<1>(0))
    node T_168362 = and(UInt<1>(0), enq.valid)
    node T_168363 = or(T_168361, T_168362)
    deq.valid := T_168363
    node T_168364 = eq(full, UInt<1>(0))
    node T_168365 = and(UInt<1>(0), deq.ready)
    node T_168366 = or(T_168364, T_168365)
    enq.ready := T_168366
    wire T_168367 : UInt<3>[3]
    T_168367[0] := UInt<3>(0)
    T_168367[1] := UInt<3>(1)
    T_168367[2] := UInt<3>(2)
    wire T_168368 : UInt<2>[2]
    T_168368[0] := UInt<2>(0)
    T_168368[1] := UInt<2>(1)
    wire T_168369 : UInt<2>[3]
    T_168369[0] := UInt<2>(1)
    T_168369[1] := UInt<2>(2)
    T_168369[2] := UInt<2>(3)
    wire T_168370 : UInt<2>[2]
    T_168370[0] := UInt<2>(2)
    T_168370[1] := UInt<2>(3)
    wire T_168371 : UInt<2>[1]
    T_168371[0] := UInt<2>(3)
    accessor T_168372 = ram[T_168340]
    wire T_168373 : UInt<3>[3]
    T_168373[0] := UInt<3>(0)
    T_168373[1] := UInt<3>(1)
    T_168373[2] := UInt<3>(2)
    wire T_168374 : UInt<2>[2]
    T_168374[0] := UInt<2>(0)
    T_168374[1] := UInt<2>(1)
    wire T_168375 : UInt<2>[3]
    T_168375[0] := UInt<2>(1)
    T_168375[1] := UInt<2>(2)
    T_168375[2] := UInt<2>(3)
    wire T_168376 : UInt<2>[2]
    T_168376[0] := UInt<2>(2)
    T_168376[1] := UInt<2>(3)
    wire T_168377 : UInt<2>[1]
    T_168377[0] := UInt<2>(3)
    wire T_168378 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    T_168378 := T_168372
    when maybe_flow : T_168378 := enq.bits
    deq.bits := T_168378
    node ptr_diff = subw(T_168339, T_168340)
    node T_168379 = and(maybe_full, ptr_match)
    node T_168380 = cat(T_168379, ptr_diff)
    count := T_168380
  module Queue_40530 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output count : UInt<2>
    
    wire T_168381 : UInt<3>[3]
    T_168381[0] := UInt<3>(0)
    T_168381[1] := UInt<3>(1)
    T_168381[2] := UInt<3>(2)
    wire T_168382 : UInt<2>[2]
    T_168382[0] := UInt<2>(0)
    T_168382[1] := UInt<2>(1)
    wire T_168383 : UInt<2>[3]
    T_168383[0] := UInt<2>(1)
    T_168383[1] := UInt<2>(2)
    T_168383[2] := UInt<2>(3)
    wire T_168384 : UInt<2>[2]
    T_168384[0] := UInt<2>(2)
    T_168384[1] := UInt<2>(3)
    wire T_168385 : UInt<2>[1]
    T_168385[0] := UInt<2>(3)
    wire T_168386 : UInt<3>[3]
    T_168386[0] := UInt<3>(0)
    T_168386[1] := UInt<3>(1)
    T_168386[2] := UInt<3>(2)
    wire T_168387 : UInt<2>[2]
    T_168387[0] := UInt<2>(0)
    T_168387[1] := UInt<2>(1)
    wire T_168388 : UInt<2>[3]
    T_168388[0] := UInt<2>(1)
    T_168388[1] := UInt<2>(2)
    T_168388[2] := UInt<2>(3)
    wire T_168389 : UInt<2>[2]
    T_168389[0] := UInt<2>(2)
    T_168389[1] := UInt<2>(3)
    wire T_168390 : UInt<2>[1]
    T_168390[0] := UInt<2>(3)
    wire T_168391 : UInt<3>[3]
    T_168391[0] := UInt<3>(0)
    T_168391[1] := UInt<3>(1)
    T_168391[2] := UInt<3>(2)
    wire T_168392 : UInt<2>[2]
    T_168392[0] := UInt<2>(0)
    T_168392[1] := UInt<2>(1)
    wire T_168393 : UInt<2>[3]
    T_168393[0] := UInt<2>(1)
    T_168393[1] := UInt<2>(2)
    T_168393[2] := UInt<2>(3)
    wire T_168394 : UInt<2>[2]
    T_168394[0] := UInt<2>(2)
    T_168394[1] := UInt<2>(3)
    wire T_168395 : UInt<2>[1]
    T_168395[0] := UInt<2>(3)
    wire T_168396 : UInt<3>[3]
    T_168396[0] := UInt<3>(0)
    T_168396[1] := UInt<3>(1)
    T_168396[2] := UInt<3>(2)
    wire T_168397 : UInt<2>[2]
    T_168397[0] := UInt<2>(0)
    T_168397[1] := UInt<2>(1)
    wire T_168398 : UInt<2>[3]
    T_168398[0] := UInt<2>(1)
    T_168398[1] := UInt<2>(2)
    T_168398[2] := UInt<2>(3)
    wire T_168399 : UInt<2>[2]
    T_168399[0] := UInt<2>(2)
    T_168399[1] := UInt<2>(3)
    wire T_168400 : UInt<2>[1]
    T_168400[0] := UInt<2>(3)
    wire T_168401 : UInt<3>[3]
    T_168401[0] := UInt<3>(0)
    T_168401[1] := UInt<3>(1)
    T_168401[2] := UInt<3>(2)
    wire T_168402 : UInt<2>[2]
    T_168402[0] := UInt<2>(0)
    T_168402[1] := UInt<2>(1)
    wire T_168403 : UInt<2>[3]
    T_168403[0] := UInt<2>(1)
    T_168403[1] := UInt<2>(2)
    T_168403[2] := UInt<2>(3)
    wire T_168404 : UInt<2>[2]
    T_168404[0] := UInt<2>(2)
    T_168404[1] := UInt<2>(3)
    wire T_168405 : UInt<2>[1]
    T_168405[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}[2]
    reg T_168406 : UInt<1>
    onreset T_168406 := UInt<1>(0)
    reg T_168407 : UInt<1>
    onreset T_168407 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_168406, T_168407)
    node T_168408 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_168408)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_168409 = and(enq.ready, enq.valid)
    node T_168410 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_168409, T_168410)
    node T_168411 = and(deq.ready, deq.valid)
    node T_168412 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_168411, T_168412)
    when do_enq : 
      wire T_168413 : UInt<3>[3]
      T_168413[0] := UInt<3>(0)
      T_168413[1] := UInt<3>(1)
      T_168413[2] := UInt<3>(2)
      wire T_168414 : UInt<2>[2]
      T_168414[0] := UInt<2>(0)
      T_168414[1] := UInt<2>(1)
      wire T_168415 : UInt<2>[3]
      T_168415[0] := UInt<2>(1)
      T_168415[1] := UInt<2>(2)
      T_168415[2] := UInt<2>(3)
      wire T_168416 : UInt<2>[2]
      T_168416[0] := UInt<2>(2)
      T_168416[1] := UInt<2>(3)
      wire T_168417 : UInt<2>[1]
      T_168417[0] := UInt<2>(3)
      accessor T_168418 = ram[T_168406]
      T_168418 := enq.bits
      node T_168419 = eq(T_168406, UInt<1>(1))
      node T_168420 = and(UInt<1>(0), T_168419)
      node T_168421 = addw(T_168406, UInt<1>(1))
      wire T_168422 : UInt<1>
      T_168422 := T_168421
      when T_168420 : T_168422 := UInt<1>(0)
      T_168406 := T_168422
    when do_deq : 
      node T_168423 = eq(T_168407, UInt<1>(1))
      node T_168424 = and(UInt<1>(0), T_168423)
      node T_168425 = addw(T_168407, UInt<1>(1))
      wire T_168426 : UInt<1>
      T_168426 := T_168425
      when T_168424 : T_168426 := UInt<1>(0)
      T_168407 := T_168426
    
    node T_168427 = neq(do_enq, do_deq)
    when T_168427 : maybe_full := do_enq
    node T_168428 = eq(empty, UInt<1>(0))
    node T_168429 = and(UInt<1>(0), enq.valid)
    node T_168430 = or(T_168428, T_168429)
    deq.valid := T_168430
    node T_168431 = eq(full, UInt<1>(0))
    node T_168432 = and(UInt<1>(0), deq.ready)
    node T_168433 = or(T_168431, T_168432)
    enq.ready := T_168433
    wire T_168434 : UInt<3>[3]
    T_168434[0] := UInt<3>(0)
    T_168434[1] := UInt<3>(1)
    T_168434[2] := UInt<3>(2)
    wire T_168435 : UInt<2>[2]
    T_168435[0] := UInt<2>(0)
    T_168435[1] := UInt<2>(1)
    wire T_168436 : UInt<2>[3]
    T_168436[0] := UInt<2>(1)
    T_168436[1] := UInt<2>(2)
    T_168436[2] := UInt<2>(3)
    wire T_168437 : UInt<2>[2]
    T_168437[0] := UInt<2>(2)
    T_168437[1] := UInt<2>(3)
    wire T_168438 : UInt<2>[1]
    T_168438[0] := UInt<2>(3)
    accessor T_168439 = ram[T_168407]
    wire T_168440 : UInt<3>[3]
    T_168440[0] := UInt<3>(0)
    T_168440[1] := UInt<3>(1)
    T_168440[2] := UInt<3>(2)
    wire T_168441 : UInt<2>[2]
    T_168441[0] := UInt<2>(0)
    T_168441[1] := UInt<2>(1)
    wire T_168442 : UInt<2>[3]
    T_168442[0] := UInt<2>(1)
    T_168442[1] := UInt<2>(2)
    T_168442[2] := UInt<2>(3)
    wire T_168443 : UInt<2>[2]
    T_168443[0] := UInt<2>(2)
    T_168443[1] := UInt<2>(3)
    wire T_168444 : UInt<2>[1]
    T_168444[0] := UInt<2>(3)
    wire T_168445 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    T_168445 := T_168439
    when maybe_flow : T_168445 := enq.bits
    deq.bits := T_168445
    node ptr_diff = subw(T_168406, T_168407)
    node T_168446 = and(maybe_full, ptr_match)
    node T_168447 = cat(T_168446, ptr_diff)
    count := T_168447
  module Queue_41160 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output count : UInt<2>
    
    wire T_168448 : UInt<3>[3]
    T_168448[0] := UInt<3>(0)
    T_168448[1] := UInt<3>(1)
    T_168448[2] := UInt<3>(2)
    wire T_168449 : UInt<2>[2]
    T_168449[0] := UInt<2>(0)
    T_168449[1] := UInt<2>(1)
    wire T_168450 : UInt<2>[3]
    T_168450[0] := UInt<2>(1)
    T_168450[1] := UInt<2>(2)
    T_168450[2] := UInt<2>(3)
    wire T_168451 : UInt<2>[2]
    T_168451[0] := UInt<2>(2)
    T_168451[1] := UInt<2>(3)
    wire T_168452 : UInt<2>[1]
    T_168452[0] := UInt<2>(3)
    wire T_168453 : UInt<3>[3]
    T_168453[0] := UInt<3>(0)
    T_168453[1] := UInt<3>(1)
    T_168453[2] := UInt<3>(2)
    wire T_168454 : UInt<2>[2]
    T_168454[0] := UInt<2>(0)
    T_168454[1] := UInt<2>(1)
    wire T_168455 : UInt<2>[3]
    T_168455[0] := UInt<2>(1)
    T_168455[1] := UInt<2>(2)
    T_168455[2] := UInt<2>(3)
    wire T_168456 : UInt<2>[2]
    T_168456[0] := UInt<2>(2)
    T_168456[1] := UInt<2>(3)
    wire T_168457 : UInt<2>[1]
    T_168457[0] := UInt<2>(3)
    wire T_168458 : UInt<3>[3]
    T_168458[0] := UInt<3>(0)
    T_168458[1] := UInt<3>(1)
    T_168458[2] := UInt<3>(2)
    wire T_168459 : UInt<2>[2]
    T_168459[0] := UInt<2>(0)
    T_168459[1] := UInt<2>(1)
    wire T_168460 : UInt<2>[3]
    T_168460[0] := UInt<2>(1)
    T_168460[1] := UInt<2>(2)
    T_168460[2] := UInt<2>(3)
    wire T_168461 : UInt<2>[2]
    T_168461[0] := UInt<2>(2)
    T_168461[1] := UInt<2>(3)
    wire T_168462 : UInt<2>[1]
    T_168462[0] := UInt<2>(3)
    wire T_168463 : UInt<3>[3]
    T_168463[0] := UInt<3>(0)
    T_168463[1] := UInt<3>(1)
    T_168463[2] := UInt<3>(2)
    wire T_168464 : UInt<2>[2]
    T_168464[0] := UInt<2>(0)
    T_168464[1] := UInt<2>(1)
    wire T_168465 : UInt<2>[3]
    T_168465[0] := UInt<2>(1)
    T_168465[1] := UInt<2>(2)
    T_168465[2] := UInt<2>(3)
    wire T_168466 : UInt<2>[2]
    T_168466[0] := UInt<2>(2)
    T_168466[1] := UInt<2>(3)
    wire T_168467 : UInt<2>[1]
    T_168467[0] := UInt<2>(3)
    wire T_168468 : UInt<3>[3]
    T_168468[0] := UInt<3>(0)
    T_168468[1] := UInt<3>(1)
    T_168468[2] := UInt<3>(2)
    wire T_168469 : UInt<2>[2]
    T_168469[0] := UInt<2>(0)
    T_168469[1] := UInt<2>(1)
    wire T_168470 : UInt<2>[3]
    T_168470[0] := UInt<2>(1)
    T_168470[1] := UInt<2>(2)
    T_168470[2] := UInt<2>(3)
    wire T_168471 : UInt<2>[2]
    T_168471[0] := UInt<2>(2)
    T_168471[1] := UInt<2>(3)
    wire T_168472 : UInt<2>[1]
    T_168472[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}[2]
    reg T_168473 : UInt<1>
    onreset T_168473 := UInt<1>(0)
    reg T_168474 : UInt<1>
    onreset T_168474 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_168473, T_168474)
    node T_168475 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_168475)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_168476 = and(enq.ready, enq.valid)
    node T_168477 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_168476, T_168477)
    node T_168478 = and(deq.ready, deq.valid)
    node T_168479 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_168478, T_168479)
    when do_enq : 
      wire T_168480 : UInt<3>[3]
      T_168480[0] := UInt<3>(0)
      T_168480[1] := UInt<3>(1)
      T_168480[2] := UInt<3>(2)
      wire T_168481 : UInt<2>[2]
      T_168481[0] := UInt<2>(0)
      T_168481[1] := UInt<2>(1)
      wire T_168482 : UInt<2>[3]
      T_168482[0] := UInt<2>(1)
      T_168482[1] := UInt<2>(2)
      T_168482[2] := UInt<2>(3)
      wire T_168483 : UInt<2>[2]
      T_168483[0] := UInt<2>(2)
      T_168483[1] := UInt<2>(3)
      wire T_168484 : UInt<2>[1]
      T_168484[0] := UInt<2>(3)
      accessor T_168485 = ram[T_168473]
      T_168485 := enq.bits
      node T_168486 = eq(T_168473, UInt<1>(1))
      node T_168487 = and(UInt<1>(0), T_168486)
      node T_168488 = addw(T_168473, UInt<1>(1))
      wire T_168489 : UInt<1>
      T_168489 := T_168488
      when T_168487 : T_168489 := UInt<1>(0)
      T_168473 := T_168489
    when do_deq : 
      node T_168490 = eq(T_168474, UInt<1>(1))
      node T_168491 = and(UInt<1>(0), T_168490)
      node T_168492 = addw(T_168474, UInt<1>(1))
      wire T_168493 : UInt<1>
      T_168493 := T_168492
      when T_168491 : T_168493 := UInt<1>(0)
      T_168474 := T_168493
    
    node T_168494 = neq(do_enq, do_deq)
    when T_168494 : maybe_full := do_enq
    node T_168495 = eq(empty, UInt<1>(0))
    node T_168496 = and(UInt<1>(0), enq.valid)
    node T_168497 = or(T_168495, T_168496)
    deq.valid := T_168497
    node T_168498 = eq(full, UInt<1>(0))
    node T_168499 = and(UInt<1>(0), deq.ready)
    node T_168500 = or(T_168498, T_168499)
    enq.ready := T_168500
    wire T_168501 : UInt<3>[3]
    T_168501[0] := UInt<3>(0)
    T_168501[1] := UInt<3>(1)
    T_168501[2] := UInt<3>(2)
    wire T_168502 : UInt<2>[2]
    T_168502[0] := UInt<2>(0)
    T_168502[1] := UInt<2>(1)
    wire T_168503 : UInt<2>[3]
    T_168503[0] := UInt<2>(1)
    T_168503[1] := UInt<2>(2)
    T_168503[2] := UInt<2>(3)
    wire T_168504 : UInt<2>[2]
    T_168504[0] := UInt<2>(2)
    T_168504[1] := UInt<2>(3)
    wire T_168505 : UInt<2>[1]
    T_168505[0] := UInt<2>(3)
    accessor T_168506 = ram[T_168474]
    wire T_168507 : UInt<3>[3]
    T_168507[0] := UInt<3>(0)
    T_168507[1] := UInt<3>(1)
    T_168507[2] := UInt<3>(2)
    wire T_168508 : UInt<2>[2]
    T_168508[0] := UInt<2>(0)
    T_168508[1] := UInt<2>(1)
    wire T_168509 : UInt<2>[3]
    T_168509[0] := UInt<2>(1)
    T_168509[1] := UInt<2>(2)
    T_168509[2] := UInt<2>(3)
    wire T_168510 : UInt<2>[2]
    T_168510[0] := UInt<2>(2)
    T_168510[1] := UInt<2>(3)
    wire T_168511 : UInt<2>[1]
    T_168511[0] := UInt<2>(3)
    wire T_168512 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}
    T_168512 := T_168506
    when maybe_flow : T_168512 := enq.bits
    deq.bits := T_168512
    node ptr_diff = subw(T_168473, T_168474)
    node T_168513 = and(maybe_full, ptr_match)
    node T_168514 = cat(T_168513, ptr_diff)
    count := T_168514
  module TileLinkEnqueuer_41161 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_168515 : UInt<3>[3]
    T_168515[0] := UInt<3>(0)
    T_168515[1] := UInt<3>(1)
    T_168515[2] := UInt<3>(2)
    wire T_168516 : UInt<2>[2]
    T_168516[0] := UInt<2>(0)
    T_168516[1] := UInt<2>(1)
    wire T_168517 : UInt<2>[3]
    T_168517[0] := UInt<2>(1)
    T_168517[1] := UInt<2>(2)
    T_168517[2] := UInt<2>(3)
    wire T_168518 : UInt<2>[2]
    T_168518[0] := UInt<2>(2)
    T_168518[1] := UInt<2>(3)
    wire T_168519 : UInt<2>[1]
    T_168519[0] := UInt<2>(3)
    wire T_168520 : UInt<3>[3]
    T_168520[0] := UInt<3>(0)
    T_168520[1] := UInt<3>(1)
    T_168520[2] := UInt<3>(2)
    wire T_168521 : UInt<2>[2]
    T_168521[0] := UInt<2>(0)
    T_168521[1] := UInt<2>(1)
    wire T_168522 : UInt<2>[3]
    T_168522[0] := UInt<2>(1)
    T_168522[1] := UInt<2>(2)
    T_168522[2] := UInt<2>(3)
    wire T_168523 : UInt<2>[2]
    T_168523[0] := UInt<2>(2)
    T_168523[1] := UInt<2>(3)
    wire T_168524 : UInt<2>[1]
    T_168524[0] := UInt<2>(3)
    wire T_168525 : UInt<3>[3]
    T_168525[0] := UInt<3>(0)
    T_168525[1] := UInt<3>(1)
    T_168525[2] := UInt<3>(2)
    wire T_168526 : UInt<2>[2]
    T_168526[0] := UInt<2>(0)
    T_168526[1] := UInt<2>(1)
    wire T_168527 : UInt<2>[3]
    T_168527[0] := UInt<2>(1)
    T_168527[1] := UInt<2>(2)
    T_168527[2] := UInt<2>(3)
    wire T_168528 : UInt<2>[2]
    T_168528[0] := UInt<2>(2)
    T_168528[1] := UInt<2>(3)
    wire T_168529 : UInt<2>[1]
    T_168529[0] := UInt<2>(3)
    wire T_168530 : UInt<3>[3]
    T_168530[0] := UInt<3>(0)
    T_168530[1] := UInt<3>(1)
    T_168530[2] := UInt<3>(2)
    wire T_168531 : UInt<2>[2]
    T_168531[0] := UInt<2>(0)
    T_168531[1] := UInt<2>(1)
    wire T_168532 : UInt<2>[3]
    T_168532[0] := UInt<2>(1)
    T_168532[1] := UInt<2>(2)
    T_168532[2] := UInt<2>(3)
    wire T_168533 : UInt<2>[2]
    T_168533[0] := UInt<2>(2)
    T_168533[1] := UInt<2>(3)
    wire T_168534 : UInt<2>[1]
    T_168534[0] := UInt<2>(3)
    wire T_168535 : UInt<3>[3]
    T_168535[0] := UInt<3>(0)
    T_168535[1] := UInt<3>(1)
    T_168535[2] := UInt<3>(2)
    wire T_168536 : UInt<2>[2]
    T_168536[0] := UInt<2>(0)
    T_168536[1] := UInt<2>(1)
    wire T_168537 : UInt<2>[3]
    T_168537[0] := UInt<2>(1)
    T_168537[1] := UInt<2>(2)
    T_168537[2] := UInt<2>(3)
    wire T_168538 : UInt<2>[2]
    T_168538[0] := UInt<2>(2)
    T_168538[1] := UInt<2>(3)
    wire T_168539 : UInt<2>[1]
    T_168539[0] := UInt<2>(3)
    wire T_168540 : UInt<3>[3]
    T_168540[0] := UInt<3>(0)
    T_168540[1] := UInt<3>(1)
    T_168540[2] := UInt<3>(2)
    wire T_168541 : UInt<2>[2]
    T_168541[0] := UInt<2>(0)
    T_168541[1] := UInt<2>(1)
    wire T_168542 : UInt<2>[3]
    T_168542[0] := UInt<2>(1)
    T_168542[1] := UInt<2>(2)
    T_168542[2] := UInt<2>(3)
    wire T_168543 : UInt<2>[2]
    T_168543[0] := UInt<2>(2)
    T_168543[1] := UInt<2>(3)
    wire T_168544 : UInt<2>[1]
    T_168544[0] := UInt<2>(3)
    wire T_168545 : UInt<3>[3]
    T_168545[0] := UInt<3>(0)
    T_168545[1] := UInt<3>(1)
    T_168545[2] := UInt<3>(2)
    wire T_168546 : UInt<2>[2]
    T_168546[0] := UInt<2>(0)
    T_168546[1] := UInt<2>(1)
    wire T_168547 : UInt<2>[3]
    T_168547[0] := UInt<2>(1)
    T_168547[1] := UInt<2>(2)
    T_168547[2] := UInt<2>(3)
    wire T_168548 : UInt<2>[2]
    T_168548[0] := UInt<2>(2)
    T_168548[1] := UInt<2>(3)
    wire T_168549 : UInt<2>[1]
    T_168549[0] := UInt<2>(3)
    wire T_168550 : UInt<3>[3]
    T_168550[0] := UInt<3>(0)
    T_168550[1] := UInt<3>(1)
    T_168550[2] := UInt<3>(2)
    wire T_168551 : UInt<2>[2]
    T_168551[0] := UInt<2>(0)
    T_168551[1] := UInt<2>(1)
    wire T_168552 : UInt<2>[3]
    T_168552[0] := UInt<2>(1)
    T_168552[1] := UInt<2>(2)
    T_168552[2] := UInt<2>(3)
    wire T_168553 : UInt<2>[2]
    T_168553[0] := UInt<2>(2)
    T_168553[1] := UInt<2>(3)
    wire T_168554 : UInt<2>[1]
    T_168554[0] := UInt<2>(3)
    wire T_168555 : UInt<3>[3]
    T_168555[0] := UInt<3>(0)
    T_168555[1] := UInt<3>(1)
    T_168555[2] := UInt<3>(2)
    wire T_168556 : UInt<2>[2]
    T_168556[0] := UInt<2>(0)
    T_168556[1] := UInt<2>(1)
    wire T_168557 : UInt<2>[3]
    T_168557[0] := UInt<2>(1)
    T_168557[1] := UInt<2>(2)
    T_168557[2] := UInt<2>(3)
    wire T_168558 : UInt<2>[2]
    T_168558[0] := UInt<2>(2)
    T_168558[1] := UInt<2>(3)
    wire T_168559 : UInt<2>[1]
    T_168559[0] := UInt<2>(3)
    wire T_168560 : UInt<3>[3]
    T_168560[0] := UInt<3>(0)
    T_168560[1] := UInt<3>(1)
    T_168560[2] := UInt<3>(2)
    wire T_168561 : UInt<2>[2]
    T_168561[0] := UInt<2>(0)
    T_168561[1] := UInt<2>(1)
    wire T_168562 : UInt<2>[3]
    T_168562[0] := UInt<2>(1)
    T_168562[1] := UInt<2>(2)
    T_168562[2] := UInt<2>(3)
    wire T_168563 : UInt<2>[2]
    T_168563[0] := UInt<2>(2)
    T_168563[1] := UInt<2>(3)
    wire T_168564 : UInt<2>[1]
    T_168564[0] := UInt<2>(3)
    wire T_168565 : UInt<3>[3]
    T_168565[0] := UInt<3>(0)
    T_168565[1] := UInt<3>(1)
    T_168565[2] := UInt<3>(2)
    wire T_168566 : UInt<2>[2]
    T_168566[0] := UInt<2>(0)
    T_168566[1] := UInt<2>(1)
    wire T_168567 : UInt<2>[3]
    T_168567[0] := UInt<2>(1)
    T_168567[1] := UInt<2>(2)
    T_168567[2] := UInt<2>(3)
    wire T_168568 : UInt<2>[2]
    T_168568[0] := UInt<2>(2)
    T_168568[1] := UInt<2>(3)
    wire T_168569 : UInt<2>[1]
    T_168569[0] := UInt<2>(3)
    wire T_168570 : UInt<3>[3]
    T_168570[0] := UInt<3>(0)
    T_168570[1] := UInt<3>(1)
    T_168570[2] := UInt<3>(2)
    wire T_168571 : UInt<2>[2]
    T_168571[0] := UInt<2>(0)
    T_168571[1] := UInt<2>(1)
    wire T_168572 : UInt<2>[3]
    T_168572[0] := UInt<2>(1)
    T_168572[1] := UInt<2>(2)
    T_168572[2] := UInt<2>(3)
    wire T_168573 : UInt<2>[2]
    T_168573[0] := UInt<2>(2)
    T_168573[1] := UInt<2>(3)
    wire T_168574 : UInt<2>[1]
    T_168574[0] := UInt<2>(3)
    wire T_168575 : UInt<3>[3]
    T_168575[0] := UInt<3>(0)
    T_168575[1] := UInt<3>(1)
    T_168575[2] := UInt<3>(2)
    wire T_168576 : UInt<2>[2]
    T_168576[0] := UInt<2>(0)
    T_168576[1] := UInt<2>(1)
    wire T_168577 : UInt<2>[3]
    T_168577[0] := UInt<2>(1)
    T_168577[1] := UInt<2>(2)
    T_168577[2] := UInt<2>(3)
    wire T_168578 : UInt<2>[2]
    T_168578[0] := UInt<2>(2)
    T_168578[1] := UInt<2>(3)
    wire T_168579 : UInt<2>[1]
    T_168579[0] := UInt<2>(3)
    wire T_168580 : UInt<3>[3]
    T_168580[0] := UInt<3>(0)
    T_168580[1] := UInt<3>(1)
    T_168580[2] := UInt<3>(2)
    wire T_168581 : UInt<2>[2]
    T_168581[0] := UInt<2>(0)
    T_168581[1] := UInt<2>(1)
    wire T_168582 : UInt<2>[3]
    T_168582[0] := UInt<2>(1)
    T_168582[1] := UInt<2>(2)
    T_168582[2] := UInt<2>(3)
    wire T_168583 : UInt<2>[2]
    T_168583[0] := UInt<2>(2)
    T_168583[1] := UInt<2>(3)
    wire T_168584 : UInt<2>[1]
    T_168584[0] := UInt<2>(3)
    wire T_168585 : UInt<3>[3]
    T_168585[0] := UInt<3>(0)
    T_168585[1] := UInt<3>(1)
    T_168585[2] := UInt<3>(2)
    wire T_168586 : UInt<2>[2]
    T_168586[0] := UInt<2>(0)
    T_168586[1] := UInt<2>(1)
    wire T_168587 : UInt<2>[3]
    T_168587[0] := UInt<2>(1)
    T_168587[1] := UInt<2>(2)
    T_168587[2] := UInt<2>(3)
    wire T_168588 : UInt<2>[2]
    T_168588[0] := UInt<2>(2)
    T_168588[1] := UInt<2>(3)
    wire T_168589 : UInt<2>[1]
    T_168589[0] := UInt<2>(3)
    wire T_168590 : UInt<3>[3]
    T_168590[0] := UInt<3>(0)
    T_168590[1] := UInt<3>(1)
    T_168590[2] := UInt<3>(2)
    wire T_168591 : UInt<2>[2]
    T_168591[0] := UInt<2>(0)
    T_168591[1] := UInt<2>(1)
    wire T_168592 : UInt<2>[3]
    T_168592[0] := UInt<2>(1)
    T_168592[1] := UInt<2>(2)
    T_168592[2] := UInt<2>(3)
    wire T_168593 : UInt<2>[2]
    T_168593[0] := UInt<2>(2)
    T_168593[1] := UInt<2>(3)
    wire T_168594 : UInt<2>[1]
    T_168594[0] := UInt<2>(3)
    wire T_168595 : UInt<3>[3]
    T_168595[0] := UInt<3>(0)
    T_168595[1] := UInt<3>(1)
    T_168595[2] := UInt<3>(2)
    wire T_168596 : UInt<2>[2]
    T_168596[0] := UInt<2>(0)
    T_168596[1] := UInt<2>(1)
    wire T_168597 : UInt<2>[3]
    T_168597[0] := UInt<2>(1)
    T_168597[1] := UInt<2>(2)
    T_168597[2] := UInt<2>(3)
    wire T_168598 : UInt<2>[2]
    T_168598[0] := UInt<2>(2)
    T_168598[1] := UInt<2>(3)
    wire T_168599 : UInt<2>[1]
    T_168599[0] := UInt<2>(3)
    wire T_168600 : UInt<3>[3]
    T_168600[0] := UInt<3>(0)
    T_168600[1] := UInt<3>(1)
    T_168600[2] := UInt<3>(2)
    wire T_168601 : UInt<2>[2]
    T_168601[0] := UInt<2>(0)
    T_168601[1] := UInt<2>(1)
    wire T_168602 : UInt<2>[3]
    T_168602[0] := UInt<2>(1)
    T_168602[1] := UInt<2>(2)
    T_168602[2] := UInt<2>(3)
    wire T_168603 : UInt<2>[2]
    T_168603[0] := UInt<2>(2)
    T_168603[1] := UInt<2>(3)
    wire T_168604 : UInt<2>[1]
    T_168604[0] := UInt<2>(3)
    wire T_168605 : UInt<3>[3]
    T_168605[0] := UInt<3>(0)
    T_168605[1] := UInt<3>(1)
    T_168605[2] := UInt<3>(2)
    wire T_168606 : UInt<2>[2]
    T_168606[0] := UInt<2>(0)
    T_168606[1] := UInt<2>(1)
    wire T_168607 : UInt<2>[3]
    T_168607[0] := UInt<2>(1)
    T_168607[1] := UInt<2>(2)
    T_168607[2] := UInt<2>(3)
    wire T_168608 : UInt<2>[2]
    T_168608[0] := UInt<2>(2)
    T_168608[1] := UInt<2>(3)
    wire T_168609 : UInt<2>[1]
    T_168609[0] := UInt<2>(3)
    wire T_168610 : UInt<3>[3]
    T_168610[0] := UInt<3>(0)
    T_168610[1] := UInt<3>(1)
    T_168610[2] := UInt<3>(2)
    wire T_168611 : UInt<2>[2]
    T_168611[0] := UInt<2>(0)
    T_168611[1] := UInt<2>(1)
    wire T_168612 : UInt<2>[3]
    T_168612[0] := UInt<2>(1)
    T_168612[1] := UInt<2>(2)
    T_168612[2] := UInt<2>(3)
    wire T_168613 : UInt<2>[2]
    T_168613[0] := UInt<2>(2)
    T_168613[1] := UInt<2>(3)
    wire T_168614 : UInt<2>[1]
    T_168614[0] := UInt<2>(3)
    wire T_168615 : UInt<3>[3]
    T_168615[0] := UInt<3>(0)
    T_168615[1] := UInt<3>(1)
    T_168615[2] := UInt<3>(2)
    wire T_168616 : UInt<2>[2]
    T_168616[0] := UInt<2>(0)
    T_168616[1] := UInt<2>(1)
    wire T_168617 : UInt<2>[3]
    T_168617[0] := UInt<2>(1)
    T_168617[1] := UInt<2>(2)
    T_168617[2] := UInt<2>(3)
    wire T_168618 : UInt<2>[2]
    T_168618[0] := UInt<2>(2)
    T_168618[1] := UInt<2>(3)
    wire T_168619 : UInt<2>[1]
    T_168619[0] := UInt<2>(3)
    wire T_168620 : UInt<3>[3]
    T_168620[0] := UInt<3>(0)
    T_168620[1] := UInt<3>(1)
    T_168620[2] := UInt<3>(2)
    wire T_168621 : UInt<2>[2]
    T_168621[0] := UInt<2>(0)
    T_168621[1] := UInt<2>(1)
    wire T_168622 : UInt<2>[3]
    T_168622[0] := UInt<2>(1)
    T_168622[1] := UInt<2>(2)
    T_168622[2] := UInt<2>(3)
    wire T_168623 : UInt<2>[2]
    T_168623[0] := UInt<2>(2)
    T_168623[1] := UInt<2>(3)
    wire T_168624 : UInt<2>[1]
    T_168624[0] := UInt<2>(3)
    wire T_168625 : UInt<3>[3]
    T_168625[0] := UInt<3>(0)
    T_168625[1] := UInt<3>(1)
    T_168625[2] := UInt<3>(2)
    wire T_168626 : UInt<2>[2]
    T_168626[0] := UInt<2>(0)
    T_168626[1] := UInt<2>(1)
    wire T_168627 : UInt<2>[3]
    T_168627[0] := UInt<2>(1)
    T_168627[1] := UInt<2>(2)
    T_168627[2] := UInt<2>(3)
    wire T_168628 : UInt<2>[2]
    T_168628[0] := UInt<2>(2)
    T_168628[1] := UInt<2>(3)
    wire T_168629 : UInt<2>[1]
    T_168629[0] := UInt<2>(3)
    wire T_168630 : UInt<3>[3]
    T_168630[0] := UInt<3>(0)
    T_168630[1] := UInt<3>(1)
    T_168630[2] := UInt<3>(2)
    wire T_168631 : UInt<2>[2]
    T_168631[0] := UInt<2>(0)
    T_168631[1] := UInt<2>(1)
    wire T_168632 : UInt<2>[3]
    T_168632[0] := UInt<2>(1)
    T_168632[1] := UInt<2>(2)
    T_168632[2] := UInt<2>(3)
    wire T_168633 : UInt<2>[2]
    T_168633[0] := UInt<2>(2)
    T_168633[1] := UInt<2>(3)
    wire T_168634 : UInt<2>[1]
    T_168634[0] := UInt<2>(3)
    wire T_168635 : UInt<3>[3]
    T_168635[0] := UInt<3>(0)
    T_168635[1] := UInt<3>(1)
    T_168635[2] := UInt<3>(2)
    wire T_168636 : UInt<2>[2]
    T_168636[0] := UInt<2>(0)
    T_168636[1] := UInt<2>(1)
    wire T_168637 : UInt<2>[3]
    T_168637[0] := UInt<2>(1)
    T_168637[1] := UInt<2>(2)
    T_168637[2] := UInt<2>(3)
    wire T_168638 : UInt<2>[2]
    T_168638[0] := UInt<2>(2)
    T_168638[1] := UInt<2>(3)
    wire T_168639 : UInt<2>[1]
    T_168639[0] := UInt<2>(3)
    wire T_168640 : UInt<3>[3]
    T_168640[0] := UInt<3>(0)
    T_168640[1] := UInt<3>(1)
    T_168640[2] := UInt<3>(2)
    wire T_168641 : UInt<2>[2]
    T_168641[0] := UInt<2>(0)
    T_168641[1] := UInt<2>(1)
    wire T_168642 : UInt<2>[3]
    T_168642[0] := UInt<2>(1)
    T_168642[1] := UInt<2>(2)
    T_168642[2] := UInt<2>(3)
    wire T_168643 : UInt<2>[2]
    T_168643[0] := UInt<2>(2)
    T_168643[1] := UInt<2>(3)
    wire T_168644 : UInt<2>[1]
    T_168644[0] := UInt<2>(3)
    wire T_168645 : UInt<3>[3]
    T_168645[0] := UInt<3>(0)
    T_168645[1] := UInt<3>(1)
    T_168645[2] := UInt<3>(2)
    wire T_168646 : UInt<2>[2]
    T_168646[0] := UInt<2>(0)
    T_168646[1] := UInt<2>(1)
    wire T_168647 : UInt<2>[3]
    T_168647[0] := UInt<2>(1)
    T_168647[1] := UInt<2>(2)
    T_168647[2] := UInt<2>(3)
    wire T_168648 : UInt<2>[2]
    T_168648[0] := UInt<2>(2)
    T_168648[1] := UInt<2>(3)
    wire T_168649 : UInt<2>[1]
    T_168649[0] := UInt<2>(3)
    wire T_168650 : UInt<3>[3]
    T_168650[0] := UInt<3>(0)
    T_168650[1] := UInt<3>(1)
    T_168650[2] := UInt<3>(2)
    wire T_168651 : UInt<2>[2]
    T_168651[0] := UInt<2>(0)
    T_168651[1] := UInt<2>(1)
    wire T_168652 : UInt<2>[3]
    T_168652[0] := UInt<2>(1)
    T_168652[1] := UInt<2>(2)
    T_168652[2] := UInt<2>(3)
    wire T_168653 : UInt<2>[2]
    T_168653[0] := UInt<2>(2)
    T_168653[1] := UInt<2>(3)
    wire T_168654 : UInt<2>[1]
    T_168654[0] := UInt<2>(3)
    wire T_168655 : UInt<3>[3]
    T_168655[0] := UInt<3>(0)
    T_168655[1] := UInt<3>(1)
    T_168655[2] := UInt<3>(2)
    wire T_168656 : UInt<2>[2]
    T_168656[0] := UInt<2>(0)
    T_168656[1] := UInt<2>(1)
    wire T_168657 : UInt<2>[3]
    T_168657[0] := UInt<2>(1)
    T_168657[1] := UInt<2>(2)
    T_168657[2] := UInt<2>(3)
    wire T_168658 : UInt<2>[2]
    T_168658[0] := UInt<2>(2)
    T_168658[1] := UInt<2>(3)
    wire T_168659 : UInt<2>[1]
    T_168659[0] := UInt<2>(3)
    wire T_168660 : UInt<3>[3]
    T_168660[0] := UInt<3>(0)
    T_168660[1] := UInt<3>(1)
    T_168660[2] := UInt<3>(2)
    wire T_168661 : UInt<2>[2]
    T_168661[0] := UInt<2>(0)
    T_168661[1] := UInt<2>(1)
    wire T_168662 : UInt<2>[3]
    T_168662[0] := UInt<2>(1)
    T_168662[1] := UInt<2>(2)
    T_168662[2] := UInt<2>(3)
    wire T_168663 : UInt<2>[2]
    T_168663[0] := UInt<2>(2)
    T_168663[1] := UInt<2>(3)
    wire T_168664 : UInt<2>[1]
    T_168664[0] := UInt<2>(3)
    wire T_168665 : UInt<3>[3]
    T_168665[0] := UInt<3>(0)
    T_168665[1] := UInt<3>(1)
    T_168665[2] := UInt<3>(2)
    wire T_168666 : UInt<2>[2]
    T_168666[0] := UInt<2>(0)
    T_168666[1] := UInt<2>(1)
    wire T_168667 : UInt<2>[3]
    T_168667[0] := UInt<2>(1)
    T_168667[1] := UInt<2>(2)
    T_168667[2] := UInt<2>(3)
    wire T_168668 : UInt<2>[2]
    T_168668[0] := UInt<2>(2)
    T_168668[1] := UInt<2>(3)
    wire T_168669 : UInt<2>[1]
    T_168669[0] := UInt<2>(3)
    wire T_168670 : UInt<3>[3]
    T_168670[0] := UInt<3>(0)
    T_168670[1] := UInt<3>(1)
    T_168670[2] := UInt<3>(2)
    wire T_168671 : UInt<2>[2]
    T_168671[0] := UInt<2>(0)
    T_168671[1] := UInt<2>(1)
    wire T_168672 : UInt<2>[3]
    T_168672[0] := UInt<2>(1)
    T_168672[1] := UInt<2>(2)
    T_168672[2] := UInt<2>(3)
    wire T_168673 : UInt<2>[2]
    T_168673[0] := UInt<2>(2)
    T_168673[1] := UInt<2>(3)
    wire T_168674 : UInt<2>[1]
    T_168674[0] := UInt<2>(3)
    wire T_168675 : UInt<3>[3]
    T_168675[0] := UInt<3>(0)
    T_168675[1] := UInt<3>(1)
    T_168675[2] := UInt<3>(2)
    wire T_168676 : UInt<2>[2]
    T_168676[0] := UInt<2>(0)
    T_168676[1] := UInt<2>(1)
    wire T_168677 : UInt<2>[3]
    T_168677[0] := UInt<2>(1)
    T_168677[1] := UInt<2>(2)
    T_168677[2] := UInt<2>(3)
    wire T_168678 : UInt<2>[2]
    T_168678[0] := UInt<2>(2)
    T_168678[1] := UInt<2>(3)
    wire T_168679 : UInt<2>[1]
    T_168679[0] := UInt<2>(3)
    inst T_168680 of Queue_38541
    T_168680.enq.valid := client.acquire.valid
    T_168680.enq.bits := client.acquire.bits
    client.acquire.ready := T_168680.enq.ready
    manager.acquire <> T_168680.deq
    wire T_168681 : UInt<3>[3]
    T_168681[0] := UInt<3>(0)
    T_168681[1] := UInt<3>(1)
    T_168681[2] := UInt<3>(2)
    wire T_168682 : UInt<2>[2]
    T_168682[0] := UInt<2>(0)
    T_168682[1] := UInt<2>(1)
    wire T_168683 : UInt<2>[3]
    T_168683[0] := UInt<2>(1)
    T_168683[1] := UInt<2>(2)
    T_168683[2] := UInt<2>(3)
    wire T_168684 : UInt<2>[2]
    T_168684[0] := UInt<2>(2)
    T_168684[1] := UInt<2>(3)
    wire T_168685 : UInt<2>[1]
    T_168685[0] := UInt<2>(3)
    inst T_168686 of Queue_39180
    T_168686.enq.valid := manager.probe.valid
    T_168686.enq.bits := manager.probe.bits
    manager.probe.ready := T_168686.enq.ready
    client.probe <> T_168686.deq
    wire T_168687 : UInt<3>[3]
    T_168687[0] := UInt<3>(0)
    T_168687[1] := UInt<3>(1)
    T_168687[2] := UInt<3>(2)
    wire T_168688 : UInt<2>[2]
    T_168688[0] := UInt<2>(0)
    T_168688[1] := UInt<2>(1)
    wire T_168689 : UInt<2>[3]
    T_168689[0] := UInt<2>(1)
    T_168689[1] := UInt<2>(2)
    T_168689[2] := UInt<2>(3)
    wire T_168690 : UInt<2>[2]
    T_168690[0] := UInt<2>(2)
    T_168690[1] := UInt<2>(3)
    wire T_168691 : UInt<2>[1]
    T_168691[0] := UInt<2>(3)
    inst T_168692 of Queue_39855
    T_168692.enq.valid := client.release.valid
    T_168692.enq.bits := client.release.bits
    client.release.ready := T_168692.enq.ready
    manager.release <> T_168692.deq
    wire T_168693 : UInt<3>[3]
    T_168693[0] := UInt<3>(0)
    T_168693[1] := UInt<3>(1)
    T_168693[2] := UInt<3>(2)
    wire T_168694 : UInt<2>[2]
    T_168694[0] := UInt<2>(0)
    T_168694[1] := UInt<2>(1)
    wire T_168695 : UInt<2>[3]
    T_168695[0] := UInt<2>(1)
    T_168695[1] := UInt<2>(2)
    T_168695[2] := UInt<2>(3)
    wire T_168696 : UInt<2>[2]
    T_168696[0] := UInt<2>(2)
    T_168696[1] := UInt<2>(3)
    wire T_168697 : UInt<2>[1]
    T_168697[0] := UInt<2>(3)
    inst T_168698 of Queue_40530
    T_168698.enq.valid := manager.grant.valid
    T_168698.enq.bits := manager.grant.bits
    manager.grant.ready := T_168698.enq.ready
    client.grant <> T_168698.deq
    wire T_168699 : UInt<3>[3]
    T_168699[0] := UInt<3>(0)
    T_168699[1] := UInt<3>(1)
    T_168699[2] := UInt<3>(2)
    wire T_168700 : UInt<2>[2]
    T_168700[0] := UInt<2>(0)
    T_168700[1] := UInt<2>(1)
    wire T_168701 : UInt<2>[3]
    T_168701[0] := UInt<2>(1)
    T_168701[1] := UInt<2>(2)
    T_168701[2] := UInt<2>(3)
    wire T_168702 : UInt<2>[2]
    T_168702[0] := UInt<2>(2)
    T_168702[1] := UInt<2>(3)
    wire T_168703 : UInt<2>[1]
    T_168703[0] := UInt<2>(3)
    inst T_168704 of Queue_41160
    T_168704.enq.valid := client.finish.valid
    T_168704.enq.bits := client.finish.bits
    client.finish.ready := T_168704.enq.ready
    manager.finish <> T_168704.deq
  module ManagerTileLinkNetworkPort : 
    input manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_168705 : UInt<3>[3]
    T_168705[0] := UInt<3>(0)
    T_168705[1] := UInt<3>(1)
    T_168705[2] := UInt<3>(2)
    wire T_168706 : UInt<2>[2]
    T_168706[0] := UInt<2>(0)
    T_168706[1] := UInt<2>(1)
    wire T_168707 : UInt<2>[3]
    T_168707[0] := UInt<2>(1)
    T_168707[1] := UInt<2>(2)
    T_168707[2] := UInt<2>(3)
    wire T_168708 : UInt<2>[2]
    T_168708[0] := UInt<2>(2)
    T_168708[1] := UInt<2>(3)
    wire T_168709 : UInt<2>[1]
    T_168709[0] := UInt<2>(3)
    wire T_168710 : UInt<3>[3]
    T_168710[0] := UInt<3>(0)
    T_168710[1] := UInt<3>(1)
    T_168710[2] := UInt<3>(2)
    wire T_168711 : UInt<2>[2]
    T_168711[0] := UInt<2>(0)
    T_168711[1] := UInt<2>(1)
    wire T_168712 : UInt<2>[3]
    T_168712[0] := UInt<2>(1)
    T_168712[1] := UInt<2>(2)
    T_168712[2] := UInt<2>(3)
    wire T_168713 : UInt<2>[2]
    T_168713[0] := UInt<2>(2)
    T_168713[1] := UInt<2>(3)
    wire T_168714 : UInt<2>[1]
    T_168714[0] := UInt<2>(3)
    wire T_168715 : UInt<3>[3]
    T_168715[0] := UInt<3>(0)
    T_168715[1] := UInt<3>(1)
    T_168715[2] := UInt<3>(2)
    wire T_168716 : UInt<2>[2]
    T_168716[0] := UInt<2>(0)
    T_168716[1] := UInt<2>(1)
    wire T_168717 : UInt<2>[3]
    T_168717[0] := UInt<2>(1)
    T_168717[1] := UInt<2>(2)
    T_168717[2] := UInt<2>(3)
    wire T_168718 : UInt<2>[2]
    T_168718[0] := UInt<2>(2)
    T_168718[1] := UInt<2>(3)
    wire T_168719 : UInt<2>[1]
    T_168719[0] := UInt<2>(3)
    wire T_168720 : UInt<3>[3]
    T_168720[0] := UInt<3>(0)
    T_168720[1] := UInt<3>(1)
    T_168720[2] := UInt<3>(2)
    wire T_168721 : UInt<2>[2]
    T_168721[0] := UInt<2>(0)
    T_168721[1] := UInt<2>(1)
    wire T_168722 : UInt<2>[3]
    T_168722[0] := UInt<2>(1)
    T_168722[1] := UInt<2>(2)
    T_168722[2] := UInt<2>(3)
    wire T_168723 : UInt<2>[2]
    T_168723[0] := UInt<2>(2)
    T_168723[1] := UInt<2>(3)
    wire T_168724 : UInt<2>[1]
    T_168724[0] := UInt<2>(3)
    wire T_168725 : UInt<3>[3]
    T_168725[0] := UInt<3>(0)
    T_168725[1] := UInt<3>(1)
    T_168725[2] := UInt<3>(2)
    wire T_168726 : UInt<2>[2]
    T_168726[0] := UInt<2>(0)
    T_168726[1] := UInt<2>(1)
    wire T_168727 : UInt<2>[3]
    T_168727[0] := UInt<2>(1)
    T_168727[1] := UInt<2>(2)
    T_168727[2] := UInt<2>(3)
    wire T_168728 : UInt<2>[2]
    T_168728[0] := UInt<2>(2)
    T_168728[1] := UInt<2>(3)
    wire T_168729 : UInt<2>[1]
    T_168729[0] := UInt<2>(3)
    wire T_168730 : UInt<3>[3]
    T_168730[0] := UInt<3>(0)
    T_168730[1] := UInt<3>(1)
    T_168730[2] := UInt<3>(2)
    wire T_168731 : UInt<2>[2]
    T_168731[0] := UInt<2>(0)
    T_168731[1] := UInt<2>(1)
    wire T_168732 : UInt<2>[3]
    T_168732[0] := UInt<2>(1)
    T_168732[1] := UInt<2>(2)
    T_168732[2] := UInt<2>(3)
    wire T_168733 : UInt<2>[2]
    T_168733[0] := UInt<2>(2)
    T_168733[1] := UInt<2>(3)
    wire T_168734 : UInt<2>[1]
    T_168734[0] := UInt<2>(3)
    wire T_168735 : UInt<3>[3]
    T_168735[0] := UInt<3>(0)
    T_168735[1] := UInt<3>(1)
    T_168735[2] := UInt<3>(2)
    wire T_168736 : UInt<2>[2]
    T_168736[0] := UInt<2>(0)
    T_168736[1] := UInt<2>(1)
    wire T_168737 : UInt<2>[3]
    T_168737[0] := UInt<2>(1)
    T_168737[1] := UInt<2>(2)
    T_168737[2] := UInt<2>(3)
    wire T_168738 : UInt<2>[2]
    T_168738[0] := UInt<2>(2)
    T_168738[1] := UInt<2>(3)
    wire T_168739 : UInt<2>[1]
    T_168739[0] := UInt<2>(3)
    wire T_168740 : UInt<3>[3]
    T_168740[0] := UInt<3>(0)
    T_168740[1] := UInt<3>(1)
    T_168740[2] := UInt<3>(2)
    wire T_168741 : UInt<2>[2]
    T_168741[0] := UInt<2>(0)
    T_168741[1] := UInt<2>(1)
    wire T_168742 : UInt<2>[3]
    T_168742[0] := UInt<2>(1)
    T_168742[1] := UInt<2>(2)
    T_168742[2] := UInt<2>(3)
    wire T_168743 : UInt<2>[2]
    T_168743[0] := UInt<2>(2)
    T_168743[1] := UInt<2>(3)
    wire T_168744 : UInt<2>[1]
    T_168744[0] := UInt<2>(3)
    wire T_168745 : UInt<3>[3]
    T_168745[0] := UInt<3>(0)
    T_168745[1] := UInt<3>(1)
    T_168745[2] := UInt<3>(2)
    wire T_168746 : UInt<2>[2]
    T_168746[0] := UInt<2>(0)
    T_168746[1] := UInt<2>(1)
    wire T_168747 : UInt<2>[3]
    T_168747[0] := UInt<2>(1)
    T_168747[1] := UInt<2>(2)
    T_168747[2] := UInt<2>(3)
    wire T_168748 : UInt<2>[2]
    T_168748[0] := UInt<2>(2)
    T_168748[1] := UInt<2>(3)
    wire T_168749 : UInt<2>[1]
    T_168749[0] := UInt<2>(3)
    wire T_168750 : UInt<3>[3]
    T_168750[0] := UInt<3>(0)
    T_168750[1] := UInt<3>(1)
    T_168750[2] := UInt<3>(2)
    wire T_168751 : UInt<2>[2]
    T_168751[0] := UInt<2>(0)
    T_168751[1] := UInt<2>(1)
    wire T_168752 : UInt<2>[3]
    T_168752[0] := UInt<2>(1)
    T_168752[1] := UInt<2>(2)
    T_168752[2] := UInt<2>(3)
    wire T_168753 : UInt<2>[2]
    T_168753[0] := UInt<2>(2)
    T_168753[1] := UInt<2>(3)
    wire T_168754 : UInt<2>[1]
    T_168754[0] := UInt<2>(3)
    wire T_168755 : UInt<3>[3]
    T_168755[0] := UInt<3>(0)
    T_168755[1] := UInt<3>(1)
    T_168755[2] := UInt<3>(2)
    wire T_168756 : UInt<2>[2]
    T_168756[0] := UInt<2>(0)
    T_168756[1] := UInt<2>(1)
    wire T_168757 : UInt<2>[3]
    T_168757[0] := UInt<2>(1)
    T_168757[1] := UInt<2>(2)
    T_168757[2] := UInt<2>(3)
    wire T_168758 : UInt<2>[2]
    T_168758[0] := UInt<2>(2)
    T_168758[1] := UInt<2>(3)
    wire T_168759 : UInt<2>[1]
    T_168759[0] := UInt<2>(3)
    wire T_168760 : UInt<3>[3]
    T_168760[0] := UInt<3>(0)
    T_168760[1] := UInt<3>(1)
    T_168760[2] := UInt<3>(2)
    wire T_168761 : UInt<2>[2]
    T_168761[0] := UInt<2>(0)
    T_168761[1] := UInt<2>(1)
    wire T_168762 : UInt<2>[3]
    T_168762[0] := UInt<2>(1)
    T_168762[1] := UInt<2>(2)
    T_168762[2] := UInt<2>(3)
    wire T_168763 : UInt<2>[2]
    T_168763[0] := UInt<2>(2)
    T_168763[1] := UInt<2>(3)
    wire T_168764 : UInt<2>[1]
    T_168764[0] := UInt<2>(3)
    wire T_168765 : UInt<3>[3]
    T_168765[0] := UInt<3>(0)
    T_168765[1] := UInt<3>(1)
    T_168765[2] := UInt<3>(2)
    wire T_168766 : UInt<2>[2]
    T_168766[0] := UInt<2>(0)
    T_168766[1] := UInt<2>(1)
    wire T_168767 : UInt<2>[3]
    T_168767[0] := UInt<2>(1)
    T_168767[1] := UInt<2>(2)
    T_168767[2] := UInt<2>(3)
    wire T_168768 : UInt<2>[2]
    T_168768[0] := UInt<2>(2)
    T_168768[1] := UInt<2>(3)
    wire T_168769 : UInt<2>[1]
    T_168769[0] := UInt<2>(3)
    wire T_168770 : UInt<3>[3]
    T_168770[0] := UInt<3>(0)
    T_168770[1] := UInt<3>(1)
    T_168770[2] := UInt<3>(2)
    wire T_168771 : UInt<2>[2]
    T_168771[0] := UInt<2>(0)
    T_168771[1] := UInt<2>(1)
    wire T_168772 : UInt<2>[3]
    T_168772[0] := UInt<2>(1)
    T_168772[1] := UInt<2>(2)
    T_168772[2] := UInt<2>(3)
    wire T_168773 : UInt<2>[2]
    T_168773[0] := UInt<2>(2)
    T_168773[1] := UInt<2>(3)
    wire T_168774 : UInt<2>[1]
    T_168774[0] := UInt<2>(3)
    wire T_168775 : UInt<3>[3]
    T_168775[0] := UInt<3>(0)
    T_168775[1] := UInt<3>(1)
    T_168775[2] := UInt<3>(2)
    wire T_168776 : UInt<2>[2]
    T_168776[0] := UInt<2>(0)
    T_168776[1] := UInt<2>(1)
    wire T_168777 : UInt<2>[3]
    T_168777[0] := UInt<2>(1)
    T_168777[1] := UInt<2>(2)
    T_168777[2] := UInt<2>(3)
    wire T_168778 : UInt<2>[2]
    T_168778[0] := UInt<2>(2)
    T_168778[1] := UInt<2>(3)
    wire T_168779 : UInt<2>[1]
    T_168779[0] := UInt<2>(3)
    wire T_168780 : UInt<3>[3]
    T_168780[0] := UInt<3>(0)
    T_168780[1] := UInt<3>(1)
    T_168780[2] := UInt<3>(2)
    wire T_168781 : UInt<2>[2]
    T_168781[0] := UInt<2>(0)
    T_168781[1] := UInt<2>(1)
    wire T_168782 : UInt<2>[3]
    T_168782[0] := UInt<2>(1)
    T_168782[1] := UInt<2>(2)
    T_168782[2] := UInt<2>(3)
    wire T_168783 : UInt<2>[2]
    T_168783[0] := UInt<2>(2)
    T_168783[1] := UInt<2>(3)
    wire T_168784 : UInt<2>[1]
    T_168784[0] := UInt<2>(3)
    wire T_168785 : UInt<3>[3]
    T_168785[0] := UInt<3>(0)
    T_168785[1] := UInt<3>(1)
    T_168785[2] := UInt<3>(2)
    wire T_168786 : UInt<2>[2]
    T_168786[0] := UInt<2>(0)
    T_168786[1] := UInt<2>(1)
    wire T_168787 : UInt<2>[3]
    T_168787[0] := UInt<2>(1)
    T_168787[1] := UInt<2>(2)
    T_168787[2] := UInt<2>(3)
    wire T_168788 : UInt<2>[2]
    T_168788[0] := UInt<2>(2)
    T_168788[1] := UInt<2>(3)
    wire T_168789 : UInt<2>[1]
    T_168789[0] := UInt<2>(3)
    wire T_168790 : UInt<3>[3]
    T_168790[0] := UInt<3>(0)
    T_168790[1] := UInt<3>(1)
    T_168790[2] := UInt<3>(2)
    wire T_168791 : UInt<2>[2]
    T_168791[0] := UInt<2>(0)
    T_168791[1] := UInt<2>(1)
    wire T_168792 : UInt<2>[3]
    T_168792[0] := UInt<2>(1)
    T_168792[1] := UInt<2>(2)
    T_168792[2] := UInt<2>(3)
    wire T_168793 : UInt<2>[2]
    T_168793[0] := UInt<2>(2)
    T_168793[1] := UInt<2>(3)
    wire T_168794 : UInt<2>[1]
    T_168794[0] := UInt<2>(3)
    wire T_168795 : UInt<3>[3]
    T_168795[0] := UInt<3>(0)
    T_168795[1] := UInt<3>(1)
    T_168795[2] := UInt<3>(2)
    wire T_168796 : UInt<2>[2]
    T_168796[0] := UInt<2>(0)
    T_168796[1] := UInt<2>(1)
    wire T_168797 : UInt<2>[3]
    T_168797[0] := UInt<2>(1)
    T_168797[1] := UInt<2>(2)
    T_168797[2] := UInt<2>(3)
    wire T_168798 : UInt<2>[2]
    T_168798[0] := UInt<2>(2)
    T_168798[1] := UInt<2>(3)
    wire T_168799 : UInt<2>[1]
    T_168799[0] := UInt<2>(3)
    wire T_168800 : UInt<3>[3]
    T_168800[0] := UInt<3>(0)
    T_168800[1] := UInt<3>(1)
    T_168800[2] := UInt<3>(2)
    wire T_168801 : UInt<2>[2]
    T_168801[0] := UInt<2>(0)
    T_168801[1] := UInt<2>(1)
    wire T_168802 : UInt<2>[3]
    T_168802[0] := UInt<2>(1)
    T_168802[1] := UInt<2>(2)
    T_168802[2] := UInt<2>(3)
    wire T_168803 : UInt<2>[2]
    T_168803[0] := UInt<2>(2)
    T_168803[1] := UInt<2>(3)
    wire T_168804 : UInt<2>[1]
    T_168804[0] := UInt<2>(3)
    wire T_168805 : UInt<3>[3]
    T_168805[0] := UInt<3>(0)
    T_168805[1] := UInt<3>(1)
    T_168805[2] := UInt<3>(2)
    wire T_168806 : UInt<2>[2]
    T_168806[0] := UInt<2>(0)
    T_168806[1] := UInt<2>(1)
    wire T_168807 : UInt<2>[3]
    T_168807[0] := UInt<2>(1)
    T_168807[1] := UInt<2>(2)
    T_168807[2] := UInt<2>(3)
    wire T_168808 : UInt<2>[2]
    T_168808[0] := UInt<2>(2)
    T_168808[1] := UInt<2>(3)
    wire T_168809 : UInt<2>[1]
    T_168809[0] := UInt<2>(3)
    wire T_168810 : UInt<3>[3]
    T_168810[0] := UInt<3>(0)
    T_168810[1] := UInt<3>(1)
    T_168810[2] := UInt<3>(2)
    wire T_168811 : UInt<2>[2]
    T_168811[0] := UInt<2>(0)
    T_168811[1] := UInt<2>(1)
    wire T_168812 : UInt<2>[3]
    T_168812[0] := UInt<2>(1)
    T_168812[1] := UInt<2>(2)
    T_168812[2] := UInt<2>(3)
    wire T_168813 : UInt<2>[2]
    T_168813[0] := UInt<2>(2)
    T_168813[1] := UInt<2>(3)
    wire T_168814 : UInt<2>[1]
    T_168814[0] := UInt<2>(3)
    wire T_168815 : UInt<3>[3]
    T_168815[0] := UInt<3>(0)
    T_168815[1] := UInt<3>(1)
    T_168815[2] := UInt<3>(2)
    wire T_168816 : UInt<2>[2]
    T_168816[0] := UInt<2>(0)
    T_168816[1] := UInt<2>(1)
    wire T_168817 : UInt<2>[3]
    T_168817[0] := UInt<2>(1)
    T_168817[1] := UInt<2>(2)
    T_168817[2] := UInt<2>(3)
    wire T_168818 : UInt<2>[2]
    T_168818[0] := UInt<2>(2)
    T_168818[1] := UInt<2>(3)
    wire T_168819 : UInt<2>[1]
    T_168819[0] := UInt<2>(3)
    wire T_168820 : UInt<3>[3]
    T_168820[0] := UInt<3>(0)
    T_168820[1] := UInt<3>(1)
    T_168820[2] := UInt<3>(2)
    wire T_168821 : UInt<2>[2]
    T_168821[0] := UInt<2>(0)
    T_168821[1] := UInt<2>(1)
    wire T_168822 : UInt<2>[3]
    T_168822[0] := UInt<2>(1)
    T_168822[1] := UInt<2>(2)
    T_168822[2] := UInt<2>(3)
    wire T_168823 : UInt<2>[2]
    T_168823[0] := UInt<2>(2)
    T_168823[1] := UInt<2>(3)
    wire T_168824 : UInt<2>[1]
    T_168824[0] := UInt<2>(3)
    wire T_168825 : UInt<3>[3]
    T_168825[0] := UInt<3>(0)
    T_168825[1] := UInt<3>(1)
    T_168825[2] := UInt<3>(2)
    wire T_168826 : UInt<2>[2]
    T_168826[0] := UInt<2>(0)
    T_168826[1] := UInt<2>(1)
    wire T_168827 : UInt<2>[3]
    T_168827[0] := UInt<2>(1)
    T_168827[1] := UInt<2>(2)
    T_168827[2] := UInt<2>(3)
    wire T_168828 : UInt<2>[2]
    T_168828[0] := UInt<2>(2)
    T_168828[1] := UInt<2>(3)
    wire T_168829 : UInt<2>[1]
    T_168829[0] := UInt<2>(3)
    wire T_168830 : UInt<3>[3]
    T_168830[0] := UInt<3>(0)
    T_168830[1] := UInt<3>(1)
    T_168830[2] := UInt<3>(2)
    wire T_168831 : UInt<2>[2]
    T_168831[0] := UInt<2>(0)
    T_168831[1] := UInt<2>(1)
    wire T_168832 : UInt<2>[3]
    T_168832[0] := UInt<2>(1)
    T_168832[1] := UInt<2>(2)
    T_168832[2] := UInt<2>(3)
    wire T_168833 : UInt<2>[2]
    T_168833[0] := UInt<2>(2)
    T_168833[1] := UInt<2>(3)
    wire T_168834 : UInt<2>[1]
    T_168834[0] := UInt<2>(3)
    wire T_168835 : UInt<3>[3]
    T_168835[0] := UInt<3>(0)
    T_168835[1] := UInt<3>(1)
    T_168835[2] := UInt<3>(2)
    wire T_168836 : UInt<2>[2]
    T_168836[0] := UInt<2>(0)
    T_168836[1] := UInt<2>(1)
    wire T_168837 : UInt<2>[3]
    T_168837[0] := UInt<2>(1)
    T_168837[1] := UInt<2>(2)
    T_168837[2] := UInt<2>(3)
    wire T_168838 : UInt<2>[2]
    T_168838[0] := UInt<2>(2)
    T_168838[1] := UInt<2>(3)
    wire T_168839 : UInt<2>[1]
    T_168839[0] := UInt<2>(3)
    wire T_168840 : UInt<3>[3]
    T_168840[0] := UInt<3>(0)
    T_168840[1] := UInt<3>(1)
    T_168840[2] := UInt<3>(2)
    wire T_168841 : UInt<2>[2]
    T_168841[0] := UInt<2>(0)
    T_168841[1] := UInt<2>(1)
    wire T_168842 : UInt<2>[3]
    T_168842[0] := UInt<2>(1)
    T_168842[1] := UInt<2>(2)
    T_168842[2] := UInt<2>(3)
    wire T_168843 : UInt<2>[2]
    T_168843[0] := UInt<2>(2)
    T_168843[1] := UInt<2>(3)
    wire T_168844 : UInt<2>[1]
    T_168844[0] := UInt<2>(3)
    wire T_168845 : UInt<3>[3]
    T_168845[0] := UInt<3>(0)
    T_168845[1] := UInt<3>(1)
    T_168845[2] := UInt<3>(2)
    wire T_168846 : UInt<2>[2]
    T_168846[0] := UInt<2>(0)
    T_168846[1] := UInt<2>(1)
    wire T_168847 : UInt<2>[3]
    T_168847[0] := UInt<2>(1)
    T_168847[1] := UInt<2>(2)
    T_168847[2] := UInt<2>(3)
    wire T_168848 : UInt<2>[2]
    T_168848[0] := UInt<2>(2)
    T_168848[1] := UInt<2>(3)
    wire T_168849 : UInt<2>[1]
    T_168849[0] := UInt<2>(3)
    wire T_168850 : UInt<3>[3]
    T_168850[0] := UInt<3>(0)
    T_168850[1] := UInt<3>(1)
    T_168850[2] := UInt<3>(2)
    wire T_168851 : UInt<2>[2]
    T_168851[0] := UInt<2>(0)
    T_168851[1] := UInt<2>(1)
    wire T_168852 : UInt<2>[3]
    T_168852[0] := UInt<2>(1)
    T_168852[1] := UInt<2>(2)
    T_168852[2] := UInt<2>(3)
    wire T_168853 : UInt<2>[2]
    T_168853[0] := UInt<2>(2)
    T_168853[1] := UInt<2>(3)
    wire T_168854 : UInt<2>[1]
    T_168854[0] := UInt<2>(3)
    wire T_168855 : UInt<3>[3]
    T_168855[0] := UInt<3>(0)
    T_168855[1] := UInt<3>(1)
    T_168855[2] := UInt<3>(2)
    wire T_168856 : UInt<2>[2]
    T_168856[0] := UInt<2>(0)
    T_168856[1] := UInt<2>(1)
    wire T_168857 : UInt<2>[3]
    T_168857[0] := UInt<2>(1)
    T_168857[1] := UInt<2>(2)
    T_168857[2] := UInt<2>(3)
    wire T_168858 : UInt<2>[2]
    T_168858[0] := UInt<2>(2)
    T_168858[1] := UInt<2>(3)
    wire T_168859 : UInt<2>[1]
    T_168859[0] := UInt<2>(3)
    wire T_168860 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}}
    T_168860.bits.payload := manager.grant.bits
    T_168860.bits.header.src := UInt<1>(0)
    T_168860.bits.header.dst := manager.grant.bits.client_id
    T_168860.valid := manager.grant.valid
    manager.grant.ready := T_168860.ready
    network.grant <> T_168860
    wire T_168861 : UInt<3>[3]
    T_168861[0] := UInt<3>(0)
    T_168861[1] := UInt<3>(1)
    T_168861[2] := UInt<3>(2)
    wire T_168862 : UInt<2>[2]
    T_168862[0] := UInt<2>(0)
    T_168862[1] := UInt<2>(1)
    wire T_168863 : UInt<2>[3]
    T_168863[0] := UInt<2>(1)
    T_168863[1] := UInt<2>(2)
    T_168863[2] := UInt<2>(3)
    wire T_168864 : UInt<2>[2]
    T_168864[0] := UInt<2>(2)
    T_168864[1] := UInt<2>(3)
    wire T_168865 : UInt<2>[1]
    T_168865[0] := UInt<2>(3)
    wire T_168866 : UInt<3>[3]
    T_168866[0] := UInt<3>(0)
    T_168866[1] := UInt<3>(1)
    T_168866[2] := UInt<3>(2)
    wire T_168867 : UInt<2>[2]
    T_168867[0] := UInt<2>(0)
    T_168867[1] := UInt<2>(1)
    wire T_168868 : UInt<2>[3]
    T_168868[0] := UInt<2>(1)
    T_168868[1] := UInt<2>(2)
    T_168868[2] := UInt<2>(3)
    wire T_168869 : UInt<2>[2]
    T_168869[0] := UInt<2>(2)
    T_168869[1] := UInt<2>(3)
    wire T_168870 : UInt<2>[1]
    T_168870[0] := UInt<2>(3)
    wire T_168871 : UInt<3>[3]
    T_168871[0] := UInt<3>(0)
    T_168871[1] := UInt<3>(1)
    T_168871[2] := UInt<3>(2)
    wire T_168872 : UInt<2>[2]
    T_168872[0] := UInt<2>(0)
    T_168872[1] := UInt<2>(1)
    wire T_168873 : UInt<2>[3]
    T_168873[0] := UInt<2>(1)
    T_168873[1] := UInt<2>(2)
    T_168873[2] := UInt<2>(3)
    wire T_168874 : UInt<2>[2]
    T_168874[0] := UInt<2>(2)
    T_168874[1] := UInt<2>(3)
    wire T_168875 : UInt<2>[1]
    T_168875[0] := UInt<2>(3)
    wire T_168876 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}}
    T_168876.bits.payload := manager.probe.bits
    T_168876.bits.header.src := UInt<1>(0)
    T_168876.bits.header.dst := manager.probe.bits.client_id
    T_168876.valid := manager.probe.valid
    manager.probe.ready := T_168876.ready
    network.probe <> T_168876
    manager.acquire.bits.client_id := network.acquire.bits.header.src
    wire T_168877 : UInt<3>[3]
    T_168877[0] := UInt<3>(0)
    T_168877[1] := UInt<3>(1)
    T_168877[2] := UInt<3>(2)
    wire T_168878 : UInt<2>[2]
    T_168878[0] := UInt<2>(0)
    T_168878[1] := UInt<2>(1)
    wire T_168879 : UInt<2>[3]
    T_168879[0] := UInt<2>(1)
    T_168879[1] := UInt<2>(2)
    T_168879[2] := UInt<2>(3)
    wire T_168880 : UInt<2>[2]
    T_168880[0] := UInt<2>(2)
    T_168880[1] := UInt<2>(3)
    wire T_168881 : UInt<2>[1]
    T_168881[0] := UInt<2>(3)
    wire T_168882 : UInt<3>[3]
    T_168882[0] := UInt<3>(0)
    T_168882[1] := UInt<3>(1)
    T_168882[2] := UInt<3>(2)
    wire T_168883 : UInt<2>[2]
    T_168883[0] := UInt<2>(0)
    T_168883[1] := UInt<2>(1)
    wire T_168884 : UInt<2>[3]
    T_168884[0] := UInt<2>(1)
    T_168884[1] := UInt<2>(2)
    T_168884[2] := UInt<2>(3)
    wire T_168885 : UInt<2>[2]
    T_168885[0] := UInt<2>(2)
    T_168885[1] := UInt<2>(3)
    wire T_168886 : UInt<2>[1]
    T_168886[0] := UInt<2>(3)
    wire T_168887 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    T_168887.valid := network.acquire.valid
    T_168887.bits := network.acquire.bits.payload
    network.acquire.ready := T_168887.ready
    manager.acquire <> T_168887
    manager.release.bits.client_id := network.release.bits.header.src
    wire T_168888 : UInt<3>[3]
    T_168888[0] := UInt<3>(0)
    T_168888[1] := UInt<3>(1)
    T_168888[2] := UInt<3>(2)
    wire T_168889 : UInt<2>[2]
    T_168889[0] := UInt<2>(0)
    T_168889[1] := UInt<2>(1)
    wire T_168890 : UInt<2>[3]
    T_168890[0] := UInt<2>(1)
    T_168890[1] := UInt<2>(2)
    T_168890[2] := UInt<2>(3)
    wire T_168891 : UInt<2>[2]
    T_168891[0] := UInt<2>(2)
    T_168891[1] := UInt<2>(3)
    wire T_168892 : UInt<2>[1]
    T_168892[0] := UInt<2>(3)
    wire T_168893 : UInt<3>[3]
    T_168893[0] := UInt<3>(0)
    T_168893[1] := UInt<3>(1)
    T_168893[2] := UInt<3>(2)
    wire T_168894 : UInt<2>[2]
    T_168894[0] := UInt<2>(0)
    T_168894[1] := UInt<2>(1)
    wire T_168895 : UInt<2>[3]
    T_168895[0] := UInt<2>(1)
    T_168895[1] := UInt<2>(2)
    T_168895[2] := UInt<2>(3)
    wire T_168896 : UInt<2>[2]
    T_168896[0] := UInt<2>(2)
    T_168896[1] := UInt<2>(3)
    wire T_168897 : UInt<2>[1]
    T_168897[0] := UInt<2>(3)
    wire T_168898 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    T_168898.valid := network.release.valid
    T_168898.bits := network.release.bits.payload
    network.release.ready := T_168898.ready
    manager.release <> T_168898
    wire T_168899 : UInt<3>[3]
    T_168899[0] := UInt<3>(0)
    T_168899[1] := UInt<3>(1)
    T_168899[2] := UInt<3>(2)
    wire T_168900 : UInt<2>[2]
    T_168900[0] := UInt<2>(0)
    T_168900[1] := UInt<2>(1)
    wire T_168901 : UInt<2>[3]
    T_168901[0] := UInt<2>(1)
    T_168901[1] := UInt<2>(2)
    T_168901[2] := UInt<2>(3)
    wire T_168902 : UInt<2>[2]
    T_168902[0] := UInt<2>(2)
    T_168902[1] := UInt<2>(3)
    wire T_168903 : UInt<2>[1]
    T_168903[0] := UInt<2>(3)
    wire T_168904 : UInt<3>[3]
    T_168904[0] := UInt<3>(0)
    T_168904[1] := UInt<3>(1)
    T_168904[2] := UInt<3>(2)
    wire T_168905 : UInt<2>[2]
    T_168905[0] := UInt<2>(0)
    T_168905[1] := UInt<2>(1)
    wire T_168906 : UInt<2>[3]
    T_168906[0] := UInt<2>(1)
    T_168906[1] := UInt<2>(2)
    T_168906[2] := UInt<2>(3)
    wire T_168907 : UInt<2>[2]
    T_168907[0] := UInt<2>(2)
    T_168907[1] := UInt<2>(3)
    wire T_168908 : UInt<2>[1]
    T_168908[0] := UInt<2>(3)
    wire T_168909 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}
    T_168909.valid := network.finish.valid
    T_168909.bits := network.finish.bits.payload
    network.finish.ready := T_168909.ready
    manager.finish <> T_168909
  module Queue_46545 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output count : UInt<1>
    
    wire T_168910 : UInt<3>[3]
    T_168910[0] := UInt<3>(0)
    T_168910[1] := UInt<3>(1)
    T_168910[2] := UInt<3>(2)
    wire T_168911 : UInt<2>[2]
    T_168911[0] := UInt<2>(0)
    T_168911[1] := UInt<2>(1)
    wire T_168912 : UInt<2>[3]
    T_168912[0] := UInt<2>(1)
    T_168912[1] := UInt<2>(2)
    T_168912[2] := UInt<2>(3)
    wire T_168913 : UInt<2>[2]
    T_168913[0] := UInt<2>(2)
    T_168913[1] := UInt<2>(3)
    wire T_168914 : UInt<2>[1]
    T_168914[0] := UInt<2>(3)
    wire T_168915 : UInt<3>[3]
    T_168915[0] := UInt<3>(0)
    T_168915[1] := UInt<3>(1)
    T_168915[2] := UInt<3>(2)
    wire T_168916 : UInt<2>[2]
    T_168916[0] := UInt<2>(0)
    T_168916[1] := UInt<2>(1)
    wire T_168917 : UInt<2>[3]
    T_168917[0] := UInt<2>(1)
    T_168917[1] := UInt<2>(2)
    T_168917[2] := UInt<2>(3)
    wire T_168918 : UInt<2>[2]
    T_168918[0] := UInt<2>(2)
    T_168918[1] := UInt<2>(3)
    wire T_168919 : UInt<2>[1]
    T_168919[0] := UInt<2>(3)
    wire T_168920 : UInt<3>[3]
    T_168920[0] := UInt<3>(0)
    T_168920[1] := UInt<3>(1)
    T_168920[2] := UInt<3>(2)
    wire T_168921 : UInt<2>[2]
    T_168921[0] := UInt<2>(0)
    T_168921[1] := UInt<2>(1)
    wire T_168922 : UInt<2>[3]
    T_168922[0] := UInt<2>(1)
    T_168922[1] := UInt<2>(2)
    T_168922[2] := UInt<2>(3)
    wire T_168923 : UInt<2>[2]
    T_168923[0] := UInt<2>(2)
    T_168923[1] := UInt<2>(3)
    wire T_168924 : UInt<2>[1]
    T_168924[0] := UInt<2>(3)
    wire T_168925 : UInt<3>[3]
    T_168925[0] := UInt<3>(0)
    T_168925[1] := UInt<3>(1)
    T_168925[2] := UInt<3>(2)
    wire T_168926 : UInt<2>[2]
    T_168926[0] := UInt<2>(0)
    T_168926[1] := UInt<2>(1)
    wire T_168927 : UInt<2>[3]
    T_168927[0] := UInt<2>(1)
    T_168927[1] := UInt<2>(2)
    T_168927[2] := UInt<2>(3)
    wire T_168928 : UInt<2>[2]
    T_168928[0] := UInt<2>(2)
    T_168928[1] := UInt<2>(3)
    wire T_168929 : UInt<2>[1]
    T_168929[0] := UInt<2>(3)
    wire T_168930 : UInt<3>[3]
    T_168930[0] := UInt<3>(0)
    T_168930[1] := UInt<3>(1)
    T_168930[2] := UInt<3>(2)
    wire T_168931 : UInt<2>[2]
    T_168931[0] := UInt<2>(0)
    T_168931[1] := UInt<2>(1)
    wire T_168932 : UInt<2>[3]
    T_168932[0] := UInt<2>(1)
    T_168932[1] := UInt<2>(2)
    T_168932[2] := UInt<2>(3)
    wire T_168933 : UInt<2>[2]
    T_168933[0] := UInt<2>(2)
    T_168933[1] := UInt<2>(3)
    wire T_168934 : UInt<2>[1]
    T_168934[0] := UInt<2>(3)
    cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[1]
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(UInt<1>(0), UInt<1>(0))
    node T_168935 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_168935)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_168936 = and(enq.ready, enq.valid)
    node T_168937 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_168936, T_168937)
    node T_168938 = and(deq.ready, deq.valid)
    node T_168939 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_168938, T_168939)
    when do_enq : 
      wire T_168940 : UInt<3>[3]
      T_168940[0] := UInt<3>(0)
      T_168940[1] := UInt<3>(1)
      T_168940[2] := UInt<3>(2)
      wire T_168941 : UInt<2>[2]
      T_168941[0] := UInt<2>(0)
      T_168941[1] := UInt<2>(1)
      wire T_168942 : UInt<2>[3]
      T_168942[0] := UInt<2>(1)
      T_168942[1] := UInt<2>(2)
      T_168942[2] := UInt<2>(3)
      wire T_168943 : UInt<2>[2]
      T_168943[0] := UInt<2>(2)
      T_168943[1] := UInt<2>(3)
      wire T_168944 : UInt<2>[1]
      T_168944[0] := UInt<2>(3)
      accessor T_168945 = ram[UInt<1>(0)]
      T_168945 := enq.bits
    when do_deq : skip
    
    node T_168946 = neq(do_enq, do_deq)
    when T_168946 : maybe_full := do_enq
    node T_168947 = eq(empty, UInt<1>(0))
    node T_168948 = and(UInt<1>(0), enq.valid)
    node T_168949 = or(T_168947, T_168948)
    deq.valid := T_168949
    node T_168950 = eq(full, UInt<1>(0))
    node T_168951 = and(UInt<1>(0), deq.ready)
    node T_168952 = or(T_168950, T_168951)
    enq.ready := T_168952
    wire T_168953 : UInt<3>[3]
    T_168953[0] := UInt<3>(0)
    T_168953[1] := UInt<3>(1)
    T_168953[2] := UInt<3>(2)
    wire T_168954 : UInt<2>[2]
    T_168954[0] := UInt<2>(0)
    T_168954[1] := UInt<2>(1)
    wire T_168955 : UInt<2>[3]
    T_168955[0] := UInt<2>(1)
    T_168955[1] := UInt<2>(2)
    T_168955[2] := UInt<2>(3)
    wire T_168956 : UInt<2>[2]
    T_168956[0] := UInt<2>(2)
    T_168956[1] := UInt<2>(3)
    wire T_168957 : UInt<2>[1]
    T_168957[0] := UInt<2>(3)
    accessor T_168958 = ram[UInt<1>(0)]
    wire T_168959 : UInt<3>[3]
    T_168959[0] := UInt<3>(0)
    T_168959[1] := UInt<3>(1)
    T_168959[2] := UInt<3>(2)
    wire T_168960 : UInt<2>[2]
    T_168960[0] := UInt<2>(0)
    T_168960[1] := UInt<2>(1)
    wire T_168961 : UInt<2>[3]
    T_168961[0] := UInt<2>(1)
    T_168961[1] := UInt<2>(2)
    T_168961[2] := UInt<2>(3)
    wire T_168962 : UInt<2>[2]
    T_168962[0] := UInt<2>(2)
    T_168962[1] := UInt<2>(3)
    wire T_168963 : UInt<2>[1]
    T_168963[0] := UInt<2>(3)
    wire T_168964 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    T_168964 := T_168958
    when maybe_flow : T_168964 := enq.bits
    deq.bits := T_168964
    node ptr_diff = subw(UInt<1>(0), UInt<1>(0))
    node T_168965 = and(maybe_full, ptr_match)
    node T_168966 = cat(T_168965, ptr_diff)
    count := T_168966
  module TileLinkEnqueuer_46546 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_168967 : UInt<3>[3]
    T_168967[0] := UInt<3>(0)
    T_168967[1] := UInt<3>(1)
    T_168967[2] := UInt<3>(2)
    wire T_168968 : UInt<2>[2]
    T_168968[0] := UInt<2>(0)
    T_168968[1] := UInt<2>(1)
    wire T_168969 : UInt<2>[3]
    T_168969[0] := UInt<2>(1)
    T_168969[1] := UInt<2>(2)
    T_168969[2] := UInt<2>(3)
    wire T_168970 : UInt<2>[2]
    T_168970[0] := UInt<2>(2)
    T_168970[1] := UInt<2>(3)
    wire T_168971 : UInt<2>[1]
    T_168971[0] := UInt<2>(3)
    wire T_168972 : UInt<3>[3]
    T_168972[0] := UInt<3>(0)
    T_168972[1] := UInt<3>(1)
    T_168972[2] := UInt<3>(2)
    wire T_168973 : UInt<2>[2]
    T_168973[0] := UInt<2>(0)
    T_168973[1] := UInt<2>(1)
    wire T_168974 : UInt<2>[3]
    T_168974[0] := UInt<2>(1)
    T_168974[1] := UInt<2>(2)
    T_168974[2] := UInt<2>(3)
    wire T_168975 : UInt<2>[2]
    T_168975[0] := UInt<2>(2)
    T_168975[1] := UInt<2>(3)
    wire T_168976 : UInt<2>[1]
    T_168976[0] := UInt<2>(3)
    wire T_168977 : UInt<3>[3]
    T_168977[0] := UInt<3>(0)
    T_168977[1] := UInt<3>(1)
    T_168977[2] := UInt<3>(2)
    wire T_168978 : UInt<2>[2]
    T_168978[0] := UInt<2>(0)
    T_168978[1] := UInt<2>(1)
    wire T_168979 : UInt<2>[3]
    T_168979[0] := UInt<2>(1)
    T_168979[1] := UInt<2>(2)
    T_168979[2] := UInt<2>(3)
    wire T_168980 : UInt<2>[2]
    T_168980[0] := UInt<2>(2)
    T_168980[1] := UInt<2>(3)
    wire T_168981 : UInt<2>[1]
    T_168981[0] := UInt<2>(3)
    wire T_168982 : UInt<3>[3]
    T_168982[0] := UInt<3>(0)
    T_168982[1] := UInt<3>(1)
    T_168982[2] := UInt<3>(2)
    wire T_168983 : UInt<2>[2]
    T_168983[0] := UInt<2>(0)
    T_168983[1] := UInt<2>(1)
    wire T_168984 : UInt<2>[3]
    T_168984[0] := UInt<2>(1)
    T_168984[1] := UInt<2>(2)
    T_168984[2] := UInt<2>(3)
    wire T_168985 : UInt<2>[2]
    T_168985[0] := UInt<2>(2)
    T_168985[1] := UInt<2>(3)
    wire T_168986 : UInt<2>[1]
    T_168986[0] := UInt<2>(3)
    wire T_168987 : UInt<3>[3]
    T_168987[0] := UInt<3>(0)
    T_168987[1] := UInt<3>(1)
    T_168987[2] := UInt<3>(2)
    wire T_168988 : UInt<2>[2]
    T_168988[0] := UInt<2>(0)
    T_168988[1] := UInt<2>(1)
    wire T_168989 : UInt<2>[3]
    T_168989[0] := UInt<2>(1)
    T_168989[1] := UInt<2>(2)
    T_168989[2] := UInt<2>(3)
    wire T_168990 : UInt<2>[2]
    T_168990[0] := UInt<2>(2)
    T_168990[1] := UInt<2>(3)
    wire T_168991 : UInt<2>[1]
    T_168991[0] := UInt<2>(3)
    wire T_168992 : UInt<3>[3]
    T_168992[0] := UInt<3>(0)
    T_168992[1] := UInt<3>(1)
    T_168992[2] := UInt<3>(2)
    wire T_168993 : UInt<2>[2]
    T_168993[0] := UInt<2>(0)
    T_168993[1] := UInt<2>(1)
    wire T_168994 : UInt<2>[3]
    T_168994[0] := UInt<2>(1)
    T_168994[1] := UInt<2>(2)
    T_168994[2] := UInt<2>(3)
    wire T_168995 : UInt<2>[2]
    T_168995[0] := UInt<2>(2)
    T_168995[1] := UInt<2>(3)
    wire T_168996 : UInt<2>[1]
    T_168996[0] := UInt<2>(3)
    wire T_168997 : UInt<3>[3]
    T_168997[0] := UInt<3>(0)
    T_168997[1] := UInt<3>(1)
    T_168997[2] := UInt<3>(2)
    wire T_168998 : UInt<2>[2]
    T_168998[0] := UInt<2>(0)
    T_168998[1] := UInt<2>(1)
    wire T_168999 : UInt<2>[3]
    T_168999[0] := UInt<2>(1)
    T_168999[1] := UInt<2>(2)
    T_168999[2] := UInt<2>(3)
    wire T_169000 : UInt<2>[2]
    T_169000[0] := UInt<2>(2)
    T_169000[1] := UInt<2>(3)
    wire T_169001 : UInt<2>[1]
    T_169001[0] := UInt<2>(3)
    wire T_169002 : UInt<3>[3]
    T_169002[0] := UInt<3>(0)
    T_169002[1] := UInt<3>(1)
    T_169002[2] := UInt<3>(2)
    wire T_169003 : UInt<2>[2]
    T_169003[0] := UInt<2>(0)
    T_169003[1] := UInt<2>(1)
    wire T_169004 : UInt<2>[3]
    T_169004[0] := UInt<2>(1)
    T_169004[1] := UInt<2>(2)
    T_169004[2] := UInt<2>(3)
    wire T_169005 : UInt<2>[2]
    T_169005[0] := UInt<2>(2)
    T_169005[1] := UInt<2>(3)
    wire T_169006 : UInt<2>[1]
    T_169006[0] := UInt<2>(3)
    wire T_169007 : UInt<3>[3]
    T_169007[0] := UInt<3>(0)
    T_169007[1] := UInt<3>(1)
    T_169007[2] := UInt<3>(2)
    wire T_169008 : UInt<2>[2]
    T_169008[0] := UInt<2>(0)
    T_169008[1] := UInt<2>(1)
    wire T_169009 : UInt<2>[3]
    T_169009[0] := UInt<2>(1)
    T_169009[1] := UInt<2>(2)
    T_169009[2] := UInt<2>(3)
    wire T_169010 : UInt<2>[2]
    T_169010[0] := UInt<2>(2)
    T_169010[1] := UInt<2>(3)
    wire T_169011 : UInt<2>[1]
    T_169011[0] := UInt<2>(3)
    wire T_169012 : UInt<3>[3]
    T_169012[0] := UInt<3>(0)
    T_169012[1] := UInt<3>(1)
    T_169012[2] := UInt<3>(2)
    wire T_169013 : UInt<2>[2]
    T_169013[0] := UInt<2>(0)
    T_169013[1] := UInt<2>(1)
    wire T_169014 : UInt<2>[3]
    T_169014[0] := UInt<2>(1)
    T_169014[1] := UInt<2>(2)
    T_169014[2] := UInt<2>(3)
    wire T_169015 : UInt<2>[2]
    T_169015[0] := UInt<2>(2)
    T_169015[1] := UInt<2>(3)
    wire T_169016 : UInt<2>[1]
    T_169016[0] := UInt<2>(3)
    wire T_169017 : UInt<3>[3]
    T_169017[0] := UInt<3>(0)
    T_169017[1] := UInt<3>(1)
    T_169017[2] := UInt<3>(2)
    wire T_169018 : UInt<2>[2]
    T_169018[0] := UInt<2>(0)
    T_169018[1] := UInt<2>(1)
    wire T_169019 : UInt<2>[3]
    T_169019[0] := UInt<2>(1)
    T_169019[1] := UInt<2>(2)
    T_169019[2] := UInt<2>(3)
    wire T_169020 : UInt<2>[2]
    T_169020[0] := UInt<2>(2)
    T_169020[1] := UInt<2>(3)
    wire T_169021 : UInt<2>[1]
    T_169021[0] := UInt<2>(3)
    wire T_169022 : UInt<3>[3]
    T_169022[0] := UInt<3>(0)
    T_169022[1] := UInt<3>(1)
    T_169022[2] := UInt<3>(2)
    wire T_169023 : UInt<2>[2]
    T_169023[0] := UInt<2>(0)
    T_169023[1] := UInt<2>(1)
    wire T_169024 : UInt<2>[3]
    T_169024[0] := UInt<2>(1)
    T_169024[1] := UInt<2>(2)
    T_169024[2] := UInt<2>(3)
    wire T_169025 : UInt<2>[2]
    T_169025[0] := UInt<2>(2)
    T_169025[1] := UInt<2>(3)
    wire T_169026 : UInt<2>[1]
    T_169026[0] := UInt<2>(3)
    wire T_169027 : UInt<3>[3]
    T_169027[0] := UInt<3>(0)
    T_169027[1] := UInt<3>(1)
    T_169027[2] := UInt<3>(2)
    wire T_169028 : UInt<2>[2]
    T_169028[0] := UInt<2>(0)
    T_169028[1] := UInt<2>(1)
    wire T_169029 : UInt<2>[3]
    T_169029[0] := UInt<2>(1)
    T_169029[1] := UInt<2>(2)
    T_169029[2] := UInt<2>(3)
    wire T_169030 : UInt<2>[2]
    T_169030[0] := UInt<2>(2)
    T_169030[1] := UInt<2>(3)
    wire T_169031 : UInt<2>[1]
    T_169031[0] := UInt<2>(3)
    wire T_169032 : UInt<3>[3]
    T_169032[0] := UInt<3>(0)
    T_169032[1] := UInt<3>(1)
    T_169032[2] := UInt<3>(2)
    wire T_169033 : UInt<2>[2]
    T_169033[0] := UInt<2>(0)
    T_169033[1] := UInt<2>(1)
    wire T_169034 : UInt<2>[3]
    T_169034[0] := UInt<2>(1)
    T_169034[1] := UInt<2>(2)
    T_169034[2] := UInt<2>(3)
    wire T_169035 : UInt<2>[2]
    T_169035[0] := UInt<2>(2)
    T_169035[1] := UInt<2>(3)
    wire T_169036 : UInt<2>[1]
    T_169036[0] := UInt<2>(3)
    wire T_169037 : UInt<3>[3]
    T_169037[0] := UInt<3>(0)
    T_169037[1] := UInt<3>(1)
    T_169037[2] := UInt<3>(2)
    wire T_169038 : UInt<2>[2]
    T_169038[0] := UInt<2>(0)
    T_169038[1] := UInt<2>(1)
    wire T_169039 : UInt<2>[3]
    T_169039[0] := UInt<2>(1)
    T_169039[1] := UInt<2>(2)
    T_169039[2] := UInt<2>(3)
    wire T_169040 : UInt<2>[2]
    T_169040[0] := UInt<2>(2)
    T_169040[1] := UInt<2>(3)
    wire T_169041 : UInt<2>[1]
    T_169041[0] := UInt<2>(3)
    wire T_169042 : UInt<3>[3]
    T_169042[0] := UInt<3>(0)
    T_169042[1] := UInt<3>(1)
    T_169042[2] := UInt<3>(2)
    wire T_169043 : UInt<2>[2]
    T_169043[0] := UInt<2>(0)
    T_169043[1] := UInt<2>(1)
    wire T_169044 : UInt<2>[3]
    T_169044[0] := UInt<2>(1)
    T_169044[1] := UInt<2>(2)
    T_169044[2] := UInt<2>(3)
    wire T_169045 : UInt<2>[2]
    T_169045[0] := UInt<2>(2)
    T_169045[1] := UInt<2>(3)
    wire T_169046 : UInt<2>[1]
    T_169046[0] := UInt<2>(3)
    wire T_169047 : UInt<3>[3]
    T_169047[0] := UInt<3>(0)
    T_169047[1] := UInt<3>(1)
    T_169047[2] := UInt<3>(2)
    wire T_169048 : UInt<2>[2]
    T_169048[0] := UInt<2>(0)
    T_169048[1] := UInt<2>(1)
    wire T_169049 : UInt<2>[3]
    T_169049[0] := UInt<2>(1)
    T_169049[1] := UInt<2>(2)
    T_169049[2] := UInt<2>(3)
    wire T_169050 : UInt<2>[2]
    T_169050[0] := UInt<2>(2)
    T_169050[1] := UInt<2>(3)
    wire T_169051 : UInt<2>[1]
    T_169051[0] := UInt<2>(3)
    wire T_169052 : UInt<3>[3]
    T_169052[0] := UInt<3>(0)
    T_169052[1] := UInt<3>(1)
    T_169052[2] := UInt<3>(2)
    wire T_169053 : UInt<2>[2]
    T_169053[0] := UInt<2>(0)
    T_169053[1] := UInt<2>(1)
    wire T_169054 : UInt<2>[3]
    T_169054[0] := UInt<2>(1)
    T_169054[1] := UInt<2>(2)
    T_169054[2] := UInt<2>(3)
    wire T_169055 : UInt<2>[2]
    T_169055[0] := UInt<2>(2)
    T_169055[1] := UInt<2>(3)
    wire T_169056 : UInt<2>[1]
    T_169056[0] := UInt<2>(3)
    wire T_169057 : UInt<3>[3]
    T_169057[0] := UInt<3>(0)
    T_169057[1] := UInt<3>(1)
    T_169057[2] := UInt<3>(2)
    wire T_169058 : UInt<2>[2]
    T_169058[0] := UInt<2>(0)
    T_169058[1] := UInt<2>(1)
    wire T_169059 : UInt<2>[3]
    T_169059[0] := UInt<2>(1)
    T_169059[1] := UInt<2>(2)
    T_169059[2] := UInt<2>(3)
    wire T_169060 : UInt<2>[2]
    T_169060[0] := UInt<2>(2)
    T_169060[1] := UInt<2>(3)
    wire T_169061 : UInt<2>[1]
    T_169061[0] := UInt<2>(3)
    wire T_169062 : UInt<3>[3]
    T_169062[0] := UInt<3>(0)
    T_169062[1] := UInt<3>(1)
    T_169062[2] := UInt<3>(2)
    wire T_169063 : UInt<2>[2]
    T_169063[0] := UInt<2>(0)
    T_169063[1] := UInt<2>(1)
    wire T_169064 : UInt<2>[3]
    T_169064[0] := UInt<2>(1)
    T_169064[1] := UInt<2>(2)
    T_169064[2] := UInt<2>(3)
    wire T_169065 : UInt<2>[2]
    T_169065[0] := UInt<2>(2)
    T_169065[1] := UInt<2>(3)
    wire T_169066 : UInt<2>[1]
    T_169066[0] := UInt<2>(3)
    wire T_169067 : UInt<3>[3]
    T_169067[0] := UInt<3>(0)
    T_169067[1] := UInt<3>(1)
    T_169067[2] := UInt<3>(2)
    wire T_169068 : UInt<2>[2]
    T_169068[0] := UInt<2>(0)
    T_169068[1] := UInt<2>(1)
    wire T_169069 : UInt<2>[3]
    T_169069[0] := UInt<2>(1)
    T_169069[1] := UInt<2>(2)
    T_169069[2] := UInt<2>(3)
    wire T_169070 : UInt<2>[2]
    T_169070[0] := UInt<2>(2)
    T_169070[1] := UInt<2>(3)
    wire T_169071 : UInt<2>[1]
    T_169071[0] := UInt<2>(3)
    wire T_169072 : UInt<3>[3]
    T_169072[0] := UInt<3>(0)
    T_169072[1] := UInt<3>(1)
    T_169072[2] := UInt<3>(2)
    wire T_169073 : UInt<2>[2]
    T_169073[0] := UInt<2>(0)
    T_169073[1] := UInt<2>(1)
    wire T_169074 : UInt<2>[3]
    T_169074[0] := UInt<2>(1)
    T_169074[1] := UInt<2>(2)
    T_169074[2] := UInt<2>(3)
    wire T_169075 : UInt<2>[2]
    T_169075[0] := UInt<2>(2)
    T_169075[1] := UInt<2>(3)
    wire T_169076 : UInt<2>[1]
    T_169076[0] := UInt<2>(3)
    wire T_169077 : UInt<3>[3]
    T_169077[0] := UInt<3>(0)
    T_169077[1] := UInt<3>(1)
    T_169077[2] := UInt<3>(2)
    wire T_169078 : UInt<2>[2]
    T_169078[0] := UInt<2>(0)
    T_169078[1] := UInt<2>(1)
    wire T_169079 : UInt<2>[3]
    T_169079[0] := UInt<2>(1)
    T_169079[1] := UInt<2>(2)
    T_169079[2] := UInt<2>(3)
    wire T_169080 : UInt<2>[2]
    T_169080[0] := UInt<2>(2)
    T_169080[1] := UInt<2>(3)
    wire T_169081 : UInt<2>[1]
    T_169081[0] := UInt<2>(3)
    wire T_169082 : UInt<3>[3]
    T_169082[0] := UInt<3>(0)
    T_169082[1] := UInt<3>(1)
    T_169082[2] := UInt<3>(2)
    wire T_169083 : UInt<2>[2]
    T_169083[0] := UInt<2>(0)
    T_169083[1] := UInt<2>(1)
    wire T_169084 : UInt<2>[3]
    T_169084[0] := UInt<2>(1)
    T_169084[1] := UInt<2>(2)
    T_169084[2] := UInt<2>(3)
    wire T_169085 : UInt<2>[2]
    T_169085[0] := UInt<2>(2)
    T_169085[1] := UInt<2>(3)
    wire T_169086 : UInt<2>[1]
    T_169086[0] := UInt<2>(3)
    wire T_169087 : UInt<3>[3]
    T_169087[0] := UInt<3>(0)
    T_169087[1] := UInt<3>(1)
    T_169087[2] := UInt<3>(2)
    wire T_169088 : UInt<2>[2]
    T_169088[0] := UInt<2>(0)
    T_169088[1] := UInt<2>(1)
    wire T_169089 : UInt<2>[3]
    T_169089[0] := UInt<2>(1)
    T_169089[1] := UInt<2>(2)
    T_169089[2] := UInt<2>(3)
    wire T_169090 : UInt<2>[2]
    T_169090[0] := UInt<2>(2)
    T_169090[1] := UInt<2>(3)
    wire T_169091 : UInt<2>[1]
    T_169091[0] := UInt<2>(3)
    wire T_169092 : UInt<3>[3]
    T_169092[0] := UInt<3>(0)
    T_169092[1] := UInt<3>(1)
    T_169092[2] := UInt<3>(2)
    wire T_169093 : UInt<2>[2]
    T_169093[0] := UInt<2>(0)
    T_169093[1] := UInt<2>(1)
    wire T_169094 : UInt<2>[3]
    T_169094[0] := UInt<2>(1)
    T_169094[1] := UInt<2>(2)
    T_169094[2] := UInt<2>(3)
    wire T_169095 : UInt<2>[2]
    T_169095[0] := UInt<2>(2)
    T_169095[1] := UInt<2>(3)
    wire T_169096 : UInt<2>[1]
    T_169096[0] := UInt<2>(3)
    wire T_169097 : UInt<3>[3]
    T_169097[0] := UInt<3>(0)
    T_169097[1] := UInt<3>(1)
    T_169097[2] := UInt<3>(2)
    wire T_169098 : UInt<2>[2]
    T_169098[0] := UInt<2>(0)
    T_169098[1] := UInt<2>(1)
    wire T_169099 : UInt<2>[3]
    T_169099[0] := UInt<2>(1)
    T_169099[1] := UInt<2>(2)
    T_169099[2] := UInt<2>(3)
    wire T_169100 : UInt<2>[2]
    T_169100[0] := UInt<2>(2)
    T_169100[1] := UInt<2>(3)
    wire T_169101 : UInt<2>[1]
    T_169101[0] := UInt<2>(3)
    wire T_169102 : UInt<3>[3]
    T_169102[0] := UInt<3>(0)
    T_169102[1] := UInt<3>(1)
    T_169102[2] := UInt<3>(2)
    wire T_169103 : UInt<2>[2]
    T_169103[0] := UInt<2>(0)
    T_169103[1] := UInt<2>(1)
    wire T_169104 : UInt<2>[3]
    T_169104[0] := UInt<2>(1)
    T_169104[1] := UInt<2>(2)
    T_169104[2] := UInt<2>(3)
    wire T_169105 : UInt<2>[2]
    T_169105[0] := UInt<2>(2)
    T_169105[1] := UInt<2>(3)
    wire T_169106 : UInt<2>[1]
    T_169106[0] := UInt<2>(3)
    wire T_169107 : UInt<3>[3]
    T_169107[0] := UInt<3>(0)
    T_169107[1] := UInt<3>(1)
    T_169107[2] := UInt<3>(2)
    wire T_169108 : UInt<2>[2]
    T_169108[0] := UInt<2>(0)
    T_169108[1] := UInt<2>(1)
    wire T_169109 : UInt<2>[3]
    T_169109[0] := UInt<2>(1)
    T_169109[1] := UInt<2>(2)
    T_169109[2] := UInt<2>(3)
    wire T_169110 : UInt<2>[2]
    T_169110[0] := UInt<2>(2)
    T_169110[1] := UInt<2>(3)
    wire T_169111 : UInt<2>[1]
    T_169111[0] := UInt<2>(3)
    wire T_169112 : UInt<3>[3]
    T_169112[0] := UInt<3>(0)
    T_169112[1] := UInt<3>(1)
    T_169112[2] := UInt<3>(2)
    wire T_169113 : UInt<2>[2]
    T_169113[0] := UInt<2>(0)
    T_169113[1] := UInt<2>(1)
    wire T_169114 : UInt<2>[3]
    T_169114[0] := UInt<2>(1)
    T_169114[1] := UInt<2>(2)
    T_169114[2] := UInt<2>(3)
    wire T_169115 : UInt<2>[2]
    T_169115[0] := UInt<2>(2)
    T_169115[1] := UInt<2>(3)
    wire T_169116 : UInt<2>[1]
    T_169116[0] := UInt<2>(3)
    wire T_169117 : UInt<3>[3]
    T_169117[0] := UInt<3>(0)
    T_169117[1] := UInt<3>(1)
    T_169117[2] := UInt<3>(2)
    wire T_169118 : UInt<2>[2]
    T_169118[0] := UInt<2>(0)
    T_169118[1] := UInt<2>(1)
    wire T_169119 : UInt<2>[3]
    T_169119[0] := UInt<2>(1)
    T_169119[1] := UInt<2>(2)
    T_169119[2] := UInt<2>(3)
    wire T_169120 : UInt<2>[2]
    T_169120[0] := UInt<2>(2)
    T_169120[1] := UInt<2>(3)
    wire T_169121 : UInt<2>[1]
    T_169121[0] := UInt<2>(3)
    wire T_169122 : UInt<3>[3]
    T_169122[0] := UInt<3>(0)
    T_169122[1] := UInt<3>(1)
    T_169122[2] := UInt<3>(2)
    wire T_169123 : UInt<2>[2]
    T_169123[0] := UInt<2>(0)
    T_169123[1] := UInt<2>(1)
    wire T_169124 : UInt<2>[3]
    T_169124[0] := UInt<2>(1)
    T_169124[1] := UInt<2>(2)
    T_169124[2] := UInt<2>(3)
    wire T_169125 : UInt<2>[2]
    T_169125[0] := UInt<2>(2)
    T_169125[1] := UInt<2>(3)
    wire T_169126 : UInt<2>[1]
    T_169126[0] := UInt<2>(3)
    manager.acquire <> client.acquire
    client.probe <> manager.probe
    wire T_169127 : UInt<3>[3]
    T_169127[0] := UInt<3>(0)
    T_169127[1] := UInt<3>(1)
    T_169127[2] := UInt<3>(2)
    wire T_169128 : UInt<2>[2]
    T_169128[0] := UInt<2>(0)
    T_169128[1] := UInt<2>(1)
    wire T_169129 : UInt<2>[3]
    T_169129[0] := UInt<2>(1)
    T_169129[1] := UInt<2>(2)
    T_169129[2] := UInt<2>(3)
    wire T_169130 : UInt<2>[2]
    T_169130[0] := UInt<2>(2)
    T_169130[1] := UInt<2>(3)
    wire T_169131 : UInt<2>[1]
    T_169131[0] := UInt<2>(3)
    inst T_169132 of Queue_46545
    T_169132.enq.valid := client.release.valid
    T_169132.enq.bits := client.release.bits
    client.release.ready := T_169132.enq.ready
    manager.release <> T_169132.deq
    client.grant <> manager.grant
    manager.finish <> client.finish
  module LockingRRArbiter : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    output chosen : UInt<2>
    
    wire T_169133 : UInt<3>[3]
    T_169133[0] := UInt<3>(0)
    T_169133[1] := UInt<3>(1)
    T_169133[2] := UInt<3>(2)
    wire T_169134 : UInt<2>[2]
    T_169134[0] := UInt<2>(0)
    T_169134[1] := UInt<2>(1)
    wire T_169135 : UInt<2>[3]
    T_169135[0] := UInt<2>(1)
    T_169135[1] := UInt<2>(2)
    T_169135[2] := UInt<2>(3)
    wire T_169136 : UInt<2>[2]
    T_169136[0] := UInt<2>(2)
    T_169136[1] := UInt<2>(3)
    wire T_169137 : UInt<2>[1]
    T_169137[0] := UInt<2>(3)
    wire T_169138 : UInt<3>[3]
    T_169138[0] := UInt<3>(0)
    T_169138[1] := UInt<3>(1)
    T_169138[2] := UInt<3>(2)
    wire T_169139 : UInt<2>[2]
    T_169139[0] := UInt<2>(0)
    T_169139[1] := UInt<2>(1)
    wire T_169140 : UInt<2>[3]
    T_169140[0] := UInt<2>(1)
    T_169140[1] := UInt<2>(2)
    T_169140[2] := UInt<2>(3)
    wire T_169141 : UInt<2>[2]
    T_169141[0] := UInt<2>(2)
    T_169141[1] := UInt<2>(3)
    wire T_169142 : UInt<2>[1]
    T_169142[0] := UInt<2>(3)
    wire T_169143 : UInt<3>[3]
    T_169143[0] := UInt<3>(0)
    T_169143[1] := UInt<3>(1)
    T_169143[2] := UInt<3>(2)
    wire T_169144 : UInt<2>[2]
    T_169144[0] := UInt<2>(0)
    T_169144[1] := UInt<2>(1)
    wire T_169145 : UInt<2>[3]
    T_169145[0] := UInt<2>(1)
    T_169145[1] := UInt<2>(2)
    T_169145[2] := UInt<2>(3)
    wire T_169146 : UInt<2>[2]
    T_169146[0] := UInt<2>(2)
    T_169146[1] := UInt<2>(3)
    wire T_169147 : UInt<2>[1]
    T_169147[0] := UInt<2>(3)
    wire T_169148 : UInt<3>[3]
    T_169148[0] := UInt<3>(0)
    T_169148[1] := UInt<3>(1)
    T_169148[2] := UInt<3>(2)
    wire T_169149 : UInt<2>[2]
    T_169149[0] := UInt<2>(0)
    T_169149[1] := UInt<2>(1)
    wire T_169150 : UInt<2>[3]
    T_169150[0] := UInt<2>(1)
    T_169150[1] := UInt<2>(2)
    T_169150[2] := UInt<2>(3)
    wire T_169151 : UInt<2>[2]
    T_169151[0] := UInt<2>(2)
    T_169151[1] := UInt<2>(3)
    wire T_169152 : UInt<2>[1]
    T_169152[0] := UInt<2>(3)
    wire T_169153 : UInt<3>[3]
    T_169153[0] := UInt<3>(0)
    T_169153[1] := UInt<3>(1)
    T_169153[2] := UInt<3>(2)
    wire T_169154 : UInt<2>[2]
    T_169154[0] := UInt<2>(0)
    T_169154[1] := UInt<2>(1)
    wire T_169155 : UInt<2>[3]
    T_169155[0] := UInt<2>(1)
    T_169155[1] := UInt<2>(2)
    T_169155[2] := UInt<2>(3)
    wire T_169156 : UInt<2>[2]
    T_169156[0] := UInt<2>(2)
    T_169156[1] := UInt<2>(3)
    wire T_169157 : UInt<2>[1]
    T_169157[0] := UInt<2>(3)
    reg T_169158 : UInt<1>
    onreset T_169158 := UInt<1>(0)
    reg T_169159 : UInt<2>
    onreset T_169159 := UInt<2>(2)
    wire T_169160 : UInt<2>
    reg last_grant : UInt<2>
    onreset last_grant := UInt<2>(0)
    node T_169161 = gt(UInt<1>(0), last_grant)
    node T_169162 = and(in[0].valid, T_169161)
    node T_169163 = gt(UInt<1>(1), last_grant)
    node T_169164 = and(in[1].valid, T_169163)
    node T_169165 = gt(UInt<2>(2), last_grant)
    node T_169166 = and(in[2].valid, T_169165)
    node T_169167 = or(UInt<1>(0), T_169162)
    node T_169168 = eq(T_169167, UInt<1>(0))
    node T_169169 = or(UInt<1>(0), T_169162)
    node T_169170 = or(T_169169, T_169164)
    node T_169171 = eq(T_169170, UInt<1>(0))
    node T_169172 = or(UInt<1>(0), T_169162)
    node T_169173 = or(T_169172, T_169164)
    node T_169174 = or(T_169173, T_169166)
    node T_169175 = eq(T_169174, UInt<1>(0))
    node T_169176 = or(UInt<1>(0), T_169162)
    node T_169177 = or(T_169176, T_169164)
    node T_169178 = or(T_169177, T_169166)
    node T_169179 = or(T_169178, in[0].valid)
    node T_169180 = eq(T_169179, UInt<1>(0))
    node T_169181 = or(UInt<1>(0), T_169162)
    node T_169182 = or(T_169181, T_169164)
    node T_169183 = or(T_169182, T_169166)
    node T_169184 = or(T_169183, in[0].valid)
    node T_169185 = or(T_169184, in[1].valid)
    node T_169186 = eq(T_169185, UInt<1>(0))
    node T_169187 = gt(UInt<1>(0), last_grant)
    node T_169188 = and(UInt<1>(1), T_169187)
    node T_169189 = or(T_169188, T_169175)
    node T_169190 = gt(UInt<1>(1), last_grant)
    node T_169191 = and(T_169168, T_169190)
    node T_169192 = or(T_169191, T_169180)
    node T_169193 = gt(UInt<2>(2), last_grant)
    node T_169194 = and(T_169171, T_169193)
    node T_169195 = or(T_169194, T_169186)
    node T_169196 = eq(T_169159, UInt<1>(0))
    wire T_169197 : UInt<1>
    T_169197 := T_169189
    when T_169158 : T_169197 := T_169196
    node T_169198 = and(T_169197, out.ready)
    in[0].ready := T_169198
    node T_169199 = eq(T_169159, UInt<1>(1))
    wire T_169200 : UInt<1>
    T_169200 := T_169192
    when T_169158 : T_169200 := T_169199
    node T_169201 = and(T_169200, out.ready)
    in[1].ready := T_169201
    node T_169202 = eq(T_169159, UInt<2>(2))
    wire T_169203 : UInt<1>
    T_169203 := T_169195
    when T_169158 : T_169203 := T_169202
    node T_169204 = and(T_169203, out.ready)
    in[2].ready := T_169204
    wire T_169205 : UInt<3>[3]
    T_169205[0] := UInt<3>(0)
    T_169205[1] := UInt<3>(1)
    T_169205[2] := UInt<3>(2)
    wire T_169206 : UInt<2>[2]
    T_169206[0] := UInt<2>(0)
    T_169206[1] := UInt<2>(1)
    wire T_169207 : UInt<2>[3]
    T_169207[0] := UInt<2>(1)
    T_169207[1] := UInt<2>(2)
    T_169207[2] := UInt<2>(3)
    wire T_169208 : UInt<2>[2]
    T_169208[0] := UInt<2>(2)
    T_169208[1] := UInt<2>(3)
    wire T_169209 : UInt<2>[1]
    T_169209[0] := UInt<2>(3)
    accessor T_169210 = in[T_169160]
    out.valid := T_169210.valid
    wire T_169211 : UInt<3>[3]
    T_169211[0] := UInt<3>(0)
    T_169211[1] := UInt<3>(1)
    T_169211[2] := UInt<3>(2)
    wire T_169212 : UInt<2>[2]
    T_169212[0] := UInt<2>(0)
    T_169212[1] := UInt<2>(1)
    wire T_169213 : UInt<2>[3]
    T_169213[0] := UInt<2>(1)
    T_169213[1] := UInt<2>(2)
    T_169213[2] := UInt<2>(3)
    wire T_169214 : UInt<2>[2]
    T_169214[0] := UInt<2>(2)
    T_169214[1] := UInt<2>(3)
    wire T_169215 : UInt<2>[1]
    T_169215[0] := UInt<2>(3)
    accessor T_169216 = in[T_169160]
    out.bits := T_169216.bits
    chosen := T_169160
    reg T_169217 : UInt<2>
    onreset T_169217 := UInt<2>(0)
    node T_169218 = addw(T_169217, UInt<1>(1))
    
    node T_169219 = and(out.ready, out.valid)
    when T_169219 : 
      
      
      node T_169220 = and(UInt<1>(1), out.bits.payload.is_builtin_type)
      wire T_169221 : UInt<3>[1]
      T_169221[0] := UInt<3>(3)
      node T_169222 = eq(T_169221[0], out.bits.payload.a_type)
      node T_169223 = or(UInt<1>(0), T_169222)
      node T_169224 = and(T_169220, T_169223)
      when T_169224 : 
        T_169217 := T_169218
        
        node T_169225 = eq(T_169158, UInt<1>(0))
        when T_169225 : 
          T_169158 := UInt<1>(1)
          node T_169226 = and(in[0].ready, in[0].valid)
          node T_169227 = and(in[1].ready, in[1].valid)
          node T_169228 = and(in[2].ready, in[2].valid)
          wire T_169229 : UInt<1>[3]
          T_169229[0] := T_169226
          T_169229[1] := T_169227
          T_169229[2] := T_169228
          wire T_169230 : UInt<2>
          T_169230 := UInt<2>(2)
          when T_169229[1] : T_169230 := UInt<1>(1)
          wire T_169231 : UInt<2>
          T_169231 := T_169230
          when T_169229[0] : T_169231 := UInt<1>(0)
          T_169159 := T_169231
      
      node T_169232 = eq(T_169218, UInt<1>(0))
      when T_169232 : T_169158 := UInt<1>(0)
    wire T_169233 : UInt<2>
    T_169233 := UInt<2>(2)
    when in[1].valid : T_169233 := UInt<1>(1)
    wire T_169234 : UInt<2>
    T_169234 := T_169233
    when in[0].valid : T_169234 := UInt<1>(0)
    node T_169235 = gt(UInt<2>(2), last_grant)
    node T_169236 = and(in[2].valid, T_169235)
    wire T_169237 : UInt<2>
    T_169237 := T_169234
    when T_169236 : T_169237 := UInt<2>(2)
    node T_169238 = gt(UInt<1>(1), last_grant)
    node T_169239 = and(in[1].valid, T_169238)
    wire choose : UInt<2>
    choose := T_169237
    when T_169239 : choose := UInt<1>(1)
    wire T_169240 : UInt<2>
    T_169240 := choose
    when T_169158 : T_169240 := T_169159
    T_169160 := T_169240
    
    node T_169241 = and(out.ready, out.valid)
    when T_169241 : last_grant := T_169160
  module LockingRRArbiter_47800 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output chosen : UInt<2>
    
    wire T_169242 : UInt<3>[3]
    T_169242[0] := UInt<3>(0)
    T_169242[1] := UInt<3>(1)
    T_169242[2] := UInt<3>(2)
    wire T_169243 : UInt<2>[2]
    T_169243[0] := UInt<2>(0)
    T_169243[1] := UInt<2>(1)
    wire T_169244 : UInt<2>[3]
    T_169244[0] := UInt<2>(1)
    T_169244[1] := UInt<2>(2)
    T_169244[2] := UInt<2>(3)
    wire T_169245 : UInt<2>[2]
    T_169245[0] := UInt<2>(2)
    T_169245[1] := UInt<2>(3)
    wire T_169246 : UInt<2>[1]
    T_169246[0] := UInt<2>(3)
    wire T_169247 : UInt<3>[3]
    T_169247[0] := UInt<3>(0)
    T_169247[1] := UInt<3>(1)
    T_169247[2] := UInt<3>(2)
    wire T_169248 : UInt<2>[2]
    T_169248[0] := UInt<2>(0)
    T_169248[1] := UInt<2>(1)
    wire T_169249 : UInt<2>[3]
    T_169249[0] := UInt<2>(1)
    T_169249[1] := UInt<2>(2)
    T_169249[2] := UInt<2>(3)
    wire T_169250 : UInt<2>[2]
    T_169250[0] := UInt<2>(2)
    T_169250[1] := UInt<2>(3)
    wire T_169251 : UInt<2>[1]
    T_169251[0] := UInt<2>(3)
    wire T_169252 : UInt<3>[3]
    T_169252[0] := UInt<3>(0)
    T_169252[1] := UInt<3>(1)
    T_169252[2] := UInt<3>(2)
    wire T_169253 : UInt<2>[2]
    T_169253[0] := UInt<2>(0)
    T_169253[1] := UInt<2>(1)
    wire T_169254 : UInt<2>[3]
    T_169254[0] := UInt<2>(1)
    T_169254[1] := UInt<2>(2)
    T_169254[2] := UInt<2>(3)
    wire T_169255 : UInt<2>[2]
    T_169255[0] := UInt<2>(2)
    T_169255[1] := UInt<2>(3)
    wire T_169256 : UInt<2>[1]
    T_169256[0] := UInt<2>(3)
    wire T_169257 : UInt<3>[3]
    T_169257[0] := UInt<3>(0)
    T_169257[1] := UInt<3>(1)
    T_169257[2] := UInt<3>(2)
    wire T_169258 : UInt<2>[2]
    T_169258[0] := UInt<2>(0)
    T_169258[1] := UInt<2>(1)
    wire T_169259 : UInt<2>[3]
    T_169259[0] := UInt<2>(1)
    T_169259[1] := UInt<2>(2)
    T_169259[2] := UInt<2>(3)
    wire T_169260 : UInt<2>[2]
    T_169260[0] := UInt<2>(2)
    T_169260[1] := UInt<2>(3)
    wire T_169261 : UInt<2>[1]
    T_169261[0] := UInt<2>(3)
    wire T_169262 : UInt<3>[3]
    T_169262[0] := UInt<3>(0)
    T_169262[1] := UInt<3>(1)
    T_169262[2] := UInt<3>(2)
    wire T_169263 : UInt<2>[2]
    T_169263[0] := UInt<2>(0)
    T_169263[1] := UInt<2>(1)
    wire T_169264 : UInt<2>[3]
    T_169264[0] := UInt<2>(1)
    T_169264[1] := UInt<2>(2)
    T_169264[2] := UInt<2>(3)
    wire T_169265 : UInt<2>[2]
    T_169265[0] := UInt<2>(2)
    T_169265[1] := UInt<2>(3)
    wire T_169266 : UInt<2>[1]
    T_169266[0] := UInt<2>(3)
    reg T_169267 : UInt<1>
    onreset T_169267 := UInt<1>(0)
    reg T_169268 : UInt<2>
    onreset T_169268 := UInt<2>(2)
    wire T_169269 : UInt<2>
    reg last_grant : UInt<2>
    onreset last_grant := UInt<2>(0)
    node T_169270 = gt(UInt<1>(0), last_grant)
    node T_169271 = and(in[0].valid, T_169270)
    node T_169272 = gt(UInt<1>(1), last_grant)
    node T_169273 = and(in[1].valid, T_169272)
    node T_169274 = gt(UInt<2>(2), last_grant)
    node T_169275 = and(in[2].valid, T_169274)
    node T_169276 = or(UInt<1>(0), T_169271)
    node T_169277 = eq(T_169276, UInt<1>(0))
    node T_169278 = or(UInt<1>(0), T_169271)
    node T_169279 = or(T_169278, T_169273)
    node T_169280 = eq(T_169279, UInt<1>(0))
    node T_169281 = or(UInt<1>(0), T_169271)
    node T_169282 = or(T_169281, T_169273)
    node T_169283 = or(T_169282, T_169275)
    node T_169284 = eq(T_169283, UInt<1>(0))
    node T_169285 = or(UInt<1>(0), T_169271)
    node T_169286 = or(T_169285, T_169273)
    node T_169287 = or(T_169286, T_169275)
    node T_169288 = or(T_169287, in[0].valid)
    node T_169289 = eq(T_169288, UInt<1>(0))
    node T_169290 = or(UInt<1>(0), T_169271)
    node T_169291 = or(T_169290, T_169273)
    node T_169292 = or(T_169291, T_169275)
    node T_169293 = or(T_169292, in[0].valid)
    node T_169294 = or(T_169293, in[1].valid)
    node T_169295 = eq(T_169294, UInt<1>(0))
    node T_169296 = gt(UInt<1>(0), last_grant)
    node T_169297 = and(UInt<1>(1), T_169296)
    node T_169298 = or(T_169297, T_169284)
    node T_169299 = gt(UInt<1>(1), last_grant)
    node T_169300 = and(T_169277, T_169299)
    node T_169301 = or(T_169300, T_169289)
    node T_169302 = gt(UInt<2>(2), last_grant)
    node T_169303 = and(T_169280, T_169302)
    node T_169304 = or(T_169303, T_169295)
    node T_169305 = eq(T_169268, UInt<1>(0))
    wire T_169306 : UInt<1>
    T_169306 := T_169298
    when T_169267 : T_169306 := T_169305
    node T_169307 = and(T_169306, out.ready)
    in[0].ready := T_169307
    node T_169308 = eq(T_169268, UInt<1>(1))
    wire T_169309 : UInt<1>
    T_169309 := T_169301
    when T_169267 : T_169309 := T_169308
    node T_169310 = and(T_169309, out.ready)
    in[1].ready := T_169310
    node T_169311 = eq(T_169268, UInt<2>(2))
    wire T_169312 : UInt<1>
    T_169312 := T_169304
    when T_169267 : T_169312 := T_169311
    node T_169313 = and(T_169312, out.ready)
    in[2].ready := T_169313
    wire T_169314 : UInt<3>[3]
    T_169314[0] := UInt<3>(0)
    T_169314[1] := UInt<3>(1)
    T_169314[2] := UInt<3>(2)
    wire T_169315 : UInt<2>[2]
    T_169315[0] := UInt<2>(0)
    T_169315[1] := UInt<2>(1)
    wire T_169316 : UInt<2>[3]
    T_169316[0] := UInt<2>(1)
    T_169316[1] := UInt<2>(2)
    T_169316[2] := UInt<2>(3)
    wire T_169317 : UInt<2>[2]
    T_169317[0] := UInt<2>(2)
    T_169317[1] := UInt<2>(3)
    wire T_169318 : UInt<2>[1]
    T_169318[0] := UInt<2>(3)
    accessor T_169319 = in[T_169269]
    out.valid := T_169319.valid
    wire T_169320 : UInt<3>[3]
    T_169320[0] := UInt<3>(0)
    T_169320[1] := UInt<3>(1)
    T_169320[2] := UInt<3>(2)
    wire T_169321 : UInt<2>[2]
    T_169321[0] := UInt<2>(0)
    T_169321[1] := UInt<2>(1)
    wire T_169322 : UInt<2>[3]
    T_169322[0] := UInt<2>(1)
    T_169322[1] := UInt<2>(2)
    T_169322[2] := UInt<2>(3)
    wire T_169323 : UInt<2>[2]
    T_169323[0] := UInt<2>(2)
    T_169323[1] := UInt<2>(3)
    wire T_169324 : UInt<2>[1]
    T_169324[0] := UInt<2>(3)
    accessor T_169325 = in[T_169269]
    out.bits := T_169325.bits
    chosen := T_169269
    reg T_169326 : UInt<2>
    onreset T_169326 := UInt<2>(0)
    node T_169327 = addw(T_169326, UInt<1>(1))
    
    node T_169328 = and(out.ready, out.valid)
    when T_169328 : 
      
      
      node T_169329 = eq(T_169262[0], out.bits.payload.r_type)
      node T_169330 = eq(T_169262[1], out.bits.payload.r_type)
      node T_169331 = eq(T_169262[2], out.bits.payload.r_type)
      node T_169332 = or(UInt<1>(0), T_169329)
      node T_169333 = or(T_169332, T_169330)
      node T_169334 = or(T_169333, T_169331)
      node T_169335 = and(UInt<1>(1), T_169334)
      when T_169335 : 
        T_169326 := T_169327
        
        node T_169336 = eq(T_169267, UInt<1>(0))
        when T_169336 : 
          T_169267 := UInt<1>(1)
          node T_169337 = and(in[0].ready, in[0].valid)
          node T_169338 = and(in[1].ready, in[1].valid)
          node T_169339 = and(in[2].ready, in[2].valid)
          wire T_169340 : UInt<1>[3]
          T_169340[0] := T_169337
          T_169340[1] := T_169338
          T_169340[2] := T_169339
          wire T_169341 : UInt<2>
          T_169341 := UInt<2>(2)
          when T_169340[1] : T_169341 := UInt<1>(1)
          wire T_169342 : UInt<2>
          T_169342 := T_169341
          when T_169340[0] : T_169342 := UInt<1>(0)
          T_169268 := T_169342
      
      node T_169343 = eq(T_169327, UInt<1>(0))
      when T_169343 : T_169267 := UInt<1>(0)
    wire T_169344 : UInt<2>
    T_169344 := UInt<2>(2)
    when in[1].valid : T_169344 := UInt<1>(1)
    wire T_169345 : UInt<2>
    T_169345 := T_169344
    when in[0].valid : T_169345 := UInt<1>(0)
    node T_169346 = gt(UInt<2>(2), last_grant)
    node T_169347 = and(in[2].valid, T_169346)
    wire T_169348 : UInt<2>
    T_169348 := T_169345
    when T_169347 : T_169348 := UInt<2>(2)
    node T_169349 = gt(UInt<1>(1), last_grant)
    node T_169350 = and(in[1].valid, T_169349)
    wire choose : UInt<2>
    choose := T_169348
    when T_169350 : choose := UInt<1>(1)
    wire T_169351 : UInt<2>
    T_169351 := choose
    when T_169267 : T_169351 := T_169268
    T_169269 := T_169351
    
    node T_169352 = and(out.ready, out.valid)
    when T_169352 : last_grant := T_169269
  module RRArbiter : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<2>}}}
    output chosen : UInt<2>
    
    wire T_169353 : UInt<3>[3]
    T_169353[0] := UInt<3>(0)
    T_169353[1] := UInt<3>(1)
    T_169353[2] := UInt<3>(2)
    wire T_169354 : UInt<2>[2]
    T_169354[0] := UInt<2>(0)
    T_169354[1] := UInt<2>(1)
    wire T_169355 : UInt<2>[3]
    T_169355[0] := UInt<2>(1)
    T_169355[1] := UInt<2>(2)
    T_169355[2] := UInt<2>(3)
    wire T_169356 : UInt<2>[2]
    T_169356[0] := UInt<2>(2)
    T_169356[1] := UInt<2>(3)
    wire T_169357 : UInt<2>[1]
    T_169357[0] := UInt<2>(3)
    wire T_169358 : UInt<3>[3]
    T_169358[0] := UInt<3>(0)
    T_169358[1] := UInt<3>(1)
    T_169358[2] := UInt<3>(2)
    wire T_169359 : UInt<2>[2]
    T_169359[0] := UInt<2>(0)
    T_169359[1] := UInt<2>(1)
    wire T_169360 : UInt<2>[3]
    T_169360[0] := UInt<2>(1)
    T_169360[1] := UInt<2>(2)
    T_169360[2] := UInt<2>(3)
    wire T_169361 : UInt<2>[2]
    T_169361[0] := UInt<2>(2)
    T_169361[1] := UInt<2>(3)
    wire T_169362 : UInt<2>[1]
    T_169362[0] := UInt<2>(3)
    wire T_169363 : UInt<3>[3]
    T_169363[0] := UInt<3>(0)
    T_169363[1] := UInt<3>(1)
    T_169363[2] := UInt<3>(2)
    wire T_169364 : UInt<2>[2]
    T_169364[0] := UInt<2>(0)
    T_169364[1] := UInt<2>(1)
    wire T_169365 : UInt<2>[3]
    T_169365[0] := UInt<2>(1)
    T_169365[1] := UInt<2>(2)
    T_169365[2] := UInt<2>(3)
    wire T_169366 : UInt<2>[2]
    T_169366[0] := UInt<2>(2)
    T_169366[1] := UInt<2>(3)
    wire T_169367 : UInt<2>[1]
    T_169367[0] := UInt<2>(3)
    wire T_169368 : UInt<3>[3]
    T_169368[0] := UInt<3>(0)
    T_169368[1] := UInt<3>(1)
    T_169368[2] := UInt<3>(2)
    wire T_169369 : UInt<2>[2]
    T_169369[0] := UInt<2>(0)
    T_169369[1] := UInt<2>(1)
    wire T_169370 : UInt<2>[3]
    T_169370[0] := UInt<2>(1)
    T_169370[1] := UInt<2>(2)
    T_169370[2] := UInt<2>(3)
    wire T_169371 : UInt<2>[2]
    T_169371[0] := UInt<2>(2)
    T_169371[1] := UInt<2>(3)
    wire T_169372 : UInt<2>[1]
    T_169372[0] := UInt<2>(3)
    wire T_169373 : UInt<3>[3]
    T_169373[0] := UInt<3>(0)
    T_169373[1] := UInt<3>(1)
    T_169373[2] := UInt<3>(2)
    wire T_169374 : UInt<2>[2]
    T_169374[0] := UInt<2>(0)
    T_169374[1] := UInt<2>(1)
    wire T_169375 : UInt<2>[3]
    T_169375[0] := UInt<2>(1)
    T_169375[1] := UInt<2>(2)
    T_169375[2] := UInt<2>(3)
    wire T_169376 : UInt<2>[2]
    T_169376[0] := UInt<2>(2)
    T_169376[1] := UInt<2>(3)
    wire T_169377 : UInt<2>[1]
    T_169377[0] := UInt<2>(3)
    wire T_169378 : UInt<2>
    reg T_169379 : UInt<2>
    onreset T_169379 := UInt<2>(0)
    node T_169380 = gt(UInt<1>(0), T_169379)
    node T_169381 = and(in[0].valid, T_169380)
    node T_169382 = gt(UInt<1>(1), T_169379)
    node T_169383 = and(in[1].valid, T_169382)
    node T_169384 = gt(UInt<2>(2), T_169379)
    node T_169385 = and(in[2].valid, T_169384)
    node T_169386 = or(UInt<1>(0), T_169381)
    node T_169387 = eq(T_169386, UInt<1>(0))
    node T_169388 = or(UInt<1>(0), T_169381)
    node T_169389 = or(T_169388, T_169383)
    node T_169390 = eq(T_169389, UInt<1>(0))
    node T_169391 = or(UInt<1>(0), T_169381)
    node T_169392 = or(T_169391, T_169383)
    node T_169393 = or(T_169392, T_169385)
    node T_169394 = eq(T_169393, UInt<1>(0))
    node T_169395 = or(UInt<1>(0), T_169381)
    node T_169396 = or(T_169395, T_169383)
    node T_169397 = or(T_169396, T_169385)
    node T_169398 = or(T_169397, in[0].valid)
    node T_169399 = eq(T_169398, UInt<1>(0))
    node T_169400 = or(UInt<1>(0), T_169381)
    node T_169401 = or(T_169400, T_169383)
    node T_169402 = or(T_169401, T_169385)
    node T_169403 = or(T_169402, in[0].valid)
    node T_169404 = or(T_169403, in[1].valid)
    node T_169405 = eq(T_169404, UInt<1>(0))
    node T_169406 = gt(UInt<1>(0), T_169379)
    node T_169407 = and(UInt<1>(1), T_169406)
    node T_169408 = or(T_169407, T_169394)
    node T_169409 = gt(UInt<1>(1), T_169379)
    node T_169410 = and(T_169387, T_169409)
    node T_169411 = or(T_169410, T_169399)
    node T_169412 = gt(UInt<2>(2), T_169379)
    node T_169413 = and(T_169390, T_169412)
    node T_169414 = or(T_169413, T_169405)
    node T_169415 = eq(UInt<2>(2), UInt<1>(0))
    wire T_169416 : UInt<1>
    T_169416 := T_169408
    when UInt<1>(0) : T_169416 := T_169415
    node T_169417 = and(T_169416, out.ready)
    in[0].ready := T_169417
    node T_169418 = eq(UInt<2>(2), UInt<1>(1))
    wire T_169419 : UInt<1>
    T_169419 := T_169411
    when UInt<1>(0) : T_169419 := T_169418
    node T_169420 = and(T_169419, out.ready)
    in[1].ready := T_169420
    node T_169421 = eq(UInt<2>(2), UInt<2>(2))
    wire T_169422 : UInt<1>
    T_169422 := T_169414
    when UInt<1>(0) : T_169422 := T_169421
    node T_169423 = and(T_169422, out.ready)
    in[2].ready := T_169423
    wire T_169424 : UInt<3>[3]
    T_169424[0] := UInt<3>(0)
    T_169424[1] := UInt<3>(1)
    T_169424[2] := UInt<3>(2)
    wire T_169425 : UInt<2>[2]
    T_169425[0] := UInt<2>(0)
    T_169425[1] := UInt<2>(1)
    wire T_169426 : UInt<2>[3]
    T_169426[0] := UInt<2>(1)
    T_169426[1] := UInt<2>(2)
    T_169426[2] := UInt<2>(3)
    wire T_169427 : UInt<2>[2]
    T_169427[0] := UInt<2>(2)
    T_169427[1] := UInt<2>(3)
    wire T_169428 : UInt<2>[1]
    T_169428[0] := UInt<2>(3)
    accessor T_169429 = in[T_169378]
    out.valid := T_169429.valid
    wire T_169430 : UInt<3>[3]
    T_169430[0] := UInt<3>(0)
    T_169430[1] := UInt<3>(1)
    T_169430[2] := UInt<3>(2)
    wire T_169431 : UInt<2>[2]
    T_169431[0] := UInt<2>(0)
    T_169431[1] := UInt<2>(1)
    wire T_169432 : UInt<2>[3]
    T_169432[0] := UInt<2>(1)
    T_169432[1] := UInt<2>(2)
    T_169432[2] := UInt<2>(3)
    wire T_169433 : UInt<2>[2]
    T_169433[0] := UInt<2>(2)
    T_169433[1] := UInt<2>(3)
    wire T_169434 : UInt<2>[1]
    T_169434[0] := UInt<2>(3)
    accessor T_169435 = in[T_169378]
    out.bits := T_169435.bits
    chosen := T_169378
    wire T_169436 : UInt<2>
    T_169436 := UInt<2>(2)
    when in[1].valid : T_169436 := UInt<1>(1)
    wire T_169437 : UInt<2>
    T_169437 := T_169436
    when in[0].valid : T_169437 := UInt<1>(0)
    node T_169438 = gt(UInt<2>(2), T_169379)
    node T_169439 = and(in[2].valid, T_169438)
    wire T_169440 : UInt<2>
    T_169440 := T_169437
    when T_169439 : T_169440 := UInt<2>(2)
    node T_169441 = gt(UInt<1>(1), T_169379)
    node T_169442 = and(in[1].valid, T_169441)
    wire T_169443 : UInt<2>
    T_169443 := T_169440
    when T_169442 : T_169443 := UInt<1>(1)
    wire T_169444 : UInt<2>
    T_169444 := T_169443
    when UInt<1>(0) : T_169444 := UInt<2>(2)
    T_169378 := T_169444
    
    node T_169445 = and(out.ready, out.valid)
    when T_169445 : T_169379 := T_169378
  module RocketChipTileLinkArbiter : 
    input clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3]
    input managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}[1]
    
    wire T_169446 : UInt<3>[3]
    T_169446[0] := UInt<3>(0)
    T_169446[1] := UInt<3>(1)
    T_169446[2] := UInt<3>(2)
    wire T_169447 : UInt<2>[2]
    T_169447[0] := UInt<2>(0)
    T_169447[1] := UInt<2>(1)
    wire T_169448 : UInt<2>[3]
    T_169448[0] := UInt<2>(1)
    T_169448[1] := UInt<2>(2)
    T_169448[2] := UInt<2>(3)
    wire T_169449 : UInt<2>[2]
    T_169449[0] := UInt<2>(2)
    T_169449[1] := UInt<2>(3)
    wire T_169450 : UInt<2>[1]
    T_169450[0] := UInt<2>(3)
    wire T_169451 : UInt<3>[3]
    T_169451[0] := UInt<3>(0)
    T_169451[1] := UInt<3>(1)
    T_169451[2] := UInt<3>(2)
    wire T_169452 : UInt<2>[2]
    T_169452[0] := UInt<2>(0)
    T_169452[1] := UInt<2>(1)
    wire T_169453 : UInt<2>[3]
    T_169453[0] := UInt<2>(1)
    T_169453[1] := UInt<2>(2)
    T_169453[2] := UInt<2>(3)
    wire T_169454 : UInt<2>[2]
    T_169454[0] := UInt<2>(2)
    T_169454[1] := UInt<2>(3)
    wire T_169455 : UInt<2>[1]
    T_169455[0] := UInt<2>(3)
    wire T_169456 : UInt<3>[3]
    T_169456[0] := UInt<3>(0)
    T_169456[1] := UInt<3>(1)
    T_169456[2] := UInt<3>(2)
    wire T_169457 : UInt<2>[2]
    T_169457[0] := UInt<2>(0)
    T_169457[1] := UInt<2>(1)
    wire T_169458 : UInt<2>[3]
    T_169458[0] := UInt<2>(1)
    T_169458[1] := UInt<2>(2)
    T_169458[2] := UInt<2>(3)
    wire T_169459 : UInt<2>[2]
    T_169459[0] := UInt<2>(2)
    T_169459[1] := UInt<2>(3)
    wire T_169460 : UInt<2>[1]
    T_169460[0] := UInt<2>(3)
    wire T_169461 : UInt<3>[3]
    T_169461[0] := UInt<3>(0)
    T_169461[1] := UInt<3>(1)
    T_169461[2] := UInt<3>(2)
    wire T_169462 : UInt<2>[2]
    T_169462[0] := UInt<2>(0)
    T_169462[1] := UInt<2>(1)
    wire T_169463 : UInt<2>[3]
    T_169463[0] := UInt<2>(1)
    T_169463[1] := UInt<2>(2)
    T_169463[2] := UInt<2>(3)
    wire T_169464 : UInt<2>[2]
    T_169464[0] := UInt<2>(2)
    T_169464[1] := UInt<2>(3)
    wire T_169465 : UInt<2>[1]
    T_169465[0] := UInt<2>(3)
    wire T_169466 : UInt<3>[3]
    T_169466[0] := UInt<3>(0)
    T_169466[1] := UInt<3>(1)
    T_169466[2] := UInt<3>(2)
    wire T_169467 : UInt<2>[2]
    T_169467[0] := UInt<2>(0)
    T_169467[1] := UInt<2>(1)
    wire T_169468 : UInt<2>[3]
    T_169468[0] := UInt<2>(1)
    T_169468[1] := UInt<2>(2)
    T_169468[2] := UInt<2>(3)
    wire T_169469 : UInt<2>[2]
    T_169469[0] := UInt<2>(2)
    T_169469[1] := UInt<2>(3)
    wire T_169470 : UInt<2>[1]
    T_169470[0] := UInt<2>(3)
    wire T_169471 : UInt<3>[3]
    T_169471[0] := UInt<3>(0)
    T_169471[1] := UInt<3>(1)
    T_169471[2] := UInt<3>(2)
    wire T_169472 : UInt<2>[2]
    T_169472[0] := UInt<2>(0)
    T_169472[1] := UInt<2>(1)
    wire T_169473 : UInt<2>[3]
    T_169473[0] := UInt<2>(1)
    T_169473[1] := UInt<2>(2)
    T_169473[2] := UInt<2>(3)
    wire T_169474 : UInt<2>[2]
    T_169474[0] := UInt<2>(2)
    T_169474[1] := UInt<2>(3)
    wire T_169475 : UInt<2>[1]
    T_169475[0] := UInt<2>(3)
    wire T_169476 : UInt<3>[3]
    T_169476[0] := UInt<3>(0)
    T_169476[1] := UInt<3>(1)
    T_169476[2] := UInt<3>(2)
    wire T_169477 : UInt<2>[2]
    T_169477[0] := UInt<2>(0)
    T_169477[1] := UInt<2>(1)
    wire T_169478 : UInt<2>[3]
    T_169478[0] := UInt<2>(1)
    T_169478[1] := UInt<2>(2)
    T_169478[2] := UInt<2>(3)
    wire T_169479 : UInt<2>[2]
    T_169479[0] := UInt<2>(2)
    T_169479[1] := UInt<2>(3)
    wire T_169480 : UInt<2>[1]
    T_169480[0] := UInt<2>(3)
    wire T_169481 : UInt<3>[3]
    T_169481[0] := UInt<3>(0)
    T_169481[1] := UInt<3>(1)
    T_169481[2] := UInt<3>(2)
    wire T_169482 : UInt<2>[2]
    T_169482[0] := UInt<2>(0)
    T_169482[1] := UInt<2>(1)
    wire T_169483 : UInt<2>[3]
    T_169483[0] := UInt<2>(1)
    T_169483[1] := UInt<2>(2)
    T_169483[2] := UInt<2>(3)
    wire T_169484 : UInt<2>[2]
    T_169484[0] := UInt<2>(2)
    T_169484[1] := UInt<2>(3)
    wire T_169485 : UInt<2>[1]
    T_169485[0] := UInt<2>(3)
    wire T_169486 : UInt<3>[3]
    T_169486[0] := UInt<3>(0)
    T_169486[1] := UInt<3>(1)
    T_169486[2] := UInt<3>(2)
    wire T_169487 : UInt<2>[2]
    T_169487[0] := UInt<2>(0)
    T_169487[1] := UInt<2>(1)
    wire T_169488 : UInt<2>[3]
    T_169488[0] := UInt<2>(1)
    T_169488[1] := UInt<2>(2)
    T_169488[2] := UInt<2>(3)
    wire T_169489 : UInt<2>[2]
    T_169489[0] := UInt<2>(2)
    T_169489[1] := UInt<2>(3)
    wire T_169490 : UInt<2>[1]
    T_169490[0] := UInt<2>(3)
    wire T_169491 : UInt<3>[3]
    T_169491[0] := UInt<3>(0)
    T_169491[1] := UInt<3>(1)
    T_169491[2] := UInt<3>(2)
    wire T_169492 : UInt<2>[2]
    T_169492[0] := UInt<2>(0)
    T_169492[1] := UInt<2>(1)
    wire T_169493 : UInt<2>[3]
    T_169493[0] := UInt<2>(1)
    T_169493[1] := UInt<2>(2)
    T_169493[2] := UInt<2>(3)
    wire T_169494 : UInt<2>[2]
    T_169494[0] := UInt<2>(2)
    T_169494[1] := UInt<2>(3)
    wire T_169495 : UInt<2>[1]
    T_169495[0] := UInt<2>(3)
    wire T_169496 : UInt<3>[3]
    T_169496[0] := UInt<3>(0)
    T_169496[1] := UInt<3>(1)
    T_169496[2] := UInt<3>(2)
    wire T_169497 : UInt<2>[2]
    T_169497[0] := UInt<2>(0)
    T_169497[1] := UInt<2>(1)
    wire T_169498 : UInt<2>[3]
    T_169498[0] := UInt<2>(1)
    T_169498[1] := UInt<2>(2)
    T_169498[2] := UInt<2>(3)
    wire T_169499 : UInt<2>[2]
    T_169499[0] := UInt<2>(2)
    T_169499[1] := UInt<2>(3)
    wire T_169500 : UInt<2>[1]
    T_169500[0] := UInt<2>(3)
    wire T_169501 : UInt<3>[3]
    T_169501[0] := UInt<3>(0)
    T_169501[1] := UInt<3>(1)
    T_169501[2] := UInt<3>(2)
    wire T_169502 : UInt<2>[2]
    T_169502[0] := UInt<2>(0)
    T_169502[1] := UInt<2>(1)
    wire T_169503 : UInt<2>[3]
    T_169503[0] := UInt<2>(1)
    T_169503[1] := UInt<2>(2)
    T_169503[2] := UInt<2>(3)
    wire T_169504 : UInt<2>[2]
    T_169504[0] := UInt<2>(2)
    T_169504[1] := UInt<2>(3)
    wire T_169505 : UInt<2>[1]
    T_169505[0] := UInt<2>(3)
    wire T_169506 : UInt<3>[3]
    T_169506[0] := UInt<3>(0)
    T_169506[1] := UInt<3>(1)
    T_169506[2] := UInt<3>(2)
    wire T_169507 : UInt<2>[2]
    T_169507[0] := UInt<2>(0)
    T_169507[1] := UInt<2>(1)
    wire T_169508 : UInt<2>[3]
    T_169508[0] := UInt<2>(1)
    T_169508[1] := UInt<2>(2)
    T_169508[2] := UInt<2>(3)
    wire T_169509 : UInt<2>[2]
    T_169509[0] := UInt<2>(2)
    T_169509[1] := UInt<2>(3)
    wire T_169510 : UInt<2>[1]
    T_169510[0] := UInt<2>(3)
    wire T_169511 : UInt<3>[3]
    T_169511[0] := UInt<3>(0)
    T_169511[1] := UInt<3>(1)
    T_169511[2] := UInt<3>(2)
    wire T_169512 : UInt<2>[2]
    T_169512[0] := UInt<2>(0)
    T_169512[1] := UInt<2>(1)
    wire T_169513 : UInt<2>[3]
    T_169513[0] := UInt<2>(1)
    T_169513[1] := UInt<2>(2)
    T_169513[2] := UInt<2>(3)
    wire T_169514 : UInt<2>[2]
    T_169514[0] := UInt<2>(2)
    T_169514[1] := UInt<2>(3)
    wire T_169515 : UInt<2>[1]
    T_169515[0] := UInt<2>(3)
    wire T_169516 : UInt<3>[3]
    T_169516[0] := UInt<3>(0)
    T_169516[1] := UInt<3>(1)
    T_169516[2] := UInt<3>(2)
    wire T_169517 : UInt<2>[2]
    T_169517[0] := UInt<2>(0)
    T_169517[1] := UInt<2>(1)
    wire T_169518 : UInt<2>[3]
    T_169518[0] := UInt<2>(1)
    T_169518[1] := UInt<2>(2)
    T_169518[2] := UInt<2>(3)
    wire T_169519 : UInt<2>[2]
    T_169519[0] := UInt<2>(2)
    T_169519[1] := UInt<2>(3)
    wire T_169520 : UInt<2>[1]
    T_169520[0] := UInt<2>(3)
    wire T_169521 : UInt<3>[3]
    T_169521[0] := UInt<3>(0)
    T_169521[1] := UInt<3>(1)
    T_169521[2] := UInt<3>(2)
    wire T_169522 : UInt<2>[2]
    T_169522[0] := UInt<2>(0)
    T_169522[1] := UInt<2>(1)
    wire T_169523 : UInt<2>[3]
    T_169523[0] := UInt<2>(1)
    T_169523[1] := UInt<2>(2)
    T_169523[2] := UInt<2>(3)
    wire T_169524 : UInt<2>[2]
    T_169524[0] := UInt<2>(2)
    T_169524[1] := UInt<2>(3)
    wire T_169525 : UInt<2>[1]
    T_169525[0] := UInt<2>(3)
    wire T_169526 : UInt<3>[3]
    T_169526[0] := UInt<3>(0)
    T_169526[1] := UInt<3>(1)
    T_169526[2] := UInt<3>(2)
    wire T_169527 : UInt<2>[2]
    T_169527[0] := UInt<2>(0)
    T_169527[1] := UInt<2>(1)
    wire T_169528 : UInt<2>[3]
    T_169528[0] := UInt<2>(1)
    T_169528[1] := UInt<2>(2)
    T_169528[2] := UInt<2>(3)
    wire T_169529 : UInt<2>[2]
    T_169529[0] := UInt<2>(2)
    T_169529[1] := UInt<2>(3)
    wire T_169530 : UInt<2>[1]
    T_169530[0] := UInt<2>(3)
    wire T_169531 : UInt<3>[3]
    T_169531[0] := UInt<3>(0)
    T_169531[1] := UInt<3>(1)
    T_169531[2] := UInt<3>(2)
    wire T_169532 : UInt<2>[2]
    T_169532[0] := UInt<2>(0)
    T_169532[1] := UInt<2>(1)
    wire T_169533 : UInt<2>[3]
    T_169533[0] := UInt<2>(1)
    T_169533[1] := UInt<2>(2)
    T_169533[2] := UInt<2>(3)
    wire T_169534 : UInt<2>[2]
    T_169534[0] := UInt<2>(2)
    T_169534[1] := UInt<2>(3)
    wire T_169535 : UInt<2>[1]
    T_169535[0] := UInt<2>(3)
    wire T_169536 : UInt<3>[3]
    T_169536[0] := UInt<3>(0)
    T_169536[1] := UInt<3>(1)
    T_169536[2] := UInt<3>(2)
    wire T_169537 : UInt<2>[2]
    T_169537[0] := UInt<2>(0)
    T_169537[1] := UInt<2>(1)
    wire T_169538 : UInt<2>[3]
    T_169538[0] := UInt<2>(1)
    T_169538[1] := UInt<2>(2)
    T_169538[2] := UInt<2>(3)
    wire T_169539 : UInt<2>[2]
    T_169539[0] := UInt<2>(2)
    T_169539[1] := UInt<2>(3)
    wire T_169540 : UInt<2>[1]
    T_169540[0] := UInt<2>(3)
    wire T_169541 : UInt<3>[3]
    T_169541[0] := UInt<3>(0)
    T_169541[1] := UInt<3>(1)
    T_169541[2] := UInt<3>(2)
    wire T_169542 : UInt<2>[2]
    T_169542[0] := UInt<2>(0)
    T_169542[1] := UInt<2>(1)
    wire T_169543 : UInt<2>[3]
    T_169543[0] := UInt<2>(1)
    T_169543[1] := UInt<2>(2)
    T_169543[2] := UInt<2>(3)
    wire T_169544 : UInt<2>[2]
    T_169544[0] := UInt<2>(2)
    T_169544[1] := UInt<2>(3)
    wire T_169545 : UInt<2>[1]
    T_169545[0] := UInt<2>(3)
    wire T_169546 : UInt<3>[3]
    T_169546[0] := UInt<3>(0)
    T_169546[1] := UInt<3>(1)
    T_169546[2] := UInt<3>(2)
    wire T_169547 : UInt<2>[2]
    T_169547[0] := UInt<2>(0)
    T_169547[1] := UInt<2>(1)
    wire T_169548 : UInt<2>[3]
    T_169548[0] := UInt<2>(1)
    T_169548[1] := UInt<2>(2)
    T_169548[2] := UInt<2>(3)
    wire T_169549 : UInt<2>[2]
    T_169549[0] := UInt<2>(2)
    T_169549[1] := UInt<2>(3)
    wire T_169550 : UInt<2>[1]
    T_169550[0] := UInt<2>(3)
    wire T_169551 : UInt<3>[3]
    T_169551[0] := UInt<3>(0)
    T_169551[1] := UInt<3>(1)
    T_169551[2] := UInt<3>(2)
    wire T_169552 : UInt<2>[2]
    T_169552[0] := UInt<2>(0)
    T_169552[1] := UInt<2>(1)
    wire T_169553 : UInt<2>[3]
    T_169553[0] := UInt<2>(1)
    T_169553[1] := UInt<2>(2)
    T_169553[2] := UInt<2>(3)
    wire T_169554 : UInt<2>[2]
    T_169554[0] := UInt<2>(2)
    T_169554[1] := UInt<2>(3)
    wire T_169555 : UInt<2>[1]
    T_169555[0] := UInt<2>(3)
    wire T_169556 : UInt<3>[3]
    T_169556[0] := UInt<3>(0)
    T_169556[1] := UInt<3>(1)
    T_169556[2] := UInt<3>(2)
    wire T_169557 : UInt<2>[2]
    T_169557[0] := UInt<2>(0)
    T_169557[1] := UInt<2>(1)
    wire T_169558 : UInt<2>[3]
    T_169558[0] := UInt<2>(1)
    T_169558[1] := UInt<2>(2)
    T_169558[2] := UInt<2>(3)
    wire T_169559 : UInt<2>[2]
    T_169559[0] := UInt<2>(2)
    T_169559[1] := UInt<2>(3)
    wire T_169560 : UInt<2>[1]
    T_169560[0] := UInt<2>(3)
    wire T_169561 : UInt<3>[3]
    T_169561[0] := UInt<3>(0)
    T_169561[1] := UInt<3>(1)
    T_169561[2] := UInt<3>(2)
    wire T_169562 : UInt<2>[2]
    T_169562[0] := UInt<2>(0)
    T_169562[1] := UInt<2>(1)
    wire T_169563 : UInt<2>[3]
    T_169563[0] := UInt<2>(1)
    T_169563[1] := UInt<2>(2)
    T_169563[2] := UInt<2>(3)
    wire T_169564 : UInt<2>[2]
    T_169564[0] := UInt<2>(2)
    T_169564[1] := UInt<2>(3)
    wire T_169565 : UInt<2>[1]
    T_169565[0] := UInt<2>(3)
    wire T_169566 : UInt<3>[3]
    T_169566[0] := UInt<3>(0)
    T_169566[1] := UInt<3>(1)
    T_169566[2] := UInt<3>(2)
    wire T_169567 : UInt<2>[2]
    T_169567[0] := UInt<2>(0)
    T_169567[1] := UInt<2>(1)
    wire T_169568 : UInt<2>[3]
    T_169568[0] := UInt<2>(1)
    T_169568[1] := UInt<2>(2)
    T_169568[2] := UInt<2>(3)
    wire T_169569 : UInt<2>[2]
    T_169569[0] := UInt<2>(2)
    T_169569[1] := UInt<2>(3)
    wire T_169570 : UInt<2>[1]
    T_169570[0] := UInt<2>(3)
    wire T_169571 : UInt<3>[3]
    T_169571[0] := UInt<3>(0)
    T_169571[1] := UInt<3>(1)
    T_169571[2] := UInt<3>(2)
    wire T_169572 : UInt<2>[2]
    T_169572[0] := UInt<2>(0)
    T_169572[1] := UInt<2>(1)
    wire T_169573 : UInt<2>[3]
    T_169573[0] := UInt<2>(1)
    T_169573[1] := UInt<2>(2)
    T_169573[2] := UInt<2>(3)
    wire T_169574 : UInt<2>[2]
    T_169574[0] := UInt<2>(2)
    T_169574[1] := UInt<2>(3)
    wire T_169575 : UInt<2>[1]
    T_169575[0] := UInt<2>(3)
    wire T_169576 : UInt<3>[3]
    T_169576[0] := UInt<3>(0)
    T_169576[1] := UInt<3>(1)
    T_169576[2] := UInt<3>(2)
    wire T_169577 : UInt<2>[2]
    T_169577[0] := UInt<2>(0)
    T_169577[1] := UInt<2>(1)
    wire T_169578 : UInt<2>[3]
    T_169578[0] := UInt<2>(1)
    T_169578[1] := UInt<2>(2)
    T_169578[2] := UInt<2>(3)
    wire T_169579 : UInt<2>[2]
    T_169579[0] := UInt<2>(2)
    T_169579[1] := UInt<2>(3)
    wire T_169580 : UInt<2>[1]
    T_169580[0] := UInt<2>(3)
    wire T_169581 : UInt<3>[3]
    T_169581[0] := UInt<3>(0)
    T_169581[1] := UInt<3>(1)
    T_169581[2] := UInt<3>(2)
    wire T_169582 : UInt<2>[2]
    T_169582[0] := UInt<2>(0)
    T_169582[1] := UInt<2>(1)
    wire T_169583 : UInt<2>[3]
    T_169583[0] := UInt<2>(1)
    T_169583[1] := UInt<2>(2)
    T_169583[2] := UInt<2>(3)
    wire T_169584 : UInt<2>[2]
    T_169584[0] := UInt<2>(2)
    T_169584[1] := UInt<2>(3)
    wire T_169585 : UInt<2>[1]
    T_169585[0] := UInt<2>(3)
    wire T_169586 : UInt<3>[3]
    T_169586[0] := UInt<3>(0)
    T_169586[1] := UInt<3>(1)
    T_169586[2] := UInt<3>(2)
    wire T_169587 : UInt<2>[2]
    T_169587[0] := UInt<2>(0)
    T_169587[1] := UInt<2>(1)
    wire T_169588 : UInt<2>[3]
    T_169588[0] := UInt<2>(1)
    T_169588[1] := UInt<2>(2)
    T_169588[2] := UInt<2>(3)
    wire T_169589 : UInt<2>[2]
    T_169589[0] := UInt<2>(2)
    T_169589[1] := UInt<2>(3)
    wire T_169590 : UInt<2>[1]
    T_169590[0] := UInt<2>(3)
    wire T_169591 : UInt<3>[3]
    T_169591[0] := UInt<3>(0)
    T_169591[1] := UInt<3>(1)
    T_169591[2] := UInt<3>(2)
    wire T_169592 : UInt<2>[2]
    T_169592[0] := UInt<2>(0)
    T_169592[1] := UInt<2>(1)
    wire T_169593 : UInt<2>[3]
    T_169593[0] := UInt<2>(1)
    T_169593[1] := UInt<2>(2)
    T_169593[2] := UInt<2>(3)
    wire T_169594 : UInt<2>[2]
    T_169594[0] := UInt<2>(2)
    T_169594[1] := UInt<2>(3)
    wire T_169595 : UInt<2>[1]
    T_169595[0] := UInt<2>(3)
    wire T_169596 : UInt<3>[3]
    T_169596[0] := UInt<3>(0)
    T_169596[1] := UInt<3>(1)
    T_169596[2] := UInt<3>(2)
    wire T_169597 : UInt<2>[2]
    T_169597[0] := UInt<2>(0)
    T_169597[1] := UInt<2>(1)
    wire T_169598 : UInt<2>[3]
    T_169598[0] := UInt<2>(1)
    T_169598[1] := UInt<2>(2)
    T_169598[2] := UInt<2>(3)
    wire T_169599 : UInt<2>[2]
    T_169599[0] := UInt<2>(2)
    T_169599[1] := UInt<2>(3)
    wire T_169600 : UInt<2>[1]
    T_169600[0] := UInt<2>(3)
    wire T_169601 : UInt<3>[3]
    T_169601[0] := UInt<3>(0)
    T_169601[1] := UInt<3>(1)
    T_169601[2] := UInt<3>(2)
    wire T_169602 : UInt<2>[2]
    T_169602[0] := UInt<2>(0)
    T_169602[1] := UInt<2>(1)
    wire T_169603 : UInt<2>[3]
    T_169603[0] := UInt<2>(1)
    T_169603[1] := UInt<2>(2)
    T_169603[2] := UInt<2>(3)
    wire T_169604 : UInt<2>[2]
    T_169604[0] := UInt<2>(2)
    T_169604[1] := UInt<2>(3)
    wire T_169605 : UInt<2>[1]
    T_169605[0] := UInt<2>(3)
    wire T_169606 : UInt<3>[3]
    T_169606[0] := UInt<3>(0)
    T_169606[1] := UInt<3>(1)
    T_169606[2] := UInt<3>(2)
    wire T_169607 : UInt<2>[2]
    T_169607[0] := UInt<2>(0)
    T_169607[1] := UInt<2>(1)
    wire T_169608 : UInt<2>[3]
    T_169608[0] := UInt<2>(1)
    T_169608[1] := UInt<2>(2)
    T_169608[2] := UInt<2>(3)
    wire T_169609 : UInt<2>[2]
    T_169609[0] := UInt<2>(2)
    T_169609[1] := UInt<2>(3)
    wire T_169610 : UInt<2>[1]
    T_169610[0] := UInt<2>(3)
    wire T_169611 : UInt<3>[3]
    T_169611[0] := UInt<3>(0)
    T_169611[1] := UInt<3>(1)
    T_169611[2] := UInt<3>(2)
    wire T_169612 : UInt<2>[2]
    T_169612[0] := UInt<2>(0)
    T_169612[1] := UInt<2>(1)
    wire T_169613 : UInt<2>[3]
    T_169613[0] := UInt<2>(1)
    T_169613[1] := UInt<2>(2)
    T_169613[2] := UInt<2>(3)
    wire T_169614 : UInt<2>[2]
    T_169614[0] := UInt<2>(2)
    T_169614[1] := UInt<2>(3)
    wire T_169615 : UInt<2>[1]
    T_169615[0] := UInt<2>(3)
    wire T_169616 : UInt<3>[3]
    T_169616[0] := UInt<3>(0)
    T_169616[1] := UInt<3>(1)
    T_169616[2] := UInt<3>(2)
    wire T_169617 : UInt<2>[2]
    T_169617[0] := UInt<2>(0)
    T_169617[1] := UInt<2>(1)
    wire T_169618 : UInt<2>[3]
    T_169618[0] := UInt<2>(1)
    T_169618[1] := UInt<2>(2)
    T_169618[2] := UInt<2>(3)
    wire T_169619 : UInt<2>[2]
    T_169619[0] := UInt<2>(2)
    T_169619[1] := UInt<2>(3)
    wire T_169620 : UInt<2>[1]
    T_169620[0] := UInt<2>(3)
    wire T_169621 : UInt<3>[3]
    T_169621[0] := UInt<3>(0)
    T_169621[1] := UInt<3>(1)
    T_169621[2] := UInt<3>(2)
    wire T_169622 : UInt<2>[2]
    T_169622[0] := UInt<2>(0)
    T_169622[1] := UInt<2>(1)
    wire T_169623 : UInt<2>[3]
    T_169623[0] := UInt<2>(1)
    T_169623[1] := UInt<2>(2)
    T_169623[2] := UInt<2>(3)
    wire T_169624 : UInt<2>[2]
    T_169624[0] := UInt<2>(2)
    T_169624[1] := UInt<2>(3)
    wire T_169625 : UInt<2>[1]
    T_169625[0] := UInt<2>(3)
    wire T_169626 : UInt<3>[3]
    T_169626[0] := UInt<3>(0)
    T_169626[1] := UInt<3>(1)
    T_169626[2] := UInt<3>(2)
    wire T_169627 : UInt<2>[2]
    T_169627[0] := UInt<2>(0)
    T_169627[1] := UInt<2>(1)
    wire T_169628 : UInt<2>[3]
    T_169628[0] := UInt<2>(1)
    T_169628[1] := UInt<2>(2)
    T_169628[2] := UInt<2>(3)
    wire T_169629 : UInt<2>[2]
    T_169629[0] := UInt<2>(2)
    T_169629[1] := UInt<2>(3)
    wire T_169630 : UInt<2>[1]
    T_169630[0] := UInt<2>(3)
    wire T_169631 : UInt<3>[3]
    T_169631[0] := UInt<3>(0)
    T_169631[1] := UInt<3>(1)
    T_169631[2] := UInt<3>(2)
    wire T_169632 : UInt<2>[2]
    T_169632[0] := UInt<2>(0)
    T_169632[1] := UInt<2>(1)
    wire T_169633 : UInt<2>[3]
    T_169633[0] := UInt<2>(1)
    T_169633[1] := UInt<2>(2)
    T_169633[2] := UInt<2>(3)
    wire T_169634 : UInt<2>[2]
    T_169634[0] := UInt<2>(2)
    T_169634[1] := UInt<2>(3)
    wire T_169635 : UInt<2>[1]
    T_169635[0] := UInt<2>(3)
    wire T_169636 : UInt<3>[3]
    T_169636[0] := UInt<3>(0)
    T_169636[1] := UInt<3>(1)
    T_169636[2] := UInt<3>(2)
    wire T_169637 : UInt<2>[2]
    T_169637[0] := UInt<2>(0)
    T_169637[1] := UInt<2>(1)
    wire T_169638 : UInt<2>[3]
    T_169638[0] := UInt<2>(1)
    T_169638[1] := UInt<2>(2)
    T_169638[2] := UInt<2>(3)
    wire T_169639 : UInt<2>[2]
    T_169639[0] := UInt<2>(2)
    T_169639[1] := UInt<2>(3)
    wire T_169640 : UInt<2>[1]
    T_169640[0] := UInt<2>(3)
    wire T_169641 : UInt<3>[3]
    T_169641[0] := UInt<3>(0)
    T_169641[1] := UInt<3>(1)
    T_169641[2] := UInt<3>(2)
    wire T_169642 : UInt<2>[2]
    T_169642[0] := UInt<2>(0)
    T_169642[1] := UInt<2>(1)
    wire T_169643 : UInt<2>[3]
    T_169643[0] := UInt<2>(1)
    T_169643[1] := UInt<2>(2)
    T_169643[2] := UInt<2>(3)
    wire T_169644 : UInt<2>[2]
    T_169644[0] := UInt<2>(2)
    T_169644[1] := UInt<2>(3)
    wire T_169645 : UInt<2>[1]
    T_169645[0] := UInt<2>(3)
    wire T_169646 : UInt<3>[3]
    T_169646[0] := UInt<3>(0)
    T_169646[1] := UInt<3>(1)
    T_169646[2] := UInt<3>(2)
    wire T_169647 : UInt<2>[2]
    T_169647[0] := UInt<2>(0)
    T_169647[1] := UInt<2>(1)
    wire T_169648 : UInt<2>[3]
    T_169648[0] := UInt<2>(1)
    T_169648[1] := UInt<2>(2)
    T_169648[2] := UInt<2>(3)
    wire T_169649 : UInt<2>[2]
    T_169649[0] := UInt<2>(2)
    T_169649[1] := UInt<2>(3)
    wire T_169650 : UInt<2>[1]
    T_169650[0] := UInt<2>(3)
    wire T_169651 : UInt<3>[3]
    T_169651[0] := UInt<3>(0)
    T_169651[1] := UInt<3>(1)
    T_169651[2] := UInt<3>(2)
    wire T_169652 : UInt<2>[2]
    T_169652[0] := UInt<2>(0)
    T_169652[1] := UInt<2>(1)
    wire T_169653 : UInt<2>[3]
    T_169653[0] := UInt<2>(1)
    T_169653[1] := UInt<2>(2)
    T_169653[2] := UInt<2>(3)
    wire T_169654 : UInt<2>[2]
    T_169654[0] := UInt<2>(2)
    T_169654[1] := UInt<2>(3)
    wire T_169655 : UInt<2>[1]
    T_169655[0] := UInt<2>(3)
    wire T_169656 : UInt<3>[3]
    T_169656[0] := UInt<3>(0)
    T_169656[1] := UInt<3>(1)
    T_169656[2] := UInt<3>(2)
    wire T_169657 : UInt<2>[2]
    T_169657[0] := UInt<2>(0)
    T_169657[1] := UInt<2>(1)
    wire T_169658 : UInt<2>[3]
    T_169658[0] := UInt<2>(1)
    T_169658[1] := UInt<2>(2)
    T_169658[2] := UInt<2>(3)
    wire T_169659 : UInt<2>[2]
    T_169659[0] := UInt<2>(2)
    T_169659[1] := UInt<2>(3)
    wire T_169660 : UInt<2>[1]
    T_169660[0] := UInt<2>(3)
    wire T_169661 : UInt<3>[3]
    T_169661[0] := UInt<3>(0)
    T_169661[1] := UInt<3>(1)
    T_169661[2] := UInt<3>(2)
    wire T_169662 : UInt<2>[2]
    T_169662[0] := UInt<2>(0)
    T_169662[1] := UInt<2>(1)
    wire T_169663 : UInt<2>[3]
    T_169663[0] := UInt<2>(1)
    T_169663[1] := UInt<2>(2)
    T_169663[2] := UInt<2>(3)
    wire T_169664 : UInt<2>[2]
    T_169664[0] := UInt<2>(2)
    T_169664[1] := UInt<2>(3)
    wire T_169665 : UInt<2>[1]
    T_169665[0] := UInt<2>(3)
    wire T_169666 : UInt<3>[3]
    T_169666[0] := UInt<3>(0)
    T_169666[1] := UInt<3>(1)
    T_169666[2] := UInt<3>(2)
    wire T_169667 : UInt<2>[2]
    T_169667[0] := UInt<2>(0)
    T_169667[1] := UInt<2>(1)
    wire T_169668 : UInt<2>[3]
    T_169668[0] := UInt<2>(1)
    T_169668[1] := UInt<2>(2)
    T_169668[2] := UInt<2>(3)
    wire T_169669 : UInt<2>[2]
    T_169669[0] := UInt<2>(2)
    T_169669[1] := UInt<2>(3)
    wire T_169670 : UInt<2>[1]
    T_169670[0] := UInt<2>(3)
    wire T_169671 : UInt<3>[3]
    T_169671[0] := UInt<3>(0)
    T_169671[1] := UInt<3>(1)
    T_169671[2] := UInt<3>(2)
    wire T_169672 : UInt<2>[2]
    T_169672[0] := UInt<2>(0)
    T_169672[1] := UInt<2>(1)
    wire T_169673 : UInt<2>[3]
    T_169673[0] := UInt<2>(1)
    T_169673[1] := UInt<2>(2)
    T_169673[2] := UInt<2>(3)
    wire T_169674 : UInt<2>[2]
    T_169674[0] := UInt<2>(2)
    T_169674[1] := UInt<2>(3)
    wire T_169675 : UInt<2>[1]
    T_169675[0] := UInt<2>(3)
    wire T_169676 : UInt<3>[3]
    T_169676[0] := UInt<3>(0)
    T_169676[1] := UInt<3>(1)
    T_169676[2] := UInt<3>(2)
    wire T_169677 : UInt<2>[2]
    T_169677[0] := UInt<2>(0)
    T_169677[1] := UInt<2>(1)
    wire T_169678 : UInt<2>[3]
    T_169678[0] := UInt<2>(1)
    T_169678[1] := UInt<2>(2)
    T_169678[2] := UInt<2>(3)
    wire T_169679 : UInt<2>[2]
    T_169679[0] := UInt<2>(2)
    T_169679[1] := UInt<2>(3)
    wire T_169680 : UInt<2>[1]
    T_169680[0] := UInt<2>(3)
    wire T_169681 : UInt<3>[3]
    T_169681[0] := UInt<3>(0)
    T_169681[1] := UInt<3>(1)
    T_169681[2] := UInt<3>(2)
    wire T_169682 : UInt<2>[2]
    T_169682[0] := UInt<2>(0)
    T_169682[1] := UInt<2>(1)
    wire T_169683 : UInt<2>[3]
    T_169683[0] := UInt<2>(1)
    T_169683[1] := UInt<2>(2)
    T_169683[2] := UInt<2>(3)
    wire T_169684 : UInt<2>[2]
    T_169684[0] := UInt<2>(2)
    T_169684[1] := UInt<2>(3)
    wire T_169685 : UInt<2>[1]
    T_169685[0] := UInt<2>(3)
    wire T_169686 : UInt<3>[3]
    T_169686[0] := UInt<3>(0)
    T_169686[1] := UInt<3>(1)
    T_169686[2] := UInt<3>(2)
    wire T_169687 : UInt<2>[2]
    T_169687[0] := UInt<2>(0)
    T_169687[1] := UInt<2>(1)
    wire T_169688 : UInt<2>[3]
    T_169688[0] := UInt<2>(1)
    T_169688[1] := UInt<2>(2)
    T_169688[2] := UInt<2>(3)
    wire T_169689 : UInt<2>[2]
    T_169689[0] := UInt<2>(2)
    T_169689[1] := UInt<2>(3)
    wire T_169690 : UInt<2>[1]
    T_169690[0] := UInt<2>(3)
    wire T_169691 : UInt<3>[3]
    T_169691[0] := UInt<3>(0)
    T_169691[1] := UInt<3>(1)
    T_169691[2] := UInt<3>(2)
    wire T_169692 : UInt<2>[2]
    T_169692[0] := UInt<2>(0)
    T_169692[1] := UInt<2>(1)
    wire T_169693 : UInt<2>[3]
    T_169693[0] := UInt<2>(1)
    T_169693[1] := UInt<2>(2)
    T_169693[2] := UInt<2>(3)
    wire T_169694 : UInt<2>[2]
    T_169694[0] := UInt<2>(2)
    T_169694[1] := UInt<2>(3)
    wire T_169695 : UInt<2>[1]
    T_169695[0] := UInt<2>(3)
    wire T_169696 : UInt<3>[3]
    T_169696[0] := UInt<3>(0)
    T_169696[1] := UInt<3>(1)
    T_169696[2] := UInt<3>(2)
    wire T_169697 : UInt<2>[2]
    T_169697[0] := UInt<2>(0)
    T_169697[1] := UInt<2>(1)
    wire T_169698 : UInt<2>[3]
    T_169698[0] := UInt<2>(1)
    T_169698[1] := UInt<2>(2)
    T_169698[2] := UInt<2>(3)
    wire T_169699 : UInt<2>[2]
    T_169699[0] := UInt<2>(2)
    T_169699[1] := UInt<2>(3)
    wire T_169700 : UInt<2>[1]
    T_169700[0] := UInt<2>(3)
    wire T_169701 : UInt<3>[3]
    T_169701[0] := UInt<3>(0)
    T_169701[1] := UInt<3>(1)
    T_169701[2] := UInt<3>(2)
    wire T_169702 : UInt<2>[2]
    T_169702[0] := UInt<2>(0)
    T_169702[1] := UInt<2>(1)
    wire T_169703 : UInt<2>[3]
    T_169703[0] := UInt<2>(1)
    T_169703[1] := UInt<2>(2)
    T_169703[2] := UInt<2>(3)
    wire T_169704 : UInt<2>[2]
    T_169704[0] := UInt<2>(2)
    T_169704[1] := UInt<2>(3)
    wire T_169705 : UInt<2>[1]
    T_169705[0] := UInt<2>(3)
    wire T_169706 : UInt<3>[3]
    T_169706[0] := UInt<3>(0)
    T_169706[1] := UInt<3>(1)
    T_169706[2] := UInt<3>(2)
    wire T_169707 : UInt<2>[2]
    T_169707[0] := UInt<2>(0)
    T_169707[1] := UInt<2>(1)
    wire T_169708 : UInt<2>[3]
    T_169708[0] := UInt<2>(1)
    T_169708[1] := UInt<2>(2)
    T_169708[2] := UInt<2>(3)
    wire T_169709 : UInt<2>[2]
    T_169709[0] := UInt<2>(2)
    T_169709[1] := UInt<2>(3)
    wire T_169710 : UInt<2>[1]
    T_169710[0] := UInt<2>(3)
    wire T_169711 : UInt<3>[3]
    T_169711[0] := UInt<3>(0)
    T_169711[1] := UInt<3>(1)
    T_169711[2] := UInt<3>(2)
    wire T_169712 : UInt<2>[2]
    T_169712[0] := UInt<2>(0)
    T_169712[1] := UInt<2>(1)
    wire T_169713 : UInt<2>[3]
    T_169713[0] := UInt<2>(1)
    T_169713[1] := UInt<2>(2)
    T_169713[2] := UInt<2>(3)
    wire T_169714 : UInt<2>[2]
    T_169714[0] := UInt<2>(2)
    T_169714[1] := UInt<2>(3)
    wire T_169715 : UInt<2>[1]
    T_169715[0] := UInt<2>(3)
    wire T_169716 : UInt<3>[3]
    T_169716[0] := UInt<3>(0)
    T_169716[1] := UInt<3>(1)
    T_169716[2] := UInt<3>(2)
    wire T_169717 : UInt<2>[2]
    T_169717[0] := UInt<2>(0)
    T_169717[1] := UInt<2>(1)
    wire T_169718 : UInt<2>[3]
    T_169718[0] := UInt<2>(1)
    T_169718[1] := UInt<2>(2)
    T_169718[2] := UInt<2>(3)
    wire T_169719 : UInt<2>[2]
    T_169719[0] := UInt<2>(2)
    T_169719[1] := UInt<2>(3)
    wire T_169720 : UInt<2>[1]
    T_169720[0] := UInt<2>(3)
    wire clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[3]
    clients[0] := T_169721
    clients[1] := T_169722
    clients[2] := T_169723
    wire T_169724 : UInt<3>[3]
    T_169724[0] := UInt<3>(0)
    T_169724[1] := UInt<3>(1)
    T_169724[2] := UInt<3>(2)
    wire T_169725 : UInt<2>[2]
    T_169725[0] := UInt<2>(0)
    T_169725[1] := UInt<2>(1)
    wire T_169726 : UInt<2>[3]
    T_169726[0] := UInt<2>(1)
    T_169726[1] := UInt<2>(2)
    T_169726[2] := UInt<2>(3)
    wire T_169727 : UInt<2>[2]
    T_169727[0] := UInt<2>(2)
    T_169727[1] := UInt<2>(3)
    wire T_169728 : UInt<2>[1]
    T_169728[0] := UInt<2>(3)
    wire T_169729 : UInt<3>[3]
    T_169729[0] := UInt<3>(0)
    T_169729[1] := UInt<3>(1)
    T_169729[2] := UInt<3>(2)
    wire T_169730 : UInt<2>[2]
    T_169730[0] := UInt<2>(0)
    T_169730[1] := UInt<2>(1)
    wire T_169731 : UInt<2>[3]
    T_169731[0] := UInt<2>(1)
    T_169731[1] := UInt<2>(2)
    T_169731[2] := UInt<2>(3)
    wire T_169732 : UInt<2>[2]
    T_169732[0] := UInt<2>(2)
    T_169732[1] := UInt<2>(3)
    wire T_169733 : UInt<2>[1]
    T_169733[0] := UInt<2>(3)
    wire T_169734 : UInt<3>[3]
    T_169734[0] := UInt<3>(0)
    T_169734[1] := UInt<3>(1)
    T_169734[2] := UInt<3>(2)
    wire T_169735 : UInt<2>[2]
    T_169735[0] := UInt<2>(0)
    T_169735[1] := UInt<2>(1)
    wire T_169736 : UInt<2>[3]
    T_169736[0] := UInt<2>(1)
    T_169736[1] := UInt<2>(2)
    T_169736[2] := UInt<2>(3)
    wire T_169737 : UInt<2>[2]
    T_169737[0] := UInt<2>(2)
    T_169737[1] := UInt<2>(3)
    wire T_169738 : UInt<2>[1]
    T_169738[0] := UInt<2>(3)
    wire T_169739 : UInt<3>[3]
    T_169739[0] := UInt<3>(0)
    T_169739[1] := UInt<3>(1)
    T_169739[2] := UInt<3>(2)
    wire T_169740 : UInt<2>[2]
    T_169740[0] := UInt<2>(0)
    T_169740[1] := UInt<2>(1)
    wire T_169741 : UInt<2>[3]
    T_169741[0] := UInt<2>(1)
    T_169741[1] := UInt<2>(2)
    T_169741[2] := UInt<2>(3)
    wire T_169742 : UInt<2>[2]
    T_169742[0] := UInt<2>(2)
    T_169742[1] := UInt<2>(3)
    wire T_169743 : UInt<2>[1]
    T_169743[0] := UInt<2>(3)
    wire T_169744 : UInt<3>[3]
    T_169744[0] := UInt<3>(0)
    T_169744[1] := UInt<3>(1)
    T_169744[2] := UInt<3>(2)
    wire T_169745 : UInt<2>[2]
    T_169745[0] := UInt<2>(0)
    T_169745[1] := UInt<2>(1)
    wire T_169746 : UInt<2>[3]
    T_169746[0] := UInt<2>(1)
    T_169746[1] := UInt<2>(2)
    T_169746[2] := UInt<2>(3)
    wire T_169747 : UInt<2>[2]
    T_169747[0] := UInt<2>(2)
    T_169747[1] := UInt<2>(3)
    wire T_169748 : UInt<2>[1]
    T_169748[0] := UInt<2>(3)
    wire T_169749 : UInt<3>[3]
    T_169749[0] := UInt<3>(0)
    T_169749[1] := UInt<3>(1)
    T_169749[2] := UInt<3>(2)
    wire T_169750 : UInt<2>[2]
    T_169750[0] := UInt<2>(0)
    T_169750[1] := UInt<2>(1)
    wire T_169751 : UInt<2>[3]
    T_169751[0] := UInt<2>(1)
    T_169751[1] := UInt<2>(2)
    T_169751[2] := UInt<2>(3)
    wire T_169752 : UInt<2>[2]
    T_169752[0] := UInt<2>(2)
    T_169752[1] := UInt<2>(3)
    wire T_169753 : UInt<2>[1]
    T_169753[0] := UInt<2>(3)
    wire T_169754 : UInt<3>[3]
    T_169754[0] := UInt<3>(0)
    T_169754[1] := UInt<3>(1)
    T_169754[2] := UInt<3>(2)
    wire T_169755 : UInt<2>[2]
    T_169755[0] := UInt<2>(0)
    T_169755[1] := UInt<2>(1)
    wire T_169756 : UInt<2>[3]
    T_169756[0] := UInt<2>(1)
    T_169756[1] := UInt<2>(2)
    T_169756[2] := UInt<2>(3)
    wire T_169757 : UInt<2>[2]
    T_169757[0] := UInt<2>(2)
    T_169757[1] := UInt<2>(3)
    wire T_169758 : UInt<2>[1]
    T_169758[0] := UInt<2>(3)
    wire T_169759 : UInt<3>[3]
    T_169759[0] := UInt<3>(0)
    T_169759[1] := UInt<3>(1)
    T_169759[2] := UInt<3>(2)
    wire T_169760 : UInt<2>[2]
    T_169760[0] := UInt<2>(0)
    T_169760[1] := UInt<2>(1)
    wire T_169761 : UInt<2>[3]
    T_169761[0] := UInt<2>(1)
    T_169761[1] := UInt<2>(2)
    T_169761[2] := UInt<2>(3)
    wire T_169762 : UInt<2>[2]
    T_169762[0] := UInt<2>(2)
    T_169762[1] := UInt<2>(3)
    wire T_169763 : UInt<2>[1]
    T_169763[0] := UInt<2>(3)
    wire T_169764 : UInt<3>[3]
    T_169764[0] := UInt<3>(0)
    T_169764[1] := UInt<3>(1)
    T_169764[2] := UInt<3>(2)
    wire T_169765 : UInt<2>[2]
    T_169765[0] := UInt<2>(0)
    T_169765[1] := UInt<2>(1)
    wire T_169766 : UInt<2>[3]
    T_169766[0] := UInt<2>(1)
    T_169766[1] := UInt<2>(2)
    T_169766[2] := UInt<2>(3)
    wire T_169767 : UInt<2>[2]
    T_169767[0] := UInt<2>(2)
    T_169767[1] := UInt<2>(3)
    wire T_169768 : UInt<2>[1]
    T_169768[0] := UInt<2>(3)
    wire T_169769 : UInt<3>[3]
    T_169769[0] := UInt<3>(0)
    T_169769[1] := UInt<3>(1)
    T_169769[2] := UInt<3>(2)
    wire T_169770 : UInt<2>[2]
    T_169770[0] := UInt<2>(0)
    T_169770[1] := UInt<2>(1)
    wire T_169771 : UInt<2>[3]
    T_169771[0] := UInt<2>(1)
    T_169771[1] := UInt<2>(2)
    T_169771[2] := UInt<2>(3)
    wire T_169772 : UInt<2>[2]
    T_169772[0] := UInt<2>(2)
    T_169772[1] := UInt<2>(3)
    wire T_169773 : UInt<2>[1]
    T_169773[0] := UInt<2>(3)
    wire T_169774 : UInt<3>[3]
    T_169774[0] := UInt<3>(0)
    T_169774[1] := UInt<3>(1)
    T_169774[2] := UInt<3>(2)
    wire T_169775 : UInt<2>[2]
    T_169775[0] := UInt<2>(0)
    T_169775[1] := UInt<2>(1)
    wire T_169776 : UInt<2>[3]
    T_169776[0] := UInt<2>(1)
    T_169776[1] := UInt<2>(2)
    T_169776[2] := UInt<2>(3)
    wire T_169777 : UInt<2>[2]
    T_169777[0] := UInt<2>(2)
    T_169777[1] := UInt<2>(3)
    wire T_169778 : UInt<2>[1]
    T_169778[0] := UInt<2>(3)
    wire T_169779 : UInt<3>[3]
    T_169779[0] := UInt<3>(0)
    T_169779[1] := UInt<3>(1)
    T_169779[2] := UInt<3>(2)
    wire T_169780 : UInt<2>[2]
    T_169780[0] := UInt<2>(0)
    T_169780[1] := UInt<2>(1)
    wire T_169781 : UInt<2>[3]
    T_169781[0] := UInt<2>(1)
    T_169781[1] := UInt<2>(2)
    T_169781[2] := UInt<2>(3)
    wire T_169782 : UInt<2>[2]
    T_169782[0] := UInt<2>(2)
    T_169782[1] := UInt<2>(3)
    wire T_169783 : UInt<2>[1]
    T_169783[0] := UInt<2>(3)
    wire T_169784 : UInt<3>[3]
    T_169784[0] := UInt<3>(0)
    T_169784[1] := UInt<3>(1)
    T_169784[2] := UInt<3>(2)
    wire T_169785 : UInt<2>[2]
    T_169785[0] := UInt<2>(0)
    T_169785[1] := UInt<2>(1)
    wire T_169786 : UInt<2>[3]
    T_169786[0] := UInt<2>(1)
    T_169786[1] := UInt<2>(2)
    T_169786[2] := UInt<2>(3)
    wire T_169787 : UInt<2>[2]
    T_169787[0] := UInt<2>(2)
    T_169787[1] := UInt<2>(3)
    wire T_169788 : UInt<2>[1]
    T_169788[0] := UInt<2>(3)
    wire T_169789 : UInt<3>[3]
    T_169789[0] := UInt<3>(0)
    T_169789[1] := UInt<3>(1)
    T_169789[2] := UInt<3>(2)
    wire T_169790 : UInt<2>[2]
    T_169790[0] := UInt<2>(0)
    T_169790[1] := UInt<2>(1)
    wire T_169791 : UInt<2>[3]
    T_169791[0] := UInt<2>(1)
    T_169791[1] := UInt<2>(2)
    T_169791[2] := UInt<2>(3)
    wire T_169792 : UInt<2>[2]
    T_169792[0] := UInt<2>(2)
    T_169792[1] := UInt<2>(3)
    wire T_169793 : UInt<2>[1]
    T_169793[0] := UInt<2>(3)
    wire T_169794 : UInt<3>[3]
    T_169794[0] := UInt<3>(0)
    T_169794[1] := UInt<3>(1)
    T_169794[2] := UInt<3>(2)
    wire T_169795 : UInt<2>[2]
    T_169795[0] := UInt<2>(0)
    T_169795[1] := UInt<2>(1)
    wire T_169796 : UInt<2>[3]
    T_169796[0] := UInt<2>(1)
    T_169796[1] := UInt<2>(2)
    T_169796[2] := UInt<2>(3)
    wire T_169797 : UInt<2>[2]
    T_169797[0] := UInt<2>(2)
    T_169797[1] := UInt<2>(3)
    wire T_169798 : UInt<2>[1]
    T_169798[0] := UInt<2>(3)
    wire T_169799 : UInt<3>[3]
    T_169799[0] := UInt<3>(0)
    T_169799[1] := UInt<3>(1)
    T_169799[2] := UInt<3>(2)
    wire T_169800 : UInt<2>[2]
    T_169800[0] := UInt<2>(0)
    T_169800[1] := UInt<2>(1)
    wire T_169801 : UInt<2>[3]
    T_169801[0] := UInt<2>(1)
    T_169801[1] := UInt<2>(2)
    T_169801[2] := UInt<2>(3)
    wire T_169802 : UInt<2>[2]
    T_169802[0] := UInt<2>(2)
    T_169802[1] := UInt<2>(3)
    wire T_169803 : UInt<2>[1]
    T_169803[0] := UInt<2>(3)
    wire T_169804 : UInt<3>[3]
    T_169804[0] := UInt<3>(0)
    T_169804[1] := UInt<3>(1)
    T_169804[2] := UInt<3>(2)
    wire T_169805 : UInt<2>[2]
    T_169805[0] := UInt<2>(0)
    T_169805[1] := UInt<2>(1)
    wire T_169806 : UInt<2>[3]
    T_169806[0] := UInt<2>(1)
    T_169806[1] := UInt<2>(2)
    T_169806[2] := UInt<2>(3)
    wire T_169807 : UInt<2>[2]
    T_169807[0] := UInt<2>(2)
    T_169807[1] := UInt<2>(3)
    wire T_169808 : UInt<2>[1]
    T_169808[0] := UInt<2>(3)
    wire T_169809 : UInt<3>[3]
    T_169809[0] := UInt<3>(0)
    T_169809[1] := UInt<3>(1)
    T_169809[2] := UInt<3>(2)
    wire T_169810 : UInt<2>[2]
    T_169810[0] := UInt<2>(0)
    T_169810[1] := UInt<2>(1)
    wire T_169811 : UInt<2>[3]
    T_169811[0] := UInt<2>(1)
    T_169811[1] := UInt<2>(2)
    T_169811[2] := UInt<2>(3)
    wire T_169812 : UInt<2>[2]
    T_169812[0] := UInt<2>(2)
    T_169812[1] := UInt<2>(3)
    wire T_169813 : UInt<2>[1]
    T_169813[0] := UInt<2>(3)
    wire T_169814 : UInt<3>[3]
    T_169814[0] := UInt<3>(0)
    T_169814[1] := UInt<3>(1)
    T_169814[2] := UInt<3>(2)
    wire T_169815 : UInt<2>[2]
    T_169815[0] := UInt<2>(0)
    T_169815[1] := UInt<2>(1)
    wire T_169816 : UInt<2>[3]
    T_169816[0] := UInt<2>(1)
    T_169816[1] := UInt<2>(2)
    T_169816[2] := UInt<2>(3)
    wire T_169817 : UInt<2>[2]
    T_169817[0] := UInt<2>(2)
    T_169817[1] := UInt<2>(3)
    wire T_169818 : UInt<2>[1]
    T_169818[0] := UInt<2>(3)
    wire T_169819 : UInt<3>[3]
    T_169819[0] := UInt<3>(0)
    T_169819[1] := UInt<3>(1)
    T_169819[2] := UInt<3>(2)
    wire T_169820 : UInt<2>[2]
    T_169820[0] := UInt<2>(0)
    T_169820[1] := UInt<2>(1)
    wire T_169821 : UInt<2>[3]
    T_169821[0] := UInt<2>(1)
    T_169821[1] := UInt<2>(2)
    T_169821[2] := UInt<2>(3)
    wire T_169822 : UInt<2>[2]
    T_169822[0] := UInt<2>(2)
    T_169822[1] := UInt<2>(3)
    wire T_169823 : UInt<2>[1]
    T_169823[0] := UInt<2>(3)
    wire T_169824 : UInt<3>[3]
    T_169824[0] := UInt<3>(0)
    T_169824[1] := UInt<3>(1)
    T_169824[2] := UInt<3>(2)
    wire T_169825 : UInt<2>[2]
    T_169825[0] := UInt<2>(0)
    T_169825[1] := UInt<2>(1)
    wire T_169826 : UInt<2>[3]
    T_169826[0] := UInt<2>(1)
    T_169826[1] := UInt<2>(2)
    T_169826[2] := UInt<2>(3)
    wire T_169827 : UInt<2>[2]
    T_169827[0] := UInt<2>(2)
    T_169827[1] := UInt<2>(3)
    wire T_169828 : UInt<2>[1]
    T_169828[0] := UInt<2>(3)
    wire T_169829 : UInt<3>[3]
    T_169829[0] := UInt<3>(0)
    T_169829[1] := UInt<3>(1)
    T_169829[2] := UInt<3>(2)
    wire T_169830 : UInt<2>[2]
    T_169830[0] := UInt<2>(0)
    T_169830[1] := UInt<2>(1)
    wire T_169831 : UInt<2>[3]
    T_169831[0] := UInt<2>(1)
    T_169831[1] := UInt<2>(2)
    T_169831[2] := UInt<2>(3)
    wire T_169832 : UInt<2>[2]
    T_169832[0] := UInt<2>(2)
    T_169832[1] := UInt<2>(3)
    wire T_169833 : UInt<2>[1]
    T_169833[0] := UInt<2>(3)
    wire managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}[1]
    managers[0] := T_169834
    inst T_169835 of ClientTileLinkNetworkPort
    inst T_169836 of TileLinkEnqueuer
    T_169835.client <> clients[0]
    T_169836.client <> T_169835.network
    inst T_169837 of ClientTileLinkNetworkPort_26210
    inst T_169838 of TileLinkEnqueuer_31615
    T_169837.client <> clients[1]
    T_169838.client <> T_169837.network
    inst T_169839 of ClientTileLinkNetworkPort_35756
    inst T_169840 of TileLinkEnqueuer_41161
    T_169839.client <> clients[2]
    T_169840.client <> T_169839.network
    inst T_169841 of ManagerTileLinkNetworkPort
    inst T_169842 of TileLinkEnqueuer_46546
    managers[0] <> T_169841.manager
    T_169841.network <> T_169842.manager
    inst T_169843 of LockingRRArbiter
    T_169843.in[0].valid := T_169836.manager.acquire.valid
    T_169843.in[0].bits := T_169836.manager.acquire.bits
    T_169843.in[0].bits.payload.client_xact_id := T_169836.manager.acquire.bits.payload.client_xact_id
    T_169836.manager.acquire.ready := T_169843.in[0].ready
    T_169843.in[1].valid := T_169838.manager.acquire.valid
    T_169843.in[1].bits := T_169838.manager.acquire.bits
    T_169843.in[1].bits.payload.client_xact_id := T_169838.manager.acquire.bits.payload.client_xact_id
    T_169838.manager.acquire.ready := T_169843.in[1].ready
    T_169843.in[2].valid := T_169840.manager.acquire.valid
    T_169843.in[2].bits := T_169840.manager.acquire.bits
    T_169843.in[2].bits.payload.client_xact_id := T_169840.manager.acquire.bits.payload.client_xact_id
    T_169840.manager.acquire.ready := T_169843.in[2].ready
    T_169843.out <> T_169842.client.acquire
    inst T_169844 of LockingRRArbiter_47800
    T_169844.in[0].valid := T_169836.manager.release.valid
    T_169844.in[0].bits := T_169836.manager.release.bits
    T_169844.in[0].bits.payload.client_xact_id := T_169836.manager.release.bits.payload.client_xact_id
    T_169836.manager.release.ready := T_169844.in[0].ready
    T_169844.in[1].valid := T_169838.manager.release.valid
    T_169844.in[1].bits := T_169838.manager.release.bits
    T_169844.in[1].bits.payload.client_xact_id := T_169838.manager.release.bits.payload.client_xact_id
    T_169838.manager.release.ready := T_169844.in[1].ready
    T_169844.in[2].valid := T_169840.manager.release.valid
    T_169844.in[2].bits := T_169840.manager.release.bits
    T_169844.in[2].bits.payload.client_xact_id := T_169840.manager.release.bits.payload.client_xact_id
    T_169840.manager.release.ready := T_169844.in[2].ready
    T_169844.out <> T_169842.client.release
    inst T_169845 of RRArbiter
    T_169845.in[0] <> T_169836.manager.finish
    T_169845.in[1] <> T_169838.manager.finish
    T_169845.in[2] <> T_169840.manager.finish
    T_169845.out <> T_169842.client.finish
    T_169842.client.probe.ready := UInt<1>(0)
    T_169836.manager.probe.valid := UInt<1>(0)
    
    node T_169846 = eq(T_169842.client.probe.bits.header.dst, UInt<1>(0))
    when T_169846 : 
      T_169836.manager.probe.valid := T_169842.client.probe.valid
      T_169842.client.probe.ready := T_169836.manager.probe.ready
    T_169836.manager.probe.bits := T_169842.client.probe.bits
    T_169838.manager.probe.valid := UInt<1>(0)
    
    node T_169847 = eq(T_169842.client.probe.bits.header.dst, UInt<1>(1))
    when T_169847 : 
      T_169838.manager.probe.valid := T_169842.client.probe.valid
      T_169842.client.probe.ready := T_169838.manager.probe.ready
    T_169838.manager.probe.bits := T_169842.client.probe.bits
    T_169840.manager.probe.valid := UInt<1>(0)
    
    node T_169848 = eq(T_169842.client.probe.bits.header.dst, UInt<2>(2))
    when T_169848 : 
      T_169840.manager.probe.valid := T_169842.client.probe.valid
      T_169842.client.probe.ready := T_169840.manager.probe.ready
    T_169840.manager.probe.bits := T_169842.client.probe.bits
    T_169842.client.grant.ready := UInt<1>(0)
    T_169836.manager.grant.valid := UInt<1>(0)
    
    node T_169849 = eq(T_169842.client.grant.bits.header.dst, UInt<1>(0))
    when T_169849 : 
      T_169836.manager.grant.valid := T_169842.client.grant.valid
      T_169842.client.grant.ready := T_169836.manager.grant.ready
    T_169836.manager.grant.bits := T_169842.client.grant.bits
    T_169838.manager.grant.valid := UInt<1>(0)
    
    node T_169850 = eq(T_169842.client.grant.bits.header.dst, UInt<1>(1))
    when T_169850 : 
      T_169838.manager.grant.valid := T_169842.client.grant.valid
      T_169842.client.grant.ready := T_169838.manager.grant.ready
    T_169838.manager.grant.bits := T_169842.client.grant.bits
    T_169840.manager.grant.valid := UInt<1>(0)
    
    node T_169851 = eq(T_169842.client.grant.bits.header.dst, UInt<2>(2))
    when T_169851 : 
      T_169840.manager.grant.valid := T_169842.client.grant.valid
      T_169842.client.grant.ready := T_169840.manager.grant.ready
    T_169840.manager.grant.bits := T_169842.client.grant.bits
  module MetadataArray : 
    input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>}}
    input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}}
    output resp : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}[8]
    
    wire T_169852 : UInt<3>[3]
    T_169852[0] := UInt<3>(0)
    T_169852[1] := UInt<3>(1)
    T_169852[2] := UInt<3>(2)
    wire T_169853 : UInt<2>[2]
    T_169853[0] := UInt<2>(0)
    T_169853[1] := UInt<2>(1)
    wire T_169854 : UInt<2>[3]
    T_169854[0] := UInt<2>(1)
    T_169854[1] := UInt<2>(2)
    T_169854[2] := UInt<2>(3)
    wire T_169855 : UInt<2>[2]
    T_169855[0] := UInt<2>(2)
    T_169855[1] := UInt<2>(3)
    wire T_169856 : UInt<2>[1]
    T_169856[0] := UInt<2>(3)
    wire T_169857 : UInt<3>[3]
    T_169857[0] := UInt<3>(0)
    T_169857[1] := UInt<3>(1)
    T_169857[2] := UInt<3>(2)
    wire T_169858 : UInt<2>[2]
    T_169858[0] := UInt<2>(0)
    T_169858[1] := UInt<2>(1)
    wire T_169859 : UInt<2>[3]
    T_169859[0] := UInt<2>(1)
    T_169859[1] := UInt<2>(2)
    T_169859[2] := UInt<2>(3)
    wire T_169860 : UInt<2>[2]
    T_169860[0] := UInt<2>(2)
    T_169860[1] := UInt<2>(3)
    wire T_169861 : UInt<2>[1]
    T_169861[0] := UInt<2>(3)
    wire T_169862 : UInt<3>[3]
    T_169862[0] := UInt<3>(0)
    T_169862[1] := UInt<3>(1)
    T_169862[2] := UInt<3>(2)
    wire T_169863 : UInt<2>[2]
    T_169863[0] := UInt<2>(0)
    T_169863[1] := UInt<2>(1)
    wire T_169864 : UInt<2>[3]
    T_169864[0] := UInt<2>(1)
    T_169864[1] := UInt<2>(2)
    T_169864[2] := UInt<2>(3)
    wire T_169865 : UInt<2>[2]
    T_169865[0] := UInt<2>(2)
    T_169865[1] := UInt<2>(3)
    wire T_169866 : UInt<2>[1]
    T_169866[0] := UInt<2>(3)
    wire T_169867 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_169867.sharers := UInt<1>(0)
    wire T_169868 : UInt<3>[3]
    T_169868[0] := UInt<3>(0)
    T_169868[1] := UInt<3>(1)
    T_169868[2] := UInt<3>(2)
    wire T_169869 : UInt<2>[2]
    T_169869[0] := UInt<2>(0)
    T_169869[1] := UInt<2>(1)
    wire T_169870 : UInt<2>[3]
    T_169870[0] := UInt<2>(1)
    T_169870[1] := UInt<2>(2)
    T_169870[2] := UInt<2>(3)
    wire T_169871 : UInt<2>[2]
    T_169871[0] := UInt<2>(2)
    T_169871[1] := UInt<2>(3)
    wire T_169872 : UInt<2>[1]
    T_169872[0] := UInt<2>(3)
    wire T_169873 : UInt<3>[3]
    T_169873[0] := UInt<3>(0)
    T_169873[1] := UInt<3>(1)
    T_169873[2] := UInt<3>(2)
    wire T_169874 : UInt<2>[2]
    T_169874[0] := UInt<2>(0)
    T_169874[1] := UInt<2>(1)
    wire T_169875 : UInt<2>[3]
    T_169875[0] := UInt<2>(1)
    T_169875[1] := UInt<2>(2)
    T_169875[2] := UInt<2>(3)
    wire T_169876 : UInt<2>[2]
    T_169876[0] := UInt<2>(2)
    T_169876[1] := UInt<2>(3)
    wire T_169877 : UInt<2>[1]
    T_169877[0] := UInt<2>(3)
    wire T_169878 : UInt<3>[3]
    T_169878[0] := UInt<3>(0)
    T_169878[1] := UInt<3>(1)
    T_169878[2] := UInt<3>(2)
    wire T_169879 : UInt<2>[2]
    T_169879[0] := UInt<2>(0)
    T_169879[1] := UInt<2>(1)
    wire T_169880 : UInt<2>[3]
    T_169880[0] := UInt<2>(1)
    T_169880[1] := UInt<2>(2)
    T_169880[2] := UInt<2>(3)
    wire T_169881 : UInt<2>[2]
    T_169881[0] := UInt<2>(2)
    T_169881[1] := UInt<2>(3)
    wire T_169882 : UInt<2>[1]
    T_169882[0] := UInt<2>(3)
    wire T_169883 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_169883.state := UInt<2>(0)
    wire T_169884 : UInt<3>[3]
    T_169884[0] := UInt<3>(0)
    T_169884[1] := UInt<3>(1)
    T_169884[2] := UInt<3>(2)
    wire T_169885 : UInt<2>[2]
    T_169885[0] := UInt<2>(0)
    T_169885[1] := UInt<2>(1)
    wire T_169886 : UInt<2>[3]
    T_169886[0] := UInt<2>(1)
    T_169886[1] := UInt<2>(2)
    T_169886[2] := UInt<2>(3)
    wire T_169887 : UInt<2>[2]
    T_169887[0] := UInt<2>(2)
    T_169887[1] := UInt<2>(3)
    wire T_169888 : UInt<2>[1]
    T_169888[0] := UInt<2>(3)
    wire T_169889 : UInt<3>[3]
    T_169889[0] := UInt<3>(0)
    T_169889[1] := UInt<3>(1)
    T_169889[2] := UInt<3>(2)
    wire T_169890 : UInt<2>[2]
    T_169890[0] := UInt<2>(0)
    T_169890[1] := UInt<2>(1)
    wire T_169891 : UInt<2>[3]
    T_169891[0] := UInt<2>(1)
    T_169891[1] := UInt<2>(2)
    T_169891[2] := UInt<2>(3)
    wire T_169892 : UInt<2>[2]
    T_169892[0] := UInt<2>(2)
    T_169892[1] := UInt<2>(3)
    wire T_169893 : UInt<2>[1]
    T_169893[0] := UInt<2>(3)
    wire T_169894 : UInt<3>[3]
    T_169894[0] := UInt<3>(0)
    T_169894[1] := UInt<3>(1)
    T_169894[2] := UInt<3>(2)
    wire T_169895 : UInt<0>[1]
    T_169895[0] := UInt<0>(0)
    wire T_169896 : UInt<2>[2]
    T_169896[0] := UInt<2>(1)
    T_169896[1] := UInt<2>(2)
    wire T_169897 : UInt<2>[2]
    T_169897[0] := UInt<2>(1)
    T_169897[1] := UInt<2>(2)
    wire T_169898 : UInt<2>[1]
    T_169898[0] := UInt<2>(2)
    wire T_169899 : UInt<3>[3]
    T_169899[0] := UInt<3>(0)
    T_169899[1] := UInt<3>(1)
    T_169899[2] := UInt<3>(2)
    wire T_169900 : UInt<2>[2]
    T_169900[0] := UInt<2>(0)
    T_169900[1] := UInt<2>(1)
    wire T_169901 : UInt<2>[3]
    T_169901[0] := UInt<2>(1)
    T_169901[1] := UInt<2>(2)
    T_169901[2] := UInt<2>(3)
    wire T_169902 : UInt<2>[2]
    T_169902[0] := UInt<2>(2)
    T_169902[1] := UInt<2>(3)
    wire T_169903 : UInt<2>[1]
    T_169903[0] := UInt<2>(3)
    wire T_169904 : UInt<3>[3]
    T_169904[0] := UInt<3>(0)
    T_169904[1] := UInt<3>(1)
    T_169904[2] := UInt<3>(2)
    wire T_169905 : UInt<2>[2]
    T_169905[0] := UInt<2>(0)
    T_169905[1] := UInt<2>(1)
    wire T_169906 : UInt<2>[3]
    T_169906[0] := UInt<2>(1)
    T_169906[1] := UInt<2>(2)
    T_169906[2] := UInt<2>(3)
    wire T_169907 : UInt<2>[2]
    T_169907[0] := UInt<2>(2)
    T_169907[1] := UInt<2>(3)
    wire T_169908 : UInt<2>[1]
    T_169908[0] := UInt<2>(3)
    wire T_169909 : UInt<3>[3]
    T_169909[0] := UInt<3>(0)
    T_169909[1] := UInt<3>(1)
    T_169909[2] := UInt<3>(2)
    wire T_169910 : UInt<0>[1]
    T_169910[0] := UInt<0>(0)
    wire T_169911 : UInt<2>[2]
    T_169911[0] := UInt<2>(1)
    T_169911[1] := UInt<2>(2)
    wire T_169912 : UInt<2>[2]
    T_169912[0] := UInt<2>(1)
    T_169912[1] := UInt<2>(2)
    wire T_169913 : UInt<2>[1]
    T_169913[0] := UInt<2>(2)
    wire T_169914 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    T_169914.inner := T_169867
    T_169914.outer := T_169883
    wire T_169915 : UInt<3>[3]
    T_169915[0] := UInt<3>(0)
    T_169915[1] := UInt<3>(1)
    T_169915[2] := UInt<3>(2)
    wire T_169916 : UInt<2>[2]
    T_169916[0] := UInt<2>(0)
    T_169916[1] := UInt<2>(1)
    wire T_169917 : UInt<2>[3]
    T_169917[0] := UInt<2>(1)
    T_169917[1] := UInt<2>(2)
    T_169917[2] := UInt<2>(3)
    wire T_169918 : UInt<2>[2]
    T_169918[0] := UInt<2>(2)
    T_169918[1] := UInt<2>(3)
    wire T_169919 : UInt<2>[1]
    T_169919[0] := UInt<2>(3)
    wire T_169920 : UInt<3>[3]
    T_169920[0] := UInt<3>(0)
    T_169920[1] := UInt<3>(1)
    T_169920[2] := UInt<3>(2)
    wire T_169921 : UInt<2>[2]
    T_169921[0] := UInt<2>(0)
    T_169921[1] := UInt<2>(1)
    wire T_169922 : UInt<2>[3]
    T_169922[0] := UInt<2>(1)
    T_169922[1] := UInt<2>(2)
    T_169922[2] := UInt<2>(3)
    wire T_169923 : UInt<2>[2]
    T_169923[0] := UInt<2>(2)
    T_169923[1] := UInt<2>(3)
    wire T_169924 : UInt<2>[1]
    T_169924[0] := UInt<2>(3)
    wire T_169925 : UInt<3>[3]
    T_169925[0] := UInt<3>(0)
    T_169925[1] := UInt<3>(1)
    T_169925[2] := UInt<3>(2)
    wire T_169926 : UInt<0>[1]
    T_169926[0] := UInt<0>(0)
    wire T_169927 : UInt<2>[2]
    T_169927[0] := UInt<2>(1)
    T_169927[1] := UInt<2>(2)
    wire T_169928 : UInt<2>[2]
    T_169928[0] := UInt<2>(1)
    T_169928[1] := UInt<2>(2)
    wire T_169929 : UInt<2>[1]
    T_169929[0] := UInt<2>(2)
    wire T_169930 : UInt<3>[3]
    T_169930[0] := UInt<3>(0)
    T_169930[1] := UInt<3>(1)
    T_169930[2] := UInt<3>(2)
    wire T_169931 : UInt<2>[2]
    T_169931[0] := UInt<2>(0)
    T_169931[1] := UInt<2>(1)
    wire T_169932 : UInt<2>[3]
    T_169932[0] := UInt<2>(1)
    T_169932[1] := UInt<2>(2)
    T_169932[2] := UInt<2>(3)
    wire T_169933 : UInt<2>[2]
    T_169933[0] := UInt<2>(2)
    T_169933[1] := UInt<2>(3)
    wire T_169934 : UInt<2>[1]
    T_169934[0] := UInt<2>(3)
    wire T_169935 : UInt<3>[3]
    T_169935[0] := UInt<3>(0)
    T_169935[1] := UInt<3>(1)
    T_169935[2] := UInt<3>(2)
    wire T_169936 : UInt<2>[2]
    T_169936[0] := UInt<2>(0)
    T_169936[1] := UInt<2>(1)
    wire T_169937 : UInt<2>[3]
    T_169937[0] := UInt<2>(1)
    T_169937[1] := UInt<2>(2)
    T_169937[2] := UInt<2>(3)
    wire T_169938 : UInt<2>[2]
    T_169938[0] := UInt<2>(2)
    T_169938[1] := UInt<2>(3)
    wire T_169939 : UInt<2>[1]
    T_169939[0] := UInt<2>(3)
    wire T_169940 : UInt<3>[3]
    T_169940[0] := UInt<3>(0)
    T_169940[1] := UInt<3>(1)
    T_169940[2] := UInt<3>(2)
    wire T_169941 : UInt<0>[1]
    T_169941[0] := UInt<0>(0)
    wire T_169942 : UInt<2>[2]
    T_169942[0] := UInt<2>(1)
    T_169942[1] := UInt<2>(2)
    wire T_169943 : UInt<2>[2]
    T_169943[0] := UInt<2>(1)
    T_169943[1] := UInt<2>(2)
    wire T_169944 : UInt<2>[1]
    T_169944[0] := UInt<2>(2)
    wire rstVal : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    rstVal.tag := UInt<1>(0)
    rstVal.coh := T_169914
    wire T_169945 : UInt<3>[3]
    T_169945[0] := UInt<3>(0)
    T_169945[1] := UInt<3>(1)
    T_169945[2] := UInt<3>(2)
    wire T_169946 : UInt<2>[2]
    T_169946[0] := UInt<2>(0)
    T_169946[1] := UInt<2>(1)
    wire T_169947 : UInt<2>[3]
    T_169947[0] := UInt<2>(1)
    T_169947[1] := UInt<2>(2)
    T_169947[2] := UInt<2>(3)
    wire T_169948 : UInt<2>[2]
    T_169948[0] := UInt<2>(2)
    T_169948[1] := UInt<2>(3)
    wire T_169949 : UInt<2>[1]
    T_169949[0] := UInt<2>(3)
    wire T_169950 : UInt<3>[3]
    T_169950[0] := UInt<3>(0)
    T_169950[1] := UInt<3>(1)
    T_169950[2] := UInt<3>(2)
    wire T_169951 : UInt<2>[2]
    T_169951[0] := UInt<2>(0)
    T_169951[1] := UInt<2>(1)
    wire T_169952 : UInt<2>[3]
    T_169952[0] := UInt<2>(1)
    T_169952[1] := UInt<2>(2)
    T_169952[2] := UInt<2>(3)
    wire T_169953 : UInt<2>[2]
    T_169953[0] := UInt<2>(2)
    T_169953[1] := UInt<2>(3)
    wire T_169954 : UInt<2>[1]
    T_169954[0] := UInt<2>(3)
    wire T_169955 : UInt<3>[3]
    T_169955[0] := UInt<3>(0)
    T_169955[1] := UInt<3>(1)
    T_169955[2] := UInt<3>(2)
    wire T_169956 : UInt<0>[1]
    T_169956[0] := UInt<0>(0)
    wire T_169957 : UInt<2>[2]
    T_169957[0] := UInt<2>(1)
    T_169957[1] := UInt<2>(2)
    wire T_169958 : UInt<2>[2]
    T_169958[0] := UInt<2>(1)
    T_169958[1] := UInt<2>(2)
    wire T_169959 : UInt<2>[1]
    T_169959[0] := UInt<2>(2)
    wire T_169960 : UInt<3>[3]
    T_169960[0] := UInt<3>(0)
    T_169960[1] := UInt<3>(1)
    T_169960[2] := UInt<3>(2)
    wire T_169961 : UInt<2>[2]
    T_169961[0] := UInt<2>(0)
    T_169961[1] := UInt<2>(1)
    wire T_169962 : UInt<2>[3]
    T_169962[0] := UInt<2>(1)
    T_169962[1] := UInt<2>(2)
    T_169962[2] := UInt<2>(3)
    wire T_169963 : UInt<2>[2]
    T_169963[0] := UInt<2>(2)
    T_169963[1] := UInt<2>(3)
    wire T_169964 : UInt<2>[1]
    T_169964[0] := UInt<2>(3)
    wire T_169965 : UInt<3>[3]
    T_169965[0] := UInt<3>(0)
    T_169965[1] := UInt<3>(1)
    T_169965[2] := UInt<3>(2)
    wire T_169966 : UInt<2>[2]
    T_169966[0] := UInt<2>(0)
    T_169966[1] := UInt<2>(1)
    wire T_169967 : UInt<2>[3]
    T_169967[0] := UInt<2>(1)
    T_169967[1] := UInt<2>(2)
    T_169967[2] := UInt<2>(3)
    wire T_169968 : UInt<2>[2]
    T_169968[0] := UInt<2>(2)
    T_169968[1] := UInt<2>(3)
    wire T_169969 : UInt<2>[1]
    T_169969[0] := UInt<2>(3)
    wire T_169970 : UInt<3>[3]
    T_169970[0] := UInt<3>(0)
    T_169970[1] := UInt<3>(1)
    T_169970[2] := UInt<3>(2)
    wire T_169971 : UInt<0>[1]
    T_169971[0] := UInt<0>(0)
    wire T_169972 : UInt<2>[2]
    T_169972[0] := UInt<2>(1)
    T_169972[1] := UInt<2>(2)
    wire T_169973 : UInt<2>[2]
    T_169973[0] := UInt<2>(1)
    T_169973[1] := UInt<2>(2)
    wire T_169974 : UInt<2>[1]
    T_169974[0] := UInt<2>(2)
    wire T_169975 : UInt<3>[3]
    T_169975[0] := UInt<3>(0)
    T_169975[1] := UInt<3>(1)
    T_169975[2] := UInt<3>(2)
    wire T_169976 : UInt<2>[2]
    T_169976[0] := UInt<2>(0)
    T_169976[1] := UInt<2>(1)
    wire T_169977 : UInt<2>[3]
    T_169977[0] := UInt<2>(1)
    T_169977[1] := UInt<2>(2)
    T_169977[2] := UInt<2>(3)
    wire T_169978 : UInt<2>[2]
    T_169978[0] := UInt<2>(2)
    T_169978[1] := UInt<2>(3)
    wire T_169979 : UInt<2>[1]
    T_169979[0] := UInt<2>(3)
    wire T_169980 : UInt<3>[3]
    T_169980[0] := UInt<3>(0)
    T_169980[1] := UInt<3>(1)
    T_169980[2] := UInt<3>(2)
    wire T_169981 : UInt<2>[2]
    T_169981[0] := UInt<2>(0)
    T_169981[1] := UInt<2>(1)
    wire T_169982 : UInt<2>[3]
    T_169982[0] := UInt<2>(1)
    T_169982[1] := UInt<2>(2)
    T_169982[2] := UInt<2>(3)
    wire T_169983 : UInt<2>[2]
    T_169983[0] := UInt<2>(2)
    T_169983[1] := UInt<2>(3)
    wire T_169984 : UInt<2>[1]
    T_169984[0] := UInt<2>(3)
    wire T_169985 : UInt<3>[3]
    T_169985[0] := UInt<3>(0)
    T_169985[1] := UInt<3>(1)
    T_169985[2] := UInt<3>(2)
    wire T_169986 : UInt<0>[1]
    T_169986[0] := UInt<0>(0)
    wire T_169987 : UInt<2>[2]
    T_169987[0] := UInt<2>(1)
    T_169987[1] := UInt<2>(2)
    wire T_169988 : UInt<2>[2]
    T_169988[0] := UInt<2>(1)
    T_169988[1] := UInt<2>(2)
    wire T_169989 : UInt<2>[1]
    T_169989[0] := UInt<2>(2)
    wire T_169990 : UInt<3>[3]
    T_169990[0] := UInt<3>(0)
    T_169990[1] := UInt<3>(1)
    T_169990[2] := UInt<3>(2)
    wire T_169991 : UInt<2>[2]
    T_169991[0] := UInt<2>(0)
    T_169991[1] := UInt<2>(1)
    wire T_169992 : UInt<2>[3]
    T_169992[0] := UInt<2>(1)
    T_169992[1] := UInt<2>(2)
    T_169992[2] := UInt<2>(3)
    wire T_169993 : UInt<2>[2]
    T_169993[0] := UInt<2>(2)
    T_169993[1] := UInt<2>(3)
    wire T_169994 : UInt<2>[1]
    T_169994[0] := UInt<2>(3)
    wire T_169995 : UInt<3>[3]
    T_169995[0] := UInt<3>(0)
    T_169995[1] := UInt<3>(1)
    T_169995[2] := UInt<3>(2)
    wire T_169996 : UInt<2>[2]
    T_169996[0] := UInt<2>(0)
    T_169996[1] := UInt<2>(1)
    wire T_169997 : UInt<2>[3]
    T_169997[0] := UInt<2>(1)
    T_169997[1] := UInt<2>(2)
    T_169997[2] := UInt<2>(3)
    wire T_169998 : UInt<2>[2]
    T_169998[0] := UInt<2>(2)
    T_169998[1] := UInt<2>(3)
    wire T_169999 : UInt<2>[1]
    T_169999[0] := UInt<2>(3)
    wire T_170000 : UInt<3>[3]
    T_170000[0] := UInt<3>(0)
    T_170000[1] := UInt<3>(1)
    T_170000[2] := UInt<3>(2)
    wire T_170001 : UInt<0>[1]
    T_170001[0] := UInt<0>(0)
    wire T_170002 : UInt<2>[2]
    T_170002[0] := UInt<2>(1)
    T_170002[1] := UInt<2>(2)
    wire T_170003 : UInt<2>[2]
    T_170003[0] := UInt<2>(1)
    T_170003[1] := UInt<2>(2)
    wire T_170004 : UInt<2>[1]
    T_170004[0] := UInt<2>(2)
    wire T_170005 : UInt<3>[3]
    T_170005[0] := UInt<3>(0)
    T_170005[1] := UInt<3>(1)
    T_170005[2] := UInt<3>(2)
    wire T_170006 : UInt<2>[2]
    T_170006[0] := UInt<2>(0)
    T_170006[1] := UInt<2>(1)
    wire T_170007 : UInt<2>[3]
    T_170007[0] := UInt<2>(1)
    T_170007[1] := UInt<2>(2)
    T_170007[2] := UInt<2>(3)
    wire T_170008 : UInt<2>[2]
    T_170008[0] := UInt<2>(2)
    T_170008[1] := UInt<2>(3)
    wire T_170009 : UInt<2>[1]
    T_170009[0] := UInt<2>(3)
    wire T_170010 : UInt<3>[3]
    T_170010[0] := UInt<3>(0)
    T_170010[1] := UInt<3>(1)
    T_170010[2] := UInt<3>(2)
    wire T_170011 : UInt<2>[2]
    T_170011[0] := UInt<2>(0)
    T_170011[1] := UInt<2>(1)
    wire T_170012 : UInt<2>[3]
    T_170012[0] := UInt<2>(1)
    T_170012[1] := UInt<2>(2)
    T_170012[2] := UInt<2>(3)
    wire T_170013 : UInt<2>[2]
    T_170013[0] := UInt<2>(2)
    T_170013[1] := UInt<2>(3)
    wire T_170014 : UInt<2>[1]
    T_170014[0] := UInt<2>(3)
    wire T_170015 : UInt<3>[3]
    T_170015[0] := UInt<3>(0)
    T_170015[1] := UInt<3>(1)
    T_170015[2] := UInt<3>(2)
    wire T_170016 : UInt<0>[1]
    T_170016[0] := UInt<0>(0)
    wire T_170017 : UInt<2>[2]
    T_170017[0] := UInt<2>(1)
    T_170017[1] := UInt<2>(2)
    wire T_170018 : UInt<2>[2]
    T_170018[0] := UInt<2>(1)
    T_170018[1] := UInt<2>(2)
    wire T_170019 : UInt<2>[1]
    T_170019[0] := UInt<2>(2)
    wire T_170020 : UInt<3>[3]
    T_170020[0] := UInt<3>(0)
    T_170020[1] := UInt<3>(1)
    T_170020[2] := UInt<3>(2)
    wire T_170021 : UInt<2>[2]
    T_170021[0] := UInt<2>(0)
    T_170021[1] := UInt<2>(1)
    wire T_170022 : UInt<2>[3]
    T_170022[0] := UInt<2>(1)
    T_170022[1] := UInt<2>(2)
    T_170022[2] := UInt<2>(3)
    wire T_170023 : UInt<2>[2]
    T_170023[0] := UInt<2>(2)
    T_170023[1] := UInt<2>(3)
    wire T_170024 : UInt<2>[1]
    T_170024[0] := UInt<2>(3)
    wire T_170025 : UInt<3>[3]
    T_170025[0] := UInt<3>(0)
    T_170025[1] := UInt<3>(1)
    T_170025[2] := UInt<3>(2)
    wire T_170026 : UInt<2>[2]
    T_170026[0] := UInt<2>(0)
    T_170026[1] := UInt<2>(1)
    wire T_170027 : UInt<2>[3]
    T_170027[0] := UInt<2>(1)
    T_170027[1] := UInt<2>(2)
    T_170027[2] := UInt<2>(3)
    wire T_170028 : UInt<2>[2]
    T_170028[0] := UInt<2>(2)
    T_170028[1] := UInt<2>(3)
    wire T_170029 : UInt<2>[1]
    T_170029[0] := UInt<2>(3)
    wire T_170030 : UInt<3>[3]
    T_170030[0] := UInt<3>(0)
    T_170030[1] := UInt<3>(1)
    T_170030[2] := UInt<3>(2)
    wire T_170031 : UInt<0>[1]
    T_170031[0] := UInt<0>(0)
    wire T_170032 : UInt<2>[2]
    T_170032[0] := UInt<2>(1)
    T_170032[1] := UInt<2>(2)
    wire T_170033 : UInt<2>[2]
    T_170033[0] := UInt<2>(1)
    T_170033[1] := UInt<2>(2)
    wire T_170034 : UInt<2>[1]
    T_170034[0] := UInt<2>(2)
    wire T_170035 : UInt<3>[3]
    T_170035[0] := UInt<3>(0)
    T_170035[1] := UInt<3>(1)
    T_170035[2] := UInt<3>(2)
    wire T_170036 : UInt<2>[2]
    T_170036[0] := UInt<2>(0)
    T_170036[1] := UInt<2>(1)
    wire T_170037 : UInt<2>[3]
    T_170037[0] := UInt<2>(1)
    T_170037[1] := UInt<2>(2)
    T_170037[2] := UInt<2>(3)
    wire T_170038 : UInt<2>[2]
    T_170038[0] := UInt<2>(2)
    T_170038[1] := UInt<2>(3)
    wire T_170039 : UInt<2>[1]
    T_170039[0] := UInt<2>(3)
    wire T_170040 : UInt<3>[3]
    T_170040[0] := UInt<3>(0)
    T_170040[1] := UInt<3>(1)
    T_170040[2] := UInt<3>(2)
    wire T_170041 : UInt<2>[2]
    T_170041[0] := UInt<2>(0)
    T_170041[1] := UInt<2>(1)
    wire T_170042 : UInt<2>[3]
    T_170042[0] := UInt<2>(1)
    T_170042[1] := UInt<2>(2)
    T_170042[2] := UInt<2>(3)
    wire T_170043 : UInt<2>[2]
    T_170043[0] := UInt<2>(2)
    T_170043[1] := UInt<2>(3)
    wire T_170044 : UInt<2>[1]
    T_170044[0] := UInt<2>(3)
    wire T_170045 : UInt<3>[3]
    T_170045[0] := UInt<3>(0)
    T_170045[1] := UInt<3>(1)
    T_170045[2] := UInt<3>(2)
    wire T_170046 : UInt<0>[1]
    T_170046[0] := UInt<0>(0)
    wire T_170047 : UInt<2>[2]
    T_170047[0] := UInt<2>(1)
    T_170047[1] := UInt<2>(2)
    wire T_170048 : UInt<2>[2]
    T_170048[0] := UInt<2>(1)
    T_170048[1] := UInt<2>(2)
    wire T_170049 : UInt<2>[1]
    T_170049[0] := UInt<2>(2)
    wire T_170050 : UInt<3>[3]
    T_170050[0] := UInt<3>(0)
    T_170050[1] := UInt<3>(1)
    T_170050[2] := UInt<3>(2)
    wire T_170051 : UInt<2>[2]
    T_170051[0] := UInt<2>(0)
    T_170051[1] := UInt<2>(1)
    wire T_170052 : UInt<2>[3]
    T_170052[0] := UInt<2>(1)
    T_170052[1] := UInt<2>(2)
    T_170052[2] := UInt<2>(3)
    wire T_170053 : UInt<2>[2]
    T_170053[0] := UInt<2>(2)
    T_170053[1] := UInt<2>(3)
    wire T_170054 : UInt<2>[1]
    T_170054[0] := UInt<2>(3)
    wire T_170055 : UInt<3>[3]
    T_170055[0] := UInt<3>(0)
    T_170055[1] := UInt<3>(1)
    T_170055[2] := UInt<3>(2)
    wire T_170056 : UInt<2>[2]
    T_170056[0] := UInt<2>(0)
    T_170056[1] := UInt<2>(1)
    wire T_170057 : UInt<2>[3]
    T_170057[0] := UInt<2>(1)
    T_170057[1] := UInt<2>(2)
    T_170057[2] := UInt<2>(3)
    wire T_170058 : UInt<2>[2]
    T_170058[0] := UInt<2>(2)
    T_170058[1] := UInt<2>(3)
    wire T_170059 : UInt<2>[1]
    T_170059[0] := UInt<2>(3)
    wire T_170060 : UInt<3>[3]
    T_170060[0] := UInt<3>(0)
    T_170060[1] := UInt<3>(1)
    T_170060[2] := UInt<3>(2)
    wire T_170061 : UInt<0>[1]
    T_170061[0] := UInt<0>(0)
    wire T_170062 : UInt<2>[2]
    T_170062[0] := UInt<2>(1)
    T_170062[1] := UInt<2>(2)
    wire T_170063 : UInt<2>[2]
    T_170063[0] := UInt<2>(1)
    T_170063[1] := UInt<2>(2)
    wire T_170064 : UInt<2>[1]
    T_170064[0] := UInt<2>(2)
    wire T_170065 : UInt<3>[3]
    T_170065[0] := UInt<3>(0)
    T_170065[1] := UInt<3>(1)
    T_170065[2] := UInt<3>(2)
    wire T_170066 : UInt<2>[2]
    T_170066[0] := UInt<2>(0)
    T_170066[1] := UInt<2>(1)
    wire T_170067 : UInt<2>[3]
    T_170067[0] := UInt<2>(1)
    T_170067[1] := UInt<2>(2)
    T_170067[2] := UInt<2>(3)
    wire T_170068 : UInt<2>[2]
    T_170068[0] := UInt<2>(2)
    T_170068[1] := UInt<2>(3)
    wire T_170069 : UInt<2>[1]
    T_170069[0] := UInt<2>(3)
    wire T_170070 : UInt<3>[3]
    T_170070[0] := UInt<3>(0)
    T_170070[1] := UInt<3>(1)
    T_170070[2] := UInt<3>(2)
    wire T_170071 : UInt<2>[2]
    T_170071[0] := UInt<2>(0)
    T_170071[1] := UInt<2>(1)
    wire T_170072 : UInt<2>[3]
    T_170072[0] := UInt<2>(1)
    T_170072[1] := UInt<2>(2)
    T_170072[2] := UInt<2>(3)
    wire T_170073 : UInt<2>[2]
    T_170073[0] := UInt<2>(2)
    T_170073[1] := UInt<2>(3)
    wire T_170074 : UInt<2>[1]
    T_170074[0] := UInt<2>(3)
    wire T_170075 : UInt<3>[3]
    T_170075[0] := UInt<3>(0)
    T_170075[1] := UInt<3>(1)
    T_170075[2] := UInt<3>(2)
    wire T_170076 : UInt<0>[1]
    T_170076[0] := UInt<0>(0)
    wire T_170077 : UInt<2>[2]
    T_170077[0] := UInt<2>(1)
    T_170077[1] := UInt<2>(2)
    wire T_170078 : UInt<2>[2]
    T_170078[0] := UInt<2>(1)
    T_170078[1] := UInt<2>(2)
    wire T_170079 : UInt<2>[1]
    T_170079[0] := UInt<2>(2)
    wire T_170080 : UInt<3>[3]
    T_170080[0] := UInt<3>(0)
    T_170080[1] := UInt<3>(1)
    T_170080[2] := UInt<3>(2)
    wire T_170081 : UInt<2>[2]
    T_170081[0] := UInt<2>(0)
    T_170081[1] := UInt<2>(1)
    wire T_170082 : UInt<2>[3]
    T_170082[0] := UInt<2>(1)
    T_170082[1] := UInt<2>(2)
    T_170082[2] := UInt<2>(3)
    wire T_170083 : UInt<2>[2]
    T_170083[0] := UInt<2>(2)
    T_170083[1] := UInt<2>(3)
    wire T_170084 : UInt<2>[1]
    T_170084[0] := UInt<2>(3)
    wire T_170085 : UInt<3>[3]
    T_170085[0] := UInt<3>(0)
    T_170085[1] := UInt<3>(1)
    T_170085[2] := UInt<3>(2)
    wire T_170086 : UInt<2>[2]
    T_170086[0] := UInt<2>(0)
    T_170086[1] := UInt<2>(1)
    wire T_170087 : UInt<2>[3]
    T_170087[0] := UInt<2>(1)
    T_170087[1] := UInt<2>(2)
    T_170087[2] := UInt<2>(3)
    wire T_170088 : UInt<2>[2]
    T_170088[0] := UInt<2>(2)
    T_170088[1] := UInt<2>(3)
    wire T_170089 : UInt<2>[1]
    T_170089[0] := UInt<2>(3)
    wire T_170090 : UInt<3>[3]
    T_170090[0] := UInt<3>(0)
    T_170090[1] := UInt<3>(1)
    T_170090[2] := UInt<3>(2)
    wire T_170091 : UInt<0>[1]
    T_170091[0] := UInt<0>(0)
    wire T_170092 : UInt<2>[2]
    T_170092[0] := UInt<2>(1)
    T_170092[1] := UInt<2>(2)
    wire T_170093 : UInt<2>[2]
    T_170093[0] := UInt<2>(1)
    T_170093[1] := UInt<2>(2)
    wire T_170094 : UInt<2>[1]
    T_170094[0] := UInt<2>(2)
    wire T_170095 : UInt<3>[3]
    T_170095[0] := UInt<3>(0)
    T_170095[1] := UInt<3>(1)
    T_170095[2] := UInt<3>(2)
    wire T_170096 : UInt<2>[2]
    T_170096[0] := UInt<2>(0)
    T_170096[1] := UInt<2>(1)
    wire T_170097 : UInt<2>[3]
    T_170097[0] := UInt<2>(1)
    T_170097[1] := UInt<2>(2)
    T_170097[2] := UInt<2>(3)
    wire T_170098 : UInt<2>[2]
    T_170098[0] := UInt<2>(2)
    T_170098[1] := UInt<2>(3)
    wire T_170099 : UInt<2>[1]
    T_170099[0] := UInt<2>(3)
    wire T_170100 : UInt<3>[3]
    T_170100[0] := UInt<3>(0)
    T_170100[1] := UInt<3>(1)
    T_170100[2] := UInt<3>(2)
    wire T_170101 : UInt<2>[2]
    T_170101[0] := UInt<2>(0)
    T_170101[1] := UInt<2>(1)
    wire T_170102 : UInt<2>[3]
    T_170102[0] := UInt<2>(1)
    T_170102[1] := UInt<2>(2)
    T_170102[2] := UInt<2>(3)
    wire T_170103 : UInt<2>[2]
    T_170103[0] := UInt<2>(2)
    T_170103[1] := UInt<2>(3)
    wire T_170104 : UInt<2>[1]
    T_170104[0] := UInt<2>(3)
    wire T_170105 : UInt<3>[3]
    T_170105[0] := UInt<3>(0)
    T_170105[1] := UInt<3>(1)
    T_170105[2] := UInt<3>(2)
    wire T_170106 : UInt<0>[1]
    T_170106[0] := UInt<0>(0)
    wire T_170107 : UInt<2>[2]
    T_170107[0] := UInt<2>(1)
    T_170107[1] := UInt<2>(2)
    wire T_170108 : UInt<2>[2]
    T_170108[0] := UInt<2>(1)
    T_170108[1] := UInt<2>(2)
    wire T_170109 : UInt<2>[1]
    T_170109[0] := UInt<2>(2)
    wire T_170110 : UInt<3>[3]
    T_170110[0] := UInt<3>(0)
    T_170110[1] := UInt<3>(1)
    T_170110[2] := UInt<3>(2)
    wire T_170111 : UInt<2>[2]
    T_170111[0] := UInt<2>(0)
    T_170111[1] := UInt<2>(1)
    wire T_170112 : UInt<2>[3]
    T_170112[0] := UInt<2>(1)
    T_170112[1] := UInt<2>(2)
    T_170112[2] := UInt<2>(3)
    wire T_170113 : UInt<2>[2]
    T_170113[0] := UInt<2>(2)
    T_170113[1] := UInt<2>(3)
    wire T_170114 : UInt<2>[1]
    T_170114[0] := UInt<2>(3)
    wire T_170115 : UInt<3>[3]
    T_170115[0] := UInt<3>(0)
    T_170115[1] := UInt<3>(1)
    T_170115[2] := UInt<3>(2)
    wire T_170116 : UInt<2>[2]
    T_170116[0] := UInt<2>(0)
    T_170116[1] := UInt<2>(1)
    wire T_170117 : UInt<2>[3]
    T_170117[0] := UInt<2>(1)
    T_170117[1] := UInt<2>(2)
    T_170117[2] := UInt<2>(3)
    wire T_170118 : UInt<2>[2]
    T_170118[0] := UInt<2>(2)
    T_170118[1] := UInt<2>(3)
    wire T_170119 : UInt<2>[1]
    T_170119[0] := UInt<2>(3)
    wire T_170120 : UInt<3>[3]
    T_170120[0] := UInt<3>(0)
    T_170120[1] := UInt<3>(1)
    T_170120[2] := UInt<3>(2)
    wire T_170121 : UInt<0>[1]
    T_170121[0] := UInt<0>(0)
    wire T_170122 : UInt<2>[2]
    T_170122[0] := UInt<2>(1)
    T_170122[1] := UInt<2>(2)
    wire T_170123 : UInt<2>[2]
    T_170123[0] := UInt<2>(1)
    T_170123[1] := UInt<2>(2)
    wire T_170124 : UInt<2>[1]
    T_170124[0] := UInt<2>(2)
    wire T_170125 : UInt<3>[3]
    T_170125[0] := UInt<3>(0)
    T_170125[1] := UInt<3>(1)
    T_170125[2] := UInt<3>(2)
    wire T_170126 : UInt<2>[2]
    T_170126[0] := UInt<2>(0)
    T_170126[1] := UInt<2>(1)
    wire T_170127 : UInt<2>[3]
    T_170127[0] := UInt<2>(1)
    T_170127[1] := UInt<2>(2)
    T_170127[2] := UInt<2>(3)
    wire T_170128 : UInt<2>[2]
    T_170128[0] := UInt<2>(2)
    T_170128[1] := UInt<2>(3)
    wire T_170129 : UInt<2>[1]
    T_170129[0] := UInt<2>(3)
    wire T_170130 : UInt<3>[3]
    T_170130[0] := UInt<3>(0)
    T_170130[1] := UInt<3>(1)
    T_170130[2] := UInt<3>(2)
    wire T_170131 : UInt<2>[2]
    T_170131[0] := UInt<2>(0)
    T_170131[1] := UInt<2>(1)
    wire T_170132 : UInt<2>[3]
    T_170132[0] := UInt<2>(1)
    T_170132[1] := UInt<2>(2)
    T_170132[2] := UInt<2>(3)
    wire T_170133 : UInt<2>[2]
    T_170133[0] := UInt<2>(2)
    T_170133[1] := UInt<2>(3)
    wire T_170134 : UInt<2>[1]
    T_170134[0] := UInt<2>(3)
    wire T_170135 : UInt<3>[3]
    T_170135[0] := UInt<3>(0)
    T_170135[1] := UInt<3>(1)
    T_170135[2] := UInt<3>(2)
    wire T_170136 : UInt<0>[1]
    T_170136[0] := UInt<0>(0)
    wire T_170137 : UInt<2>[2]
    T_170137[0] := UInt<2>(1)
    T_170137[1] := UInt<2>(2)
    wire T_170138 : UInt<2>[2]
    T_170138[0] := UInt<2>(1)
    T_170138[1] := UInt<2>(2)
    wire T_170139 : UInt<2>[1]
    T_170139[0] := UInt<2>(2)
    wire T_170140 : UInt<3>[3]
    T_170140[0] := UInt<3>(0)
    T_170140[1] := UInt<3>(1)
    T_170140[2] := UInt<3>(2)
    wire T_170141 : UInt<2>[2]
    T_170141[0] := UInt<2>(0)
    T_170141[1] := UInt<2>(1)
    wire T_170142 : UInt<2>[3]
    T_170142[0] := UInt<2>(1)
    T_170142[1] := UInt<2>(2)
    T_170142[2] := UInt<2>(3)
    wire T_170143 : UInt<2>[2]
    T_170143[0] := UInt<2>(2)
    T_170143[1] := UInt<2>(3)
    wire T_170144 : UInt<2>[1]
    T_170144[0] := UInt<2>(3)
    wire T_170145 : UInt<3>[3]
    T_170145[0] := UInt<3>(0)
    T_170145[1] := UInt<3>(1)
    T_170145[2] := UInt<3>(2)
    wire T_170146 : UInt<2>[2]
    T_170146[0] := UInt<2>(0)
    T_170146[1] := UInt<2>(1)
    wire T_170147 : UInt<2>[3]
    T_170147[0] := UInt<2>(1)
    T_170147[1] := UInt<2>(2)
    T_170147[2] := UInt<2>(3)
    wire T_170148 : UInt<2>[2]
    T_170148[0] := UInt<2>(2)
    T_170148[1] := UInt<2>(3)
    wire T_170149 : UInt<2>[1]
    T_170149[0] := UInt<2>(3)
    wire T_170150 : UInt<3>[3]
    T_170150[0] := UInt<3>(0)
    T_170150[1] := UInt<3>(1)
    T_170150[2] := UInt<3>(2)
    wire T_170151 : UInt<0>[1]
    T_170151[0] := UInt<0>(0)
    wire T_170152 : UInt<2>[2]
    T_170152[0] := UInt<2>(1)
    T_170152[1] := UInt<2>(2)
    wire T_170153 : UInt<2>[2]
    T_170153[0] := UInt<2>(1)
    T_170153[1] := UInt<2>(2)
    wire T_170154 : UInt<2>[1]
    T_170154[0] := UInt<2>(2)
    wire T_170155 : UInt<3>[3]
    T_170155[0] := UInt<3>(0)
    T_170155[1] := UInt<3>(1)
    T_170155[2] := UInt<3>(2)
    wire T_170156 : UInt<2>[2]
    T_170156[0] := UInt<2>(0)
    T_170156[1] := UInt<2>(1)
    wire T_170157 : UInt<2>[3]
    T_170157[0] := UInt<2>(1)
    T_170157[1] := UInt<2>(2)
    T_170157[2] := UInt<2>(3)
    wire T_170158 : UInt<2>[2]
    T_170158[0] := UInt<2>(2)
    T_170158[1] := UInt<2>(3)
    wire T_170159 : UInt<2>[1]
    T_170159[0] := UInt<2>(3)
    wire T_170160 : UInt<3>[3]
    T_170160[0] := UInt<3>(0)
    T_170160[1] := UInt<3>(1)
    T_170160[2] := UInt<3>(2)
    wire T_170161 : UInt<2>[2]
    T_170161[0] := UInt<2>(0)
    T_170161[1] := UInt<2>(1)
    wire T_170162 : UInt<2>[3]
    T_170162[0] := UInt<2>(1)
    T_170162[1] := UInt<2>(2)
    T_170162[2] := UInt<2>(3)
    wire T_170163 : UInt<2>[2]
    T_170163[0] := UInt<2>(2)
    T_170163[1] := UInt<2>(3)
    wire T_170164 : UInt<2>[1]
    T_170164[0] := UInt<2>(3)
    wire T_170165 : UInt<3>[3]
    T_170165[0] := UInt<3>(0)
    T_170165[1] := UInt<3>(1)
    T_170165[2] := UInt<3>(2)
    wire T_170166 : UInt<0>[1]
    T_170166[0] := UInt<0>(0)
    wire T_170167 : UInt<2>[2]
    T_170167[0] := UInt<2>(1)
    T_170167[1] := UInt<2>(2)
    wire T_170168 : UInt<2>[2]
    T_170168[0] := UInt<2>(1)
    T_170168[1] := UInt<2>(2)
    wire T_170169 : UInt<2>[1]
    T_170169[0] := UInt<2>(2)
    wire T_170170 : UInt<3>[3]
    T_170170[0] := UInt<3>(0)
    T_170170[1] := UInt<3>(1)
    T_170170[2] := UInt<3>(2)
    wire T_170171 : UInt<2>[2]
    T_170171[0] := UInt<2>(0)
    T_170171[1] := UInt<2>(1)
    wire T_170172 : UInt<2>[3]
    T_170172[0] := UInt<2>(1)
    T_170172[1] := UInt<2>(2)
    T_170172[2] := UInt<2>(3)
    wire T_170173 : UInt<2>[2]
    T_170173[0] := UInt<2>(2)
    T_170173[1] := UInt<2>(3)
    wire T_170174 : UInt<2>[1]
    T_170174[0] := UInt<2>(3)
    wire T_170175 : UInt<3>[3]
    T_170175[0] := UInt<3>(0)
    T_170175[1] := UInt<3>(1)
    T_170175[2] := UInt<3>(2)
    wire T_170176 : UInt<2>[2]
    T_170176[0] := UInt<2>(0)
    T_170176[1] := UInt<2>(1)
    wire T_170177 : UInt<2>[3]
    T_170177[0] := UInt<2>(1)
    T_170177[1] := UInt<2>(2)
    T_170177[2] := UInt<2>(3)
    wire T_170178 : UInt<2>[2]
    T_170178[0] := UInt<2>(2)
    T_170178[1] := UInt<2>(3)
    wire T_170179 : UInt<2>[1]
    T_170179[0] := UInt<2>(3)
    wire T_170180 : UInt<3>[3]
    T_170180[0] := UInt<3>(0)
    T_170180[1] := UInt<3>(1)
    T_170180[2] := UInt<3>(2)
    wire T_170181 : UInt<0>[1]
    T_170181[0] := UInt<0>(0)
    wire T_170182 : UInt<2>[2]
    T_170182[0] := UInt<2>(1)
    T_170182[1] := UInt<2>(2)
    wire T_170183 : UInt<2>[2]
    T_170183[0] := UInt<2>(1)
    T_170183[1] := UInt<2>(2)
    wire T_170184 : UInt<2>[1]
    T_170184[0] := UInt<2>(2)
    wire T_170185 : UInt<3>[3]
    T_170185[0] := UInt<3>(0)
    T_170185[1] := UInt<3>(1)
    T_170185[2] := UInt<3>(2)
    wire T_170186 : UInt<2>[2]
    T_170186[0] := UInt<2>(0)
    T_170186[1] := UInt<2>(1)
    wire T_170187 : UInt<2>[3]
    T_170187[0] := UInt<2>(1)
    T_170187[1] := UInt<2>(2)
    T_170187[2] := UInt<2>(3)
    wire T_170188 : UInt<2>[2]
    T_170188[0] := UInt<2>(2)
    T_170188[1] := UInt<2>(3)
    wire T_170189 : UInt<2>[1]
    T_170189[0] := UInt<2>(3)
    wire T_170190 : UInt<3>[3]
    T_170190[0] := UInt<3>(0)
    T_170190[1] := UInt<3>(1)
    T_170190[2] := UInt<3>(2)
    wire T_170191 : UInt<2>[2]
    T_170191[0] := UInt<2>(0)
    T_170191[1] := UInt<2>(1)
    wire T_170192 : UInt<2>[3]
    T_170192[0] := UInt<2>(1)
    T_170192[1] := UInt<2>(2)
    T_170192[2] := UInt<2>(3)
    wire T_170193 : UInt<2>[2]
    T_170193[0] := UInt<2>(2)
    T_170193[1] := UInt<2>(3)
    wire T_170194 : UInt<2>[1]
    T_170194[0] := UInt<2>(3)
    wire T_170195 : UInt<3>[3]
    T_170195[0] := UInt<3>(0)
    T_170195[1] := UInt<3>(1)
    T_170195[2] := UInt<3>(2)
    wire T_170196 : UInt<0>[1]
    T_170196[0] := UInt<0>(0)
    wire T_170197 : UInt<2>[2]
    T_170197[0] := UInt<2>(1)
    T_170197[1] := UInt<2>(2)
    wire T_170198 : UInt<2>[2]
    T_170198[0] := UInt<2>(1)
    T_170198[1] := UInt<2>(2)
    wire T_170199 : UInt<2>[1]
    T_170199[0] := UInt<2>(2)
    wire T_170200 : UInt<3>[3]
    T_170200[0] := UInt<3>(0)
    T_170200[1] := UInt<3>(1)
    T_170200[2] := UInt<3>(2)
    wire T_170201 : UInt<2>[2]
    T_170201[0] := UInt<2>(0)
    T_170201[1] := UInt<2>(1)
    wire T_170202 : UInt<2>[3]
    T_170202[0] := UInt<2>(1)
    T_170202[1] := UInt<2>(2)
    T_170202[2] := UInt<2>(3)
    wire T_170203 : UInt<2>[2]
    T_170203[0] := UInt<2>(2)
    T_170203[1] := UInt<2>(3)
    wire T_170204 : UInt<2>[1]
    T_170204[0] := UInt<2>(3)
    wire T_170205 : UInt<3>[3]
    T_170205[0] := UInt<3>(0)
    T_170205[1] := UInt<3>(1)
    T_170205[2] := UInt<3>(2)
    wire T_170206 : UInt<2>[2]
    T_170206[0] := UInt<2>(0)
    T_170206[1] := UInt<2>(1)
    wire T_170207 : UInt<2>[3]
    T_170207[0] := UInt<2>(1)
    T_170207[1] := UInt<2>(2)
    T_170207[2] := UInt<2>(3)
    wire T_170208 : UInt<2>[2]
    T_170208[0] := UInt<2>(2)
    T_170208[1] := UInt<2>(3)
    wire T_170209 : UInt<2>[1]
    T_170209[0] := UInt<2>(3)
    wire T_170210 : UInt<3>[3]
    T_170210[0] := UInt<3>(0)
    T_170210[1] := UInt<3>(1)
    T_170210[2] := UInt<3>(2)
    wire T_170211 : UInt<0>[1]
    T_170211[0] := UInt<0>(0)
    wire T_170212 : UInt<2>[2]
    T_170212[0] := UInt<2>(1)
    T_170212[1] := UInt<2>(2)
    wire T_170213 : UInt<2>[2]
    T_170213[0] := UInt<2>(1)
    T_170213[1] := UInt<2>(2)
    wire T_170214 : UInt<2>[1]
    T_170214[0] := UInt<2>(2)
    wire resp : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}[8]
    resp[0] := T_170215
    resp[1] := T_170216
    resp[2] := T_170217
    resp[3] := T_170218
    resp[4] := T_170219
    resp[5] := T_170220
    resp[6] := T_170221
    resp[7] := T_170222
    reg rst_cnt : UInt<13>
    onreset rst_cnt := UInt<13>(0)
    node rst = lt(rst_cnt, UInt<13>(4096))
    wire waddr : UInt<12>
    waddr := write.bits.idx
    when rst : waddr := rst_cnt
    wire T_170223 : UInt<3>[3]
    T_170223[0] := UInt<3>(0)
    T_170223[1] := UInt<3>(1)
    T_170223[2] := UInt<3>(2)
    wire T_170224 : UInt<2>[2]
    T_170224[0] := UInt<2>(0)
    T_170224[1] := UInt<2>(1)
    wire T_170225 : UInt<2>[3]
    T_170225[0] := UInt<2>(1)
    T_170225[1] := UInt<2>(2)
    T_170225[2] := UInt<2>(3)
    wire T_170226 : UInt<2>[2]
    T_170226[0] := UInt<2>(2)
    T_170226[1] := UInt<2>(3)
    wire T_170227 : UInt<2>[1]
    T_170227[0] := UInt<2>(3)
    wire T_170228 : UInt<3>[3]
    T_170228[0] := UInt<3>(0)
    T_170228[1] := UInt<3>(1)
    T_170228[2] := UInt<3>(2)
    wire T_170229 : UInt<2>[2]
    T_170229[0] := UInt<2>(0)
    T_170229[1] := UInt<2>(1)
    wire T_170230 : UInt<2>[3]
    T_170230[0] := UInt<2>(1)
    T_170230[1] := UInt<2>(2)
    T_170230[2] := UInt<2>(3)
    wire T_170231 : UInt<2>[2]
    T_170231[0] := UInt<2>(2)
    T_170231[1] := UInt<2>(3)
    wire T_170232 : UInt<2>[1]
    T_170232[0] := UInt<2>(3)
    wire T_170233 : UInt<3>[3]
    T_170233[0] := UInt<3>(0)
    T_170233[1] := UInt<3>(1)
    T_170233[2] := UInt<3>(2)
    wire T_170234 : UInt<0>[1]
    T_170234[0] := UInt<0>(0)
    wire T_170235 : UInt<2>[2]
    T_170235[0] := UInt<2>(1)
    T_170235[1] := UInt<2>(2)
    wire T_170236 : UInt<2>[2]
    T_170236[0] := UInt<2>(1)
    T_170236[1] := UInt<2>(2)
    wire T_170237 : UInt<2>[1]
    T_170237[0] := UInt<2>(2)
    wire T_170238 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    T_170238 := write.bits.data
    when rst : T_170238 := rstVal
    node T_170239 = cat(T_170238.tag, T_170238.coh.inner.sharers)
    node T_170240 = cat(UInt<1>(0), T_170238.coh.outer.state)
    node T_170241 = cat(UInt<1>(0), T_170240)
    node T_170242 = cat(T_170239, T_170241)
    node T_170243 = cat(T_170242, UInt<5>(0))
    node T_170244 = cat(UInt<1>(0), T_170238.coh.inner.sharers)
    node T_170245 = cat(UInt<1>(0), T_170238.coh.outer.state)
    node T_170246 = cat(UInt<1>(0), T_170245)
    node T_170247 = cat(T_170244, T_170246)
    node T_170248 = cat(T_170247, UInt<6>(0))
    node wdata = cat(T_170243, T_170248)
    node T_170249 = asSInt(write.bits.way_en)
    wire T_170250 : SInt<8>
    T_170250 := T_170249
    when rst : T_170250 := SInt<1>(-1)
    node wmask = asUInt(T_170250)
    when rst : 
      node T_170251 = addw(rst_cnt, UInt<1>(1))
      rst_cnt := T_170251
    cmem T_170252 : UInt<288>[4096]
    
    node T_170253 = or(rst, write.valid)
    when T_170253 : 
      node T_170254 = cat(wdata, wdata)
      node T_170255 = cat(T_170254, T_170254)
      node T_170256 = cat(T_170255, T_170255)
      node T_170257 = bit(wmask, 0)
      node T_170258 = bit(wmask, 1)
      node T_170259 = bit(wmask, 2)
      node T_170260 = bit(wmask, 3)
      node T_170261 = bit(wmask, 4)
      node T_170262 = bit(wmask, 5)
      node T_170263 = bit(wmask, 6)
      node T_170264 = bit(wmask, 7)
      wire T_170265 : UInt<1>[8]
      T_170265[0] := T_170257
      T_170265[1] := T_170258
      T_170265[2] := T_170259
      T_170265[3] := T_170260
      T_170265[4] := T_170261
      T_170265[5] := T_170262
      T_170265[6] := T_170263
      T_170265[7] := T_170264
      node T_170266 = subw(UInt<36>(0), UInt<6>(36))
      node T_170267 = subw(UInt<36>(0), UInt<6>(36))
      node T_170268 = subw(UInt<36>(0), UInt<6>(36))
      node T_170269 = subw(UInt<36>(0), UInt<6>(36))
      node T_170270 = subw(UInt<36>(0), UInt<6>(36))
      node T_170271 = subw(UInt<36>(0), UInt<6>(36))
      node T_170272 = subw(UInt<36>(0), UInt<6>(36))
      node T_170273 = subw(UInt<36>(0), UInt<6>(36))
      wire T_170274 : UInt<36>[8]
      T_170274[0] := T_170266
      T_170274[1] := T_170267
      T_170274[2] := T_170268
      T_170274[3] := T_170269
      T_170274[4] := T_170270
      T_170274[5] := T_170271
      T_170274[6] := T_170272
      T_170274[7] := T_170273
      node T_170275 = cat(T_170274[7], T_170274[6])
      node T_170276 = cat(T_170274[5], T_170274[4])
      node T_170277 = cat(T_170275, T_170276)
      node T_170278 = cat(T_170274[3], T_170274[2])
      node T_170279 = cat(T_170274[1], T_170274[0])
      node T_170280 = cat(T_170278, T_170279)
      node T_170281 = cat(T_170277, T_170280)
      accessor T_170282 = T_170252[waddr]
      node T_170283 = not(T_170281)
      node T_170284 = and(T_170282, T_170283)
      node T_170285 = and(T_170256, T_170281)
      node T_170286 = or(T_170284, T_170285)
      wire T_170287 : UInt<288>
      node T_170288 = bits(T_170286, 287, 0)
      T_170287 := T_170288
      accessor T_170289 = T_170252[waddr]
      T_170289 := T_170287
    reg T_170290 : UInt<12>
    when read.valid : T_170290 := read.bits.idx
    accessor tags = T_170252[T_170290]
    wire T_170291 : UInt<3>[3]
    T_170291[0] := UInt<3>(0)
    T_170291[1] := UInt<3>(1)
    T_170291[2] := UInt<3>(2)
    wire T_170292 : UInt<2>[2]
    T_170292[0] := UInt<2>(0)
    T_170292[1] := UInt<2>(1)
    wire T_170293 : UInt<2>[3]
    T_170293[0] := UInt<2>(1)
    T_170293[1] := UInt<2>(2)
    T_170293[2] := UInt<2>(3)
    wire T_170294 : UInt<2>[2]
    T_170294[0] := UInt<2>(2)
    T_170294[1] := UInt<2>(3)
    wire T_170295 : UInt<2>[1]
    T_170295[0] := UInt<2>(3)
    wire T_170296 : UInt<3>[3]
    T_170296[0] := UInt<3>(0)
    T_170296[1] := UInt<3>(1)
    T_170296[2] := UInt<3>(2)
    wire T_170297 : UInt<2>[2]
    T_170297[0] := UInt<2>(0)
    T_170297[1] := UInt<2>(1)
    wire T_170298 : UInt<2>[3]
    T_170298[0] := UInt<2>(1)
    T_170298[1] := UInt<2>(2)
    T_170298[2] := UInt<2>(3)
    wire T_170299 : UInt<2>[2]
    T_170299[0] := UInt<2>(2)
    T_170299[1] := UInt<2>(3)
    wire T_170300 : UInt<2>[1]
    T_170300[0] := UInt<2>(3)
    wire T_170301 : UInt<3>[3]
    T_170301[0] := UInt<3>(0)
    T_170301[1] := UInt<3>(1)
    T_170301[2] := UInt<3>(2)
    wire T_170302 : UInt<0>[1]
    T_170302[0] := UInt<0>(0)
    wire T_170303 : UInt<2>[2]
    T_170303[0] := UInt<2>(1)
    T_170303[1] := UInt<2>(2)
    wire T_170304 : UInt<2>[2]
    T_170304[0] := UInt<2>(1)
    T_170304[1] := UInt<2>(2)
    wire T_170305 : UInt<2>[1]
    T_170305[0] := UInt<2>(2)
    wire T_170306 : UInt<3>[3]
    T_170306[0] := UInt<3>(0)
    T_170306[1] := UInt<3>(1)
    T_170306[2] := UInt<3>(2)
    wire T_170307 : UInt<2>[2]
    T_170307[0] := UInt<2>(0)
    T_170307[1] := UInt<2>(1)
    wire T_170308 : UInt<2>[3]
    T_170308[0] := UInt<2>(1)
    T_170308[1] := UInt<2>(2)
    T_170308[2] := UInt<2>(3)
    wire T_170309 : UInt<2>[2]
    T_170309[0] := UInt<2>(2)
    T_170309[1] := UInt<2>(3)
    wire T_170310 : UInt<2>[1]
    T_170310[0] := UInt<2>(3)
    wire T_170311 : UInt<3>[3]
    T_170311[0] := UInt<3>(0)
    T_170311[1] := UInt<3>(1)
    T_170311[2] := UInt<3>(2)
    wire T_170312 : UInt<2>[2]
    T_170312[0] := UInt<2>(0)
    T_170312[1] := UInt<2>(1)
    wire T_170313 : UInt<2>[3]
    T_170313[0] := UInt<2>(1)
    T_170313[1] := UInt<2>(2)
    T_170313[2] := UInt<2>(3)
    wire T_170314 : UInt<2>[2]
    T_170314[0] := UInt<2>(2)
    T_170314[1] := UInt<2>(3)
    wire T_170315 : UInt<2>[1]
    T_170315[0] := UInt<2>(3)
    wire T_170316 : UInt<3>[3]
    T_170316[0] := UInt<3>(0)
    T_170316[1] := UInt<3>(1)
    T_170316[2] := UInt<3>(2)
    wire T_170317 : UInt<0>[1]
    T_170317[0] := UInt<0>(0)
    wire T_170318 : UInt<2>[2]
    T_170318[0] := UInt<2>(1)
    T_170318[1] := UInt<2>(2)
    wire T_170319 : UInt<2>[2]
    T_170319[0] := UInt<2>(1)
    T_170319[1] := UInt<2>(2)
    wire T_170320 : UInt<2>[1]
    T_170320[0] := UInt<2>(2)
    wire T_170321 : UInt<3>[3]
    T_170321[0] := UInt<3>(0)
    T_170321[1] := UInt<3>(1)
    T_170321[2] := UInt<3>(2)
    wire T_170322 : UInt<2>[2]
    T_170322[0] := UInt<2>(0)
    T_170322[1] := UInt<2>(1)
    wire T_170323 : UInt<2>[3]
    T_170323[0] := UInt<2>(1)
    T_170323[1] := UInt<2>(2)
    T_170323[2] := UInt<2>(3)
    wire T_170324 : UInt<2>[2]
    T_170324[0] := UInt<2>(2)
    T_170324[1] := UInt<2>(3)
    wire T_170325 : UInt<2>[1]
    T_170325[0] := UInt<2>(3)
    wire T_170326 : UInt<3>[3]
    T_170326[0] := UInt<3>(0)
    T_170326[1] := UInt<3>(1)
    T_170326[2] := UInt<3>(2)
    wire T_170327 : UInt<2>[2]
    T_170327[0] := UInt<2>(0)
    T_170327[1] := UInt<2>(1)
    wire T_170328 : UInt<2>[3]
    T_170328[0] := UInt<2>(1)
    T_170328[1] := UInt<2>(2)
    T_170328[2] := UInt<2>(3)
    wire T_170329 : UInt<2>[2]
    T_170329[0] := UInt<2>(2)
    T_170329[1] := UInt<2>(3)
    wire T_170330 : UInt<2>[1]
    T_170330[0] := UInt<2>(3)
    wire T_170331 : UInt<3>[3]
    T_170331[0] := UInt<3>(0)
    T_170331[1] := UInt<3>(1)
    T_170331[2] := UInt<3>(2)
    wire T_170332 : UInt<0>[1]
    T_170332[0] := UInt<0>(0)
    wire T_170333 : UInt<2>[2]
    T_170333[0] := UInt<2>(1)
    T_170333[1] := UInt<2>(2)
    wire T_170334 : UInt<2>[2]
    T_170334[0] := UInt<2>(1)
    T_170334[1] := UInt<2>(2)
    wire T_170335 : UInt<2>[1]
    T_170335[0] := UInt<2>(2)
    wire T_170336 : UInt<3>[3]
    T_170336[0] := UInt<3>(0)
    T_170336[1] := UInt<3>(1)
    T_170336[2] := UInt<3>(2)
    wire T_170337 : UInt<2>[2]
    T_170337[0] := UInt<2>(0)
    T_170337[1] := UInt<2>(1)
    wire T_170338 : UInt<2>[3]
    T_170338[0] := UInt<2>(1)
    T_170338[1] := UInt<2>(2)
    T_170338[2] := UInt<2>(3)
    wire T_170339 : UInt<2>[2]
    T_170339[0] := UInt<2>(2)
    T_170339[1] := UInt<2>(3)
    wire T_170340 : UInt<2>[1]
    T_170340[0] := UInt<2>(3)
    wire T_170341 : UInt<3>[3]
    T_170341[0] := UInt<3>(0)
    T_170341[1] := UInt<3>(1)
    T_170341[2] := UInt<3>(2)
    wire T_170342 : UInt<2>[2]
    T_170342[0] := UInt<2>(0)
    T_170342[1] := UInt<2>(1)
    wire T_170343 : UInt<2>[3]
    T_170343[0] := UInt<2>(1)
    T_170343[1] := UInt<2>(2)
    T_170343[2] := UInt<2>(3)
    wire T_170344 : UInt<2>[2]
    T_170344[0] := UInt<2>(2)
    T_170344[1] := UInt<2>(3)
    wire T_170345 : UInt<2>[1]
    T_170345[0] := UInt<2>(3)
    wire T_170346 : UInt<3>[3]
    T_170346[0] := UInt<3>(0)
    T_170346[1] := UInt<3>(1)
    T_170346[2] := UInt<3>(2)
    wire T_170347 : UInt<0>[1]
    T_170347[0] := UInt<0>(0)
    wire T_170348 : UInt<2>[2]
    T_170348[0] := UInt<2>(1)
    T_170348[1] := UInt<2>(2)
    wire T_170349 : UInt<2>[2]
    T_170349[0] := UInt<2>(1)
    T_170349[1] := UInt<2>(2)
    wire T_170350 : UInt<2>[1]
    T_170350[0] := UInt<2>(2)
    wire T_170351 : UInt<3>[3]
    T_170351[0] := UInt<3>(0)
    T_170351[1] := UInt<3>(1)
    T_170351[2] := UInt<3>(2)
    wire T_170352 : UInt<2>[2]
    T_170352[0] := UInt<2>(0)
    T_170352[1] := UInt<2>(1)
    wire T_170353 : UInt<2>[3]
    T_170353[0] := UInt<2>(1)
    T_170353[1] := UInt<2>(2)
    T_170353[2] := UInt<2>(3)
    wire T_170354 : UInt<2>[2]
    T_170354[0] := UInt<2>(2)
    T_170354[1] := UInt<2>(3)
    wire T_170355 : UInt<2>[1]
    T_170355[0] := UInt<2>(3)
    wire T_170356 : UInt<3>[3]
    T_170356[0] := UInt<3>(0)
    T_170356[1] := UInt<3>(1)
    T_170356[2] := UInt<3>(2)
    wire T_170357 : UInt<2>[2]
    T_170357[0] := UInt<2>(0)
    T_170357[1] := UInt<2>(1)
    wire T_170358 : UInt<2>[3]
    T_170358[0] := UInt<2>(1)
    T_170358[1] := UInt<2>(2)
    T_170358[2] := UInt<2>(3)
    wire T_170359 : UInt<2>[2]
    T_170359[0] := UInt<2>(2)
    T_170359[1] := UInt<2>(3)
    wire T_170360 : UInt<2>[1]
    T_170360[0] := UInt<2>(3)
    wire T_170361 : UInt<3>[3]
    T_170361[0] := UInt<3>(0)
    T_170361[1] := UInt<3>(1)
    T_170361[2] := UInt<3>(2)
    wire T_170362 : UInt<0>[1]
    T_170362[0] := UInt<0>(0)
    wire T_170363 : UInt<2>[2]
    T_170363[0] := UInt<2>(1)
    T_170363[1] := UInt<2>(2)
    wire T_170364 : UInt<2>[2]
    T_170364[0] := UInt<2>(1)
    T_170364[1] := UInt<2>(2)
    wire T_170365 : UInt<2>[1]
    T_170365[0] := UInt<2>(2)
    wire T_170366 : UInt<3>[3]
    T_170366[0] := UInt<3>(0)
    T_170366[1] := UInt<3>(1)
    T_170366[2] := UInt<3>(2)
    wire T_170367 : UInt<2>[2]
    T_170367[0] := UInt<2>(0)
    T_170367[1] := UInt<2>(1)
    wire T_170368 : UInt<2>[3]
    T_170368[0] := UInt<2>(1)
    T_170368[1] := UInt<2>(2)
    T_170368[2] := UInt<2>(3)
    wire T_170369 : UInt<2>[2]
    T_170369[0] := UInt<2>(2)
    T_170369[1] := UInt<2>(3)
    wire T_170370 : UInt<2>[1]
    T_170370[0] := UInt<2>(3)
    wire T_170371 : UInt<3>[3]
    T_170371[0] := UInt<3>(0)
    T_170371[1] := UInt<3>(1)
    T_170371[2] := UInt<3>(2)
    wire T_170372 : UInt<2>[2]
    T_170372[0] := UInt<2>(0)
    T_170372[1] := UInt<2>(1)
    wire T_170373 : UInt<2>[3]
    T_170373[0] := UInt<2>(1)
    T_170373[1] := UInt<2>(2)
    T_170373[2] := UInt<2>(3)
    wire T_170374 : UInt<2>[2]
    T_170374[0] := UInt<2>(2)
    T_170374[1] := UInt<2>(3)
    wire T_170375 : UInt<2>[1]
    T_170375[0] := UInt<2>(3)
    wire T_170376 : UInt<3>[3]
    T_170376[0] := UInt<3>(0)
    T_170376[1] := UInt<3>(1)
    T_170376[2] := UInt<3>(2)
    wire T_170377 : UInt<0>[1]
    T_170377[0] := UInt<0>(0)
    wire T_170378 : UInt<2>[2]
    T_170378[0] := UInt<2>(1)
    T_170378[1] := UInt<2>(2)
    wire T_170379 : UInt<2>[2]
    T_170379[0] := UInt<2>(1)
    T_170379[1] := UInt<2>(2)
    wire T_170380 : UInt<2>[1]
    T_170380[0] := UInt<2>(2)
    wire T_170381 : UInt<3>[3]
    T_170381[0] := UInt<3>(0)
    T_170381[1] := UInt<3>(1)
    T_170381[2] := UInt<3>(2)
    wire T_170382 : UInt<2>[2]
    T_170382[0] := UInt<2>(0)
    T_170382[1] := UInt<2>(1)
    wire T_170383 : UInt<2>[3]
    T_170383[0] := UInt<2>(1)
    T_170383[1] := UInt<2>(2)
    T_170383[2] := UInt<2>(3)
    wire T_170384 : UInt<2>[2]
    T_170384[0] := UInt<2>(2)
    T_170384[1] := UInt<2>(3)
    wire T_170385 : UInt<2>[1]
    T_170385[0] := UInt<2>(3)
    wire T_170386 : UInt<3>[3]
    T_170386[0] := UInt<3>(0)
    T_170386[1] := UInt<3>(1)
    T_170386[2] := UInt<3>(2)
    wire T_170387 : UInt<2>[2]
    T_170387[0] := UInt<2>(0)
    T_170387[1] := UInt<2>(1)
    wire T_170388 : UInt<2>[3]
    T_170388[0] := UInt<2>(1)
    T_170388[1] := UInt<2>(2)
    T_170388[2] := UInt<2>(3)
    wire T_170389 : UInt<2>[2]
    T_170389[0] := UInt<2>(2)
    T_170389[1] := UInt<2>(3)
    wire T_170390 : UInt<2>[1]
    T_170390[0] := UInt<2>(3)
    wire T_170391 : UInt<3>[3]
    T_170391[0] := UInt<3>(0)
    T_170391[1] := UInt<3>(1)
    T_170391[2] := UInt<3>(2)
    wire T_170392 : UInt<0>[1]
    T_170392[0] := UInt<0>(0)
    wire T_170393 : UInt<2>[2]
    T_170393[0] := UInt<2>(1)
    T_170393[1] := UInt<2>(2)
    wire T_170394 : UInt<2>[2]
    T_170394[0] := UInt<2>(1)
    T_170394[1] := UInt<2>(2)
    wire T_170395 : UInt<2>[1]
    T_170395[0] := UInt<2>(2)
    wire T_170396 : UInt<3>[3]
    T_170396[0] := UInt<3>(0)
    T_170396[1] := UInt<3>(1)
    T_170396[2] := UInt<3>(2)
    wire T_170397 : UInt<2>[2]
    T_170397[0] := UInt<2>(0)
    T_170397[1] := UInt<2>(1)
    wire T_170398 : UInt<2>[3]
    T_170398[0] := UInt<2>(1)
    T_170398[1] := UInt<2>(2)
    T_170398[2] := UInt<2>(3)
    wire T_170399 : UInt<2>[2]
    T_170399[0] := UInt<2>(2)
    T_170399[1] := UInt<2>(3)
    wire T_170400 : UInt<2>[1]
    T_170400[0] := UInt<2>(3)
    wire T_170401 : UInt<3>[3]
    T_170401[0] := UInt<3>(0)
    T_170401[1] := UInt<3>(1)
    T_170401[2] := UInt<3>(2)
    wire T_170402 : UInt<2>[2]
    T_170402[0] := UInt<2>(0)
    T_170402[1] := UInt<2>(1)
    wire T_170403 : UInt<2>[3]
    T_170403[0] := UInt<2>(1)
    T_170403[1] := UInt<2>(2)
    T_170403[2] := UInt<2>(3)
    wire T_170404 : UInt<2>[2]
    T_170404[0] := UInt<2>(2)
    T_170404[1] := UInt<2>(3)
    wire T_170405 : UInt<2>[1]
    T_170405[0] := UInt<2>(3)
    wire T_170406 : UInt<3>[3]
    T_170406[0] := UInt<3>(0)
    T_170406[1] := UInt<3>(1)
    T_170406[2] := UInt<3>(2)
    wire T_170407 : UInt<0>[1]
    T_170407[0] := UInt<0>(0)
    wire T_170408 : UInt<2>[2]
    T_170408[0] := UInt<2>(1)
    T_170408[1] := UInt<2>(2)
    wire T_170409 : UInt<2>[2]
    T_170409[0] := UInt<2>(1)
    T_170409[1] := UInt<2>(2)
    wire T_170410 : UInt<2>[1]
    T_170410[0] := UInt<2>(2)
    wire T_170411 : UInt<3>[3]
    T_170411[0] := UInt<3>(0)
    T_170411[1] := UInt<3>(1)
    T_170411[2] := UInt<3>(2)
    wire T_170412 : UInt<2>[2]
    T_170412[0] := UInt<2>(0)
    T_170412[1] := UInt<2>(1)
    wire T_170413 : UInt<2>[3]
    T_170413[0] := UInt<2>(1)
    T_170413[1] := UInt<2>(2)
    T_170413[2] := UInt<2>(3)
    wire T_170414 : UInt<2>[2]
    T_170414[0] := UInt<2>(2)
    T_170414[1] := UInt<2>(3)
    wire T_170415 : UInt<2>[1]
    T_170415[0] := UInt<2>(3)
    wire T_170416 : UInt<3>[3]
    T_170416[0] := UInt<3>(0)
    T_170416[1] := UInt<3>(1)
    T_170416[2] := UInt<3>(2)
    wire T_170417 : UInt<2>[2]
    T_170417[0] := UInt<2>(0)
    T_170417[1] := UInt<2>(1)
    wire T_170418 : UInt<2>[3]
    T_170418[0] := UInt<2>(1)
    T_170418[1] := UInt<2>(2)
    T_170418[2] := UInt<2>(3)
    wire T_170419 : UInt<2>[2]
    T_170419[0] := UInt<2>(2)
    T_170419[1] := UInt<2>(3)
    wire T_170420 : UInt<2>[1]
    T_170420[0] := UInt<2>(3)
    wire T_170421 : UInt<3>[3]
    T_170421[0] := UInt<3>(0)
    T_170421[1] := UInt<3>(1)
    T_170421[2] := UInt<3>(2)
    wire T_170422 : UInt<0>[1]
    T_170422[0] := UInt<0>(0)
    wire T_170423 : UInt<2>[2]
    T_170423[0] := UInt<2>(1)
    T_170423[1] := UInt<2>(2)
    wire T_170424 : UInt<2>[2]
    T_170424[0] := UInt<2>(1)
    T_170424[1] := UInt<2>(2)
    wire T_170425 : UInt<2>[1]
    T_170425[0] := UInt<2>(2)
    wire T_170426 : UInt<3>[3]
    T_170426[0] := UInt<3>(0)
    T_170426[1] := UInt<3>(1)
    T_170426[2] := UInt<3>(2)
    wire T_170427 : UInt<2>[2]
    T_170427[0] := UInt<2>(0)
    T_170427[1] := UInt<2>(1)
    wire T_170428 : UInt<2>[3]
    T_170428[0] := UInt<2>(1)
    T_170428[1] := UInt<2>(2)
    T_170428[2] := UInt<2>(3)
    wire T_170429 : UInt<2>[2]
    T_170429[0] := UInt<2>(2)
    T_170429[1] := UInt<2>(3)
    wire T_170430 : UInt<2>[1]
    T_170430[0] := UInt<2>(3)
    wire T_170431 : UInt<3>[3]
    T_170431[0] := UInt<3>(0)
    T_170431[1] := UInt<3>(1)
    T_170431[2] := UInt<3>(2)
    wire T_170432 : UInt<2>[2]
    T_170432[0] := UInt<2>(0)
    T_170432[1] := UInt<2>(1)
    wire T_170433 : UInt<2>[3]
    T_170433[0] := UInt<2>(1)
    T_170433[1] := UInt<2>(2)
    T_170433[2] := UInt<2>(3)
    wire T_170434 : UInt<2>[2]
    T_170434[0] := UInt<2>(2)
    T_170434[1] := UInt<2>(3)
    wire T_170435 : UInt<2>[1]
    T_170435[0] := UInt<2>(3)
    wire T_170436 : UInt<3>[3]
    T_170436[0] := UInt<3>(0)
    T_170436[1] := UInt<3>(1)
    T_170436[2] := UInt<3>(2)
    wire T_170437 : UInt<0>[1]
    T_170437[0] := UInt<0>(0)
    wire T_170438 : UInt<2>[2]
    T_170438[0] := UInt<2>(1)
    T_170438[1] := UInt<2>(2)
    wire T_170439 : UInt<2>[2]
    T_170439[0] := UInt<2>(1)
    T_170439[1] := UInt<2>(2)
    wire T_170440 : UInt<2>[1]
    T_170440[0] := UInt<2>(2)
    wire T_170441 : UInt<3>[3]
    T_170441[0] := UInt<3>(0)
    T_170441[1] := UInt<3>(1)
    T_170441[2] := UInt<3>(2)
    wire T_170442 : UInt<2>[2]
    T_170442[0] := UInt<2>(0)
    T_170442[1] := UInt<2>(1)
    wire T_170443 : UInt<2>[3]
    T_170443[0] := UInt<2>(1)
    T_170443[1] := UInt<2>(2)
    T_170443[2] := UInt<2>(3)
    wire T_170444 : UInt<2>[2]
    T_170444[0] := UInt<2>(2)
    T_170444[1] := UInt<2>(3)
    wire T_170445 : UInt<2>[1]
    T_170445[0] := UInt<2>(3)
    wire T_170446 : UInt<3>[3]
    T_170446[0] := UInt<3>(0)
    T_170446[1] := UInt<3>(1)
    T_170446[2] := UInt<3>(2)
    wire T_170447 : UInt<2>[2]
    T_170447[0] := UInt<2>(0)
    T_170447[1] := UInt<2>(1)
    wire T_170448 : UInt<2>[3]
    T_170448[0] := UInt<2>(1)
    T_170448[1] := UInt<2>(2)
    T_170448[2] := UInt<2>(3)
    wire T_170449 : UInt<2>[2]
    T_170449[0] := UInt<2>(2)
    T_170449[1] := UInt<2>(3)
    wire T_170450 : UInt<2>[1]
    T_170450[0] := UInt<2>(3)
    wire T_170451 : UInt<3>[3]
    T_170451[0] := UInt<3>(0)
    T_170451[1] := UInt<3>(1)
    T_170451[2] := UInt<3>(2)
    wire T_170452 : UInt<0>[1]
    T_170452[0] := UInt<0>(0)
    wire T_170453 : UInt<2>[2]
    T_170453[0] := UInt<2>(1)
    T_170453[1] := UInt<2>(2)
    wire T_170454 : UInt<2>[2]
    T_170454[0] := UInt<2>(1)
    T_170454[1] := UInt<2>(2)
    wire T_170455 : UInt<2>[1]
    T_170455[0] := UInt<2>(2)
    wire T_170456 : UInt<3>[3]
    T_170456[0] := UInt<3>(0)
    T_170456[1] := UInt<3>(1)
    T_170456[2] := UInt<3>(2)
    wire T_170457 : UInt<2>[2]
    T_170457[0] := UInt<2>(0)
    T_170457[1] := UInt<2>(1)
    wire T_170458 : UInt<2>[3]
    T_170458[0] := UInt<2>(1)
    T_170458[1] := UInt<2>(2)
    T_170458[2] := UInt<2>(3)
    wire T_170459 : UInt<2>[2]
    T_170459[0] := UInt<2>(2)
    T_170459[1] := UInt<2>(3)
    wire T_170460 : UInt<2>[1]
    T_170460[0] := UInt<2>(3)
    wire T_170461 : UInt<3>[3]
    T_170461[0] := UInt<3>(0)
    T_170461[1] := UInt<3>(1)
    T_170461[2] := UInt<3>(2)
    wire T_170462 : UInt<2>[2]
    T_170462[0] := UInt<2>(0)
    T_170462[1] := UInt<2>(1)
    wire T_170463 : UInt<2>[3]
    T_170463[0] := UInt<2>(1)
    T_170463[1] := UInt<2>(2)
    T_170463[2] := UInt<2>(3)
    wire T_170464 : UInt<2>[2]
    T_170464[0] := UInt<2>(2)
    T_170464[1] := UInt<2>(3)
    wire T_170465 : UInt<2>[1]
    T_170465[0] := UInt<2>(3)
    wire T_170466 : UInt<3>[3]
    T_170466[0] := UInt<3>(0)
    T_170466[1] := UInt<3>(1)
    T_170466[2] := UInt<3>(2)
    wire T_170467 : UInt<0>[1]
    T_170467[0] := UInt<0>(0)
    wire T_170468 : UInt<2>[2]
    T_170468[0] := UInt<2>(1)
    T_170468[1] := UInt<2>(2)
    wire T_170469 : UInt<2>[2]
    T_170469[0] := UInt<2>(1)
    T_170469[1] := UInt<2>(2)
    wire T_170470 : UInt<2>[1]
    T_170470[0] := UInt<2>(2)
    wire T_170471 : UInt<3>[3]
    T_170471[0] := UInt<3>(0)
    T_170471[1] := UInt<3>(1)
    T_170471[2] := UInt<3>(2)
    wire T_170472 : UInt<2>[2]
    T_170472[0] := UInt<2>(0)
    T_170472[1] := UInt<2>(1)
    wire T_170473 : UInt<2>[3]
    T_170473[0] := UInt<2>(1)
    T_170473[1] := UInt<2>(2)
    T_170473[2] := UInt<2>(3)
    wire T_170474 : UInt<2>[2]
    T_170474[0] := UInt<2>(2)
    T_170474[1] := UInt<2>(3)
    wire T_170475 : UInt<2>[1]
    T_170475[0] := UInt<2>(3)
    wire T_170476 : UInt<3>[3]
    T_170476[0] := UInt<3>(0)
    T_170476[1] := UInt<3>(1)
    T_170476[2] := UInt<3>(2)
    wire T_170477 : UInt<2>[2]
    T_170477[0] := UInt<2>(0)
    T_170477[1] := UInt<2>(1)
    wire T_170478 : UInt<2>[3]
    T_170478[0] := UInt<2>(1)
    T_170478[1] := UInt<2>(2)
    T_170478[2] := UInt<2>(3)
    wire T_170479 : UInt<2>[2]
    T_170479[0] := UInt<2>(2)
    T_170479[1] := UInt<2>(3)
    wire T_170480 : UInt<2>[1]
    T_170480[0] := UInt<2>(3)
    wire T_170481 : UInt<3>[3]
    T_170481[0] := UInt<3>(0)
    T_170481[1] := UInt<3>(1)
    T_170481[2] := UInt<3>(2)
    wire T_170482 : UInt<0>[1]
    T_170482[0] := UInt<0>(0)
    wire T_170483 : UInt<2>[2]
    T_170483[0] := UInt<2>(1)
    T_170483[1] := UInt<2>(2)
    wire T_170484 : UInt<2>[2]
    T_170484[0] := UInt<2>(1)
    T_170484[1] := UInt<2>(2)
    wire T_170485 : UInt<2>[1]
    T_170485[0] := UInt<2>(2)
    wire T_170486 : UInt<3>[3]
    T_170486[0] := UInt<3>(0)
    T_170486[1] := UInt<3>(1)
    T_170486[2] := UInt<3>(2)
    wire T_170487 : UInt<2>[2]
    T_170487[0] := UInt<2>(0)
    T_170487[1] := UInt<2>(1)
    wire T_170488 : UInt<2>[3]
    T_170488[0] := UInt<2>(1)
    T_170488[1] := UInt<2>(2)
    T_170488[2] := UInt<2>(3)
    wire T_170489 : UInt<2>[2]
    T_170489[0] := UInt<2>(2)
    T_170489[1] := UInt<2>(3)
    wire T_170490 : UInt<2>[1]
    T_170490[0] := UInt<2>(3)
    wire T_170491 : UInt<3>[3]
    T_170491[0] := UInt<3>(0)
    T_170491[1] := UInt<3>(1)
    T_170491[2] := UInt<3>(2)
    wire T_170492 : UInt<2>[2]
    T_170492[0] := UInt<2>(0)
    T_170492[1] := UInt<2>(1)
    wire T_170493 : UInt<2>[3]
    T_170493[0] := UInt<2>(1)
    T_170493[1] := UInt<2>(2)
    T_170493[2] := UInt<2>(3)
    wire T_170494 : UInt<2>[2]
    T_170494[0] := UInt<2>(2)
    T_170494[1] := UInt<2>(3)
    wire T_170495 : UInt<2>[1]
    T_170495[0] := UInt<2>(3)
    wire T_170496 : UInt<3>[3]
    T_170496[0] := UInt<3>(0)
    T_170496[1] := UInt<3>(1)
    T_170496[2] := UInt<3>(2)
    wire T_170497 : UInt<0>[1]
    T_170497[0] := UInt<0>(0)
    wire T_170498 : UInt<2>[2]
    T_170498[0] := UInt<2>(1)
    T_170498[1] := UInt<2>(2)
    wire T_170499 : UInt<2>[2]
    T_170499[0] := UInt<2>(1)
    T_170499[1] := UInt<2>(2)
    wire T_170500 : UInt<2>[1]
    T_170500[0] := UInt<2>(2)
    wire T_170501 : UInt<3>[3]
    T_170501[0] := UInt<3>(0)
    T_170501[1] := UInt<3>(1)
    T_170501[2] := UInt<3>(2)
    wire T_170502 : UInt<2>[2]
    T_170502[0] := UInt<2>(0)
    T_170502[1] := UInt<2>(1)
    wire T_170503 : UInt<2>[3]
    T_170503[0] := UInt<2>(1)
    T_170503[1] := UInt<2>(2)
    T_170503[2] := UInt<2>(3)
    wire T_170504 : UInt<2>[2]
    T_170504[0] := UInt<2>(2)
    T_170504[1] := UInt<2>(3)
    wire T_170505 : UInt<2>[1]
    T_170505[0] := UInt<2>(3)
    wire T_170506 : UInt<3>[3]
    T_170506[0] := UInt<3>(0)
    T_170506[1] := UInt<3>(1)
    T_170506[2] := UInt<3>(2)
    wire T_170507 : UInt<2>[2]
    T_170507[0] := UInt<2>(0)
    T_170507[1] := UInt<2>(1)
    wire T_170508 : UInt<2>[3]
    T_170508[0] := UInt<2>(1)
    T_170508[1] := UInt<2>(2)
    T_170508[2] := UInt<2>(3)
    wire T_170509 : UInt<2>[2]
    T_170509[0] := UInt<2>(2)
    T_170509[1] := UInt<2>(3)
    wire T_170510 : UInt<2>[1]
    T_170510[0] := UInt<2>(3)
    wire T_170511 : UInt<3>[3]
    T_170511[0] := UInt<3>(0)
    T_170511[1] := UInt<3>(1)
    T_170511[2] := UInt<3>(2)
    wire T_170512 : UInt<0>[1]
    T_170512[0] := UInt<0>(0)
    wire T_170513 : UInt<2>[2]
    T_170513[0] := UInt<2>(1)
    T_170513[1] := UInt<2>(2)
    wire T_170514 : UInt<2>[2]
    T_170514[0] := UInt<2>(1)
    T_170514[1] := UInt<2>(2)
    wire T_170515 : UInt<2>[1]
    T_170515[0] := UInt<2>(2)
    wire T_170516 : UInt<3>[3]
    T_170516[0] := UInt<3>(0)
    T_170516[1] := UInt<3>(1)
    T_170516[2] := UInt<3>(2)
    wire T_170517 : UInt<2>[2]
    T_170517[0] := UInt<2>(0)
    T_170517[1] := UInt<2>(1)
    wire T_170518 : UInt<2>[3]
    T_170518[0] := UInt<2>(1)
    T_170518[1] := UInt<2>(2)
    T_170518[2] := UInt<2>(3)
    wire T_170519 : UInt<2>[2]
    T_170519[0] := UInt<2>(2)
    T_170519[1] := UInt<2>(3)
    wire T_170520 : UInt<2>[1]
    T_170520[0] := UInt<2>(3)
    wire T_170521 : UInt<3>[3]
    T_170521[0] := UInt<3>(0)
    T_170521[1] := UInt<3>(1)
    T_170521[2] := UInt<3>(2)
    wire T_170522 : UInt<2>[2]
    T_170522[0] := UInt<2>(0)
    T_170522[1] := UInt<2>(1)
    wire T_170523 : UInt<2>[3]
    T_170523[0] := UInt<2>(1)
    T_170523[1] := UInt<2>(2)
    T_170523[2] := UInt<2>(3)
    wire T_170524 : UInt<2>[2]
    T_170524[0] := UInt<2>(2)
    T_170524[1] := UInt<2>(3)
    wire T_170525 : UInt<2>[1]
    T_170525[0] := UInt<2>(3)
    wire T_170526 : UInt<3>[3]
    T_170526[0] := UInt<3>(0)
    T_170526[1] := UInt<3>(1)
    T_170526[2] := UInt<3>(2)
    wire T_170527 : UInt<0>[1]
    T_170527[0] := UInt<0>(0)
    wire T_170528 : UInt<2>[2]
    T_170528[0] := UInt<2>(1)
    T_170528[1] := UInt<2>(2)
    wire T_170529 : UInt<2>[2]
    T_170529[0] := UInt<2>(1)
    T_170529[1] := UInt<2>(2)
    wire T_170530 : UInt<2>[1]
    T_170530[0] := UInt<2>(2)
    wire T_170531 : UInt<3>[3]
    T_170531[0] := UInt<3>(0)
    T_170531[1] := UInt<3>(1)
    T_170531[2] := UInt<3>(2)
    wire T_170532 : UInt<2>[2]
    T_170532[0] := UInt<2>(0)
    T_170532[1] := UInt<2>(1)
    wire T_170533 : UInt<2>[3]
    T_170533[0] := UInt<2>(1)
    T_170533[1] := UInt<2>(2)
    T_170533[2] := UInt<2>(3)
    wire T_170534 : UInt<2>[2]
    T_170534[0] := UInt<2>(2)
    T_170534[1] := UInt<2>(3)
    wire T_170535 : UInt<2>[1]
    T_170535[0] := UInt<2>(3)
    wire T_170536 : UInt<3>[3]
    T_170536[0] := UInt<3>(0)
    T_170536[1] := UInt<3>(1)
    T_170536[2] := UInt<3>(2)
    wire T_170537 : UInt<2>[2]
    T_170537[0] := UInt<2>(0)
    T_170537[1] := UInt<2>(1)
    wire T_170538 : UInt<2>[3]
    T_170538[0] := UInt<2>(1)
    T_170538[1] := UInt<2>(2)
    T_170538[2] := UInt<2>(3)
    wire T_170539 : UInt<2>[2]
    T_170539[0] := UInt<2>(2)
    T_170539[1] := UInt<2>(3)
    wire T_170540 : UInt<2>[1]
    T_170540[0] := UInt<2>(3)
    wire T_170541 : UInt<3>[3]
    T_170541[0] := UInt<3>(0)
    T_170541[1] := UInt<3>(1)
    T_170541[2] := UInt<3>(2)
    wire T_170542 : UInt<0>[1]
    T_170542[0] := UInt<0>(0)
    wire T_170543 : UInt<2>[2]
    T_170543[0] := UInt<2>(1)
    T_170543[1] := UInt<2>(2)
    wire T_170544 : UInt<2>[2]
    T_170544[0] := UInt<2>(1)
    T_170544[1] := UInt<2>(2)
    wire T_170545 : UInt<2>[1]
    T_170545[0] := UInt<2>(2)
    wire T_170546 : UInt<3>[3]
    T_170546[0] := UInt<3>(0)
    T_170546[1] := UInt<3>(1)
    T_170546[2] := UInt<3>(2)
    wire T_170547 : UInt<2>[2]
    T_170547[0] := UInt<2>(0)
    T_170547[1] := UInt<2>(1)
    wire T_170548 : UInt<2>[3]
    T_170548[0] := UInt<2>(1)
    T_170548[1] := UInt<2>(2)
    T_170548[2] := UInt<2>(3)
    wire T_170549 : UInt<2>[2]
    T_170549[0] := UInt<2>(2)
    T_170549[1] := UInt<2>(3)
    wire T_170550 : UInt<2>[1]
    T_170550[0] := UInt<2>(3)
    wire T_170551 : UInt<3>[3]
    T_170551[0] := UInt<3>(0)
    T_170551[1] := UInt<3>(1)
    T_170551[2] := UInt<3>(2)
    wire T_170552 : UInt<2>[2]
    T_170552[0] := UInt<2>(0)
    T_170552[1] := UInt<2>(1)
    wire T_170553 : UInt<2>[3]
    T_170553[0] := UInt<2>(1)
    T_170553[1] := UInt<2>(2)
    T_170553[2] := UInt<2>(3)
    wire T_170554 : UInt<2>[2]
    T_170554[0] := UInt<2>(2)
    T_170554[1] := UInt<2>(3)
    wire T_170555 : UInt<2>[1]
    T_170555[0] := UInt<2>(3)
    wire T_170556 : UInt<3>[3]
    T_170556[0] := UInt<3>(0)
    T_170556[1] := UInt<3>(1)
    T_170556[2] := UInt<3>(2)
    wire T_170557 : UInt<0>[1]
    T_170557[0] := UInt<0>(0)
    wire T_170558 : UInt<2>[2]
    T_170558[0] := UInt<2>(1)
    T_170558[1] := UInt<2>(2)
    wire T_170559 : UInt<2>[2]
    T_170559[0] := UInt<2>(1)
    T_170559[1] := UInt<2>(2)
    wire T_170560 : UInt<2>[1]
    T_170560[0] := UInt<2>(2)
    wire T_170561 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}[8]
    node T_170562 = bits(tags, 0, 0)
    T_170561[0].coh.outer.makeVoluntaryWriteback$default$4 := T_170562
    node T_170563 = bits(tags, 1, 1)
    T_170561[0].coh.outer.makeVoluntaryWriteback$default$3 := T_170563
    node T_170564 = bits(tags, 2, 2)
    T_170561[0].coh.outer.makeVoluntaryRelease$default$5 := T_170564
    node T_170565 = bits(tags, 3, 3)
    T_170561[0].coh.outer.makeVoluntaryRelease$default$4 := T_170565
    node T_170566 = bits(tags, 4, 4)
    T_170561[0].coh.outer.makeRelease$default$3 := T_170566
    node T_170567 = bits(tags, 5, 5)
    T_170561[0].coh.outer.makeRelease$default$2 := T_170567
    node T_170568 = bits(tags, 7, 6)
    T_170561[0].coh.outer.state := T_170568
    node T_170569 = bits(tags, 8, 8)
    T_170561[0].coh.inner.makeGrant$default$4 := T_170569
    node T_170570 = bits(tags, 9, 9)
    T_170561[0].coh.inner.makeGrant$default$3 := T_170570
    node T_170571 = bits(tags, 10, 10)
    T_170561[0].coh.inner.sharers := T_170571
    node T_170572 = bits(tags, 11, 11)
    T_170561[0].coh.outer.makeVoluntaryWriteback$default$4 := T_170572
    node T_170573 = bits(tags, 12, 12)
    T_170561[0].coh.outer.makeVoluntaryWriteback$default$3 := T_170573
    node T_170574 = bits(tags, 13, 13)
    T_170561[0].coh.outer.makeVoluntaryRelease$default$5 := T_170574
    node T_170575 = bits(tags, 14, 14)
    T_170561[0].coh.outer.makeVoluntaryRelease$default$4 := T_170575
    node T_170576 = bits(tags, 15, 15)
    T_170561[0].coh.outer.makeRelease$default$3 := T_170576
    node T_170577 = bits(tags, 16, 16)
    T_170561[0].coh.outer.makeRelease$default$2 := T_170577
    node T_170578 = bits(tags, 18, 17)
    T_170561[0].coh.outer.state := T_170578
    node T_170579 = bits(tags, 19, 19)
    T_170561[0].coh.inner.makeGrant$default$4 := T_170579
    node T_170580 = bits(tags, 20, 20)
    T_170561[0].coh.inner.makeGrant$default$3 := T_170580
    node T_170581 = bits(tags, 21, 21)
    T_170561[0].coh.inner.sharers := T_170581
    node T_170582 = bits(tags, 35, 22)
    T_170561[0].tag := T_170582
    node T_170583 = bits(tags, 36, 36)
    T_170561[1].coh.outer.makeVoluntaryWriteback$default$4 := T_170583
    node T_170584 = bits(tags, 37, 37)
    T_170561[1].coh.outer.makeVoluntaryWriteback$default$3 := T_170584
    node T_170585 = bits(tags, 38, 38)
    T_170561[1].coh.outer.makeVoluntaryRelease$default$5 := T_170585
    node T_170586 = bits(tags, 39, 39)
    T_170561[1].coh.outer.makeVoluntaryRelease$default$4 := T_170586
    node T_170587 = bits(tags, 40, 40)
    T_170561[1].coh.outer.makeRelease$default$3 := T_170587
    node T_170588 = bits(tags, 41, 41)
    T_170561[1].coh.outer.makeRelease$default$2 := T_170588
    node T_170589 = bits(tags, 43, 42)
    T_170561[1].coh.outer.state := T_170589
    node T_170590 = bits(tags, 44, 44)
    T_170561[1].coh.inner.makeGrant$default$4 := T_170590
    node T_170591 = bits(tags, 45, 45)
    T_170561[1].coh.inner.makeGrant$default$3 := T_170591
    node T_170592 = bits(tags, 46, 46)
    T_170561[1].coh.inner.sharers := T_170592
    node T_170593 = bits(tags, 47, 47)
    T_170561[1].coh.outer.makeVoluntaryWriteback$default$4 := T_170593
    node T_170594 = bits(tags, 48, 48)
    T_170561[1].coh.outer.makeVoluntaryWriteback$default$3 := T_170594
    node T_170595 = bits(tags, 49, 49)
    T_170561[1].coh.outer.makeVoluntaryRelease$default$5 := T_170595
    node T_170596 = bits(tags, 50, 50)
    T_170561[1].coh.outer.makeVoluntaryRelease$default$4 := T_170596
    node T_170597 = bits(tags, 51, 51)
    T_170561[1].coh.outer.makeRelease$default$3 := T_170597
    node T_170598 = bits(tags, 52, 52)
    T_170561[1].coh.outer.makeRelease$default$2 := T_170598
    node T_170599 = bits(tags, 54, 53)
    T_170561[1].coh.outer.state := T_170599
    node T_170600 = bits(tags, 55, 55)
    T_170561[1].coh.inner.makeGrant$default$4 := T_170600
    node T_170601 = bits(tags, 56, 56)
    T_170561[1].coh.inner.makeGrant$default$3 := T_170601
    node T_170602 = bits(tags, 57, 57)
    T_170561[1].coh.inner.sharers := T_170602
    node T_170603 = bits(tags, 71, 58)
    T_170561[1].tag := T_170603
    node T_170604 = bits(tags, 72, 72)
    T_170561[2].coh.outer.makeVoluntaryWriteback$default$4 := T_170604
    node T_170605 = bits(tags, 73, 73)
    T_170561[2].coh.outer.makeVoluntaryWriteback$default$3 := T_170605
    node T_170606 = bits(tags, 74, 74)
    T_170561[2].coh.outer.makeVoluntaryRelease$default$5 := T_170606
    node T_170607 = bits(tags, 75, 75)
    T_170561[2].coh.outer.makeVoluntaryRelease$default$4 := T_170607
    node T_170608 = bits(tags, 76, 76)
    T_170561[2].coh.outer.makeRelease$default$3 := T_170608
    node T_170609 = bits(tags, 77, 77)
    T_170561[2].coh.outer.makeRelease$default$2 := T_170609
    node T_170610 = bits(tags, 79, 78)
    T_170561[2].coh.outer.state := T_170610
    node T_170611 = bits(tags, 80, 80)
    T_170561[2].coh.inner.makeGrant$default$4 := T_170611
    node T_170612 = bits(tags, 81, 81)
    T_170561[2].coh.inner.makeGrant$default$3 := T_170612
    node T_170613 = bits(tags, 82, 82)
    T_170561[2].coh.inner.sharers := T_170613
    node T_170614 = bits(tags, 83, 83)
    T_170561[2].coh.outer.makeVoluntaryWriteback$default$4 := T_170614
    node T_170615 = bits(tags, 84, 84)
    T_170561[2].coh.outer.makeVoluntaryWriteback$default$3 := T_170615
    node T_170616 = bits(tags, 85, 85)
    T_170561[2].coh.outer.makeVoluntaryRelease$default$5 := T_170616
    node T_170617 = bits(tags, 86, 86)
    T_170561[2].coh.outer.makeVoluntaryRelease$default$4 := T_170617
    node T_170618 = bits(tags, 87, 87)
    T_170561[2].coh.outer.makeRelease$default$3 := T_170618
    node T_170619 = bits(tags, 88, 88)
    T_170561[2].coh.outer.makeRelease$default$2 := T_170619
    node T_170620 = bits(tags, 90, 89)
    T_170561[2].coh.outer.state := T_170620
    node T_170621 = bits(tags, 91, 91)
    T_170561[2].coh.inner.makeGrant$default$4 := T_170621
    node T_170622 = bits(tags, 92, 92)
    T_170561[2].coh.inner.makeGrant$default$3 := T_170622
    node T_170623 = bits(tags, 93, 93)
    T_170561[2].coh.inner.sharers := T_170623
    node T_170624 = bits(tags, 107, 94)
    T_170561[2].tag := T_170624
    node T_170625 = bits(tags, 108, 108)
    T_170561[3].coh.outer.makeVoluntaryWriteback$default$4 := T_170625
    node T_170626 = bits(tags, 109, 109)
    T_170561[3].coh.outer.makeVoluntaryWriteback$default$3 := T_170626
    node T_170627 = bits(tags, 110, 110)
    T_170561[3].coh.outer.makeVoluntaryRelease$default$5 := T_170627
    node T_170628 = bits(tags, 111, 111)
    T_170561[3].coh.outer.makeVoluntaryRelease$default$4 := T_170628
    node T_170629 = bits(tags, 112, 112)
    T_170561[3].coh.outer.makeRelease$default$3 := T_170629
    node T_170630 = bits(tags, 113, 113)
    T_170561[3].coh.outer.makeRelease$default$2 := T_170630
    node T_170631 = bits(tags, 115, 114)
    T_170561[3].coh.outer.state := T_170631
    node T_170632 = bits(tags, 116, 116)
    T_170561[3].coh.inner.makeGrant$default$4 := T_170632
    node T_170633 = bits(tags, 117, 117)
    T_170561[3].coh.inner.makeGrant$default$3 := T_170633
    node T_170634 = bits(tags, 118, 118)
    T_170561[3].coh.inner.sharers := T_170634
    node T_170635 = bits(tags, 119, 119)
    T_170561[3].coh.outer.makeVoluntaryWriteback$default$4 := T_170635
    node T_170636 = bits(tags, 120, 120)
    T_170561[3].coh.outer.makeVoluntaryWriteback$default$3 := T_170636
    node T_170637 = bits(tags, 121, 121)
    T_170561[3].coh.outer.makeVoluntaryRelease$default$5 := T_170637
    node T_170638 = bits(tags, 122, 122)
    T_170561[3].coh.outer.makeVoluntaryRelease$default$4 := T_170638
    node T_170639 = bits(tags, 123, 123)
    T_170561[3].coh.outer.makeRelease$default$3 := T_170639
    node T_170640 = bits(tags, 124, 124)
    T_170561[3].coh.outer.makeRelease$default$2 := T_170640
    node T_170641 = bits(tags, 126, 125)
    T_170561[3].coh.outer.state := T_170641
    node T_170642 = bits(tags, 127, 127)
    T_170561[3].coh.inner.makeGrant$default$4 := T_170642
    node T_170643 = bits(tags, 128, 128)
    T_170561[3].coh.inner.makeGrant$default$3 := T_170643
    node T_170644 = bits(tags, 129, 129)
    T_170561[3].coh.inner.sharers := T_170644
    node T_170645 = bits(tags, 143, 130)
    T_170561[3].tag := T_170645
    node T_170646 = bits(tags, 144, 144)
    T_170561[4].coh.outer.makeVoluntaryWriteback$default$4 := T_170646
    node T_170647 = bits(tags, 145, 145)
    T_170561[4].coh.outer.makeVoluntaryWriteback$default$3 := T_170647
    node T_170648 = bits(tags, 146, 146)
    T_170561[4].coh.outer.makeVoluntaryRelease$default$5 := T_170648
    node T_170649 = bits(tags, 147, 147)
    T_170561[4].coh.outer.makeVoluntaryRelease$default$4 := T_170649
    node T_170650 = bits(tags, 148, 148)
    T_170561[4].coh.outer.makeRelease$default$3 := T_170650
    node T_170651 = bits(tags, 149, 149)
    T_170561[4].coh.outer.makeRelease$default$2 := T_170651
    node T_170652 = bits(tags, 151, 150)
    T_170561[4].coh.outer.state := T_170652
    node T_170653 = bits(tags, 152, 152)
    T_170561[4].coh.inner.makeGrant$default$4 := T_170653
    node T_170654 = bits(tags, 153, 153)
    T_170561[4].coh.inner.makeGrant$default$3 := T_170654
    node T_170655 = bits(tags, 154, 154)
    T_170561[4].coh.inner.sharers := T_170655
    node T_170656 = bits(tags, 155, 155)
    T_170561[4].coh.outer.makeVoluntaryWriteback$default$4 := T_170656
    node T_170657 = bits(tags, 156, 156)
    T_170561[4].coh.outer.makeVoluntaryWriteback$default$3 := T_170657
    node T_170658 = bits(tags, 157, 157)
    T_170561[4].coh.outer.makeVoluntaryRelease$default$5 := T_170658
    node T_170659 = bits(tags, 158, 158)
    T_170561[4].coh.outer.makeVoluntaryRelease$default$4 := T_170659
    node T_170660 = bits(tags, 159, 159)
    T_170561[4].coh.outer.makeRelease$default$3 := T_170660
    node T_170661 = bits(tags, 160, 160)
    T_170561[4].coh.outer.makeRelease$default$2 := T_170661
    node T_170662 = bits(tags, 162, 161)
    T_170561[4].coh.outer.state := T_170662
    node T_170663 = bits(tags, 163, 163)
    T_170561[4].coh.inner.makeGrant$default$4 := T_170663
    node T_170664 = bits(tags, 164, 164)
    T_170561[4].coh.inner.makeGrant$default$3 := T_170664
    node T_170665 = bits(tags, 165, 165)
    T_170561[4].coh.inner.sharers := T_170665
    node T_170666 = bits(tags, 179, 166)
    T_170561[4].tag := T_170666
    node T_170667 = bits(tags, 180, 180)
    T_170561[5].coh.outer.makeVoluntaryWriteback$default$4 := T_170667
    node T_170668 = bits(tags, 181, 181)
    T_170561[5].coh.outer.makeVoluntaryWriteback$default$3 := T_170668
    node T_170669 = bits(tags, 182, 182)
    T_170561[5].coh.outer.makeVoluntaryRelease$default$5 := T_170669
    node T_170670 = bits(tags, 183, 183)
    T_170561[5].coh.outer.makeVoluntaryRelease$default$4 := T_170670
    node T_170671 = bits(tags, 184, 184)
    T_170561[5].coh.outer.makeRelease$default$3 := T_170671
    node T_170672 = bits(tags, 185, 185)
    T_170561[5].coh.outer.makeRelease$default$2 := T_170672
    node T_170673 = bits(tags, 187, 186)
    T_170561[5].coh.outer.state := T_170673
    node T_170674 = bits(tags, 188, 188)
    T_170561[5].coh.inner.makeGrant$default$4 := T_170674
    node T_170675 = bits(tags, 189, 189)
    T_170561[5].coh.inner.makeGrant$default$3 := T_170675
    node T_170676 = bits(tags, 190, 190)
    T_170561[5].coh.inner.sharers := T_170676
    node T_170677 = bits(tags, 191, 191)
    T_170561[5].coh.outer.makeVoluntaryWriteback$default$4 := T_170677
    node T_170678 = bits(tags, 192, 192)
    T_170561[5].coh.outer.makeVoluntaryWriteback$default$3 := T_170678
    node T_170679 = bits(tags, 193, 193)
    T_170561[5].coh.outer.makeVoluntaryRelease$default$5 := T_170679
    node T_170680 = bits(tags, 194, 194)
    T_170561[5].coh.outer.makeVoluntaryRelease$default$4 := T_170680
    node T_170681 = bits(tags, 195, 195)
    T_170561[5].coh.outer.makeRelease$default$3 := T_170681
    node T_170682 = bits(tags, 196, 196)
    T_170561[5].coh.outer.makeRelease$default$2 := T_170682
    node T_170683 = bits(tags, 198, 197)
    T_170561[5].coh.outer.state := T_170683
    node T_170684 = bits(tags, 199, 199)
    T_170561[5].coh.inner.makeGrant$default$4 := T_170684
    node T_170685 = bits(tags, 200, 200)
    T_170561[5].coh.inner.makeGrant$default$3 := T_170685
    node T_170686 = bits(tags, 201, 201)
    T_170561[5].coh.inner.sharers := T_170686
    node T_170687 = bits(tags, 215, 202)
    T_170561[5].tag := T_170687
    node T_170688 = bits(tags, 216, 216)
    T_170561[6].coh.outer.makeVoluntaryWriteback$default$4 := T_170688
    node T_170689 = bits(tags, 217, 217)
    T_170561[6].coh.outer.makeVoluntaryWriteback$default$3 := T_170689
    node T_170690 = bits(tags, 218, 218)
    T_170561[6].coh.outer.makeVoluntaryRelease$default$5 := T_170690
    node T_170691 = bits(tags, 219, 219)
    T_170561[6].coh.outer.makeVoluntaryRelease$default$4 := T_170691
    node T_170692 = bits(tags, 220, 220)
    T_170561[6].coh.outer.makeRelease$default$3 := T_170692
    node T_170693 = bits(tags, 221, 221)
    T_170561[6].coh.outer.makeRelease$default$2 := T_170693
    node T_170694 = bits(tags, 223, 222)
    T_170561[6].coh.outer.state := T_170694
    node T_170695 = bits(tags, 224, 224)
    T_170561[6].coh.inner.makeGrant$default$4 := T_170695
    node T_170696 = bits(tags, 225, 225)
    T_170561[6].coh.inner.makeGrant$default$3 := T_170696
    node T_170697 = bits(tags, 226, 226)
    T_170561[6].coh.inner.sharers := T_170697
    node T_170698 = bits(tags, 227, 227)
    T_170561[6].coh.outer.makeVoluntaryWriteback$default$4 := T_170698
    node T_170699 = bits(tags, 228, 228)
    T_170561[6].coh.outer.makeVoluntaryWriteback$default$3 := T_170699
    node T_170700 = bits(tags, 229, 229)
    T_170561[6].coh.outer.makeVoluntaryRelease$default$5 := T_170700
    node T_170701 = bits(tags, 230, 230)
    T_170561[6].coh.outer.makeVoluntaryRelease$default$4 := T_170701
    node T_170702 = bits(tags, 231, 231)
    T_170561[6].coh.outer.makeRelease$default$3 := T_170702
    node T_170703 = bits(tags, 232, 232)
    T_170561[6].coh.outer.makeRelease$default$2 := T_170703
    node T_170704 = bits(tags, 234, 233)
    T_170561[6].coh.outer.state := T_170704
    node T_170705 = bits(tags, 235, 235)
    T_170561[6].coh.inner.makeGrant$default$4 := T_170705
    node T_170706 = bits(tags, 236, 236)
    T_170561[6].coh.inner.makeGrant$default$3 := T_170706
    node T_170707 = bits(tags, 237, 237)
    T_170561[6].coh.inner.sharers := T_170707
    node T_170708 = bits(tags, 251, 238)
    T_170561[6].tag := T_170708
    node T_170709 = bits(tags, 252, 252)
    T_170561[7].coh.outer.makeVoluntaryWriteback$default$4 := T_170709
    node T_170710 = bits(tags, 253, 253)
    T_170561[7].coh.outer.makeVoluntaryWriteback$default$3 := T_170710
    node T_170711 = bits(tags, 254, 254)
    T_170561[7].coh.outer.makeVoluntaryRelease$default$5 := T_170711
    node T_170712 = bits(tags, 255, 255)
    T_170561[7].coh.outer.makeVoluntaryRelease$default$4 := T_170712
    node T_170713 = bits(tags, 256, 256)
    T_170561[7].coh.outer.makeRelease$default$3 := T_170713
    node T_170714 = bits(tags, 257, 257)
    T_170561[7].coh.outer.makeRelease$default$2 := T_170714
    node T_170715 = bits(tags, 259, 258)
    T_170561[7].coh.outer.state := T_170715
    node T_170716 = bits(tags, 260, 260)
    T_170561[7].coh.inner.makeGrant$default$4 := T_170716
    node T_170717 = bits(tags, 261, 261)
    T_170561[7].coh.inner.makeGrant$default$3 := T_170717
    node T_170718 = bits(tags, 262, 262)
    T_170561[7].coh.inner.sharers := T_170718
    node T_170719 = bits(tags, 263, 263)
    T_170561[7].coh.outer.makeVoluntaryWriteback$default$4 := T_170719
    node T_170720 = bits(tags, 264, 264)
    T_170561[7].coh.outer.makeVoluntaryWriteback$default$3 := T_170720
    node T_170721 = bits(tags, 265, 265)
    T_170561[7].coh.outer.makeVoluntaryRelease$default$5 := T_170721
    node T_170722 = bits(tags, 266, 266)
    T_170561[7].coh.outer.makeVoluntaryRelease$default$4 := T_170722
    node T_170723 = bits(tags, 267, 267)
    T_170561[7].coh.outer.makeRelease$default$3 := T_170723
    node T_170724 = bits(tags, 268, 268)
    T_170561[7].coh.outer.makeRelease$default$2 := T_170724
    node T_170725 = bits(tags, 270, 269)
    T_170561[7].coh.outer.state := T_170725
    node T_170726 = bits(tags, 271, 271)
    T_170561[7].coh.inner.makeGrant$default$4 := T_170726
    node T_170727 = bits(tags, 272, 272)
    T_170561[7].coh.inner.makeGrant$default$3 := T_170727
    node T_170728 = bits(tags, 273, 273)
    T_170561[7].coh.inner.sharers := T_170728
    node T_170729 = bits(tags, 287, 274)
    T_170561[7].tag := T_170729
    resp[0] := T_170561[0]
    resp[1] := T_170561[1]
    resp[2] := T_170561[2]
    resp[3] := T_170561[3]
    resp[4] := T_170561[4]
    resp[5] := T_170561[5]
    resp[6] := T_170561[6]
    resp[7] := T_170561[7]
    node T_170730 = eq(rst, UInt<1>(0))
    node T_170731 = eq(write.valid, UInt<1>(0))
    node T_170732 = and(T_170730, T_170731)
    read.ready := T_170732
    node T_170733 = eq(rst, UInt<1>(0))
    write.ready := T_170733
  module L2MetadataArray : 
    output read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}
    input resp : {valid : UInt<1>, bits : {id : UInt<2>, tag_match : UInt<1>, meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, way_en : UInt<8>}}
    output write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}
    
    wire T_170734 : UInt<3>[3]
    T_170734[0] := UInt<3>(0)
    T_170734[1] := UInt<3>(1)
    T_170734[2] := UInt<3>(2)
    wire T_170735 : UInt<2>[2]
    T_170735[0] := UInt<2>(0)
    T_170735[1] := UInt<2>(1)
    wire T_170736 : UInt<2>[3]
    T_170736[0] := UInt<2>(1)
    T_170736[1] := UInt<2>(2)
    T_170736[2] := UInt<2>(3)
    wire T_170737 : UInt<2>[2]
    T_170737[0] := UInt<2>(2)
    T_170737[1] := UInt<2>(3)
    wire T_170738 : UInt<2>[1]
    T_170738[0] := UInt<2>(3)
    wire T_170739 : UInt<3>[3]
    T_170739[0] := UInt<3>(0)
    T_170739[1] := UInt<3>(1)
    T_170739[2] := UInt<3>(2)
    wire T_170740 : UInt<2>[2]
    T_170740[0] := UInt<2>(0)
    T_170740[1] := UInt<2>(1)
    wire T_170741 : UInt<2>[3]
    T_170741[0] := UInt<2>(1)
    T_170741[1] := UInt<2>(2)
    T_170741[2] := UInt<2>(3)
    wire T_170742 : UInt<2>[2]
    T_170742[0] := UInt<2>(2)
    T_170742[1] := UInt<2>(3)
    wire T_170743 : UInt<2>[1]
    T_170743[0] := UInt<2>(3)
    wire T_170744 : UInt<3>[3]
    T_170744[0] := UInt<3>(0)
    T_170744[1] := UInt<3>(1)
    T_170744[2] := UInt<3>(2)
    wire T_170745 : UInt<0>[1]
    T_170745[0] := UInt<0>(0)
    wire T_170746 : UInt<2>[2]
    T_170746[0] := UInt<2>(1)
    T_170746[1] := UInt<2>(2)
    wire T_170747 : UInt<2>[2]
    T_170747[0] := UInt<2>(1)
    T_170747[1] := UInt<2>(2)
    wire T_170748 : UInt<2>[1]
    T_170748[0] := UInt<2>(2)
    wire T_170749 : UInt<3>[3]
    T_170749[0] := UInt<3>(0)
    T_170749[1] := UInt<3>(1)
    T_170749[2] := UInt<3>(2)
    wire T_170750 : UInt<2>[2]
    T_170750[0] := UInt<2>(0)
    T_170750[1] := UInt<2>(1)
    wire T_170751 : UInt<2>[3]
    T_170751[0] := UInt<2>(1)
    T_170751[1] := UInt<2>(2)
    T_170751[2] := UInt<2>(3)
    wire T_170752 : UInt<2>[2]
    T_170752[0] := UInt<2>(2)
    T_170752[1] := UInt<2>(3)
    wire T_170753 : UInt<2>[1]
    T_170753[0] := UInt<2>(3)
    wire T_170754 : UInt<3>[3]
    T_170754[0] := UInt<3>(0)
    T_170754[1] := UInt<3>(1)
    T_170754[2] := UInt<3>(2)
    wire T_170755 : UInt<2>[2]
    T_170755[0] := UInt<2>(0)
    T_170755[1] := UInt<2>(1)
    wire T_170756 : UInt<2>[3]
    T_170756[0] := UInt<2>(1)
    T_170756[1] := UInt<2>(2)
    T_170756[2] := UInt<2>(3)
    wire T_170757 : UInt<2>[2]
    T_170757[0] := UInt<2>(2)
    T_170757[1] := UInt<2>(3)
    wire T_170758 : UInt<2>[1]
    T_170758[0] := UInt<2>(3)
    wire T_170759 : UInt<3>[3]
    T_170759[0] := UInt<3>(0)
    T_170759[1] := UInt<3>(1)
    T_170759[2] := UInt<3>(2)
    wire T_170760 : UInt<0>[1]
    T_170760[0] := UInt<0>(0)
    wire T_170761 : UInt<2>[2]
    T_170761[0] := UInt<2>(1)
    T_170761[1] := UInt<2>(2)
    wire T_170762 : UInt<2>[2]
    T_170762[0] := UInt<2>(1)
    T_170762[1] := UInt<2>(2)
    wire T_170763 : UInt<2>[1]
    T_170763[0] := UInt<2>(2)
    wire T_170764 : UInt<3>[3]
    T_170764[0] := UInt<3>(0)
    T_170764[1] := UInt<3>(1)
    T_170764[2] := UInt<3>(2)
    wire T_170765 : UInt<2>[2]
    T_170765[0] := UInt<2>(0)
    T_170765[1] := UInt<2>(1)
    wire T_170766 : UInt<2>[3]
    T_170766[0] := UInt<2>(1)
    T_170766[1] := UInt<2>(2)
    T_170766[2] := UInt<2>(3)
    wire T_170767 : UInt<2>[2]
    T_170767[0] := UInt<2>(2)
    T_170767[1] := UInt<2>(3)
    wire T_170768 : UInt<2>[1]
    T_170768[0] := UInt<2>(3)
    wire T_170769 : UInt<3>[3]
    T_170769[0] := UInt<3>(0)
    T_170769[1] := UInt<3>(1)
    T_170769[2] := UInt<3>(2)
    wire T_170770 : UInt<2>[2]
    T_170770[0] := UInt<2>(0)
    T_170770[1] := UInt<2>(1)
    wire T_170771 : UInt<2>[3]
    T_170771[0] := UInt<2>(1)
    T_170771[1] := UInt<2>(2)
    T_170771[2] := UInt<2>(3)
    wire T_170772 : UInt<2>[2]
    T_170772[0] := UInt<2>(2)
    T_170772[1] := UInt<2>(3)
    wire T_170773 : UInt<2>[1]
    T_170773[0] := UInt<2>(3)
    wire T_170774 : UInt<3>[3]
    T_170774[0] := UInt<3>(0)
    T_170774[1] := UInt<3>(1)
    T_170774[2] := UInt<3>(2)
    wire T_170775 : UInt<0>[1]
    T_170775[0] := UInt<0>(0)
    wire T_170776 : UInt<2>[2]
    T_170776[0] := UInt<2>(1)
    T_170776[1] := UInt<2>(2)
    wire T_170777 : UInt<2>[2]
    T_170777[0] := UInt<2>(1)
    T_170777[1] := UInt<2>(2)
    wire T_170778 : UInt<2>[1]
    T_170778[0] := UInt<2>(2)
    wire T_170779 : UInt<3>[3]
    T_170779[0] := UInt<3>(0)
    T_170779[1] := UInt<3>(1)
    T_170779[2] := UInt<3>(2)
    wire T_170780 : UInt<2>[2]
    T_170780[0] := UInt<2>(0)
    T_170780[1] := UInt<2>(1)
    wire T_170781 : UInt<2>[3]
    T_170781[0] := UInt<2>(1)
    T_170781[1] := UInt<2>(2)
    T_170781[2] := UInt<2>(3)
    wire T_170782 : UInt<2>[2]
    T_170782[0] := UInt<2>(2)
    T_170782[1] := UInt<2>(3)
    wire T_170783 : UInt<2>[1]
    T_170783[0] := UInt<2>(3)
    wire T_170784 : UInt<3>[3]
    T_170784[0] := UInt<3>(0)
    T_170784[1] := UInt<3>(1)
    T_170784[2] := UInt<3>(2)
    wire T_170785 : UInt<2>[2]
    T_170785[0] := UInt<2>(0)
    T_170785[1] := UInt<2>(1)
    wire T_170786 : UInt<2>[3]
    T_170786[0] := UInt<2>(1)
    T_170786[1] := UInt<2>(2)
    T_170786[2] := UInt<2>(3)
    wire T_170787 : UInt<2>[2]
    T_170787[0] := UInt<2>(2)
    T_170787[1] := UInt<2>(3)
    wire T_170788 : UInt<2>[1]
    T_170788[0] := UInt<2>(3)
    wire T_170789 : UInt<3>[3]
    T_170789[0] := UInt<3>(0)
    T_170789[1] := UInt<3>(1)
    T_170789[2] := UInt<3>(2)
    wire T_170790 : UInt<0>[1]
    T_170790[0] := UInt<0>(0)
    wire T_170791 : UInt<2>[2]
    T_170791[0] := UInt<2>(1)
    T_170791[1] := UInt<2>(2)
    wire T_170792 : UInt<2>[2]
    T_170792[0] := UInt<2>(1)
    T_170792[1] := UInt<2>(2)
    wire T_170793 : UInt<2>[1]
    T_170793[0] := UInt<2>(2)
    wire T_170794 : UInt<3>[3]
    T_170794[0] := UInt<3>(0)
    T_170794[1] := UInt<3>(1)
    T_170794[2] := UInt<3>(2)
    wire T_170795 : UInt<2>[2]
    T_170795[0] := UInt<2>(0)
    T_170795[1] := UInt<2>(1)
    wire T_170796 : UInt<2>[3]
    T_170796[0] := UInt<2>(1)
    T_170796[1] := UInt<2>(2)
    T_170796[2] := UInt<2>(3)
    wire T_170797 : UInt<2>[2]
    T_170797[0] := UInt<2>(2)
    T_170797[1] := UInt<2>(3)
    wire T_170798 : UInt<2>[1]
    T_170798[0] := UInt<2>(3)
    wire T_170799 : UInt<3>[3]
    T_170799[0] := UInt<3>(0)
    T_170799[1] := UInt<3>(1)
    T_170799[2] := UInt<3>(2)
    wire T_170800 : UInt<2>[2]
    T_170800[0] := UInt<2>(0)
    T_170800[1] := UInt<2>(1)
    wire T_170801 : UInt<2>[3]
    T_170801[0] := UInt<2>(1)
    T_170801[1] := UInt<2>(2)
    T_170801[2] := UInt<2>(3)
    wire T_170802 : UInt<2>[2]
    T_170802[0] := UInt<2>(2)
    T_170802[1] := UInt<2>(3)
    wire T_170803 : UInt<2>[1]
    T_170803[0] := UInt<2>(3)
    wire T_170804 : UInt<3>[3]
    T_170804[0] := UInt<3>(0)
    T_170804[1] := UInt<3>(1)
    T_170804[2] := UInt<3>(2)
    wire T_170805 : UInt<0>[1]
    T_170805[0] := UInt<0>(0)
    wire T_170806 : UInt<2>[2]
    T_170806[0] := UInt<2>(1)
    T_170806[1] := UInt<2>(2)
    wire T_170807 : UInt<2>[2]
    T_170807[0] := UInt<2>(1)
    T_170807[1] := UInt<2>(2)
    wire T_170808 : UInt<2>[1]
    T_170808[0] := UInt<2>(2)
    wire T_170809 : UInt<3>[3]
    T_170809[0] := UInt<3>(0)
    T_170809[1] := UInt<3>(1)
    T_170809[2] := UInt<3>(2)
    wire T_170810 : UInt<2>[2]
    T_170810[0] := UInt<2>(0)
    T_170810[1] := UInt<2>(1)
    wire T_170811 : UInt<2>[3]
    T_170811[0] := UInt<2>(1)
    T_170811[1] := UInt<2>(2)
    T_170811[2] := UInt<2>(3)
    wire T_170812 : UInt<2>[2]
    T_170812[0] := UInt<2>(2)
    T_170812[1] := UInt<2>(3)
    wire T_170813 : UInt<2>[1]
    T_170813[0] := UInt<2>(3)
    wire T_170814 : UInt<3>[3]
    T_170814[0] := UInt<3>(0)
    T_170814[1] := UInt<3>(1)
    T_170814[2] := UInt<3>(2)
    wire T_170815 : UInt<2>[2]
    T_170815[0] := UInt<2>(0)
    T_170815[1] := UInt<2>(1)
    wire T_170816 : UInt<2>[3]
    T_170816[0] := UInt<2>(1)
    T_170816[1] := UInt<2>(2)
    T_170816[2] := UInt<2>(3)
    wire T_170817 : UInt<2>[2]
    T_170817[0] := UInt<2>(2)
    T_170817[1] := UInt<2>(3)
    wire T_170818 : UInt<2>[1]
    T_170818[0] := UInt<2>(3)
    wire T_170819 : UInt<3>[3]
    T_170819[0] := UInt<3>(0)
    T_170819[1] := UInt<3>(1)
    T_170819[2] := UInt<3>(2)
    wire T_170820 : UInt<0>[1]
    T_170820[0] := UInt<0>(0)
    wire T_170821 : UInt<2>[2]
    T_170821[0] := UInt<2>(1)
    T_170821[1] := UInt<2>(2)
    wire T_170822 : UInt<2>[2]
    T_170822[0] := UInt<2>(1)
    T_170822[1] := UInt<2>(2)
    wire T_170823 : UInt<2>[1]
    T_170823[0] := UInt<2>(2)
    inst meta of MetadataArray
    meta.read <> read
    meta.write <> write
    reg s1_tag : UInt<14>
    when read.valid : s1_tag := read.bits.tag
    reg s1_id : UInt<2>
    when read.valid : s1_id := read.bits.id
    node T_170824 = and(read.ready, read.valid)
    reg s1_clk_en : UInt<1>
    s1_clk_en := T_170824
    node T_170825 = eq(meta.resp[0].tag, s1_tag)
    node T_170826 = eq(meta.resp[1].tag, s1_tag)
    node T_170827 = eq(meta.resp[2].tag, s1_tag)
    node T_170828 = eq(meta.resp[3].tag, s1_tag)
    node T_170829 = eq(meta.resp[4].tag, s1_tag)
    node T_170830 = eq(meta.resp[5].tag, s1_tag)
    node T_170831 = eq(meta.resp[6].tag, s1_tag)
    node T_170832 = eq(meta.resp[7].tag, s1_tag)
    wire s1_tag_eq_way : UInt<1>[8]
    s1_tag_eq_way[0] := T_170825
    s1_tag_eq_way[1] := T_170826
    s1_tag_eq_way[2] := T_170827
    s1_tag_eq_way[3] := T_170828
    s1_tag_eq_way[4] := T_170829
    s1_tag_eq_way[5] := T_170830
    s1_tag_eq_way[6] := T_170831
    s1_tag_eq_way[7] := T_170832
    node T_170833 = neq(meta.resp[0].coh.outer.state, UInt<2>(0))
    node T_170834 = and(s1_tag_eq_way[0], T_170833)
    node T_170835 = neq(meta.resp[1].coh.outer.state, UInt<2>(0))
    node T_170836 = and(s1_tag_eq_way[1], T_170835)
    node T_170837 = neq(meta.resp[2].coh.outer.state, UInt<2>(0))
    node T_170838 = and(s1_tag_eq_way[2], T_170837)
    node T_170839 = neq(meta.resp[3].coh.outer.state, UInt<2>(0))
    node T_170840 = and(s1_tag_eq_way[3], T_170839)
    node T_170841 = neq(meta.resp[4].coh.outer.state, UInt<2>(0))
    node T_170842 = and(s1_tag_eq_way[4], T_170841)
    node T_170843 = neq(meta.resp[5].coh.outer.state, UInt<2>(0))
    node T_170844 = and(s1_tag_eq_way[5], T_170843)
    node T_170845 = neq(meta.resp[6].coh.outer.state, UInt<2>(0))
    node T_170846 = and(s1_tag_eq_way[6], T_170845)
    node T_170847 = neq(meta.resp[7].coh.outer.state, UInt<2>(0))
    node T_170848 = and(s1_tag_eq_way[7], T_170847)
    wire T_170849 : UInt<1>[8]
    T_170849[0] := T_170834
    T_170849[1] := T_170836
    T_170849[2] := T_170838
    T_170849[3] := T_170840
    T_170849[4] := T_170842
    T_170849[5] := T_170844
    T_170849[6] := T_170846
    T_170849[7] := T_170848
    node T_170850 = cat(T_170849[7], T_170849[6])
    node T_170851 = cat(T_170849[5], T_170849[4])
    node T_170852 = cat(T_170850, T_170851)
    node T_170853 = cat(T_170849[3], T_170849[2])
    node T_170854 = cat(T_170849[1], T_170849[0])
    node T_170855 = cat(T_170853, T_170854)
    node s1_tag_match_way = cat(T_170852, T_170855)
    reg s2_tag_match_way : UInt<8>
    when s1_clk_en : s2_tag_match_way := s1_tag_match_way
    node T_170856 = eq(s2_tag_match_way, UInt<1>(0))
    node s2_tag_match = eq(T_170856, UInt<1>(0))
    wire T_170857 : UInt<3>[3]
    T_170857[0] := UInt<3>(0)
    T_170857[1] := UInt<3>(1)
    T_170857[2] := UInt<3>(2)
    wire T_170858 : UInt<2>[2]
    T_170858[0] := UInt<2>(0)
    T_170858[1] := UInt<2>(1)
    wire T_170859 : UInt<2>[3]
    T_170859[0] := UInt<2>(1)
    T_170859[1] := UInt<2>(2)
    T_170859[2] := UInt<2>(3)
    wire T_170860 : UInt<2>[2]
    T_170860[0] := UInt<2>(2)
    T_170860[1] := UInt<2>(3)
    wire T_170861 : UInt<2>[1]
    T_170861[0] := UInt<2>(3)
    wire T_170862 : UInt<3>[3]
    T_170862[0] := UInt<3>(0)
    T_170862[1] := UInt<3>(1)
    T_170862[2] := UInt<3>(2)
    wire T_170863 : UInt<2>[2]
    T_170863[0] := UInt<2>(0)
    T_170863[1] := UInt<2>(1)
    wire T_170864 : UInt<2>[3]
    T_170864[0] := UInt<2>(1)
    T_170864[1] := UInt<2>(2)
    T_170864[2] := UInt<2>(3)
    wire T_170865 : UInt<2>[2]
    T_170865[0] := UInt<2>(2)
    T_170865[1] := UInt<2>(3)
    wire T_170866 : UInt<2>[1]
    T_170866[0] := UInt<2>(3)
    wire T_170867 : UInt<3>[3]
    T_170867[0] := UInt<3>(0)
    T_170867[1] := UInt<3>(1)
    T_170867[2] := UInt<3>(2)
    wire T_170868 : UInt<0>[1]
    T_170868[0] := UInt<0>(0)
    wire T_170869 : UInt<2>[2]
    T_170869[0] := UInt<2>(1)
    T_170869[1] := UInt<2>(2)
    wire T_170870 : UInt<2>[2]
    T_170870[0] := UInt<2>(1)
    T_170870[1] := UInt<2>(2)
    wire T_170871 : UInt<2>[1]
    T_170871[0] := UInt<2>(2)
    reg T_170872 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170872 := meta.resp[0].coh
    wire T_170873 : UInt<3>[3]
    T_170873[0] := UInt<3>(0)
    T_170873[1] := UInt<3>(1)
    T_170873[2] := UInt<3>(2)
    wire T_170874 : UInt<2>[2]
    T_170874[0] := UInt<2>(0)
    T_170874[1] := UInt<2>(1)
    wire T_170875 : UInt<2>[3]
    T_170875[0] := UInt<2>(1)
    T_170875[1] := UInt<2>(2)
    T_170875[2] := UInt<2>(3)
    wire T_170876 : UInt<2>[2]
    T_170876[0] := UInt<2>(2)
    T_170876[1] := UInt<2>(3)
    wire T_170877 : UInt<2>[1]
    T_170877[0] := UInt<2>(3)
    wire T_170878 : UInt<3>[3]
    T_170878[0] := UInt<3>(0)
    T_170878[1] := UInt<3>(1)
    T_170878[2] := UInt<3>(2)
    wire T_170879 : UInt<2>[2]
    T_170879[0] := UInt<2>(0)
    T_170879[1] := UInt<2>(1)
    wire T_170880 : UInt<2>[3]
    T_170880[0] := UInt<2>(1)
    T_170880[1] := UInt<2>(2)
    T_170880[2] := UInt<2>(3)
    wire T_170881 : UInt<2>[2]
    T_170881[0] := UInt<2>(2)
    T_170881[1] := UInt<2>(3)
    wire T_170882 : UInt<2>[1]
    T_170882[0] := UInt<2>(3)
    wire T_170883 : UInt<3>[3]
    T_170883[0] := UInt<3>(0)
    T_170883[1] := UInt<3>(1)
    T_170883[2] := UInt<3>(2)
    wire T_170884 : UInt<0>[1]
    T_170884[0] := UInt<0>(0)
    wire T_170885 : UInt<2>[2]
    T_170885[0] := UInt<2>(1)
    T_170885[1] := UInt<2>(2)
    wire T_170886 : UInt<2>[2]
    T_170886[0] := UInt<2>(1)
    T_170886[1] := UInt<2>(2)
    wire T_170887 : UInt<2>[1]
    T_170887[0] := UInt<2>(2)
    reg T_170888 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170888 := meta.resp[1].coh
    wire T_170889 : UInt<3>[3]
    T_170889[0] := UInt<3>(0)
    T_170889[1] := UInt<3>(1)
    T_170889[2] := UInt<3>(2)
    wire T_170890 : UInt<2>[2]
    T_170890[0] := UInt<2>(0)
    T_170890[1] := UInt<2>(1)
    wire T_170891 : UInt<2>[3]
    T_170891[0] := UInt<2>(1)
    T_170891[1] := UInt<2>(2)
    T_170891[2] := UInt<2>(3)
    wire T_170892 : UInt<2>[2]
    T_170892[0] := UInt<2>(2)
    T_170892[1] := UInt<2>(3)
    wire T_170893 : UInt<2>[1]
    T_170893[0] := UInt<2>(3)
    wire T_170894 : UInt<3>[3]
    T_170894[0] := UInt<3>(0)
    T_170894[1] := UInt<3>(1)
    T_170894[2] := UInt<3>(2)
    wire T_170895 : UInt<2>[2]
    T_170895[0] := UInt<2>(0)
    T_170895[1] := UInt<2>(1)
    wire T_170896 : UInt<2>[3]
    T_170896[0] := UInt<2>(1)
    T_170896[1] := UInt<2>(2)
    T_170896[2] := UInt<2>(3)
    wire T_170897 : UInt<2>[2]
    T_170897[0] := UInt<2>(2)
    T_170897[1] := UInt<2>(3)
    wire T_170898 : UInt<2>[1]
    T_170898[0] := UInt<2>(3)
    wire T_170899 : UInt<3>[3]
    T_170899[0] := UInt<3>(0)
    T_170899[1] := UInt<3>(1)
    T_170899[2] := UInt<3>(2)
    wire T_170900 : UInt<0>[1]
    T_170900[0] := UInt<0>(0)
    wire T_170901 : UInt<2>[2]
    T_170901[0] := UInt<2>(1)
    T_170901[1] := UInt<2>(2)
    wire T_170902 : UInt<2>[2]
    T_170902[0] := UInt<2>(1)
    T_170902[1] := UInt<2>(2)
    wire T_170903 : UInt<2>[1]
    T_170903[0] := UInt<2>(2)
    reg T_170904 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170904 := meta.resp[2].coh
    wire T_170905 : UInt<3>[3]
    T_170905[0] := UInt<3>(0)
    T_170905[1] := UInt<3>(1)
    T_170905[2] := UInt<3>(2)
    wire T_170906 : UInt<2>[2]
    T_170906[0] := UInt<2>(0)
    T_170906[1] := UInt<2>(1)
    wire T_170907 : UInt<2>[3]
    T_170907[0] := UInt<2>(1)
    T_170907[1] := UInt<2>(2)
    T_170907[2] := UInt<2>(3)
    wire T_170908 : UInt<2>[2]
    T_170908[0] := UInt<2>(2)
    T_170908[1] := UInt<2>(3)
    wire T_170909 : UInt<2>[1]
    T_170909[0] := UInt<2>(3)
    wire T_170910 : UInt<3>[3]
    T_170910[0] := UInt<3>(0)
    T_170910[1] := UInt<3>(1)
    T_170910[2] := UInt<3>(2)
    wire T_170911 : UInt<2>[2]
    T_170911[0] := UInt<2>(0)
    T_170911[1] := UInt<2>(1)
    wire T_170912 : UInt<2>[3]
    T_170912[0] := UInt<2>(1)
    T_170912[1] := UInt<2>(2)
    T_170912[2] := UInt<2>(3)
    wire T_170913 : UInt<2>[2]
    T_170913[0] := UInt<2>(2)
    T_170913[1] := UInt<2>(3)
    wire T_170914 : UInt<2>[1]
    T_170914[0] := UInt<2>(3)
    wire T_170915 : UInt<3>[3]
    T_170915[0] := UInt<3>(0)
    T_170915[1] := UInt<3>(1)
    T_170915[2] := UInt<3>(2)
    wire T_170916 : UInt<0>[1]
    T_170916[0] := UInt<0>(0)
    wire T_170917 : UInt<2>[2]
    T_170917[0] := UInt<2>(1)
    T_170917[1] := UInt<2>(2)
    wire T_170918 : UInt<2>[2]
    T_170918[0] := UInt<2>(1)
    T_170918[1] := UInt<2>(2)
    wire T_170919 : UInt<2>[1]
    T_170919[0] := UInt<2>(2)
    reg T_170920 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170920 := meta.resp[3].coh
    wire T_170921 : UInt<3>[3]
    T_170921[0] := UInt<3>(0)
    T_170921[1] := UInt<3>(1)
    T_170921[2] := UInt<3>(2)
    wire T_170922 : UInt<2>[2]
    T_170922[0] := UInt<2>(0)
    T_170922[1] := UInt<2>(1)
    wire T_170923 : UInt<2>[3]
    T_170923[0] := UInt<2>(1)
    T_170923[1] := UInt<2>(2)
    T_170923[2] := UInt<2>(3)
    wire T_170924 : UInt<2>[2]
    T_170924[0] := UInt<2>(2)
    T_170924[1] := UInt<2>(3)
    wire T_170925 : UInt<2>[1]
    T_170925[0] := UInt<2>(3)
    wire T_170926 : UInt<3>[3]
    T_170926[0] := UInt<3>(0)
    T_170926[1] := UInt<3>(1)
    T_170926[2] := UInt<3>(2)
    wire T_170927 : UInt<2>[2]
    T_170927[0] := UInt<2>(0)
    T_170927[1] := UInt<2>(1)
    wire T_170928 : UInt<2>[3]
    T_170928[0] := UInt<2>(1)
    T_170928[1] := UInt<2>(2)
    T_170928[2] := UInt<2>(3)
    wire T_170929 : UInt<2>[2]
    T_170929[0] := UInt<2>(2)
    T_170929[1] := UInt<2>(3)
    wire T_170930 : UInt<2>[1]
    T_170930[0] := UInt<2>(3)
    wire T_170931 : UInt<3>[3]
    T_170931[0] := UInt<3>(0)
    T_170931[1] := UInt<3>(1)
    T_170931[2] := UInt<3>(2)
    wire T_170932 : UInt<0>[1]
    T_170932[0] := UInt<0>(0)
    wire T_170933 : UInt<2>[2]
    T_170933[0] := UInt<2>(1)
    T_170933[1] := UInt<2>(2)
    wire T_170934 : UInt<2>[2]
    T_170934[0] := UInt<2>(1)
    T_170934[1] := UInt<2>(2)
    wire T_170935 : UInt<2>[1]
    T_170935[0] := UInt<2>(2)
    reg T_170936 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170936 := meta.resp[4].coh
    wire T_170937 : UInt<3>[3]
    T_170937[0] := UInt<3>(0)
    T_170937[1] := UInt<3>(1)
    T_170937[2] := UInt<3>(2)
    wire T_170938 : UInt<2>[2]
    T_170938[0] := UInt<2>(0)
    T_170938[1] := UInt<2>(1)
    wire T_170939 : UInt<2>[3]
    T_170939[0] := UInt<2>(1)
    T_170939[1] := UInt<2>(2)
    T_170939[2] := UInt<2>(3)
    wire T_170940 : UInt<2>[2]
    T_170940[0] := UInt<2>(2)
    T_170940[1] := UInt<2>(3)
    wire T_170941 : UInt<2>[1]
    T_170941[0] := UInt<2>(3)
    wire T_170942 : UInt<3>[3]
    T_170942[0] := UInt<3>(0)
    T_170942[1] := UInt<3>(1)
    T_170942[2] := UInt<3>(2)
    wire T_170943 : UInt<2>[2]
    T_170943[0] := UInt<2>(0)
    T_170943[1] := UInt<2>(1)
    wire T_170944 : UInt<2>[3]
    T_170944[0] := UInt<2>(1)
    T_170944[1] := UInt<2>(2)
    T_170944[2] := UInt<2>(3)
    wire T_170945 : UInt<2>[2]
    T_170945[0] := UInt<2>(2)
    T_170945[1] := UInt<2>(3)
    wire T_170946 : UInt<2>[1]
    T_170946[0] := UInt<2>(3)
    wire T_170947 : UInt<3>[3]
    T_170947[0] := UInt<3>(0)
    T_170947[1] := UInt<3>(1)
    T_170947[2] := UInt<3>(2)
    wire T_170948 : UInt<0>[1]
    T_170948[0] := UInt<0>(0)
    wire T_170949 : UInt<2>[2]
    T_170949[0] := UInt<2>(1)
    T_170949[1] := UInt<2>(2)
    wire T_170950 : UInt<2>[2]
    T_170950[0] := UInt<2>(1)
    T_170950[1] := UInt<2>(2)
    wire T_170951 : UInt<2>[1]
    T_170951[0] := UInt<2>(2)
    reg T_170952 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170952 := meta.resp[5].coh
    wire T_170953 : UInt<3>[3]
    T_170953[0] := UInt<3>(0)
    T_170953[1] := UInt<3>(1)
    T_170953[2] := UInt<3>(2)
    wire T_170954 : UInt<2>[2]
    T_170954[0] := UInt<2>(0)
    T_170954[1] := UInt<2>(1)
    wire T_170955 : UInt<2>[3]
    T_170955[0] := UInt<2>(1)
    T_170955[1] := UInt<2>(2)
    T_170955[2] := UInt<2>(3)
    wire T_170956 : UInt<2>[2]
    T_170956[0] := UInt<2>(2)
    T_170956[1] := UInt<2>(3)
    wire T_170957 : UInt<2>[1]
    T_170957[0] := UInt<2>(3)
    wire T_170958 : UInt<3>[3]
    T_170958[0] := UInt<3>(0)
    T_170958[1] := UInt<3>(1)
    T_170958[2] := UInt<3>(2)
    wire T_170959 : UInt<2>[2]
    T_170959[0] := UInt<2>(0)
    T_170959[1] := UInt<2>(1)
    wire T_170960 : UInt<2>[3]
    T_170960[0] := UInt<2>(1)
    T_170960[1] := UInt<2>(2)
    T_170960[2] := UInt<2>(3)
    wire T_170961 : UInt<2>[2]
    T_170961[0] := UInt<2>(2)
    T_170961[1] := UInt<2>(3)
    wire T_170962 : UInt<2>[1]
    T_170962[0] := UInt<2>(3)
    wire T_170963 : UInt<3>[3]
    T_170963[0] := UInt<3>(0)
    T_170963[1] := UInt<3>(1)
    T_170963[2] := UInt<3>(2)
    wire T_170964 : UInt<0>[1]
    T_170964[0] := UInt<0>(0)
    wire T_170965 : UInt<2>[2]
    T_170965[0] := UInt<2>(1)
    T_170965[1] := UInt<2>(2)
    wire T_170966 : UInt<2>[2]
    T_170966[0] := UInt<2>(1)
    T_170966[1] := UInt<2>(2)
    wire T_170967 : UInt<2>[1]
    T_170967[0] := UInt<2>(2)
    reg T_170968 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170968 := meta.resp[6].coh
    wire T_170969 : UInt<3>[3]
    T_170969[0] := UInt<3>(0)
    T_170969[1] := UInt<3>(1)
    T_170969[2] := UInt<3>(2)
    wire T_170970 : UInt<2>[2]
    T_170970[0] := UInt<2>(0)
    T_170970[1] := UInt<2>(1)
    wire T_170971 : UInt<2>[3]
    T_170971[0] := UInt<2>(1)
    T_170971[1] := UInt<2>(2)
    T_170971[2] := UInt<2>(3)
    wire T_170972 : UInt<2>[2]
    T_170972[0] := UInt<2>(2)
    T_170972[1] := UInt<2>(3)
    wire T_170973 : UInt<2>[1]
    T_170973[0] := UInt<2>(3)
    wire T_170974 : UInt<3>[3]
    T_170974[0] := UInt<3>(0)
    T_170974[1] := UInt<3>(1)
    T_170974[2] := UInt<3>(2)
    wire T_170975 : UInt<2>[2]
    T_170975[0] := UInt<2>(0)
    T_170975[1] := UInt<2>(1)
    wire T_170976 : UInt<2>[3]
    T_170976[0] := UInt<2>(1)
    T_170976[1] := UInt<2>(2)
    T_170976[2] := UInt<2>(3)
    wire T_170977 : UInt<2>[2]
    T_170977[0] := UInt<2>(2)
    T_170977[1] := UInt<2>(3)
    wire T_170978 : UInt<2>[1]
    T_170978[0] := UInt<2>(3)
    wire T_170979 : UInt<3>[3]
    T_170979[0] := UInt<3>(0)
    T_170979[1] := UInt<3>(1)
    T_170979[2] := UInt<3>(2)
    wire T_170980 : UInt<0>[1]
    T_170980[0] := UInt<0>(0)
    wire T_170981 : UInt<2>[2]
    T_170981[0] := UInt<2>(1)
    T_170981[1] := UInt<2>(2)
    wire T_170982 : UInt<2>[2]
    T_170982[0] := UInt<2>(1)
    T_170982[1] := UInt<2>(2)
    wire T_170983 : UInt<2>[1]
    T_170983[0] := UInt<2>(2)
    reg T_170984 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when s1_clk_en : T_170984 := meta.resp[7].coh
    wire T_170985 : UInt<3>[3]
    T_170985[0] := UInt<3>(0)
    T_170985[1] := UInt<3>(1)
    T_170985[2] := UInt<3>(2)
    wire T_170986 : UInt<2>[2]
    T_170986[0] := UInt<2>(0)
    T_170986[1] := UInt<2>(1)
    wire T_170987 : UInt<2>[3]
    T_170987[0] := UInt<2>(1)
    T_170987[1] := UInt<2>(2)
    T_170987[2] := UInt<2>(3)
    wire T_170988 : UInt<2>[2]
    T_170988[0] := UInt<2>(2)
    T_170988[1] := UInt<2>(3)
    wire T_170989 : UInt<2>[1]
    T_170989[0] := UInt<2>(3)
    wire T_170990 : UInt<3>[3]
    T_170990[0] := UInt<3>(0)
    T_170990[1] := UInt<3>(1)
    T_170990[2] := UInt<3>(2)
    wire T_170991 : UInt<2>[2]
    T_170991[0] := UInt<2>(0)
    T_170991[1] := UInt<2>(1)
    wire T_170992 : UInt<2>[3]
    T_170992[0] := UInt<2>(1)
    T_170992[1] := UInt<2>(2)
    T_170992[2] := UInt<2>(3)
    wire T_170993 : UInt<2>[2]
    T_170993[0] := UInt<2>(2)
    T_170993[1] := UInt<2>(3)
    wire T_170994 : UInt<2>[1]
    T_170994[0] := UInt<2>(3)
    wire T_170995 : UInt<3>[3]
    T_170995[0] := UInt<3>(0)
    T_170995[1] := UInt<3>(1)
    T_170995[2] := UInt<3>(2)
    wire T_170996 : UInt<0>[1]
    T_170996[0] := UInt<0>(0)
    wire T_170997 : UInt<2>[2]
    T_170997[0] := UInt<2>(1)
    T_170997[1] := UInt<2>(2)
    wire T_170998 : UInt<2>[2]
    T_170998[0] := UInt<2>(1)
    T_170998[1] := UInt<2>(2)
    wire T_170999 : UInt<2>[1]
    T_170999[0] := UInt<2>(2)
    wire T_171000 : UInt<3>[3]
    T_171000[0] := UInt<3>(0)
    T_171000[1] := UInt<3>(1)
    T_171000[2] := UInt<3>(2)
    wire T_171001 : UInt<2>[2]
    T_171001[0] := UInt<2>(0)
    T_171001[1] := UInt<2>(1)
    wire T_171002 : UInt<2>[3]
    T_171002[0] := UInt<2>(1)
    T_171002[1] := UInt<2>(2)
    T_171002[2] := UInt<2>(3)
    wire T_171003 : UInt<2>[2]
    T_171003[0] := UInt<2>(2)
    T_171003[1] := UInt<2>(3)
    wire T_171004 : UInt<2>[1]
    T_171004[0] := UInt<2>(3)
    wire T_171005 : UInt<3>[3]
    T_171005[0] := UInt<3>(0)
    T_171005[1] := UInt<3>(1)
    T_171005[2] := UInt<3>(2)
    wire T_171006 : UInt<2>[2]
    T_171006[0] := UInt<2>(0)
    T_171006[1] := UInt<2>(1)
    wire T_171007 : UInt<2>[3]
    T_171007[0] := UInt<2>(1)
    T_171007[1] := UInt<2>(2)
    T_171007[2] := UInt<2>(3)
    wire T_171008 : UInt<2>[2]
    T_171008[0] := UInt<2>(2)
    T_171008[1] := UInt<2>(3)
    wire T_171009 : UInt<2>[1]
    T_171009[0] := UInt<2>(3)
    wire T_171010 : UInt<3>[3]
    T_171010[0] := UInt<3>(0)
    T_171010[1] := UInt<3>(1)
    T_171010[2] := UInt<3>(2)
    wire T_171011 : UInt<0>[1]
    T_171011[0] := UInt<0>(0)
    wire T_171012 : UInt<2>[2]
    T_171012[0] := UInt<2>(1)
    T_171012[1] := UInt<2>(2)
    wire T_171013 : UInt<2>[2]
    T_171013[0] := UInt<2>(1)
    T_171013[1] := UInt<2>(2)
    wire T_171014 : UInt<2>[1]
    T_171014[0] := UInt<2>(2)
    wire T_171015 : UInt<3>[3]
    T_171015[0] := UInt<3>(0)
    T_171015[1] := UInt<3>(1)
    T_171015[2] := UInt<3>(2)
    wire T_171016 : UInt<2>[2]
    T_171016[0] := UInt<2>(0)
    T_171016[1] := UInt<2>(1)
    wire T_171017 : UInt<2>[3]
    T_171017[0] := UInt<2>(1)
    T_171017[1] := UInt<2>(2)
    T_171017[2] := UInt<2>(3)
    wire T_171018 : UInt<2>[2]
    T_171018[0] := UInt<2>(2)
    T_171018[1] := UInt<2>(3)
    wire T_171019 : UInt<2>[1]
    T_171019[0] := UInt<2>(3)
    wire T_171020 : UInt<3>[3]
    T_171020[0] := UInt<3>(0)
    T_171020[1] := UInt<3>(1)
    T_171020[2] := UInt<3>(2)
    wire T_171021 : UInt<2>[2]
    T_171021[0] := UInt<2>(0)
    T_171021[1] := UInt<2>(1)
    wire T_171022 : UInt<2>[3]
    T_171022[0] := UInt<2>(1)
    T_171022[1] := UInt<2>(2)
    T_171022[2] := UInt<2>(3)
    wire T_171023 : UInt<2>[2]
    T_171023[0] := UInt<2>(2)
    T_171023[1] := UInt<2>(3)
    wire T_171024 : UInt<2>[1]
    T_171024[0] := UInt<2>(3)
    wire T_171025 : UInt<3>[3]
    T_171025[0] := UInt<3>(0)
    T_171025[1] := UInt<3>(1)
    T_171025[2] := UInt<3>(2)
    wire T_171026 : UInt<0>[1]
    T_171026[0] := UInt<0>(0)
    wire T_171027 : UInt<2>[2]
    T_171027[0] := UInt<2>(1)
    T_171027[1] := UInt<2>(2)
    wire T_171028 : UInt<2>[2]
    T_171028[0] := UInt<2>(1)
    T_171028[1] := UInt<2>(2)
    wire T_171029 : UInt<2>[1]
    T_171029[0] := UInt<2>(2)
    wire T_171030 : UInt<3>[3]
    T_171030[0] := UInt<3>(0)
    T_171030[1] := UInt<3>(1)
    T_171030[2] := UInt<3>(2)
    wire T_171031 : UInt<2>[2]
    T_171031[0] := UInt<2>(0)
    T_171031[1] := UInt<2>(1)
    wire T_171032 : UInt<2>[3]
    T_171032[0] := UInt<2>(1)
    T_171032[1] := UInt<2>(2)
    T_171032[2] := UInt<2>(3)
    wire T_171033 : UInt<2>[2]
    T_171033[0] := UInt<2>(2)
    T_171033[1] := UInt<2>(3)
    wire T_171034 : UInt<2>[1]
    T_171034[0] := UInt<2>(3)
    wire T_171035 : UInt<3>[3]
    T_171035[0] := UInt<3>(0)
    T_171035[1] := UInt<3>(1)
    T_171035[2] := UInt<3>(2)
    wire T_171036 : UInt<2>[2]
    T_171036[0] := UInt<2>(0)
    T_171036[1] := UInt<2>(1)
    wire T_171037 : UInt<2>[3]
    T_171037[0] := UInt<2>(1)
    T_171037[1] := UInt<2>(2)
    T_171037[2] := UInt<2>(3)
    wire T_171038 : UInt<2>[2]
    T_171038[0] := UInt<2>(2)
    T_171038[1] := UInt<2>(3)
    wire T_171039 : UInt<2>[1]
    T_171039[0] := UInt<2>(3)
    wire T_171040 : UInt<3>[3]
    T_171040[0] := UInt<3>(0)
    T_171040[1] := UInt<3>(1)
    T_171040[2] := UInt<3>(2)
    wire T_171041 : UInt<0>[1]
    T_171041[0] := UInt<0>(0)
    wire T_171042 : UInt<2>[2]
    T_171042[0] := UInt<2>(1)
    T_171042[1] := UInt<2>(2)
    wire T_171043 : UInt<2>[2]
    T_171043[0] := UInt<2>(1)
    T_171043[1] := UInt<2>(2)
    wire T_171044 : UInt<2>[1]
    T_171044[0] := UInt<2>(2)
    wire T_171045 : UInt<3>[3]
    T_171045[0] := UInt<3>(0)
    T_171045[1] := UInt<3>(1)
    T_171045[2] := UInt<3>(2)
    wire T_171046 : UInt<2>[2]
    T_171046[0] := UInt<2>(0)
    T_171046[1] := UInt<2>(1)
    wire T_171047 : UInt<2>[3]
    T_171047[0] := UInt<2>(1)
    T_171047[1] := UInt<2>(2)
    T_171047[2] := UInt<2>(3)
    wire T_171048 : UInt<2>[2]
    T_171048[0] := UInt<2>(2)
    T_171048[1] := UInt<2>(3)
    wire T_171049 : UInt<2>[1]
    T_171049[0] := UInt<2>(3)
    wire T_171050 : UInt<3>[3]
    T_171050[0] := UInt<3>(0)
    T_171050[1] := UInt<3>(1)
    T_171050[2] := UInt<3>(2)
    wire T_171051 : UInt<2>[2]
    T_171051[0] := UInt<2>(0)
    T_171051[1] := UInt<2>(1)
    wire T_171052 : UInt<2>[3]
    T_171052[0] := UInt<2>(1)
    T_171052[1] := UInt<2>(2)
    T_171052[2] := UInt<2>(3)
    wire T_171053 : UInt<2>[2]
    T_171053[0] := UInt<2>(2)
    T_171053[1] := UInt<2>(3)
    wire T_171054 : UInt<2>[1]
    T_171054[0] := UInt<2>(3)
    wire T_171055 : UInt<3>[3]
    T_171055[0] := UInt<3>(0)
    T_171055[1] := UInt<3>(1)
    T_171055[2] := UInt<3>(2)
    wire T_171056 : UInt<0>[1]
    T_171056[0] := UInt<0>(0)
    wire T_171057 : UInt<2>[2]
    T_171057[0] := UInt<2>(1)
    T_171057[1] := UInt<2>(2)
    wire T_171058 : UInt<2>[2]
    T_171058[0] := UInt<2>(1)
    T_171058[1] := UInt<2>(2)
    wire T_171059 : UInt<2>[1]
    T_171059[0] := UInt<2>(2)
    wire T_171060 : UInt<3>[3]
    T_171060[0] := UInt<3>(0)
    T_171060[1] := UInt<3>(1)
    T_171060[2] := UInt<3>(2)
    wire T_171061 : UInt<2>[2]
    T_171061[0] := UInt<2>(0)
    T_171061[1] := UInt<2>(1)
    wire T_171062 : UInt<2>[3]
    T_171062[0] := UInt<2>(1)
    T_171062[1] := UInt<2>(2)
    T_171062[2] := UInt<2>(3)
    wire T_171063 : UInt<2>[2]
    T_171063[0] := UInt<2>(2)
    T_171063[1] := UInt<2>(3)
    wire T_171064 : UInt<2>[1]
    T_171064[0] := UInt<2>(3)
    wire T_171065 : UInt<3>[3]
    T_171065[0] := UInt<3>(0)
    T_171065[1] := UInt<3>(1)
    T_171065[2] := UInt<3>(2)
    wire T_171066 : UInt<2>[2]
    T_171066[0] := UInt<2>(0)
    T_171066[1] := UInt<2>(1)
    wire T_171067 : UInt<2>[3]
    T_171067[0] := UInt<2>(1)
    T_171067[1] := UInt<2>(2)
    T_171067[2] := UInt<2>(3)
    wire T_171068 : UInt<2>[2]
    T_171068[0] := UInt<2>(2)
    T_171068[1] := UInt<2>(3)
    wire T_171069 : UInt<2>[1]
    T_171069[0] := UInt<2>(3)
    wire T_171070 : UInt<3>[3]
    T_171070[0] := UInt<3>(0)
    T_171070[1] := UInt<3>(1)
    T_171070[2] := UInt<3>(2)
    wire T_171071 : UInt<0>[1]
    T_171071[0] := UInt<0>(0)
    wire T_171072 : UInt<2>[2]
    T_171072[0] := UInt<2>(1)
    T_171072[1] := UInt<2>(2)
    wire T_171073 : UInt<2>[2]
    T_171073[0] := UInt<2>(1)
    T_171073[1] := UInt<2>(2)
    wire T_171074 : UInt<2>[1]
    T_171074[0] := UInt<2>(2)
    wire T_171075 : UInt<3>[3]
    T_171075[0] := UInt<3>(0)
    T_171075[1] := UInt<3>(1)
    T_171075[2] := UInt<3>(2)
    wire T_171076 : UInt<2>[2]
    T_171076[0] := UInt<2>(0)
    T_171076[1] := UInt<2>(1)
    wire T_171077 : UInt<2>[3]
    T_171077[0] := UInt<2>(1)
    T_171077[1] := UInt<2>(2)
    T_171077[2] := UInt<2>(3)
    wire T_171078 : UInt<2>[2]
    T_171078[0] := UInt<2>(2)
    T_171078[1] := UInt<2>(3)
    wire T_171079 : UInt<2>[1]
    T_171079[0] := UInt<2>(3)
    wire T_171080 : UInt<3>[3]
    T_171080[0] := UInt<3>(0)
    T_171080[1] := UInt<3>(1)
    T_171080[2] := UInt<3>(2)
    wire T_171081 : UInt<2>[2]
    T_171081[0] := UInt<2>(0)
    T_171081[1] := UInt<2>(1)
    wire T_171082 : UInt<2>[3]
    T_171082[0] := UInt<2>(1)
    T_171082[1] := UInt<2>(2)
    T_171082[2] := UInt<2>(3)
    wire T_171083 : UInt<2>[2]
    T_171083[0] := UInt<2>(2)
    T_171083[1] := UInt<2>(3)
    wire T_171084 : UInt<2>[1]
    T_171084[0] := UInt<2>(3)
    wire T_171085 : UInt<3>[3]
    T_171085[0] := UInt<3>(0)
    T_171085[1] := UInt<3>(1)
    T_171085[2] := UInt<3>(2)
    wire T_171086 : UInt<0>[1]
    T_171086[0] := UInt<0>(0)
    wire T_171087 : UInt<2>[2]
    T_171087[0] := UInt<2>(1)
    T_171087[1] := UInt<2>(2)
    wire T_171088 : UInt<2>[2]
    T_171088[0] := UInt<2>(1)
    T_171088[1] := UInt<2>(2)
    wire T_171089 : UInt<2>[1]
    T_171089[0] := UInt<2>(2)
    wire T_171090 : UInt<3>[3]
    T_171090[0] := UInt<3>(0)
    T_171090[1] := UInt<3>(1)
    T_171090[2] := UInt<3>(2)
    wire T_171091 : UInt<2>[2]
    T_171091[0] := UInt<2>(0)
    T_171091[1] := UInt<2>(1)
    wire T_171092 : UInt<2>[3]
    T_171092[0] := UInt<2>(1)
    T_171092[1] := UInt<2>(2)
    T_171092[2] := UInt<2>(3)
    wire T_171093 : UInt<2>[2]
    T_171093[0] := UInt<2>(2)
    T_171093[1] := UInt<2>(3)
    wire T_171094 : UInt<2>[1]
    T_171094[0] := UInt<2>(3)
    wire T_171095 : UInt<3>[3]
    T_171095[0] := UInt<3>(0)
    T_171095[1] := UInt<3>(1)
    T_171095[2] := UInt<3>(2)
    wire T_171096 : UInt<2>[2]
    T_171096[0] := UInt<2>(0)
    T_171096[1] := UInt<2>(1)
    wire T_171097 : UInt<2>[3]
    T_171097[0] := UInt<2>(1)
    T_171097[1] := UInt<2>(2)
    T_171097[2] := UInt<2>(3)
    wire T_171098 : UInt<2>[2]
    T_171098[0] := UInt<2>(2)
    T_171098[1] := UInt<2>(3)
    wire T_171099 : UInt<2>[1]
    T_171099[0] := UInt<2>(3)
    wire T_171100 : UInt<3>[3]
    T_171100[0] := UInt<3>(0)
    T_171100[1] := UInt<3>(1)
    T_171100[2] := UInt<3>(2)
    wire T_171101 : UInt<0>[1]
    T_171101[0] := UInt<0>(0)
    wire T_171102 : UInt<2>[2]
    T_171102[0] := UInt<2>(1)
    T_171102[1] := UInt<2>(2)
    wire T_171103 : UInt<2>[2]
    T_171103[0] := UInt<2>(1)
    T_171103[1] := UInt<2>(2)
    wire T_171104 : UInt<2>[1]
    T_171104[0] := UInt<2>(2)
    wire T_171105 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}[8]
    T_171105[0] := T_170872
    T_171105[1] := T_170888
    T_171105[2] := T_170904
    T_171105[3] := T_170920
    T_171105[4] := T_170936
    T_171105[5] := T_170952
    T_171105[6] := T_170968
    T_171105[7] := T_170984
    node T_171106 = bit(s2_tag_match_way, 0)
    node T_171107 = bit(s2_tag_match_way, 1)
    node T_171108 = bit(s2_tag_match_way, 2)
    node T_171109 = bit(s2_tag_match_way, 3)
    node T_171110 = bit(s2_tag_match_way, 4)
    node T_171111 = bit(s2_tag_match_way, 5)
    node T_171112 = bit(s2_tag_match_way, 6)
    node T_171113 = bit(s2_tag_match_way, 7)
    node T_171114 = cat(T_171105[0].inner.sharers, UInt<1>(0))
    node T_171115 = cat(T_171105[0].outer.state, UInt<1>(0))
    node T_171116 = cat(UInt<1>(0), T_171115)
    node T_171117 = cat(T_171114, T_171116)
    node T_171118 = cat(T_171117, UInt<5>(0))
    wire T_171119 : UInt<1>
    T_171119 := UInt<1>(0)
    when T_171106 : T_171119 := T_171118
    node T_171120 = cat(T_171105[1].inner.sharers, UInt<1>(0))
    node T_171121 = cat(T_171105[1].outer.state, UInt<1>(0))
    node T_171122 = cat(UInt<1>(0), T_171121)
    node T_171123 = cat(T_171120, T_171122)
    node T_171124 = cat(T_171123, UInt<5>(0))
    wire T_171125 : UInt<1>
    T_171125 := UInt<1>(0)
    when T_171107 : T_171125 := T_171124
    node T_171126 = cat(T_171105[2].inner.sharers, UInt<1>(0))
    node T_171127 = cat(T_171105[2].outer.state, UInt<1>(0))
    node T_171128 = cat(UInt<1>(0), T_171127)
    node T_171129 = cat(T_171126, T_171128)
    node T_171130 = cat(T_171129, UInt<5>(0))
    wire T_171131 : UInt<1>
    T_171131 := UInt<1>(0)
    when T_171108 : T_171131 := T_171130
    node T_171132 = cat(T_171105[3].inner.sharers, UInt<1>(0))
    node T_171133 = cat(T_171105[3].outer.state, UInt<1>(0))
    node T_171134 = cat(UInt<1>(0), T_171133)
    node T_171135 = cat(T_171132, T_171134)
    node T_171136 = cat(T_171135, UInt<5>(0))
    wire T_171137 : UInt<1>
    T_171137 := UInt<1>(0)
    when T_171109 : T_171137 := T_171136
    node T_171138 = cat(T_171105[4].inner.sharers, UInt<1>(0))
    node T_171139 = cat(T_171105[4].outer.state, UInt<1>(0))
    node T_171140 = cat(UInt<1>(0), T_171139)
    node T_171141 = cat(T_171138, T_171140)
    node T_171142 = cat(T_171141, UInt<5>(0))
    wire T_171143 : UInt<1>
    T_171143 := UInt<1>(0)
    when T_171110 : T_171143 := T_171142
    node T_171144 = cat(T_171105[5].inner.sharers, UInt<1>(0))
    node T_171145 = cat(T_171105[5].outer.state, UInt<1>(0))
    node T_171146 = cat(UInt<1>(0), T_171145)
    node T_171147 = cat(T_171144, T_171146)
    node T_171148 = cat(T_171147, UInt<5>(0))
    wire T_171149 : UInt<1>
    T_171149 := UInt<1>(0)
    when T_171111 : T_171149 := T_171148
    node T_171150 = cat(T_171105[6].inner.sharers, UInt<1>(0))
    node T_171151 = cat(T_171105[6].outer.state, UInt<1>(0))
    node T_171152 = cat(UInt<1>(0), T_171151)
    node T_171153 = cat(T_171150, T_171152)
    node T_171154 = cat(T_171153, UInt<5>(0))
    wire T_171155 : UInt<1>
    T_171155 := UInt<1>(0)
    when T_171112 : T_171155 := T_171154
    node T_171156 = cat(T_171105[7].inner.sharers, UInt<1>(0))
    node T_171157 = cat(T_171105[7].outer.state, UInt<1>(0))
    node T_171158 = cat(UInt<1>(0), T_171157)
    node T_171159 = cat(T_171156, T_171158)
    node T_171160 = cat(T_171159, UInt<5>(0))
    wire T_171161 : UInt<1>
    T_171161 := UInt<1>(0)
    when T_171113 : T_171161 := T_171160
    node T_171162 = or(T_171119, T_171125)
    node T_171163 = or(T_171162, T_171131)
    node T_171164 = or(T_171163, T_171137)
    node T_171165 = or(T_171164, T_171143)
    node T_171166 = or(T_171165, T_171149)
    node T_171167 = or(T_171166, T_171155)
    node T_171168 = or(T_171167, T_171161)
    wire T_171169 : UInt<3>[3]
    T_171169[0] := UInt<3>(0)
    T_171169[1] := UInt<3>(1)
    T_171169[2] := UInt<3>(2)
    wire T_171170 : UInt<2>[2]
    T_171170[0] := UInt<2>(0)
    T_171170[1] := UInt<2>(1)
    wire T_171171 : UInt<2>[3]
    T_171171[0] := UInt<2>(1)
    T_171171[1] := UInt<2>(2)
    T_171171[2] := UInt<2>(3)
    wire T_171172 : UInt<2>[2]
    T_171172[0] := UInt<2>(2)
    T_171172[1] := UInt<2>(3)
    wire T_171173 : UInt<2>[1]
    T_171173[0] := UInt<2>(3)
    wire T_171174 : UInt<3>[3]
    T_171174[0] := UInt<3>(0)
    T_171174[1] := UInt<3>(1)
    T_171174[2] := UInt<3>(2)
    wire T_171175 : UInt<2>[2]
    T_171175[0] := UInt<2>(0)
    T_171175[1] := UInt<2>(1)
    wire T_171176 : UInt<2>[3]
    T_171176[0] := UInt<2>(1)
    T_171176[1] := UInt<2>(2)
    T_171176[2] := UInt<2>(3)
    wire T_171177 : UInt<2>[2]
    T_171177[0] := UInt<2>(2)
    T_171177[1] := UInt<2>(3)
    wire T_171178 : UInt<2>[1]
    T_171178[0] := UInt<2>(3)
    wire T_171179 : UInt<3>[3]
    T_171179[0] := UInt<3>(0)
    T_171179[1] := UInt<3>(1)
    T_171179[2] := UInt<3>(2)
    wire T_171180 : UInt<0>[1]
    T_171180[0] := UInt<0>(0)
    wire T_171181 : UInt<2>[2]
    T_171181[0] := UInt<2>(1)
    T_171181[1] := UInt<2>(2)
    wire T_171182 : UInt<2>[2]
    T_171182[0] := UInt<2>(1)
    T_171182[1] := UInt<2>(2)
    wire T_171183 : UInt<2>[1]
    T_171183[0] := UInt<2>(2)
    wire T_171184 : UInt<3>[3]
    T_171184[0] := UInt<3>(0)
    T_171184[1] := UInt<3>(1)
    T_171184[2] := UInt<3>(2)
    wire T_171185 : UInt<2>[2]
    T_171185[0] := UInt<2>(0)
    T_171185[1] := UInt<2>(1)
    wire T_171186 : UInt<2>[3]
    T_171186[0] := UInt<2>(1)
    T_171186[1] := UInt<2>(2)
    T_171186[2] := UInt<2>(3)
    wire T_171187 : UInt<2>[2]
    T_171187[0] := UInt<2>(2)
    T_171187[1] := UInt<2>(3)
    wire T_171188 : UInt<2>[1]
    T_171188[0] := UInt<2>(3)
    wire T_171189 : UInt<3>[3]
    T_171189[0] := UInt<3>(0)
    T_171189[1] := UInt<3>(1)
    T_171189[2] := UInt<3>(2)
    wire T_171190 : UInt<2>[2]
    T_171190[0] := UInt<2>(0)
    T_171190[1] := UInt<2>(1)
    wire T_171191 : UInt<2>[3]
    T_171191[0] := UInt<2>(1)
    T_171191[1] := UInt<2>(2)
    T_171191[2] := UInt<2>(3)
    wire T_171192 : UInt<2>[2]
    T_171192[0] := UInt<2>(2)
    T_171192[1] := UInt<2>(3)
    wire T_171193 : UInt<2>[1]
    T_171193[0] := UInt<2>(3)
    wire T_171194 : UInt<3>[3]
    T_171194[0] := UInt<3>(0)
    T_171194[1] := UInt<3>(1)
    T_171194[2] := UInt<3>(2)
    wire T_171195 : UInt<0>[1]
    T_171195[0] := UInt<0>(0)
    wire T_171196 : UInt<2>[2]
    T_171196[0] := UInt<2>(1)
    T_171196[1] := UInt<2>(2)
    wire T_171197 : UInt<2>[2]
    T_171197[0] := UInt<2>(1)
    T_171197[1] := UInt<2>(2)
    wire T_171198 : UInt<2>[1]
    T_171198[0] := UInt<2>(2)
    wire s2_hit_coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    node T_171199 = bits(T_171168, 0, 0)
    s2_hit_coh.outer.makeVoluntaryWriteback$default$4 := T_171199
    node T_171200 = bits(T_171168, 1, 1)
    s2_hit_coh.outer.makeVoluntaryWriteback$default$3 := T_171200
    node T_171201 = bits(T_171168, 2, 2)
    s2_hit_coh.outer.makeVoluntaryRelease$default$5 := T_171201
    node T_171202 = bits(T_171168, 3, 3)
    s2_hit_coh.outer.makeVoluntaryRelease$default$4 := T_171202
    node T_171203 = bits(T_171168, 4, 4)
    s2_hit_coh.outer.makeRelease$default$3 := T_171203
    node T_171204 = bits(T_171168, 5, 5)
    s2_hit_coh.outer.makeRelease$default$2 := T_171204
    node T_171205 = bits(T_171168, 7, 6)
    s2_hit_coh.outer.state := T_171205
    node T_171206 = bits(T_171168, 8, 8)
    s2_hit_coh.inner.makeGrant$default$4 := T_171206
    node T_171207 = bits(T_171168, 9, 9)
    s2_hit_coh.inner.makeGrant$default$3 := T_171207
    node T_171208 = bits(T_171168, 10, 10)
    s2_hit_coh.inner.sharers := T_171208
    wire T_171209 : UInt<1>
    T_171209 := UInt<1>(0)
    reg T_171210 : UInt<16>
    onreset T_171210 := UInt<16>(1)
    when T_171209 : 
      node T_171211 = bit(T_171210, 0)
      node T_171212 = bit(T_171210, 2)
      node T_171213 = xor(T_171211, T_171212)
      node T_171214 = bit(T_171210, 3)
      node T_171215 = xor(T_171213, T_171214)
      node T_171216 = bit(T_171210, 5)
      node T_171217 = xor(T_171215, T_171216)
      node T_171218 = bits(T_171210, 15, 1)
      node T_171219 = cat(T_171217, T_171218)
      T_171210 := T_171219
    node T_171220 = bits(T_171210, 2, 0)
    node s1_replaced_way_en = dshl(UInt<1>(1), T_171220)
    node T_171221 = bits(T_171210, 2, 0)
    reg T_171222 : UInt<3>
    when s1_clk_en : T_171222 := T_171221
    node s2_replaced_way_en = dshl(UInt<1>(1), T_171222)
    node T_171223 = bit(s1_replaced_way_en, 0)
    node T_171224 = and(s1_clk_en, T_171223)
    wire T_171225 : UInt<3>[3]
    T_171225[0] := UInt<3>(0)
    T_171225[1] := UInt<3>(1)
    T_171225[2] := UInt<3>(2)
    wire T_171226 : UInt<2>[2]
    T_171226[0] := UInt<2>(0)
    T_171226[1] := UInt<2>(1)
    wire T_171227 : UInt<2>[3]
    T_171227[0] := UInt<2>(1)
    T_171227[1] := UInt<2>(2)
    T_171227[2] := UInt<2>(3)
    wire T_171228 : UInt<2>[2]
    T_171228[0] := UInt<2>(2)
    T_171228[1] := UInt<2>(3)
    wire T_171229 : UInt<2>[1]
    T_171229[0] := UInt<2>(3)
    wire T_171230 : UInt<3>[3]
    T_171230[0] := UInt<3>(0)
    T_171230[1] := UInt<3>(1)
    T_171230[2] := UInt<3>(2)
    wire T_171231 : UInt<2>[2]
    T_171231[0] := UInt<2>(0)
    T_171231[1] := UInt<2>(1)
    wire T_171232 : UInt<2>[3]
    T_171232[0] := UInt<2>(1)
    T_171232[1] := UInt<2>(2)
    T_171232[2] := UInt<2>(3)
    wire T_171233 : UInt<2>[2]
    T_171233[0] := UInt<2>(2)
    T_171233[1] := UInt<2>(3)
    wire T_171234 : UInt<2>[1]
    T_171234[0] := UInt<2>(3)
    wire T_171235 : UInt<3>[3]
    T_171235[0] := UInt<3>(0)
    T_171235[1] := UInt<3>(1)
    T_171235[2] := UInt<3>(2)
    wire T_171236 : UInt<0>[1]
    T_171236[0] := UInt<0>(0)
    wire T_171237 : UInt<2>[2]
    T_171237[0] := UInt<2>(1)
    T_171237[1] := UInt<2>(2)
    wire T_171238 : UInt<2>[2]
    T_171238[0] := UInt<2>(1)
    T_171238[1] := UInt<2>(2)
    wire T_171239 : UInt<2>[1]
    T_171239[0] := UInt<2>(2)
    reg T_171240 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171224 : T_171240 := meta.resp[0]
    node T_171241 = bit(s1_replaced_way_en, 1)
    node T_171242 = and(s1_clk_en, T_171241)
    wire T_171243 : UInt<3>[3]
    T_171243[0] := UInt<3>(0)
    T_171243[1] := UInt<3>(1)
    T_171243[2] := UInt<3>(2)
    wire T_171244 : UInt<2>[2]
    T_171244[0] := UInt<2>(0)
    T_171244[1] := UInt<2>(1)
    wire T_171245 : UInt<2>[3]
    T_171245[0] := UInt<2>(1)
    T_171245[1] := UInt<2>(2)
    T_171245[2] := UInt<2>(3)
    wire T_171246 : UInt<2>[2]
    T_171246[0] := UInt<2>(2)
    T_171246[1] := UInt<2>(3)
    wire T_171247 : UInt<2>[1]
    T_171247[0] := UInt<2>(3)
    wire T_171248 : UInt<3>[3]
    T_171248[0] := UInt<3>(0)
    T_171248[1] := UInt<3>(1)
    T_171248[2] := UInt<3>(2)
    wire T_171249 : UInt<2>[2]
    T_171249[0] := UInt<2>(0)
    T_171249[1] := UInt<2>(1)
    wire T_171250 : UInt<2>[3]
    T_171250[0] := UInt<2>(1)
    T_171250[1] := UInt<2>(2)
    T_171250[2] := UInt<2>(3)
    wire T_171251 : UInt<2>[2]
    T_171251[0] := UInt<2>(2)
    T_171251[1] := UInt<2>(3)
    wire T_171252 : UInt<2>[1]
    T_171252[0] := UInt<2>(3)
    wire T_171253 : UInt<3>[3]
    T_171253[0] := UInt<3>(0)
    T_171253[1] := UInt<3>(1)
    T_171253[2] := UInt<3>(2)
    wire T_171254 : UInt<0>[1]
    T_171254[0] := UInt<0>(0)
    wire T_171255 : UInt<2>[2]
    T_171255[0] := UInt<2>(1)
    T_171255[1] := UInt<2>(2)
    wire T_171256 : UInt<2>[2]
    T_171256[0] := UInt<2>(1)
    T_171256[1] := UInt<2>(2)
    wire T_171257 : UInt<2>[1]
    T_171257[0] := UInt<2>(2)
    reg T_171258 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171242 : T_171258 := meta.resp[1]
    node T_171259 = bit(s1_replaced_way_en, 2)
    node T_171260 = and(s1_clk_en, T_171259)
    wire T_171261 : UInt<3>[3]
    T_171261[0] := UInt<3>(0)
    T_171261[1] := UInt<3>(1)
    T_171261[2] := UInt<3>(2)
    wire T_171262 : UInt<2>[2]
    T_171262[0] := UInt<2>(0)
    T_171262[1] := UInt<2>(1)
    wire T_171263 : UInt<2>[3]
    T_171263[0] := UInt<2>(1)
    T_171263[1] := UInt<2>(2)
    T_171263[2] := UInt<2>(3)
    wire T_171264 : UInt<2>[2]
    T_171264[0] := UInt<2>(2)
    T_171264[1] := UInt<2>(3)
    wire T_171265 : UInt<2>[1]
    T_171265[0] := UInt<2>(3)
    wire T_171266 : UInt<3>[3]
    T_171266[0] := UInt<3>(0)
    T_171266[1] := UInt<3>(1)
    T_171266[2] := UInt<3>(2)
    wire T_171267 : UInt<2>[2]
    T_171267[0] := UInt<2>(0)
    T_171267[1] := UInt<2>(1)
    wire T_171268 : UInt<2>[3]
    T_171268[0] := UInt<2>(1)
    T_171268[1] := UInt<2>(2)
    T_171268[2] := UInt<2>(3)
    wire T_171269 : UInt<2>[2]
    T_171269[0] := UInt<2>(2)
    T_171269[1] := UInt<2>(3)
    wire T_171270 : UInt<2>[1]
    T_171270[0] := UInt<2>(3)
    wire T_171271 : UInt<3>[3]
    T_171271[0] := UInt<3>(0)
    T_171271[1] := UInt<3>(1)
    T_171271[2] := UInt<3>(2)
    wire T_171272 : UInt<0>[1]
    T_171272[0] := UInt<0>(0)
    wire T_171273 : UInt<2>[2]
    T_171273[0] := UInt<2>(1)
    T_171273[1] := UInt<2>(2)
    wire T_171274 : UInt<2>[2]
    T_171274[0] := UInt<2>(1)
    T_171274[1] := UInt<2>(2)
    wire T_171275 : UInt<2>[1]
    T_171275[0] := UInt<2>(2)
    reg T_171276 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171260 : T_171276 := meta.resp[2]
    node T_171277 = bit(s1_replaced_way_en, 3)
    node T_171278 = and(s1_clk_en, T_171277)
    wire T_171279 : UInt<3>[3]
    T_171279[0] := UInt<3>(0)
    T_171279[1] := UInt<3>(1)
    T_171279[2] := UInt<3>(2)
    wire T_171280 : UInt<2>[2]
    T_171280[0] := UInt<2>(0)
    T_171280[1] := UInt<2>(1)
    wire T_171281 : UInt<2>[3]
    T_171281[0] := UInt<2>(1)
    T_171281[1] := UInt<2>(2)
    T_171281[2] := UInt<2>(3)
    wire T_171282 : UInt<2>[2]
    T_171282[0] := UInt<2>(2)
    T_171282[1] := UInt<2>(3)
    wire T_171283 : UInt<2>[1]
    T_171283[0] := UInt<2>(3)
    wire T_171284 : UInt<3>[3]
    T_171284[0] := UInt<3>(0)
    T_171284[1] := UInt<3>(1)
    T_171284[2] := UInt<3>(2)
    wire T_171285 : UInt<2>[2]
    T_171285[0] := UInt<2>(0)
    T_171285[1] := UInt<2>(1)
    wire T_171286 : UInt<2>[3]
    T_171286[0] := UInt<2>(1)
    T_171286[1] := UInt<2>(2)
    T_171286[2] := UInt<2>(3)
    wire T_171287 : UInt<2>[2]
    T_171287[0] := UInt<2>(2)
    T_171287[1] := UInt<2>(3)
    wire T_171288 : UInt<2>[1]
    T_171288[0] := UInt<2>(3)
    wire T_171289 : UInt<3>[3]
    T_171289[0] := UInt<3>(0)
    T_171289[1] := UInt<3>(1)
    T_171289[2] := UInt<3>(2)
    wire T_171290 : UInt<0>[1]
    T_171290[0] := UInt<0>(0)
    wire T_171291 : UInt<2>[2]
    T_171291[0] := UInt<2>(1)
    T_171291[1] := UInt<2>(2)
    wire T_171292 : UInt<2>[2]
    T_171292[0] := UInt<2>(1)
    T_171292[1] := UInt<2>(2)
    wire T_171293 : UInt<2>[1]
    T_171293[0] := UInt<2>(2)
    reg T_171294 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171278 : T_171294 := meta.resp[3]
    node T_171295 = bit(s1_replaced_way_en, 4)
    node T_171296 = and(s1_clk_en, T_171295)
    wire T_171297 : UInt<3>[3]
    T_171297[0] := UInt<3>(0)
    T_171297[1] := UInt<3>(1)
    T_171297[2] := UInt<3>(2)
    wire T_171298 : UInt<2>[2]
    T_171298[0] := UInt<2>(0)
    T_171298[1] := UInt<2>(1)
    wire T_171299 : UInt<2>[3]
    T_171299[0] := UInt<2>(1)
    T_171299[1] := UInt<2>(2)
    T_171299[2] := UInt<2>(3)
    wire T_171300 : UInt<2>[2]
    T_171300[0] := UInt<2>(2)
    T_171300[1] := UInt<2>(3)
    wire T_171301 : UInt<2>[1]
    T_171301[0] := UInt<2>(3)
    wire T_171302 : UInt<3>[3]
    T_171302[0] := UInt<3>(0)
    T_171302[1] := UInt<3>(1)
    T_171302[2] := UInt<3>(2)
    wire T_171303 : UInt<2>[2]
    T_171303[0] := UInt<2>(0)
    T_171303[1] := UInt<2>(1)
    wire T_171304 : UInt<2>[3]
    T_171304[0] := UInt<2>(1)
    T_171304[1] := UInt<2>(2)
    T_171304[2] := UInt<2>(3)
    wire T_171305 : UInt<2>[2]
    T_171305[0] := UInt<2>(2)
    T_171305[1] := UInt<2>(3)
    wire T_171306 : UInt<2>[1]
    T_171306[0] := UInt<2>(3)
    wire T_171307 : UInt<3>[3]
    T_171307[0] := UInt<3>(0)
    T_171307[1] := UInt<3>(1)
    T_171307[2] := UInt<3>(2)
    wire T_171308 : UInt<0>[1]
    T_171308[0] := UInt<0>(0)
    wire T_171309 : UInt<2>[2]
    T_171309[0] := UInt<2>(1)
    T_171309[1] := UInt<2>(2)
    wire T_171310 : UInt<2>[2]
    T_171310[0] := UInt<2>(1)
    T_171310[1] := UInt<2>(2)
    wire T_171311 : UInt<2>[1]
    T_171311[0] := UInt<2>(2)
    reg T_171312 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171296 : T_171312 := meta.resp[4]
    node T_171313 = bit(s1_replaced_way_en, 5)
    node T_171314 = and(s1_clk_en, T_171313)
    wire T_171315 : UInt<3>[3]
    T_171315[0] := UInt<3>(0)
    T_171315[1] := UInt<3>(1)
    T_171315[2] := UInt<3>(2)
    wire T_171316 : UInt<2>[2]
    T_171316[0] := UInt<2>(0)
    T_171316[1] := UInt<2>(1)
    wire T_171317 : UInt<2>[3]
    T_171317[0] := UInt<2>(1)
    T_171317[1] := UInt<2>(2)
    T_171317[2] := UInt<2>(3)
    wire T_171318 : UInt<2>[2]
    T_171318[0] := UInt<2>(2)
    T_171318[1] := UInt<2>(3)
    wire T_171319 : UInt<2>[1]
    T_171319[0] := UInt<2>(3)
    wire T_171320 : UInt<3>[3]
    T_171320[0] := UInt<3>(0)
    T_171320[1] := UInt<3>(1)
    T_171320[2] := UInt<3>(2)
    wire T_171321 : UInt<2>[2]
    T_171321[0] := UInt<2>(0)
    T_171321[1] := UInt<2>(1)
    wire T_171322 : UInt<2>[3]
    T_171322[0] := UInt<2>(1)
    T_171322[1] := UInt<2>(2)
    T_171322[2] := UInt<2>(3)
    wire T_171323 : UInt<2>[2]
    T_171323[0] := UInt<2>(2)
    T_171323[1] := UInt<2>(3)
    wire T_171324 : UInt<2>[1]
    T_171324[0] := UInt<2>(3)
    wire T_171325 : UInt<3>[3]
    T_171325[0] := UInt<3>(0)
    T_171325[1] := UInt<3>(1)
    T_171325[2] := UInt<3>(2)
    wire T_171326 : UInt<0>[1]
    T_171326[0] := UInt<0>(0)
    wire T_171327 : UInt<2>[2]
    T_171327[0] := UInt<2>(1)
    T_171327[1] := UInt<2>(2)
    wire T_171328 : UInt<2>[2]
    T_171328[0] := UInt<2>(1)
    T_171328[1] := UInt<2>(2)
    wire T_171329 : UInt<2>[1]
    T_171329[0] := UInt<2>(2)
    reg T_171330 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171314 : T_171330 := meta.resp[5]
    node T_171331 = bit(s1_replaced_way_en, 6)
    node T_171332 = and(s1_clk_en, T_171331)
    wire T_171333 : UInt<3>[3]
    T_171333[0] := UInt<3>(0)
    T_171333[1] := UInt<3>(1)
    T_171333[2] := UInt<3>(2)
    wire T_171334 : UInt<2>[2]
    T_171334[0] := UInt<2>(0)
    T_171334[1] := UInt<2>(1)
    wire T_171335 : UInt<2>[3]
    T_171335[0] := UInt<2>(1)
    T_171335[1] := UInt<2>(2)
    T_171335[2] := UInt<2>(3)
    wire T_171336 : UInt<2>[2]
    T_171336[0] := UInt<2>(2)
    T_171336[1] := UInt<2>(3)
    wire T_171337 : UInt<2>[1]
    T_171337[0] := UInt<2>(3)
    wire T_171338 : UInt<3>[3]
    T_171338[0] := UInt<3>(0)
    T_171338[1] := UInt<3>(1)
    T_171338[2] := UInt<3>(2)
    wire T_171339 : UInt<2>[2]
    T_171339[0] := UInt<2>(0)
    T_171339[1] := UInt<2>(1)
    wire T_171340 : UInt<2>[3]
    T_171340[0] := UInt<2>(1)
    T_171340[1] := UInt<2>(2)
    T_171340[2] := UInt<2>(3)
    wire T_171341 : UInt<2>[2]
    T_171341[0] := UInt<2>(2)
    T_171341[1] := UInt<2>(3)
    wire T_171342 : UInt<2>[1]
    T_171342[0] := UInt<2>(3)
    wire T_171343 : UInt<3>[3]
    T_171343[0] := UInt<3>(0)
    T_171343[1] := UInt<3>(1)
    T_171343[2] := UInt<3>(2)
    wire T_171344 : UInt<0>[1]
    T_171344[0] := UInt<0>(0)
    wire T_171345 : UInt<2>[2]
    T_171345[0] := UInt<2>(1)
    T_171345[1] := UInt<2>(2)
    wire T_171346 : UInt<2>[2]
    T_171346[0] := UInt<2>(1)
    T_171346[1] := UInt<2>(2)
    wire T_171347 : UInt<2>[1]
    T_171347[0] := UInt<2>(2)
    reg T_171348 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171332 : T_171348 := meta.resp[6]
    node T_171349 = bit(s1_replaced_way_en, 7)
    node T_171350 = and(s1_clk_en, T_171349)
    wire T_171351 : UInt<3>[3]
    T_171351[0] := UInt<3>(0)
    T_171351[1] := UInt<3>(1)
    T_171351[2] := UInt<3>(2)
    wire T_171352 : UInt<2>[2]
    T_171352[0] := UInt<2>(0)
    T_171352[1] := UInt<2>(1)
    wire T_171353 : UInt<2>[3]
    T_171353[0] := UInt<2>(1)
    T_171353[1] := UInt<2>(2)
    T_171353[2] := UInt<2>(3)
    wire T_171354 : UInt<2>[2]
    T_171354[0] := UInt<2>(2)
    T_171354[1] := UInt<2>(3)
    wire T_171355 : UInt<2>[1]
    T_171355[0] := UInt<2>(3)
    wire T_171356 : UInt<3>[3]
    T_171356[0] := UInt<3>(0)
    T_171356[1] := UInt<3>(1)
    T_171356[2] := UInt<3>(2)
    wire T_171357 : UInt<2>[2]
    T_171357[0] := UInt<2>(0)
    T_171357[1] := UInt<2>(1)
    wire T_171358 : UInt<2>[3]
    T_171358[0] := UInt<2>(1)
    T_171358[1] := UInt<2>(2)
    T_171358[2] := UInt<2>(3)
    wire T_171359 : UInt<2>[2]
    T_171359[0] := UInt<2>(2)
    T_171359[1] := UInt<2>(3)
    wire T_171360 : UInt<2>[1]
    T_171360[0] := UInt<2>(3)
    wire T_171361 : UInt<3>[3]
    T_171361[0] := UInt<3>(0)
    T_171361[1] := UInt<3>(1)
    T_171361[2] := UInt<3>(2)
    wire T_171362 : UInt<0>[1]
    T_171362[0] := UInt<0>(0)
    wire T_171363 : UInt<2>[2]
    T_171363[0] := UInt<2>(1)
    T_171363[1] := UInt<2>(2)
    wire T_171364 : UInt<2>[2]
    T_171364[0] := UInt<2>(1)
    T_171364[1] := UInt<2>(2)
    wire T_171365 : UInt<2>[1]
    T_171365[0] := UInt<2>(2)
    reg T_171366 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    when T_171350 : T_171366 := meta.resp[7]
    wire T_171367 : UInt<3>[3]
    T_171367[0] := UInt<3>(0)
    T_171367[1] := UInt<3>(1)
    T_171367[2] := UInt<3>(2)
    wire T_171368 : UInt<2>[2]
    T_171368[0] := UInt<2>(0)
    T_171368[1] := UInt<2>(1)
    wire T_171369 : UInt<2>[3]
    T_171369[0] := UInt<2>(1)
    T_171369[1] := UInt<2>(2)
    T_171369[2] := UInt<2>(3)
    wire T_171370 : UInt<2>[2]
    T_171370[0] := UInt<2>(2)
    T_171370[1] := UInt<2>(3)
    wire T_171371 : UInt<2>[1]
    T_171371[0] := UInt<2>(3)
    wire T_171372 : UInt<3>[3]
    T_171372[0] := UInt<3>(0)
    T_171372[1] := UInt<3>(1)
    T_171372[2] := UInt<3>(2)
    wire T_171373 : UInt<2>[2]
    T_171373[0] := UInt<2>(0)
    T_171373[1] := UInt<2>(1)
    wire T_171374 : UInt<2>[3]
    T_171374[0] := UInt<2>(1)
    T_171374[1] := UInt<2>(2)
    T_171374[2] := UInt<2>(3)
    wire T_171375 : UInt<2>[2]
    T_171375[0] := UInt<2>(2)
    T_171375[1] := UInt<2>(3)
    wire T_171376 : UInt<2>[1]
    T_171376[0] := UInt<2>(3)
    wire T_171377 : UInt<3>[3]
    T_171377[0] := UInt<3>(0)
    T_171377[1] := UInt<3>(1)
    T_171377[2] := UInt<3>(2)
    wire T_171378 : UInt<0>[1]
    T_171378[0] := UInt<0>(0)
    wire T_171379 : UInt<2>[2]
    T_171379[0] := UInt<2>(1)
    T_171379[1] := UInt<2>(2)
    wire T_171380 : UInt<2>[2]
    T_171380[0] := UInt<2>(1)
    T_171380[1] := UInt<2>(2)
    wire T_171381 : UInt<2>[1]
    T_171381[0] := UInt<2>(2)
    wire T_171382 : UInt<3>[3]
    T_171382[0] := UInt<3>(0)
    T_171382[1] := UInt<3>(1)
    T_171382[2] := UInt<3>(2)
    wire T_171383 : UInt<2>[2]
    T_171383[0] := UInt<2>(0)
    T_171383[1] := UInt<2>(1)
    wire T_171384 : UInt<2>[3]
    T_171384[0] := UInt<2>(1)
    T_171384[1] := UInt<2>(2)
    T_171384[2] := UInt<2>(3)
    wire T_171385 : UInt<2>[2]
    T_171385[0] := UInt<2>(2)
    T_171385[1] := UInt<2>(3)
    wire T_171386 : UInt<2>[1]
    T_171386[0] := UInt<2>(3)
    wire T_171387 : UInt<3>[3]
    T_171387[0] := UInt<3>(0)
    T_171387[1] := UInt<3>(1)
    T_171387[2] := UInt<3>(2)
    wire T_171388 : UInt<2>[2]
    T_171388[0] := UInt<2>(0)
    T_171388[1] := UInt<2>(1)
    wire T_171389 : UInt<2>[3]
    T_171389[0] := UInt<2>(1)
    T_171389[1] := UInt<2>(2)
    T_171389[2] := UInt<2>(3)
    wire T_171390 : UInt<2>[2]
    T_171390[0] := UInt<2>(2)
    T_171390[1] := UInt<2>(3)
    wire T_171391 : UInt<2>[1]
    T_171391[0] := UInt<2>(3)
    wire T_171392 : UInt<3>[3]
    T_171392[0] := UInt<3>(0)
    T_171392[1] := UInt<3>(1)
    T_171392[2] := UInt<3>(2)
    wire T_171393 : UInt<0>[1]
    T_171393[0] := UInt<0>(0)
    wire T_171394 : UInt<2>[2]
    T_171394[0] := UInt<2>(1)
    T_171394[1] := UInt<2>(2)
    wire T_171395 : UInt<2>[2]
    T_171395[0] := UInt<2>(1)
    T_171395[1] := UInt<2>(2)
    wire T_171396 : UInt<2>[1]
    T_171396[0] := UInt<2>(2)
    wire T_171397 : UInt<3>[3]
    T_171397[0] := UInt<3>(0)
    T_171397[1] := UInt<3>(1)
    T_171397[2] := UInt<3>(2)
    wire T_171398 : UInt<2>[2]
    T_171398[0] := UInt<2>(0)
    T_171398[1] := UInt<2>(1)
    wire T_171399 : UInt<2>[3]
    T_171399[0] := UInt<2>(1)
    T_171399[1] := UInt<2>(2)
    T_171399[2] := UInt<2>(3)
    wire T_171400 : UInt<2>[2]
    T_171400[0] := UInt<2>(2)
    T_171400[1] := UInt<2>(3)
    wire T_171401 : UInt<2>[1]
    T_171401[0] := UInt<2>(3)
    wire T_171402 : UInt<3>[3]
    T_171402[0] := UInt<3>(0)
    T_171402[1] := UInt<3>(1)
    T_171402[2] := UInt<3>(2)
    wire T_171403 : UInt<2>[2]
    T_171403[0] := UInt<2>(0)
    T_171403[1] := UInt<2>(1)
    wire T_171404 : UInt<2>[3]
    T_171404[0] := UInt<2>(1)
    T_171404[1] := UInt<2>(2)
    T_171404[2] := UInt<2>(3)
    wire T_171405 : UInt<2>[2]
    T_171405[0] := UInt<2>(2)
    T_171405[1] := UInt<2>(3)
    wire T_171406 : UInt<2>[1]
    T_171406[0] := UInt<2>(3)
    wire T_171407 : UInt<3>[3]
    T_171407[0] := UInt<3>(0)
    T_171407[1] := UInt<3>(1)
    T_171407[2] := UInt<3>(2)
    wire T_171408 : UInt<0>[1]
    T_171408[0] := UInt<0>(0)
    wire T_171409 : UInt<2>[2]
    T_171409[0] := UInt<2>(1)
    T_171409[1] := UInt<2>(2)
    wire T_171410 : UInt<2>[2]
    T_171410[0] := UInt<2>(1)
    T_171410[1] := UInt<2>(2)
    wire T_171411 : UInt<2>[1]
    T_171411[0] := UInt<2>(2)
    wire T_171412 : UInt<3>[3]
    T_171412[0] := UInt<3>(0)
    T_171412[1] := UInt<3>(1)
    T_171412[2] := UInt<3>(2)
    wire T_171413 : UInt<2>[2]
    T_171413[0] := UInt<2>(0)
    T_171413[1] := UInt<2>(1)
    wire T_171414 : UInt<2>[3]
    T_171414[0] := UInt<2>(1)
    T_171414[1] := UInt<2>(2)
    T_171414[2] := UInt<2>(3)
    wire T_171415 : UInt<2>[2]
    T_171415[0] := UInt<2>(2)
    T_171415[1] := UInt<2>(3)
    wire T_171416 : UInt<2>[1]
    T_171416[0] := UInt<2>(3)
    wire T_171417 : UInt<3>[3]
    T_171417[0] := UInt<3>(0)
    T_171417[1] := UInt<3>(1)
    T_171417[2] := UInt<3>(2)
    wire T_171418 : UInt<2>[2]
    T_171418[0] := UInt<2>(0)
    T_171418[1] := UInt<2>(1)
    wire T_171419 : UInt<2>[3]
    T_171419[0] := UInt<2>(1)
    T_171419[1] := UInt<2>(2)
    T_171419[2] := UInt<2>(3)
    wire T_171420 : UInt<2>[2]
    T_171420[0] := UInt<2>(2)
    T_171420[1] := UInt<2>(3)
    wire T_171421 : UInt<2>[1]
    T_171421[0] := UInt<2>(3)
    wire T_171422 : UInt<3>[3]
    T_171422[0] := UInt<3>(0)
    T_171422[1] := UInt<3>(1)
    T_171422[2] := UInt<3>(2)
    wire T_171423 : UInt<0>[1]
    T_171423[0] := UInt<0>(0)
    wire T_171424 : UInt<2>[2]
    T_171424[0] := UInt<2>(1)
    T_171424[1] := UInt<2>(2)
    wire T_171425 : UInt<2>[2]
    T_171425[0] := UInt<2>(1)
    T_171425[1] := UInt<2>(2)
    wire T_171426 : UInt<2>[1]
    T_171426[0] := UInt<2>(2)
    wire T_171427 : UInt<3>[3]
    T_171427[0] := UInt<3>(0)
    T_171427[1] := UInt<3>(1)
    T_171427[2] := UInt<3>(2)
    wire T_171428 : UInt<2>[2]
    T_171428[0] := UInt<2>(0)
    T_171428[1] := UInt<2>(1)
    wire T_171429 : UInt<2>[3]
    T_171429[0] := UInt<2>(1)
    T_171429[1] := UInt<2>(2)
    T_171429[2] := UInt<2>(3)
    wire T_171430 : UInt<2>[2]
    T_171430[0] := UInt<2>(2)
    T_171430[1] := UInt<2>(3)
    wire T_171431 : UInt<2>[1]
    T_171431[0] := UInt<2>(3)
    wire T_171432 : UInt<3>[3]
    T_171432[0] := UInt<3>(0)
    T_171432[1] := UInt<3>(1)
    T_171432[2] := UInt<3>(2)
    wire T_171433 : UInt<2>[2]
    T_171433[0] := UInt<2>(0)
    T_171433[1] := UInt<2>(1)
    wire T_171434 : UInt<2>[3]
    T_171434[0] := UInt<2>(1)
    T_171434[1] := UInt<2>(2)
    T_171434[2] := UInt<2>(3)
    wire T_171435 : UInt<2>[2]
    T_171435[0] := UInt<2>(2)
    T_171435[1] := UInt<2>(3)
    wire T_171436 : UInt<2>[1]
    T_171436[0] := UInt<2>(3)
    wire T_171437 : UInt<3>[3]
    T_171437[0] := UInt<3>(0)
    T_171437[1] := UInt<3>(1)
    T_171437[2] := UInt<3>(2)
    wire T_171438 : UInt<0>[1]
    T_171438[0] := UInt<0>(0)
    wire T_171439 : UInt<2>[2]
    T_171439[0] := UInt<2>(1)
    T_171439[1] := UInt<2>(2)
    wire T_171440 : UInt<2>[2]
    T_171440[0] := UInt<2>(1)
    T_171440[1] := UInt<2>(2)
    wire T_171441 : UInt<2>[1]
    T_171441[0] := UInt<2>(2)
    wire T_171442 : UInt<3>[3]
    T_171442[0] := UInt<3>(0)
    T_171442[1] := UInt<3>(1)
    T_171442[2] := UInt<3>(2)
    wire T_171443 : UInt<2>[2]
    T_171443[0] := UInt<2>(0)
    T_171443[1] := UInt<2>(1)
    wire T_171444 : UInt<2>[3]
    T_171444[0] := UInt<2>(1)
    T_171444[1] := UInt<2>(2)
    T_171444[2] := UInt<2>(3)
    wire T_171445 : UInt<2>[2]
    T_171445[0] := UInt<2>(2)
    T_171445[1] := UInt<2>(3)
    wire T_171446 : UInt<2>[1]
    T_171446[0] := UInt<2>(3)
    wire T_171447 : UInt<3>[3]
    T_171447[0] := UInt<3>(0)
    T_171447[1] := UInt<3>(1)
    T_171447[2] := UInt<3>(2)
    wire T_171448 : UInt<2>[2]
    T_171448[0] := UInt<2>(0)
    T_171448[1] := UInt<2>(1)
    wire T_171449 : UInt<2>[3]
    T_171449[0] := UInt<2>(1)
    T_171449[1] := UInt<2>(2)
    T_171449[2] := UInt<2>(3)
    wire T_171450 : UInt<2>[2]
    T_171450[0] := UInt<2>(2)
    T_171450[1] := UInt<2>(3)
    wire T_171451 : UInt<2>[1]
    T_171451[0] := UInt<2>(3)
    wire T_171452 : UInt<3>[3]
    T_171452[0] := UInt<3>(0)
    T_171452[1] := UInt<3>(1)
    T_171452[2] := UInt<3>(2)
    wire T_171453 : UInt<0>[1]
    T_171453[0] := UInt<0>(0)
    wire T_171454 : UInt<2>[2]
    T_171454[0] := UInt<2>(1)
    T_171454[1] := UInt<2>(2)
    wire T_171455 : UInt<2>[2]
    T_171455[0] := UInt<2>(1)
    T_171455[1] := UInt<2>(2)
    wire T_171456 : UInt<2>[1]
    T_171456[0] := UInt<2>(2)
    wire T_171457 : UInt<3>[3]
    T_171457[0] := UInt<3>(0)
    T_171457[1] := UInt<3>(1)
    T_171457[2] := UInt<3>(2)
    wire T_171458 : UInt<2>[2]
    T_171458[0] := UInt<2>(0)
    T_171458[1] := UInt<2>(1)
    wire T_171459 : UInt<2>[3]
    T_171459[0] := UInt<2>(1)
    T_171459[1] := UInt<2>(2)
    T_171459[2] := UInt<2>(3)
    wire T_171460 : UInt<2>[2]
    T_171460[0] := UInt<2>(2)
    T_171460[1] := UInt<2>(3)
    wire T_171461 : UInt<2>[1]
    T_171461[0] := UInt<2>(3)
    wire T_171462 : UInt<3>[3]
    T_171462[0] := UInt<3>(0)
    T_171462[1] := UInt<3>(1)
    T_171462[2] := UInt<3>(2)
    wire T_171463 : UInt<2>[2]
    T_171463[0] := UInt<2>(0)
    T_171463[1] := UInt<2>(1)
    wire T_171464 : UInt<2>[3]
    T_171464[0] := UInt<2>(1)
    T_171464[1] := UInt<2>(2)
    T_171464[2] := UInt<2>(3)
    wire T_171465 : UInt<2>[2]
    T_171465[0] := UInt<2>(2)
    T_171465[1] := UInt<2>(3)
    wire T_171466 : UInt<2>[1]
    T_171466[0] := UInt<2>(3)
    wire T_171467 : UInt<3>[3]
    T_171467[0] := UInt<3>(0)
    T_171467[1] := UInt<3>(1)
    T_171467[2] := UInt<3>(2)
    wire T_171468 : UInt<0>[1]
    T_171468[0] := UInt<0>(0)
    wire T_171469 : UInt<2>[2]
    T_171469[0] := UInt<2>(1)
    T_171469[1] := UInt<2>(2)
    wire T_171470 : UInt<2>[2]
    T_171470[0] := UInt<2>(1)
    T_171470[1] := UInt<2>(2)
    wire T_171471 : UInt<2>[1]
    T_171471[0] := UInt<2>(2)
    wire T_171472 : UInt<3>[3]
    T_171472[0] := UInt<3>(0)
    T_171472[1] := UInt<3>(1)
    T_171472[2] := UInt<3>(2)
    wire T_171473 : UInt<2>[2]
    T_171473[0] := UInt<2>(0)
    T_171473[1] := UInt<2>(1)
    wire T_171474 : UInt<2>[3]
    T_171474[0] := UInt<2>(1)
    T_171474[1] := UInt<2>(2)
    T_171474[2] := UInt<2>(3)
    wire T_171475 : UInt<2>[2]
    T_171475[0] := UInt<2>(2)
    T_171475[1] := UInt<2>(3)
    wire T_171476 : UInt<2>[1]
    T_171476[0] := UInt<2>(3)
    wire T_171477 : UInt<3>[3]
    T_171477[0] := UInt<3>(0)
    T_171477[1] := UInt<3>(1)
    T_171477[2] := UInt<3>(2)
    wire T_171478 : UInt<2>[2]
    T_171478[0] := UInt<2>(0)
    T_171478[1] := UInt<2>(1)
    wire T_171479 : UInt<2>[3]
    T_171479[0] := UInt<2>(1)
    T_171479[1] := UInt<2>(2)
    T_171479[2] := UInt<2>(3)
    wire T_171480 : UInt<2>[2]
    T_171480[0] := UInt<2>(2)
    T_171480[1] := UInt<2>(3)
    wire T_171481 : UInt<2>[1]
    T_171481[0] := UInt<2>(3)
    wire T_171482 : UInt<3>[3]
    T_171482[0] := UInt<3>(0)
    T_171482[1] := UInt<3>(1)
    T_171482[2] := UInt<3>(2)
    wire T_171483 : UInt<0>[1]
    T_171483[0] := UInt<0>(0)
    wire T_171484 : UInt<2>[2]
    T_171484[0] := UInt<2>(1)
    T_171484[1] := UInt<2>(2)
    wire T_171485 : UInt<2>[2]
    T_171485[0] := UInt<2>(1)
    T_171485[1] := UInt<2>(2)
    wire T_171486 : UInt<2>[1]
    T_171486[0] := UInt<2>(2)
    wire T_171487 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}[8]
    T_171487[0] := T_171240
    T_171487[1] := T_171258
    T_171487[2] := T_171276
    T_171487[3] := T_171294
    T_171487[4] := T_171312
    T_171487[5] := T_171330
    T_171487[6] := T_171348
    T_171487[7] := T_171366
    node T_171488 = bit(s2_replaced_way_en, 0)
    node T_171489 = bit(s2_replaced_way_en, 1)
    node T_171490 = bit(s2_replaced_way_en, 2)
    node T_171491 = bit(s2_replaced_way_en, 3)
    node T_171492 = bit(s2_replaced_way_en, 4)
    node T_171493 = bit(s2_replaced_way_en, 5)
    node T_171494 = bit(s2_replaced_way_en, 6)
    node T_171495 = bit(s2_replaced_way_en, 7)
    node T_171496 = cat(T_171487[0].tag, T_171487[0].coh.inner.sharers)
    node T_171497 = cat(UInt<1>(0), T_171487[0].coh.outer.state)
    node T_171498 = cat(UInt<1>(0), T_171497)
    node T_171499 = cat(T_171496, T_171498)
    node T_171500 = cat(T_171499, UInt<5>(0))
    node T_171501 = cat(UInt<1>(0), T_171487[0].coh.inner.sharers)
    node T_171502 = cat(UInt<1>(0), T_171487[0].coh.outer.state)
    node T_171503 = cat(UInt<1>(0), T_171502)
    node T_171504 = cat(T_171501, T_171503)
    node T_171505 = cat(T_171504, UInt<6>(0))
    node T_171506 = cat(T_171500, T_171505)
    wire T_171507 : UInt<1>
    T_171507 := UInt<1>(0)
    when T_171488 : T_171507 := T_171506
    node T_171508 = cat(T_171487[1].tag, T_171487[1].coh.inner.sharers)
    node T_171509 = cat(UInt<1>(0), T_171487[1].coh.outer.state)
    node T_171510 = cat(UInt<1>(0), T_171509)
    node T_171511 = cat(T_171508, T_171510)
    node T_171512 = cat(T_171511, UInt<5>(0))
    node T_171513 = cat(UInt<1>(0), T_171487[1].coh.inner.sharers)
    node T_171514 = cat(UInt<1>(0), T_171487[1].coh.outer.state)
    node T_171515 = cat(UInt<1>(0), T_171514)
    node T_171516 = cat(T_171513, T_171515)
    node T_171517 = cat(T_171516, UInt<6>(0))
    node T_171518 = cat(T_171512, T_171517)
    wire T_171519 : UInt<1>
    T_171519 := UInt<1>(0)
    when T_171489 : T_171519 := T_171518
    node T_171520 = cat(T_171487[2].tag, T_171487[2].coh.inner.sharers)
    node T_171521 = cat(UInt<1>(0), T_171487[2].coh.outer.state)
    node T_171522 = cat(UInt<1>(0), T_171521)
    node T_171523 = cat(T_171520, T_171522)
    node T_171524 = cat(T_171523, UInt<5>(0))
    node T_171525 = cat(UInt<1>(0), T_171487[2].coh.inner.sharers)
    node T_171526 = cat(UInt<1>(0), T_171487[2].coh.outer.state)
    node T_171527 = cat(UInt<1>(0), T_171526)
    node T_171528 = cat(T_171525, T_171527)
    node T_171529 = cat(T_171528, UInt<6>(0))
    node T_171530 = cat(T_171524, T_171529)
    wire T_171531 : UInt<1>
    T_171531 := UInt<1>(0)
    when T_171490 : T_171531 := T_171530
    node T_171532 = cat(T_171487[3].tag, T_171487[3].coh.inner.sharers)
    node T_171533 = cat(UInt<1>(0), T_171487[3].coh.outer.state)
    node T_171534 = cat(UInt<1>(0), T_171533)
    node T_171535 = cat(T_171532, T_171534)
    node T_171536 = cat(T_171535, UInt<5>(0))
    node T_171537 = cat(UInt<1>(0), T_171487[3].coh.inner.sharers)
    node T_171538 = cat(UInt<1>(0), T_171487[3].coh.outer.state)
    node T_171539 = cat(UInt<1>(0), T_171538)
    node T_171540 = cat(T_171537, T_171539)
    node T_171541 = cat(T_171540, UInt<6>(0))
    node T_171542 = cat(T_171536, T_171541)
    wire T_171543 : UInt<1>
    T_171543 := UInt<1>(0)
    when T_171491 : T_171543 := T_171542
    node T_171544 = cat(T_171487[4].tag, T_171487[4].coh.inner.sharers)
    node T_171545 = cat(UInt<1>(0), T_171487[4].coh.outer.state)
    node T_171546 = cat(UInt<1>(0), T_171545)
    node T_171547 = cat(T_171544, T_171546)
    node T_171548 = cat(T_171547, UInt<5>(0))
    node T_171549 = cat(UInt<1>(0), T_171487[4].coh.inner.sharers)
    node T_171550 = cat(UInt<1>(0), T_171487[4].coh.outer.state)
    node T_171551 = cat(UInt<1>(0), T_171550)
    node T_171552 = cat(T_171549, T_171551)
    node T_171553 = cat(T_171552, UInt<6>(0))
    node T_171554 = cat(T_171548, T_171553)
    wire T_171555 : UInt<1>
    T_171555 := UInt<1>(0)
    when T_171492 : T_171555 := T_171554
    node T_171556 = cat(T_171487[5].tag, T_171487[5].coh.inner.sharers)
    node T_171557 = cat(UInt<1>(0), T_171487[5].coh.outer.state)
    node T_171558 = cat(UInt<1>(0), T_171557)
    node T_171559 = cat(T_171556, T_171558)
    node T_171560 = cat(T_171559, UInt<5>(0))
    node T_171561 = cat(UInt<1>(0), T_171487[5].coh.inner.sharers)
    node T_171562 = cat(UInt<1>(0), T_171487[5].coh.outer.state)
    node T_171563 = cat(UInt<1>(0), T_171562)
    node T_171564 = cat(T_171561, T_171563)
    node T_171565 = cat(T_171564, UInt<6>(0))
    node T_171566 = cat(T_171560, T_171565)
    wire T_171567 : UInt<1>
    T_171567 := UInt<1>(0)
    when T_171493 : T_171567 := T_171566
    node T_171568 = cat(T_171487[6].tag, T_171487[6].coh.inner.sharers)
    node T_171569 = cat(UInt<1>(0), T_171487[6].coh.outer.state)
    node T_171570 = cat(UInt<1>(0), T_171569)
    node T_171571 = cat(T_171568, T_171570)
    node T_171572 = cat(T_171571, UInt<5>(0))
    node T_171573 = cat(UInt<1>(0), T_171487[6].coh.inner.sharers)
    node T_171574 = cat(UInt<1>(0), T_171487[6].coh.outer.state)
    node T_171575 = cat(UInt<1>(0), T_171574)
    node T_171576 = cat(T_171573, T_171575)
    node T_171577 = cat(T_171576, UInt<6>(0))
    node T_171578 = cat(T_171572, T_171577)
    wire T_171579 : UInt<1>
    T_171579 := UInt<1>(0)
    when T_171494 : T_171579 := T_171578
    node T_171580 = cat(T_171487[7].tag, T_171487[7].coh.inner.sharers)
    node T_171581 = cat(UInt<1>(0), T_171487[7].coh.outer.state)
    node T_171582 = cat(UInt<1>(0), T_171581)
    node T_171583 = cat(T_171580, T_171582)
    node T_171584 = cat(T_171583, UInt<5>(0))
    node T_171585 = cat(UInt<1>(0), T_171487[7].coh.inner.sharers)
    node T_171586 = cat(UInt<1>(0), T_171487[7].coh.outer.state)
    node T_171587 = cat(UInt<1>(0), T_171586)
    node T_171588 = cat(T_171585, T_171587)
    node T_171589 = cat(T_171588, UInt<6>(0))
    node T_171590 = cat(T_171584, T_171589)
    wire T_171591 : UInt<1>
    T_171591 := UInt<1>(0)
    when T_171495 : T_171591 := T_171590
    node T_171592 = or(T_171507, T_171519)
    node T_171593 = or(T_171592, T_171531)
    node T_171594 = or(T_171593, T_171543)
    node T_171595 = or(T_171594, T_171555)
    node T_171596 = or(T_171595, T_171567)
    node T_171597 = or(T_171596, T_171579)
    node T_171598 = or(T_171597, T_171591)
    wire T_171599 : UInt<3>[3]
    T_171599[0] := UInt<3>(0)
    T_171599[1] := UInt<3>(1)
    T_171599[2] := UInt<3>(2)
    wire T_171600 : UInt<2>[2]
    T_171600[0] := UInt<2>(0)
    T_171600[1] := UInt<2>(1)
    wire T_171601 : UInt<2>[3]
    T_171601[0] := UInt<2>(1)
    T_171601[1] := UInt<2>(2)
    T_171601[2] := UInt<2>(3)
    wire T_171602 : UInt<2>[2]
    T_171602[0] := UInt<2>(2)
    T_171602[1] := UInt<2>(3)
    wire T_171603 : UInt<2>[1]
    T_171603[0] := UInt<2>(3)
    wire T_171604 : UInt<3>[3]
    T_171604[0] := UInt<3>(0)
    T_171604[1] := UInt<3>(1)
    T_171604[2] := UInt<3>(2)
    wire T_171605 : UInt<2>[2]
    T_171605[0] := UInt<2>(0)
    T_171605[1] := UInt<2>(1)
    wire T_171606 : UInt<2>[3]
    T_171606[0] := UInt<2>(1)
    T_171606[1] := UInt<2>(2)
    T_171606[2] := UInt<2>(3)
    wire T_171607 : UInt<2>[2]
    T_171607[0] := UInt<2>(2)
    T_171607[1] := UInt<2>(3)
    wire T_171608 : UInt<2>[1]
    T_171608[0] := UInt<2>(3)
    wire T_171609 : UInt<3>[3]
    T_171609[0] := UInt<3>(0)
    T_171609[1] := UInt<3>(1)
    T_171609[2] := UInt<3>(2)
    wire T_171610 : UInt<0>[1]
    T_171610[0] := UInt<0>(0)
    wire T_171611 : UInt<2>[2]
    T_171611[0] := UInt<2>(1)
    T_171611[1] := UInt<2>(2)
    wire T_171612 : UInt<2>[2]
    T_171612[0] := UInt<2>(1)
    T_171612[1] := UInt<2>(2)
    wire T_171613 : UInt<2>[1]
    T_171613[0] := UInt<2>(2)
    wire T_171614 : UInt<3>[3]
    T_171614[0] := UInt<3>(0)
    T_171614[1] := UInt<3>(1)
    T_171614[2] := UInt<3>(2)
    wire T_171615 : UInt<2>[2]
    T_171615[0] := UInt<2>(0)
    T_171615[1] := UInt<2>(1)
    wire T_171616 : UInt<2>[3]
    T_171616[0] := UInt<2>(1)
    T_171616[1] := UInt<2>(2)
    T_171616[2] := UInt<2>(3)
    wire T_171617 : UInt<2>[2]
    T_171617[0] := UInt<2>(2)
    T_171617[1] := UInt<2>(3)
    wire T_171618 : UInt<2>[1]
    T_171618[0] := UInt<2>(3)
    wire T_171619 : UInt<3>[3]
    T_171619[0] := UInt<3>(0)
    T_171619[1] := UInt<3>(1)
    T_171619[2] := UInt<3>(2)
    wire T_171620 : UInt<2>[2]
    T_171620[0] := UInt<2>(0)
    T_171620[1] := UInt<2>(1)
    wire T_171621 : UInt<2>[3]
    T_171621[0] := UInt<2>(1)
    T_171621[1] := UInt<2>(2)
    T_171621[2] := UInt<2>(3)
    wire T_171622 : UInt<2>[2]
    T_171622[0] := UInt<2>(2)
    T_171622[1] := UInt<2>(3)
    wire T_171623 : UInt<2>[1]
    T_171623[0] := UInt<2>(3)
    wire T_171624 : UInt<3>[3]
    T_171624[0] := UInt<3>(0)
    T_171624[1] := UInt<3>(1)
    T_171624[2] := UInt<3>(2)
    wire T_171625 : UInt<0>[1]
    T_171625[0] := UInt<0>(0)
    wire T_171626 : UInt<2>[2]
    T_171626[0] := UInt<2>(1)
    T_171626[1] := UInt<2>(2)
    wire T_171627 : UInt<2>[2]
    T_171627[0] := UInt<2>(1)
    T_171627[1] := UInt<2>(2)
    wire T_171628 : UInt<2>[1]
    T_171628[0] := UInt<2>(2)
    wire s2_repl_meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    node T_171629 = bits(T_171598, 0, 0)
    s2_repl_meta.coh.outer.makeVoluntaryWriteback$default$4 := T_171629
    node T_171630 = bits(T_171598, 1, 1)
    s2_repl_meta.coh.outer.makeVoluntaryWriteback$default$3 := T_171630
    node T_171631 = bits(T_171598, 2, 2)
    s2_repl_meta.coh.outer.makeVoluntaryRelease$default$5 := T_171631
    node T_171632 = bits(T_171598, 3, 3)
    s2_repl_meta.coh.outer.makeVoluntaryRelease$default$4 := T_171632
    node T_171633 = bits(T_171598, 4, 4)
    s2_repl_meta.coh.outer.makeRelease$default$3 := T_171633
    node T_171634 = bits(T_171598, 5, 5)
    s2_repl_meta.coh.outer.makeRelease$default$2 := T_171634
    node T_171635 = bits(T_171598, 7, 6)
    s2_repl_meta.coh.outer.state := T_171635
    node T_171636 = bits(T_171598, 8, 8)
    s2_repl_meta.coh.inner.makeGrant$default$4 := T_171636
    node T_171637 = bits(T_171598, 9, 9)
    s2_repl_meta.coh.inner.makeGrant$default$3 := T_171637
    node T_171638 = bits(T_171598, 10, 10)
    s2_repl_meta.coh.inner.sharers := T_171638
    node T_171639 = bits(T_171598, 11, 11)
    s2_repl_meta.coh.outer.makeVoluntaryWriteback$default$4 := T_171639
    node T_171640 = bits(T_171598, 12, 12)
    s2_repl_meta.coh.outer.makeVoluntaryWriteback$default$3 := T_171640
    node T_171641 = bits(T_171598, 13, 13)
    s2_repl_meta.coh.outer.makeVoluntaryRelease$default$5 := T_171641
    node T_171642 = bits(T_171598, 14, 14)
    s2_repl_meta.coh.outer.makeVoluntaryRelease$default$4 := T_171642
    node T_171643 = bits(T_171598, 15, 15)
    s2_repl_meta.coh.outer.makeRelease$default$3 := T_171643
    node T_171644 = bits(T_171598, 16, 16)
    s2_repl_meta.coh.outer.makeRelease$default$2 := T_171644
    node T_171645 = bits(T_171598, 18, 17)
    s2_repl_meta.coh.outer.state := T_171645
    node T_171646 = bits(T_171598, 19, 19)
    s2_repl_meta.coh.inner.makeGrant$default$4 := T_171646
    node T_171647 = bits(T_171598, 20, 20)
    s2_repl_meta.coh.inner.makeGrant$default$3 := T_171647
    node T_171648 = bits(T_171598, 21, 21)
    s2_repl_meta.coh.inner.sharers := T_171648
    node T_171649 = bits(T_171598, 35, 22)
    s2_repl_meta.tag := T_171649
    
    node T_171650 = eq(s2_tag_match, UInt<1>(0))
    when T_171650 : T_171209 := UInt<1>(1)
    reg T_171651 : UInt<1>
    T_171651 := s1_clk_en
    resp.valid := T_171651
    reg T_171652 : UInt<2>
    when s1_clk_en : T_171652 := s1_id
    resp.bits.id := T_171652
    resp.bits.tag_match := s2_tag_match
    wire T_171653 : UInt<3>[3]
    T_171653[0] := UInt<3>(0)
    T_171653[1] := UInt<3>(1)
    T_171653[2] := UInt<3>(2)
    wire T_171654 : UInt<2>[2]
    T_171654[0] := UInt<2>(0)
    T_171654[1] := UInt<2>(1)
    wire T_171655 : UInt<2>[3]
    T_171655[0] := UInt<2>(1)
    T_171655[1] := UInt<2>(2)
    T_171655[2] := UInt<2>(3)
    wire T_171656 : UInt<2>[2]
    T_171656[0] := UInt<2>(2)
    T_171656[1] := UInt<2>(3)
    wire T_171657 : UInt<2>[1]
    T_171657[0] := UInt<2>(3)
    wire T_171658 : UInt<3>[3]
    T_171658[0] := UInt<3>(0)
    T_171658[1] := UInt<3>(1)
    T_171658[2] := UInt<3>(2)
    wire T_171659 : UInt<2>[2]
    T_171659[0] := UInt<2>(0)
    T_171659[1] := UInt<2>(1)
    wire T_171660 : UInt<2>[3]
    T_171660[0] := UInt<2>(1)
    T_171660[1] := UInt<2>(2)
    T_171660[2] := UInt<2>(3)
    wire T_171661 : UInt<2>[2]
    T_171661[0] := UInt<2>(2)
    T_171661[1] := UInt<2>(3)
    wire T_171662 : UInt<2>[1]
    T_171662[0] := UInt<2>(3)
    wire T_171663 : UInt<3>[3]
    T_171663[0] := UInt<3>(0)
    T_171663[1] := UInt<3>(1)
    T_171663[2] := UInt<3>(2)
    wire T_171664 : UInt<0>[1]
    T_171664[0] := UInt<0>(0)
    wire T_171665 : UInt<2>[2]
    T_171665[0] := UInt<2>(1)
    T_171665[1] := UInt<2>(2)
    wire T_171666 : UInt<2>[2]
    T_171666[0] := UInt<2>(1)
    T_171666[1] := UInt<2>(2)
    wire T_171667 : UInt<2>[1]
    T_171667[0] := UInt<2>(2)
    wire T_171668 : UInt<3>[3]
    T_171668[0] := UInt<3>(0)
    T_171668[1] := UInt<3>(1)
    T_171668[2] := UInt<3>(2)
    wire T_171669 : UInt<2>[2]
    T_171669[0] := UInt<2>(0)
    T_171669[1] := UInt<2>(1)
    wire T_171670 : UInt<2>[3]
    T_171670[0] := UInt<2>(1)
    T_171670[1] := UInt<2>(2)
    T_171670[2] := UInt<2>(3)
    wire T_171671 : UInt<2>[2]
    T_171671[0] := UInt<2>(2)
    T_171671[1] := UInt<2>(3)
    wire T_171672 : UInt<2>[1]
    T_171672[0] := UInt<2>(3)
    wire T_171673 : UInt<3>[3]
    T_171673[0] := UInt<3>(0)
    T_171673[1] := UInt<3>(1)
    T_171673[2] := UInt<3>(2)
    wire T_171674 : UInt<2>[2]
    T_171674[0] := UInt<2>(0)
    T_171674[1] := UInt<2>(1)
    wire T_171675 : UInt<2>[3]
    T_171675[0] := UInt<2>(1)
    T_171675[1] := UInt<2>(2)
    T_171675[2] := UInt<2>(3)
    wire T_171676 : UInt<2>[2]
    T_171676[0] := UInt<2>(2)
    T_171676[1] := UInt<2>(3)
    wire T_171677 : UInt<2>[1]
    T_171677[0] := UInt<2>(3)
    wire T_171678 : UInt<3>[3]
    T_171678[0] := UInt<3>(0)
    T_171678[1] := UInt<3>(1)
    T_171678[2] := UInt<3>(2)
    wire T_171679 : UInt<0>[1]
    T_171679[0] := UInt<0>(0)
    wire T_171680 : UInt<2>[2]
    T_171680[0] := UInt<2>(1)
    T_171680[1] := UInt<2>(2)
    wire T_171681 : UInt<2>[2]
    T_171681[0] := UInt<2>(1)
    T_171681[1] := UInt<2>(2)
    wire T_171682 : UInt<2>[1]
    T_171682[0] := UInt<2>(2)
    wire T_171683 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    T_171683.tag := s2_repl_meta.tag
    T_171683.coh := s2_hit_coh
    wire T_171684 : UInt<3>[3]
    T_171684[0] := UInt<3>(0)
    T_171684[1] := UInt<3>(1)
    T_171684[2] := UInt<3>(2)
    wire T_171685 : UInt<2>[2]
    T_171685[0] := UInt<2>(0)
    T_171685[1] := UInt<2>(1)
    wire T_171686 : UInt<2>[3]
    T_171686[0] := UInt<2>(1)
    T_171686[1] := UInt<2>(2)
    T_171686[2] := UInt<2>(3)
    wire T_171687 : UInt<2>[2]
    T_171687[0] := UInt<2>(2)
    T_171687[1] := UInt<2>(3)
    wire T_171688 : UInt<2>[1]
    T_171688[0] := UInt<2>(3)
    wire T_171689 : UInt<3>[3]
    T_171689[0] := UInt<3>(0)
    T_171689[1] := UInt<3>(1)
    T_171689[2] := UInt<3>(2)
    wire T_171690 : UInt<2>[2]
    T_171690[0] := UInt<2>(0)
    T_171690[1] := UInt<2>(1)
    wire T_171691 : UInt<2>[3]
    T_171691[0] := UInt<2>(1)
    T_171691[1] := UInt<2>(2)
    T_171691[2] := UInt<2>(3)
    wire T_171692 : UInt<2>[2]
    T_171692[0] := UInt<2>(2)
    T_171692[1] := UInt<2>(3)
    wire T_171693 : UInt<2>[1]
    T_171693[0] := UInt<2>(3)
    wire T_171694 : UInt<3>[3]
    T_171694[0] := UInt<3>(0)
    T_171694[1] := UInt<3>(1)
    T_171694[2] := UInt<3>(2)
    wire T_171695 : UInt<0>[1]
    T_171695[0] := UInt<0>(0)
    wire T_171696 : UInt<2>[2]
    T_171696[0] := UInt<2>(1)
    T_171696[1] := UInt<2>(2)
    wire T_171697 : UInt<2>[2]
    T_171697[0] := UInt<2>(1)
    T_171697[1] := UInt<2>(2)
    wire T_171698 : UInt<2>[1]
    T_171698[0] := UInt<2>(2)
    wire T_171699 : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    T_171699 := s2_repl_meta
    when s2_tag_match : T_171699 := T_171683
    resp.bits.meta := T_171699
    wire T_171700 : UInt<9>
    T_171700 := s2_replaced_way_en
    when s2_tag_match : T_171700 := s2_tag_match_way
    resp.bits.way_en := T_171700
  module L2DataArray : 
    output read : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}
    input resp : {valid : UInt<1>, bits : {id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>}}
    output write : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}
    
    cmem T_171701 : UInt<128>[131072]
    node T_171702 = eq(write.valid, UInt<1>(0))
    node ren = and(T_171702, read.valid)
    node T_171703 = bits(read.bits.way_en, 7, 4)
    node T_171704 = bits(read.bits.way_en, 3, 0)
    node T_171705 = eq(T_171703, UInt<1>(0))
    node T_171706 = eq(T_171705, UInt<1>(0))
    node T_171707 = or(T_171703, T_171704)
    node T_171708 = bits(T_171707, 3, 2)
    node T_171709 = bits(T_171707, 1, 0)
    node T_171710 = eq(T_171708, UInt<1>(0))
    node T_171711 = eq(T_171710, UInt<1>(0))
    node T_171712 = or(T_171708, T_171709)
    node T_171713 = bit(T_171712, 1)
    node T_171714 = cat(T_171711, T_171713)
    node T_171715 = cat(T_171706, T_171714)
    node T_171716 = cat(read.bits.addr_idx, read.bits.addr_beat)
    node raddr = cat(T_171715, T_171716)
    node T_171717 = bits(write.bits.way_en, 7, 4)
    node T_171718 = bits(write.bits.way_en, 3, 0)
    node T_171719 = eq(T_171717, UInt<1>(0))
    node T_171720 = eq(T_171719, UInt<1>(0))
    node T_171721 = or(T_171717, T_171718)
    node T_171722 = bits(T_171721, 3, 2)
    node T_171723 = bits(T_171721, 1, 0)
    node T_171724 = eq(T_171722, UInt<1>(0))
    node T_171725 = eq(T_171724, UInt<1>(0))
    node T_171726 = or(T_171722, T_171723)
    node T_171727 = bit(T_171726, 1)
    node T_171728 = cat(T_171725, T_171727)
    node T_171729 = cat(T_171720, T_171728)
    node T_171730 = cat(write.bits.addr_idx, write.bits.addr_beat)
    node waddr = cat(T_171729, T_171730)
    node T_171731 = bit(write.bits.wmask, 0)
    node T_171732 = bit(write.bits.wmask, 1)
    node T_171733 = bit(write.bits.wmask, 2)
    node T_171734 = bit(write.bits.wmask, 3)
    node T_171735 = bit(write.bits.wmask, 4)
    node T_171736 = bit(write.bits.wmask, 5)
    node T_171737 = bit(write.bits.wmask, 6)
    node T_171738 = bit(write.bits.wmask, 7)
    node T_171739 = bit(write.bits.wmask, 8)
    node T_171740 = bit(write.bits.wmask, 9)
    node T_171741 = bit(write.bits.wmask, 10)
    node T_171742 = bit(write.bits.wmask, 11)
    node T_171743 = bit(write.bits.wmask, 12)
    node T_171744 = bit(write.bits.wmask, 13)
    node T_171745 = bit(write.bits.wmask, 14)
    node T_171746 = bit(write.bits.wmask, 15)
    wire T_171747 : UInt<1>[16]
    T_171747[0] := T_171731
    T_171747[1] := T_171732
    T_171747[2] := T_171733
    T_171747[3] := T_171734
    T_171747[4] := T_171735
    T_171747[5] := T_171736
    T_171747[6] := T_171737
    T_171747[7] := T_171738
    T_171747[8] := T_171739
    T_171747[9] := T_171740
    T_171747[10] := T_171741
    T_171747[11] := T_171742
    T_171747[12] := T_171743
    T_171747[13] := T_171744
    T_171747[14] := T_171745
    T_171747[15] := T_171746
    node T_171748 = subw(UInt<8>(0), UInt<4>(8))
    node T_171749 = subw(UInt<8>(0), UInt<4>(8))
    node T_171750 = subw(UInt<8>(0), UInt<4>(8))
    node T_171751 = subw(UInt<8>(0), UInt<4>(8))
    node T_171752 = subw(UInt<8>(0), UInt<4>(8))
    node T_171753 = subw(UInt<8>(0), UInt<4>(8))
    node T_171754 = subw(UInt<8>(0), UInt<4>(8))
    node T_171755 = subw(UInt<8>(0), UInt<4>(8))
    node T_171756 = subw(UInt<8>(0), UInt<4>(8))
    node T_171757 = subw(UInt<8>(0), UInt<4>(8))
    node T_171758 = subw(UInt<8>(0), UInt<4>(8))
    node T_171759 = subw(UInt<8>(0), UInt<4>(8))
    node T_171760 = subw(UInt<8>(0), UInt<4>(8))
    node T_171761 = subw(UInt<8>(0), UInt<4>(8))
    node T_171762 = subw(UInt<8>(0), UInt<4>(8))
    node T_171763 = subw(UInt<8>(0), UInt<4>(8))
    wire T_171764 : UInt<8>[16]
    T_171764[0] := T_171748
    T_171764[1] := T_171749
    T_171764[2] := T_171750
    T_171764[3] := T_171751
    T_171764[4] := T_171752
    T_171764[5] := T_171753
    T_171764[6] := T_171754
    T_171764[7] := T_171755
    T_171764[8] := T_171756
    T_171764[9] := T_171757
    T_171764[10] := T_171758
    T_171764[11] := T_171759
    T_171764[12] := T_171760
    T_171764[13] := T_171761
    T_171764[14] := T_171762
    T_171764[15] := T_171763
    node T_171765 = cat(T_171764[15], T_171764[14])
    node T_171766 = cat(T_171764[13], T_171764[12])
    node T_171767 = cat(T_171765, T_171766)
    node T_171768 = cat(T_171764[11], T_171764[10])
    node T_171769 = cat(T_171764[9], T_171764[8])
    node T_171770 = cat(T_171768, T_171769)
    node T_171771 = cat(T_171767, T_171770)
    node T_171772 = cat(T_171764[7], T_171764[6])
    node T_171773 = cat(T_171764[5], T_171764[4])
    node T_171774 = cat(T_171772, T_171773)
    node T_171775 = cat(T_171764[3], T_171764[2])
    node T_171776 = cat(T_171764[1], T_171764[0])
    node T_171777 = cat(T_171775, T_171776)
    node T_171778 = cat(T_171774, T_171777)
    node wmask = cat(T_171771, T_171778)
    when write.valid : 
      accessor T_171779 = T_171701[waddr]
      node T_171780 = not(wmask)
      node T_171781 = and(T_171779, T_171780)
      node T_171782 = and(write.bits.data, wmask)
      node T_171783 = or(T_171781, T_171782)
      wire T_171784 : UInt<128>
      node T_171785 = bits(T_171783, 127, 0)
      T_171784 := T_171785
      accessor T_171786 = T_171701[waddr]
      T_171786 := T_171784
    node T_171787 = and(read.ready, read.valid)
    reg T_171788 : UInt<1>
    onreset T_171788 := UInt<1>(0)
    T_171788 := T_171787
    reg T_171789 : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}
    when T_171787 : T_171789 := read.bits
    r_req.valid <> T_171788
    r_req.bits <> T_171789
    reg T_171790 : UInt<1>
    onreset T_171790 := UInt<1>(0)
    T_171790 := r_req.valid
    reg T_171791 : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}
    when r_req.valid : T_171791 := r_req.bits
    T_171792.valid <> T_171790
    T_171792.bits <> T_171791
    resp := T_171792
    reg T_171793 : UInt<17>
    when ren : T_171793 := raddr
    accessor T_171794 = T_171701[T_171793]
    reg T_171795 : UInt<1>
    onreset T_171795 := UInt<1>(0)
    T_171795 := r_req.valid
    reg T_171796 : UInt<128>
    when r_req.valid : T_171796 := T_171794
    T_171797.valid <> T_171795
    T_171797.bits <> T_171796
    resp.bits.data := T_171797.bits
    node T_171798 = eq(write.valid, UInt<1>(0))
    read.ready := T_171798
    write.ready := UInt<1>(1)
  module L2VoluntaryReleaseTracker : 
    output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input incoherent : UInt<1>[1]
    output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output has_acquire_conflict : UInt<1>
    output has_acquire_match : UInt<1>
    output has_release_match : UInt<1>
    output data : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}}
    output meta : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, tag_match : UInt<1>, meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, way_en : UInt<8>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}}
    output wb : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>}}}
    
    wire T_171799 : UInt<3>[3]
    T_171799[0] := UInt<3>(0)
    T_171799[1] := UInt<3>(1)
    T_171799[2] := UInt<3>(2)
    wire T_171800 : UInt<2>[2]
    T_171800[0] := UInt<2>(0)
    T_171800[1] := UInt<2>(1)
    wire T_171801 : UInt<2>[3]
    T_171801[0] := UInt<2>(1)
    T_171801[1] := UInt<2>(2)
    T_171801[2] := UInt<2>(3)
    wire T_171802 : UInt<2>[2]
    T_171802[0] := UInt<2>(2)
    T_171802[1] := UInt<2>(3)
    wire T_171803 : UInt<2>[1]
    T_171803[0] := UInt<2>(3)
    wire T_171804 : UInt<3>[3]
    T_171804[0] := UInt<3>(0)
    T_171804[1] := UInt<3>(1)
    T_171804[2] := UInt<3>(2)
    wire T_171805 : UInt<2>[2]
    T_171805[0] := UInt<2>(0)
    T_171805[1] := UInt<2>(1)
    wire T_171806 : UInt<2>[3]
    T_171806[0] := UInt<2>(1)
    T_171806[1] := UInt<2>(2)
    T_171806[2] := UInt<2>(3)
    wire T_171807 : UInt<2>[2]
    T_171807[0] := UInt<2>(2)
    T_171807[1] := UInt<2>(3)
    wire T_171808 : UInt<2>[1]
    T_171808[0] := UInt<2>(3)
    wire T_171809 : UInt<3>[3]
    T_171809[0] := UInt<3>(0)
    T_171809[1] := UInt<3>(1)
    T_171809[2] := UInt<3>(2)
    wire T_171810 : UInt<2>[2]
    T_171810[0] := UInt<2>(0)
    T_171810[1] := UInt<2>(1)
    wire T_171811 : UInt<2>[3]
    T_171811[0] := UInt<2>(1)
    T_171811[1] := UInt<2>(2)
    T_171811[2] := UInt<2>(3)
    wire T_171812 : UInt<2>[2]
    T_171812[0] := UInt<2>(2)
    T_171812[1] := UInt<2>(3)
    wire T_171813 : UInt<2>[1]
    T_171813[0] := UInt<2>(3)
    wire T_171814 : UInt<3>[3]
    T_171814[0] := UInt<3>(0)
    T_171814[1] := UInt<3>(1)
    T_171814[2] := UInt<3>(2)
    wire T_171815 : UInt<2>[2]
    T_171815[0] := UInt<2>(0)
    T_171815[1] := UInt<2>(1)
    wire T_171816 : UInt<2>[3]
    T_171816[0] := UInt<2>(1)
    T_171816[1] := UInt<2>(2)
    T_171816[2] := UInt<2>(3)
    wire T_171817 : UInt<2>[2]
    T_171817[0] := UInt<2>(2)
    T_171817[1] := UInt<2>(3)
    wire T_171818 : UInt<2>[1]
    T_171818[0] := UInt<2>(3)
    wire T_171819 : UInt<3>[3]
    T_171819[0] := UInt<3>(0)
    T_171819[1] := UInt<3>(1)
    T_171819[2] := UInt<3>(2)
    wire T_171820 : UInt<2>[2]
    T_171820[0] := UInt<2>(0)
    T_171820[1] := UInt<2>(1)
    wire T_171821 : UInt<2>[3]
    T_171821[0] := UInt<2>(1)
    T_171821[1] := UInt<2>(2)
    T_171821[2] := UInt<2>(3)
    wire T_171822 : UInt<2>[2]
    T_171822[0] := UInt<2>(2)
    T_171822[1] := UInt<2>(3)
    wire T_171823 : UInt<2>[1]
    T_171823[0] := UInt<2>(3)
    wire T_171824 : UInt<3>[3]
    T_171824[0] := UInt<3>(0)
    T_171824[1] := UInt<3>(1)
    T_171824[2] := UInt<3>(2)
    wire T_171825 : UInt<2>[2]
    T_171825[0] := UInt<2>(0)
    T_171825[1] := UInt<2>(1)
    wire T_171826 : UInt<2>[3]
    T_171826[0] := UInt<2>(1)
    T_171826[1] := UInt<2>(2)
    T_171826[2] := UInt<2>(3)
    wire T_171827 : UInt<2>[2]
    T_171827[0] := UInt<2>(2)
    T_171827[1] := UInt<2>(3)
    wire T_171828 : UInt<2>[1]
    T_171828[0] := UInt<2>(3)
    wire T_171829 : UInt<3>[3]
    T_171829[0] := UInt<3>(0)
    T_171829[1] := UInt<3>(1)
    T_171829[2] := UInt<3>(2)
    wire T_171830 : UInt<2>[2]
    T_171830[0] := UInt<2>(0)
    T_171830[1] := UInt<2>(1)
    wire T_171831 : UInt<2>[3]
    T_171831[0] := UInt<2>(1)
    T_171831[1] := UInt<2>(2)
    T_171831[2] := UInt<2>(3)
    wire T_171832 : UInt<2>[2]
    T_171832[0] := UInt<2>(2)
    T_171832[1] := UInt<2>(3)
    wire T_171833 : UInt<2>[1]
    T_171833[0] := UInt<2>(3)
    wire T_171834 : UInt<3>[3]
    T_171834[0] := UInt<3>(0)
    T_171834[1] := UInt<3>(1)
    T_171834[2] := UInt<3>(2)
    wire T_171835 : UInt<2>[2]
    T_171835[0] := UInt<2>(0)
    T_171835[1] := UInt<2>(1)
    wire T_171836 : UInt<2>[3]
    T_171836[0] := UInt<2>(1)
    T_171836[1] := UInt<2>(2)
    T_171836[2] := UInt<2>(3)
    wire T_171837 : UInt<2>[2]
    T_171837[0] := UInt<2>(2)
    T_171837[1] := UInt<2>(3)
    wire T_171838 : UInt<2>[1]
    T_171838[0] := UInt<2>(3)
    wire T_171839 : UInt<3>[3]
    T_171839[0] := UInt<3>(0)
    T_171839[1] := UInt<3>(1)
    T_171839[2] := UInt<3>(2)
    wire T_171840 : UInt<2>[2]
    T_171840[0] := UInt<2>(0)
    T_171840[1] := UInt<2>(1)
    wire T_171841 : UInt<2>[3]
    T_171841[0] := UInt<2>(1)
    T_171841[1] := UInt<2>(2)
    T_171841[2] := UInt<2>(3)
    wire T_171842 : UInt<2>[2]
    T_171842[0] := UInt<2>(2)
    T_171842[1] := UInt<2>(3)
    wire T_171843 : UInt<2>[1]
    T_171843[0] := UInt<2>(3)
    wire T_171844 : UInt<3>[3]
    T_171844[0] := UInt<3>(0)
    T_171844[1] := UInt<3>(1)
    T_171844[2] := UInt<3>(2)
    wire T_171845 : UInt<2>[2]
    T_171845[0] := UInt<2>(0)
    T_171845[1] := UInt<2>(1)
    wire T_171846 : UInt<2>[3]
    T_171846[0] := UInt<2>(1)
    T_171846[1] := UInt<2>(2)
    T_171846[2] := UInt<2>(3)
    wire T_171847 : UInt<2>[2]
    T_171847[0] := UInt<2>(2)
    T_171847[1] := UInt<2>(3)
    wire T_171848 : UInt<2>[1]
    T_171848[0] := UInt<2>(3)
    wire T_171849 : UInt<3>[3]
    T_171849[0] := UInt<3>(0)
    T_171849[1] := UInt<3>(1)
    T_171849[2] := UInt<3>(2)
    wire T_171850 : UInt<2>[2]
    T_171850[0] := UInt<2>(0)
    T_171850[1] := UInt<2>(1)
    wire T_171851 : UInt<2>[3]
    T_171851[0] := UInt<2>(1)
    T_171851[1] := UInt<2>(2)
    T_171851[2] := UInt<2>(3)
    wire T_171852 : UInt<2>[2]
    T_171852[0] := UInt<2>(2)
    T_171852[1] := UInt<2>(3)
    wire T_171853 : UInt<2>[1]
    T_171853[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_171854
    wire T_171855 : UInt<3>[3]
    T_171855[0] := UInt<3>(0)
    T_171855[1] := UInt<3>(1)
    T_171855[2] := UInt<3>(2)
    wire T_171856 : UInt<0>[1]
    T_171856[0] := UInt<0>(0)
    wire T_171857 : UInt<2>[2]
    T_171857[0] := UInt<2>(1)
    T_171857[1] := UInt<2>(2)
    wire T_171858 : UInt<2>[2]
    T_171858[0] := UInt<2>(1)
    T_171858[1] := UInt<2>(2)
    wire T_171859 : UInt<2>[1]
    T_171859[0] := UInt<2>(2)
    wire T_171860 : UInt<3>[3]
    T_171860[0] := UInt<3>(0)
    T_171860[1] := UInt<3>(1)
    T_171860[2] := UInt<3>(2)
    wire T_171861 : UInt<0>[1]
    T_171861[0] := UInt<0>(0)
    wire T_171862 : UInt<2>[2]
    T_171862[0] := UInt<2>(1)
    T_171862[1] := UInt<2>(2)
    wire T_171863 : UInt<2>[2]
    T_171863[0] := UInt<2>(1)
    T_171863[1] := UInt<2>(2)
    wire T_171864 : UInt<2>[1]
    T_171864[0] := UInt<2>(2)
    wire T_171865 : UInt<3>[3]
    T_171865[0] := UInt<3>(0)
    T_171865[1] := UInt<3>(1)
    T_171865[2] := UInt<3>(2)
    wire T_171866 : UInt<0>[1]
    T_171866[0] := UInt<0>(0)
    wire T_171867 : UInt<2>[2]
    T_171867[0] := UInt<2>(1)
    T_171867[1] := UInt<2>(2)
    wire T_171868 : UInt<2>[2]
    T_171868[0] := UInt<2>(1)
    T_171868[1] := UInt<2>(2)
    wire T_171869 : UInt<2>[1]
    T_171869[0] := UInt<2>(2)
    wire T_171870 : UInt<3>[3]
    T_171870[0] := UInt<3>(0)
    T_171870[1] := UInt<3>(1)
    T_171870[2] := UInt<3>(2)
    wire T_171871 : UInt<0>[1]
    T_171871[0] := UInt<0>(0)
    wire T_171872 : UInt<2>[2]
    T_171872[0] := UInt<2>(1)
    T_171872[1] := UInt<2>(2)
    wire T_171873 : UInt<2>[2]
    T_171873[0] := UInt<2>(1)
    T_171873[1] := UInt<2>(2)
    wire T_171874 : UInt<2>[1]
    T_171874[0] := UInt<2>(2)
    wire T_171875 : UInt<3>[3]
    T_171875[0] := UInt<3>(0)
    T_171875[1] := UInt<3>(1)
    T_171875[2] := UInt<3>(2)
    wire T_171876 : UInt<0>[1]
    T_171876[0] := UInt<0>(0)
    wire T_171877 : UInt<2>[2]
    T_171877[0] := UInt<2>(1)
    T_171877[1] := UInt<2>(2)
    wire T_171878 : UInt<2>[2]
    T_171878[0] := UInt<2>(1)
    T_171878[1] := UInt<2>(2)
    wire T_171879 : UInt<2>[1]
    T_171879[0] := UInt<2>(2)
    wire T_171880 : UInt<3>[3]
    T_171880[0] := UInt<3>(0)
    T_171880[1] := UInt<3>(1)
    T_171880[2] := UInt<3>(2)
    wire T_171881 : UInt<0>[1]
    T_171881[0] := UInt<0>(0)
    wire T_171882 : UInt<2>[2]
    T_171882[0] := UInt<2>(1)
    T_171882[1] := UInt<2>(2)
    wire T_171883 : UInt<2>[2]
    T_171883[0] := UInt<2>(1)
    T_171883[1] := UInt<2>(2)
    wire T_171884 : UInt<2>[1]
    T_171884[0] := UInt<2>(2)
    wire T_171885 : UInt<3>[3]
    T_171885[0] := UInt<3>(0)
    T_171885[1] := UInt<3>(1)
    T_171885[2] := UInt<3>(2)
    wire T_171886 : UInt<0>[1]
    T_171886[0] := UInt<0>(0)
    wire T_171887 : UInt<2>[2]
    T_171887[0] := UInt<2>(1)
    T_171887[1] := UInt<2>(2)
    wire T_171888 : UInt<2>[2]
    T_171888[0] := UInt<2>(1)
    T_171888[1] := UInt<2>(2)
    wire T_171889 : UInt<2>[1]
    T_171889[0] := UInt<2>(2)
    wire T_171890 : UInt<3>[3]
    T_171890[0] := UInt<3>(0)
    T_171890[1] := UInt<3>(1)
    T_171890[2] := UInt<3>(2)
    wire T_171891 : UInt<0>[1]
    T_171891[0] := UInt<0>(0)
    wire T_171892 : UInt<2>[2]
    T_171892[0] := UInt<2>(1)
    T_171892[1] := UInt<2>(2)
    wire T_171893 : UInt<2>[2]
    T_171893[0] := UInt<2>(1)
    T_171893[1] := UInt<2>(2)
    wire T_171894 : UInt<2>[1]
    T_171894[0] := UInt<2>(2)
    wire T_171895 : UInt<3>[3]
    T_171895[0] := UInt<3>(0)
    T_171895[1] := UInt<3>(1)
    T_171895[2] := UInt<3>(2)
    wire T_171896 : UInt<0>[1]
    T_171896[0] := UInt<0>(0)
    wire T_171897 : UInt<2>[2]
    T_171897[0] := UInt<2>(1)
    T_171897[1] := UInt<2>(2)
    wire T_171898 : UInt<2>[2]
    T_171898[0] := UInt<2>(1)
    T_171898[1] := UInt<2>(2)
    wire T_171899 : UInt<2>[1]
    T_171899[0] := UInt<2>(2)
    wire T_171900 : UInt<3>[3]
    T_171900[0] := UInt<3>(0)
    T_171900[1] := UInt<3>(1)
    T_171900[2] := UInt<3>(2)
    wire T_171901 : UInt<2>[2]
    T_171901[0] := UInt<2>(0)
    T_171901[1] := UInt<2>(1)
    wire T_171902 : UInt<2>[3]
    T_171902[0] := UInt<2>(1)
    T_171902[1] := UInt<2>(2)
    T_171902[2] := UInt<2>(3)
    wire T_171903 : UInt<2>[2]
    T_171903[0] := UInt<2>(2)
    T_171903[1] := UInt<2>(3)
    wire T_171904 : UInt<2>[1]
    T_171904[0] := UInt<2>(3)
    wire T_171905 : UInt<3>[3]
    T_171905[0] := UInt<3>(0)
    T_171905[1] := UInt<3>(1)
    T_171905[2] := UInt<3>(2)
    wire T_171906 : UInt<2>[2]
    T_171906[0] := UInt<2>(0)
    T_171906[1] := UInt<2>(1)
    wire T_171907 : UInt<2>[3]
    T_171907[0] := UInt<2>(1)
    T_171907[1] := UInt<2>(2)
    T_171907[2] := UInt<2>(3)
    wire T_171908 : UInt<2>[2]
    T_171908[0] := UInt<2>(2)
    T_171908[1] := UInt<2>(3)
    wire T_171909 : UInt<2>[1]
    T_171909[0] := UInt<2>(3)
    wire T_171910 : UInt<3>[3]
    T_171910[0] := UInt<3>(0)
    T_171910[1] := UInt<3>(1)
    T_171910[2] := UInt<3>(2)
    wire T_171911 : UInt<0>[1]
    T_171911[0] := UInt<0>(0)
    wire T_171912 : UInt<2>[2]
    T_171912[0] := UInt<2>(1)
    T_171912[1] := UInt<2>(2)
    wire T_171913 : UInt<2>[2]
    T_171913[0] := UInt<2>(1)
    T_171913[1] := UInt<2>(2)
    wire T_171914 : UInt<2>[1]
    T_171914[0] := UInt<2>(2)
    wire T_171915 : UInt<3>[3]
    T_171915[0] := UInt<3>(0)
    T_171915[1] := UInt<3>(1)
    T_171915[2] := UInt<3>(2)
    wire T_171916 : UInt<2>[2]
    T_171916[0] := UInt<2>(0)
    T_171916[1] := UInt<2>(1)
    wire T_171917 : UInt<2>[3]
    T_171917[0] := UInt<2>(1)
    T_171917[1] := UInt<2>(2)
    T_171917[2] := UInt<2>(3)
    wire T_171918 : UInt<2>[2]
    T_171918[0] := UInt<2>(2)
    T_171918[1] := UInt<2>(3)
    wire T_171919 : UInt<2>[1]
    T_171919[0] := UInt<2>(3)
    wire T_171920 : UInt<3>[3]
    T_171920[0] := UInt<3>(0)
    T_171920[1] := UInt<3>(1)
    T_171920[2] := UInt<3>(2)
    wire T_171921 : UInt<2>[2]
    T_171921[0] := UInt<2>(0)
    T_171921[1] := UInt<2>(1)
    wire T_171922 : UInt<2>[3]
    T_171922[0] := UInt<2>(1)
    T_171922[1] := UInt<2>(2)
    T_171922[2] := UInt<2>(3)
    wire T_171923 : UInt<2>[2]
    T_171923[0] := UInt<2>(2)
    T_171923[1] := UInt<2>(3)
    wire T_171924 : UInt<2>[1]
    T_171924[0] := UInt<2>(3)
    wire T_171925 : UInt<3>[3]
    T_171925[0] := UInt<3>(0)
    T_171925[1] := UInt<3>(1)
    T_171925[2] := UInt<3>(2)
    wire T_171926 : UInt<0>[1]
    T_171926[0] := UInt<0>(0)
    wire T_171927 : UInt<2>[2]
    T_171927[0] := UInt<2>(1)
    T_171927[1] := UInt<2>(2)
    wire T_171928 : UInt<2>[2]
    T_171928[0] := UInt<2>(1)
    T_171928[1] := UInt<2>(2)
    wire T_171929 : UInt<2>[1]
    T_171929[0] := UInt<2>(2)
    wire T_171930 : UInt<3>[3]
    T_171930[0] := UInt<3>(0)
    T_171930[1] := UInt<3>(1)
    T_171930[2] := UInt<3>(2)
    wire T_171931 : UInt<2>[2]
    T_171931[0] := UInt<2>(0)
    T_171931[1] := UInt<2>(1)
    wire T_171932 : UInt<2>[3]
    T_171932[0] := UInt<2>(1)
    T_171932[1] := UInt<2>(2)
    T_171932[2] := UInt<2>(3)
    wire T_171933 : UInt<2>[2]
    T_171933[0] := UInt<2>(2)
    T_171933[1] := UInt<2>(3)
    wire T_171934 : UInt<2>[1]
    T_171934[0] := UInt<2>(3)
    wire T_171935 : UInt<3>[3]
    T_171935[0] := UInt<3>(0)
    T_171935[1] := UInt<3>(1)
    T_171935[2] := UInt<3>(2)
    wire T_171936 : UInt<2>[2]
    T_171936[0] := UInt<2>(0)
    T_171936[1] := UInt<2>(1)
    wire T_171937 : UInt<2>[3]
    T_171937[0] := UInt<2>(1)
    T_171937[1] := UInt<2>(2)
    T_171937[2] := UInt<2>(3)
    wire T_171938 : UInt<2>[2]
    T_171938[0] := UInt<2>(2)
    T_171938[1] := UInt<2>(3)
    wire T_171939 : UInt<2>[1]
    T_171939[0] := UInt<2>(3)
    wire T_171940 : UInt<3>[3]
    T_171940[0] := UInt<3>(0)
    T_171940[1] := UInt<3>(1)
    T_171940[2] := UInt<3>(2)
    wire T_171941 : UInt<0>[1]
    T_171941[0] := UInt<0>(0)
    wire T_171942 : UInt<2>[2]
    T_171942[0] := UInt<2>(1)
    T_171942[1] := UInt<2>(2)
    wire T_171943 : UInt<2>[2]
    T_171943[0] := UInt<2>(1)
    T_171943[1] := UInt<2>(2)
    wire T_171944 : UInt<2>[1]
    T_171944[0] := UInt<2>(2)
    wire T_171945 : UInt<3>[3]
    T_171945[0] := UInt<3>(0)
    T_171945[1] := UInt<3>(1)
    T_171945[2] := UInt<3>(2)
    wire T_171946 : UInt<2>[2]
    T_171946[0] := UInt<2>(0)
    T_171946[1] := UInt<2>(1)
    wire T_171947 : UInt<2>[3]
    T_171947[0] := UInt<2>(1)
    T_171947[1] := UInt<2>(2)
    T_171947[2] := UInt<2>(3)
    wire T_171948 : UInt<2>[2]
    T_171948[0] := UInt<2>(2)
    T_171948[1] := UInt<2>(3)
    wire T_171949 : UInt<2>[1]
    T_171949[0] := UInt<2>(3)
    wire T_171950 : UInt<3>[3]
    T_171950[0] := UInt<3>(0)
    T_171950[1] := UInt<3>(1)
    T_171950[2] := UInt<3>(2)
    wire T_171951 : UInt<2>[2]
    T_171951[0] := UInt<2>(0)
    T_171951[1] := UInt<2>(1)
    wire T_171952 : UInt<2>[3]
    T_171952[0] := UInt<2>(1)
    T_171952[1] := UInt<2>(2)
    T_171952[2] := UInt<2>(3)
    wire T_171953 : UInt<2>[2]
    T_171953[0] := UInt<2>(2)
    T_171953[1] := UInt<2>(3)
    wire T_171954 : UInt<2>[1]
    T_171954[0] := UInt<2>(3)
    wire T_171955 : UInt<3>[3]
    T_171955[0] := UInt<3>(0)
    T_171955[1] := UInt<3>(1)
    T_171955[2] := UInt<3>(2)
    wire T_171956 : UInt<0>[1]
    T_171956[0] := UInt<0>(0)
    wire T_171957 : UInt<2>[2]
    T_171957[0] := UInt<2>(1)
    T_171957[1] := UInt<2>(2)
    wire T_171958 : UInt<2>[2]
    T_171958[0] := UInt<2>(1)
    T_171958[1] := UInt<2>(2)
    wire T_171959 : UInt<2>[1]
    T_171959[0] := UInt<2>(2)
    wire T_171960 : UInt<3>[3]
    T_171960[0] := UInt<3>(0)
    T_171960[1] := UInt<3>(1)
    T_171960[2] := UInt<3>(2)
    wire T_171961 : UInt<2>[2]
    T_171961[0] := UInt<2>(0)
    T_171961[1] := UInt<2>(1)
    wire T_171962 : UInt<2>[3]
    T_171962[0] := UInt<2>(1)
    T_171962[1] := UInt<2>(2)
    T_171962[2] := UInt<2>(3)
    wire T_171963 : UInt<2>[2]
    T_171963[0] := UInt<2>(2)
    T_171963[1] := UInt<2>(3)
    wire T_171964 : UInt<2>[1]
    T_171964[0] := UInt<2>(3)
    wire T_171965 : UInt<3>[3]
    T_171965[0] := UInt<3>(0)
    T_171965[1] := UInt<3>(1)
    T_171965[2] := UInt<3>(2)
    wire T_171966 : UInt<2>[2]
    T_171966[0] := UInt<2>(0)
    T_171966[1] := UInt<2>(1)
    wire T_171967 : UInt<2>[3]
    T_171967[0] := UInt<2>(1)
    T_171967[1] := UInt<2>(2)
    T_171967[2] := UInt<2>(3)
    wire T_171968 : UInt<2>[2]
    T_171968[0] := UInt<2>(2)
    T_171968[1] := UInt<2>(3)
    wire T_171969 : UInt<2>[1]
    T_171969[0] := UInt<2>(3)
    wire T_171970 : UInt<3>[3]
    T_171970[0] := UInt<3>(0)
    T_171970[1] := UInt<3>(1)
    T_171970[2] := UInt<3>(2)
    wire T_171971 : UInt<0>[1]
    T_171971[0] := UInt<0>(0)
    wire T_171972 : UInt<2>[2]
    T_171972[0] := UInt<2>(1)
    T_171972[1] := UInt<2>(2)
    wire T_171973 : UInt<2>[2]
    T_171973[0] := UInt<2>(1)
    T_171973[1] := UInt<2>(2)
    wire T_171974 : UInt<2>[1]
    T_171974[0] := UInt<2>(2)
    wire T_171975 : UInt<3>[3]
    T_171975[0] := UInt<3>(0)
    T_171975[1] := UInt<3>(1)
    T_171975[2] := UInt<3>(2)
    wire T_171976 : UInt<2>[2]
    T_171976[0] := UInt<2>(0)
    T_171976[1] := UInt<2>(1)
    wire T_171977 : UInt<2>[3]
    T_171977[0] := UInt<2>(1)
    T_171977[1] := UInt<2>(2)
    T_171977[2] := UInt<2>(3)
    wire T_171978 : UInt<2>[2]
    T_171978[0] := UInt<2>(2)
    T_171978[1] := UInt<2>(3)
    wire T_171979 : UInt<2>[1]
    T_171979[0] := UInt<2>(3)
    wire T_171980 : UInt<3>[3]
    T_171980[0] := UInt<3>(0)
    T_171980[1] := UInt<3>(1)
    T_171980[2] := UInt<3>(2)
    wire T_171981 : UInt<2>[2]
    T_171981[0] := UInt<2>(0)
    T_171981[1] := UInt<2>(1)
    wire T_171982 : UInt<2>[3]
    T_171982[0] := UInt<2>(1)
    T_171982[1] := UInt<2>(2)
    T_171982[2] := UInt<2>(3)
    wire T_171983 : UInt<2>[2]
    T_171983[0] := UInt<2>(2)
    T_171983[1] := UInt<2>(3)
    wire T_171984 : UInt<2>[1]
    T_171984[0] := UInt<2>(3)
    wire T_171985 : UInt<3>[3]
    T_171985[0] := UInt<3>(0)
    T_171985[1] := UInt<3>(1)
    T_171985[2] := UInt<3>(2)
    wire T_171986 : UInt<0>[1]
    T_171986[0] := UInt<0>(0)
    wire T_171987 : UInt<2>[2]
    T_171987[0] := UInt<2>(1)
    T_171987[1] := UInt<2>(2)
    wire T_171988 : UInt<2>[2]
    T_171988[0] := UInt<2>(1)
    T_171988[1] := UInt<2>(2)
    wire T_171989 : UInt<2>[1]
    T_171989[0] := UInt<2>(2)
    wire T_171990 : UInt<3>[3]
    T_171990[0] := UInt<3>(0)
    T_171990[1] := UInt<3>(1)
    T_171990[2] := UInt<3>(2)
    wire T_171991 : UInt<2>[2]
    T_171991[0] := UInt<2>(0)
    T_171991[1] := UInt<2>(1)
    wire T_171992 : UInt<2>[3]
    T_171992[0] := UInt<2>(1)
    T_171992[1] := UInt<2>(2)
    T_171992[2] := UInt<2>(3)
    wire T_171993 : UInt<2>[2]
    T_171993[0] := UInt<2>(2)
    T_171993[1] := UInt<2>(3)
    wire T_171994 : UInt<2>[1]
    T_171994[0] := UInt<2>(3)
    wire T_171995 : UInt<3>[3]
    T_171995[0] := UInt<3>(0)
    T_171995[1] := UInt<3>(1)
    T_171995[2] := UInt<3>(2)
    wire T_171996 : UInt<2>[2]
    T_171996[0] := UInt<2>(0)
    T_171996[1] := UInt<2>(1)
    wire T_171997 : UInt<2>[3]
    T_171997[0] := UInt<2>(1)
    T_171997[1] := UInt<2>(2)
    T_171997[2] := UInt<2>(3)
    wire T_171998 : UInt<2>[2]
    T_171998[0] := UInt<2>(2)
    T_171998[1] := UInt<2>(3)
    wire T_171999 : UInt<2>[1]
    T_171999[0] := UInt<2>(3)
    wire T_172000 : UInt<3>[3]
    T_172000[0] := UInt<3>(0)
    T_172000[1] := UInt<3>(1)
    T_172000[2] := UInt<3>(2)
    wire T_172001 : UInt<0>[1]
    T_172001[0] := UInt<0>(0)
    wire T_172002 : UInt<2>[2]
    T_172002[0] := UInt<2>(1)
    T_172002[1] := UInt<2>(2)
    wire T_172003 : UInt<2>[2]
    T_172003[0] := UInt<2>(1)
    T_172003[1] := UInt<2>(2)
    wire T_172004 : UInt<2>[1]
    T_172004[0] := UInt<2>(2)
    wire T_172005 : UInt<3>[3]
    T_172005[0] := UInt<3>(0)
    T_172005[1] := UInt<3>(1)
    T_172005[2] := UInt<3>(2)
    wire T_172006 : UInt<2>[2]
    T_172006[0] := UInt<2>(0)
    T_172006[1] := UInt<2>(1)
    wire T_172007 : UInt<2>[3]
    T_172007[0] := UInt<2>(1)
    T_172007[1] := UInt<2>(2)
    T_172007[2] := UInt<2>(3)
    wire T_172008 : UInt<2>[2]
    T_172008[0] := UInt<2>(2)
    T_172008[1] := UInt<2>(3)
    wire T_172009 : UInt<2>[1]
    T_172009[0] := UInt<2>(3)
    wire T_172010 : UInt<3>[3]
    T_172010[0] := UInt<3>(0)
    T_172010[1] := UInt<3>(1)
    T_172010[2] := UInt<3>(2)
    wire T_172011 : UInt<2>[2]
    T_172011[0] := UInt<2>(0)
    T_172011[1] := UInt<2>(1)
    wire T_172012 : UInt<2>[3]
    T_172012[0] := UInt<2>(1)
    T_172012[1] := UInt<2>(2)
    T_172012[2] := UInt<2>(3)
    wire T_172013 : UInt<2>[2]
    T_172013[0] := UInt<2>(2)
    T_172013[1] := UInt<2>(3)
    wire T_172014 : UInt<2>[1]
    T_172014[0] := UInt<2>(3)
    wire T_172015 : UInt<3>[3]
    T_172015[0] := UInt<3>(0)
    T_172015[1] := UInt<3>(1)
    T_172015[2] := UInt<3>(2)
    wire T_172016 : UInt<0>[1]
    T_172016[0] := UInt<0>(0)
    wire T_172017 : UInt<2>[2]
    T_172017[0] := UInt<2>(1)
    T_172017[1] := UInt<2>(2)
    wire T_172018 : UInt<2>[2]
    T_172018[0] := UInt<2>(1)
    T_172018[1] := UInt<2>(2)
    wire T_172019 : UInt<2>[1]
    T_172019[0] := UInt<2>(2)
    wb.resp.valid := UInt<1>(0)
    wb.req.valid := UInt<1>(0)
    meta.write.valid := UInt<1>(0)
    meta.resp.valid := UInt<1>(0)
    meta.read.valid := UInt<1>(0)
    data.write.valid := UInt<1>(0)
    data.resp.valid := UInt<1>(0)
    data.read.valid := UInt<1>(0)
    outer.release.valid := UInt<1>(0)
    outer.probe.valid := UInt<1>(0)
    outer.grant.valid := UInt<1>(0)
    outer.acquire.valid := UInt<1>(0)
    inner.release.valid := UInt<1>(0)
    inner.probe.valid := UInt<1>(0)
    inner.finish.valid := UInt<1>(0)
    inner.grant.valid := UInt<1>(0)
    inner.acquire.valid := UInt<1>(0)
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    wire T_172020 : UInt<3>[3]
    T_172020[0] := UInt<3>(0)
    T_172020[1] := UInt<3>(1)
    T_172020[2] := UInt<3>(2)
    wire T_172021 : UInt<2>[2]
    T_172021[0] := UInt<2>(0)
    T_172021[1] := UInt<2>(1)
    wire T_172022 : UInt<2>[3]
    T_172022[0] := UInt<2>(1)
    T_172022[1] := UInt<2>(2)
    T_172022[2] := UInt<2>(3)
    wire T_172023 : UInt<2>[2]
    T_172023[0] := UInt<2>(2)
    T_172023[1] := UInt<2>(3)
    wire T_172024 : UInt<2>[1]
    T_172024[0] := UInt<2>(3)
    wire T_172025 : UInt<3>[3]
    T_172025[0] := UInt<3>(0)
    T_172025[1] := UInt<3>(1)
    T_172025[2] := UInt<3>(2)
    wire T_172026 : UInt<2>[2]
    T_172026[0] := UInt<2>(0)
    T_172026[1] := UInt<2>(1)
    wire T_172027 : UInt<2>[3]
    T_172027[0] := UInt<2>(1)
    T_172027[1] := UInt<2>(2)
    T_172027[2] := UInt<2>(3)
    wire T_172028 : UInt<2>[2]
    T_172028[0] := UInt<2>(2)
    T_172028[1] := UInt<2>(3)
    wire T_172029 : UInt<2>[1]
    T_172029[0] := UInt<2>(3)
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}
    wire T_172030 : UInt<128>[4]
    T_172030[0] := UInt<128>(0)
    T_172030[1] := UInt<128>(0)
    T_172030[2] := UInt<128>(0)
    T_172030[3] := UInt<128>(0)
    reg data_buffer : UInt<128>[4]
    onreset data_buffer := T_172030
    reg xact_way_en : UInt<8>
    wire T_172031 : UInt<3>[3]
    T_172031[0] := UInt<3>(0)
    T_172031[1] := UInt<3>(1)
    T_172031[2] := UInt<3>(2)
    wire T_172032 : UInt<2>[2]
    T_172032[0] := UInt<2>(0)
    T_172032[1] := UInt<2>(1)
    wire T_172033 : UInt<2>[3]
    T_172033[0] := UInt<2>(1)
    T_172033[1] := UInt<2>(2)
    T_172033[2] := UInt<2>(3)
    wire T_172034 : UInt<2>[2]
    T_172034[0] := UInt<2>(2)
    T_172034[1] := UInt<2>(3)
    wire T_172035 : UInt<2>[1]
    T_172035[0] := UInt<2>(3)
    wire T_172036 : UInt<3>[3]
    T_172036[0] := UInt<3>(0)
    T_172036[1] := UInt<3>(1)
    T_172036[2] := UInt<3>(2)
    wire T_172037 : UInt<2>[2]
    T_172037[0] := UInt<2>(0)
    T_172037[1] := UInt<2>(1)
    wire T_172038 : UInt<2>[3]
    T_172038[0] := UInt<2>(1)
    T_172038[1] := UInt<2>(2)
    T_172038[2] := UInt<2>(3)
    wire T_172039 : UInt<2>[2]
    T_172039[0] := UInt<2>(2)
    T_172039[1] := UInt<2>(3)
    wire T_172040 : UInt<2>[1]
    T_172040[0] := UInt<2>(3)
    wire T_172041 : UInt<3>[3]
    T_172041[0] := UInt<3>(0)
    T_172041[1] := UInt<3>(1)
    T_172041[2] := UInt<3>(2)
    wire T_172042 : UInt<0>[1]
    T_172042[0] := UInt<0>(0)
    wire T_172043 : UInt<2>[2]
    T_172043[0] := UInt<2>(1)
    T_172043[1] := UInt<2>(2)
    wire T_172044 : UInt<2>[2]
    T_172044[0] := UInt<2>(1)
    T_172044[1] := UInt<2>(2)
    wire T_172045 : UInt<2>[1]
    T_172045[0] := UInt<2>(2)
    wire T_172046 : UInt<3>[3]
    T_172046[0] := UInt<3>(0)
    T_172046[1] := UInt<3>(1)
    T_172046[2] := UInt<3>(2)
    wire T_172047 : UInt<2>[2]
    T_172047[0] := UInt<2>(0)
    T_172047[1] := UInt<2>(1)
    wire T_172048 : UInt<2>[3]
    T_172048[0] := UInt<2>(1)
    T_172048[1] := UInt<2>(2)
    T_172048[2] := UInt<2>(3)
    wire T_172049 : UInt<2>[2]
    T_172049[0] := UInt<2>(2)
    T_172049[1] := UInt<2>(3)
    wire T_172050 : UInt<2>[1]
    T_172050[0] := UInt<2>(3)
    wire T_172051 : UInt<3>[3]
    T_172051[0] := UInt<3>(0)
    T_172051[1] := UInt<3>(1)
    T_172051[2] := UInt<3>(2)
    wire T_172052 : UInt<2>[2]
    T_172052[0] := UInt<2>(0)
    T_172052[1] := UInt<2>(1)
    wire T_172053 : UInt<2>[3]
    T_172053[0] := UInt<2>(1)
    T_172053[1] := UInt<2>(2)
    T_172053[2] := UInt<2>(3)
    wire T_172054 : UInt<2>[2]
    T_172054[0] := UInt<2>(2)
    T_172054[1] := UInt<2>(3)
    wire T_172055 : UInt<2>[1]
    T_172055[0] := UInt<2>(3)
    wire T_172056 : UInt<3>[3]
    T_172056[0] := UInt<3>(0)
    T_172056[1] := UInt<3>(1)
    T_172056[2] := UInt<3>(2)
    wire T_172057 : UInt<0>[1]
    T_172057[0] := UInt<0>(0)
    wire T_172058 : UInt<2>[2]
    T_172058[0] := UInt<2>(1)
    T_172058[1] := UInt<2>(2)
    wire T_172059 : UInt<2>[2]
    T_172059[0] := UInt<2>(1)
    T_172059[1] := UInt<2>(2)
    wire T_172060 : UInt<2>[1]
    T_172060[0] := UInt<2>(2)
    reg xact_old_meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    reg pending_irels : UInt<4>
    onreset pending_irels := UInt<4>(0)
    reg pending_writes : UInt<4>
    onreset pending_writes := UInt<4>(0)
    reg pending_ignt : UInt<1>
    onreset pending_ignt := UInt<1>(0)
    node T_172061 = eq(pending_writes, UInt<1>(0))
    node T_172062 = eq(T_172061, UInt<1>(0))
    node T_172063 = or(T_172062, pending_ignt)
    node all_pending_done = eq(T_172063, UInt<1>(0))
    node T_172064 = and(inner.release.ready, inner.release.valid)
    node T_172065 = eq(T_171849[0], inner.release.bits.r_type)
    node T_172066 = eq(T_171849[1], inner.release.bits.r_type)
    node T_172067 = eq(T_171849[2], inner.release.bits.r_type)
    node T_172068 = or(UInt<1>(0), T_172065)
    node T_172069 = or(T_172068, T_172066)
    node T_172070 = or(T_172069, T_172067)
    node T_172071 = and(T_172064, T_172070)
    node T_172072 = subw(UInt<4>(0), UInt<3>(4))
    node T_172073 = not(T_172072)
    node T_172074 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_172075 = not(T_172074)
    node T_172076 = or(T_172073, T_172075)
    node T_172077 = and(pending_irels, T_172076)
    pending_irels := T_172077
    node T_172078 = eq(state, UInt<3>(0))
    node T_172079 = eq(pending_irels, UInt<1>(0))
    node T_172080 = eq(T_172079, UInt<1>(0))
    node T_172081 = or(T_172078, T_172080)
    inner.release.ready := T_172081
    
    node T_172082 = and(inner.release.ready, inner.release.valid)
    when T_172082 : 
      accessor T_172083 = data_buffer[inner.release.bits.addr_beat]
      T_172083 := inner.release.bits.data
    node T_172084 = eq(state, UInt<3>(1))
    meta.read.valid := T_172084
    meta.read.bits.id := UInt<1>(0)
    node T_172085 = bits(xact.addr_block, 11, 0)
    meta.read.bits.idx := T_172085
    node T_172086 = dshr(xact.addr_block, UInt<4>(12))
    meta.read.bits.tag := T_172086
    node T_172087 = and(data.write.ready, data.write.valid)
    node T_172088 = subw(UInt<4>(0), UInt<3>(4))
    node T_172089 = not(T_172088)
    node T_172090 = dshl(UInt<1>(1), data.write.bits.addr_beat)
    node T_172091 = not(T_172090)
    node T_172092 = or(T_172089, T_172091)
    node T_172093 = and(pending_writes, T_172092)
    node T_172094 = and(inner.release.ready, inner.release.valid)
    node T_172095 = eq(T_171849[0], inner.release.bits.r_type)
    node T_172096 = eq(T_171849[1], inner.release.bits.r_type)
    node T_172097 = eq(T_171849[2], inner.release.bits.r_type)
    node T_172098 = or(UInt<1>(0), T_172095)
    node T_172099 = or(T_172098, T_172096)
    node T_172100 = or(T_172099, T_172097)
    node T_172101 = and(T_172094, T_172100)
    node T_172102 = subw(UInt<4>(0), UInt<3>(4))
    node T_172103 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_172104 = and(T_172102, T_172103)
    node T_172105 = or(T_172093, T_172104)
    pending_writes := T_172105
    node T_172106 = bit(pending_writes, 0)
    node T_172107 = bit(pending_writes, 1)
    node T_172108 = bit(pending_writes, 2)
    node T_172109 = bit(pending_writes, 3)
    wire T_172110 : UInt<1>[4]
    T_172110[0] := T_172106
    T_172110[1] := T_172107
    T_172110[2] := T_172108
    T_172110[3] := T_172109
    wire T_172111 : UInt<2>
    T_172111 := UInt<2>(3)
    when T_172110[2] : T_172111 := UInt<2>(2)
    wire T_172112 : UInt<2>
    T_172112 := T_172111
    when T_172110[1] : T_172112 := UInt<1>(1)
    wire curr_write_beat : UInt<2>
    curr_write_beat := T_172112
    when T_172110[0] : curr_write_beat := UInt<1>(0)
    node T_172113 = eq(state, UInt<3>(3))
    node T_172114 = eq(pending_writes, UInt<1>(0))
    node T_172115 = eq(T_172114, UInt<1>(0))
    node T_172116 = and(T_172113, T_172115)
    data.write.valid := T_172116
    data.write.bits.id := UInt<1>(0)
    data.write.bits.way_en := xact_way_en
    node T_172117 = bits(xact.addr_block, 11, 0)
    data.write.bits.addr_idx := T_172117
    data.write.bits.addr_beat := curr_write_beat
    data.write.bits.wmask := SInt<1>(-1)
    accessor T_172118 = data_buffer[curr_write_beat]
    data.write.bits.data := T_172118
    node T_172119 = eq(state, UInt<3>(3))
    node T_172120 = and(T_172119, pending_ignt)
    node T_172121 = eq(pending_irels, UInt<1>(0))
    node T_172122 = and(T_172120, T_172121)
    inner.grant.valid := T_172122
    wire T_172123 : UInt<3>[3]
    T_172123[0] := UInt<3>(0)
    T_172123[1] := UInt<3>(1)
    T_172123[2] := UInt<3>(2)
    wire T_172124 : UInt<2>[2]
    T_172124[0] := UInt<2>(0)
    T_172124[1] := UInt<2>(1)
    wire T_172125 : UInt<2>[3]
    T_172125[0] := UInt<2>(1)
    T_172125[1] := UInt<2>(2)
    T_172125[2] := UInt<2>(3)
    wire T_172126 : UInt<2>[2]
    T_172126[0] := UInt<2>(2)
    T_172126[1] := UInt<2>(3)
    wire T_172127 : UInt<2>[1]
    T_172127[0] := UInt<2>(3)
    wire T_172128 : UInt<3>[3]
    T_172128[0] := UInt<3>(0)
    T_172128[1] := UInt<3>(1)
    T_172128[2] := UInt<3>(2)
    wire T_172129 : UInt<2>[2]
    T_172129[0] := UInt<2>(0)
    T_172129[1] := UInt<2>(1)
    wire T_172130 : UInt<2>[3]
    T_172130[0] := UInt<2>(1)
    T_172130[1] := UInt<2>(2)
    T_172130[2] := UInt<2>(3)
    wire T_172131 : UInt<2>[2]
    T_172131[0] := UInt<2>(2)
    T_172131[1] := UInt<2>(3)
    wire T_172132 : UInt<2>[1]
    T_172132[0] := UInt<2>(3)
    wire T_172133 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}
    T_172133.client_id := xact.client_id
    T_172133.is_builtin_type := UInt<1>(1)
    T_172133.g_type := UInt<3>(0)
    T_172133.client_xact_id := xact.client_xact_id
    T_172133.manager_xact_id := UInt<1>(0)
    T_172133.addr_beat := UInt<1>(0)
    T_172133.data := UInt<1>(0)
    inner.grant.bits := T_172133
    
    node T_172134 = and(inner.grant.ready, inner.grant.valid)
    when T_172134 : pending_ignt := UInt<1>(0)
    node T_172135 = eq(state, UInt<3>(4))
    meta.write.valid := T_172135
    meta.write.bits.id := UInt<1>(0)
    node T_172136 = bits(xact.addr_block, 11, 0)
    meta.write.bits.idx := T_172136
    meta.write.bits.way_en := xact_way_en
    node T_172137 = dshr(xact.addr_block, UInt<4>(12))
    meta.write.bits.data.tag := T_172137
    node T_172138 = dshl(UInt<1>(1), xact.client_id)
    node T_172139 = not(T_172138)
    node T_172140 = and(xact_old_meta.coh.inner.sharers, T_172139)
    wire T_172141 : UInt<3>[3]
    T_172141[0] := UInt<3>(0)
    T_172141[1] := UInt<3>(1)
    T_172141[2] := UInt<3>(2)
    wire T_172142 : UInt<2>[2]
    T_172142[0] := UInt<2>(0)
    T_172142[1] := UInt<2>(1)
    wire T_172143 : UInt<2>[3]
    T_172143[0] := UInt<2>(1)
    T_172143[1] := UInt<2>(2)
    T_172143[2] := UInt<2>(3)
    wire T_172144 : UInt<2>[2]
    T_172144[0] := UInt<2>(2)
    T_172144[1] := UInt<2>(3)
    wire T_172145 : UInt<2>[1]
    T_172145[0] := UInt<2>(3)
    wire T_172146 : UInt<3>[3]
    T_172146[0] := UInt<3>(0)
    T_172146[1] := UInt<3>(1)
    T_172146[2] := UInt<3>(2)
    wire T_172147 : UInt<2>[2]
    T_172147[0] := UInt<2>(0)
    T_172147[1] := UInt<2>(1)
    wire T_172148 : UInt<2>[3]
    T_172148[0] := UInt<2>(1)
    T_172148[1] := UInt<2>(2)
    T_172148[2] := UInt<2>(3)
    wire T_172149 : UInt<2>[2]
    T_172149[0] := UInt<2>(2)
    T_172149[1] := UInt<2>(3)
    wire T_172150 : UInt<2>[1]
    T_172150[0] := UInt<2>(3)
    wire T_172151 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_172151.sharers := T_172140
    node T_172152 = eq(xact.r_type, UInt<3>(0))
    node T_172153 = eq(xact.r_type, UInt<3>(3))
    wire T_172154 : UInt<3>[3]
    T_172154[0] := UInt<3>(0)
    T_172154[1] := UInt<3>(1)
    T_172154[2] := UInt<3>(2)
    wire T_172155 : UInt<2>[2]
    T_172155[0] := UInt<2>(0)
    T_172155[1] := UInt<2>(1)
    wire T_172156 : UInt<2>[3]
    T_172156[0] := UInt<2>(1)
    T_172156[1] := UInt<2>(2)
    T_172156[2] := UInt<2>(3)
    wire T_172157 : UInt<2>[2]
    T_172157[0] := UInt<2>(2)
    T_172157[1] := UInt<2>(3)
    wire T_172158 : UInt<2>[1]
    T_172158[0] := UInt<2>(3)
    wire T_172159 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_172159 := xact_old_meta.coh.inner
    when T_172153 : T_172159 := T_172151
    wire T_172160 : UInt<3>[3]
    T_172160[0] := UInt<3>(0)
    T_172160[1] := UInt<3>(1)
    T_172160[2] := UInt<3>(2)
    wire T_172161 : UInt<2>[2]
    T_172161[0] := UInt<2>(0)
    T_172161[1] := UInt<2>(1)
    wire T_172162 : UInt<2>[3]
    T_172162[0] := UInt<2>(1)
    T_172162[1] := UInt<2>(2)
    T_172162[2] := UInt<2>(3)
    wire T_172163 : UInt<2>[2]
    T_172163[0] := UInt<2>(2)
    T_172163[1] := UInt<2>(3)
    wire T_172164 : UInt<2>[1]
    T_172164[0] := UInt<2>(3)
    wire T_172165 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_172165 := T_172159
    when T_172152 : T_172165 := T_172151
    meta.write.bits.data.coh.inner := T_172165
    node T_172166 = eq(T_172025[0], xact.r_type)
    node T_172167 = eq(T_172025[1], xact.r_type)
    node T_172168 = eq(T_172025[2], xact.r_type)
    node T_172169 = or(UInt<1>(0), T_172166)
    node T_172170 = or(T_172169, T_172167)
    node T_172171 = or(T_172170, T_172168)
    node T_172172 = eq(UInt<5>(1), UInt<5>(1))
    node T_172173 = eq(UInt<5>(1), UInt<5>(7))
    node T_172174 = or(T_172172, T_172173)
    node T_172175 = eq(UInt<5>(1), UInt<5>(4))
    node T_172176 = or(UInt<1>(0), T_172175)
    node T_172177 = or(T_172174, T_172176)
    wire T_172178 : UInt<2>
    T_172178 := xact_old_meta.coh.outer.state
    when T_172177 : T_172178 := UInt<2>(2)
    wire T_172179 : UInt<3>[3]
    T_172179[0] := UInt<3>(0)
    T_172179[1] := UInt<3>(1)
    T_172179[2] := UInt<3>(2)
    wire T_172180 : UInt<0>[1]
    T_172180[0] := UInt<0>(0)
    wire T_172181 : UInt<2>[2]
    T_172181[0] := UInt<2>(1)
    T_172181[1] := UInt<2>(2)
    wire T_172182 : UInt<2>[2]
    T_172182[0] := UInt<2>(1)
    T_172182[1] := UInt<2>(2)
    wire T_172183 : UInt<2>[1]
    T_172183[0] := UInt<2>(2)
    wire T_172184 : UInt<3>[3]
    T_172184[0] := UInt<3>(0)
    T_172184[1] := UInt<3>(1)
    T_172184[2] := UInt<3>(2)
    wire T_172185 : UInt<0>[1]
    T_172185[0] := UInt<0>(0)
    wire T_172186 : UInt<2>[2]
    T_172186[0] := UInt<2>(1)
    T_172186[1] := UInt<2>(2)
    wire T_172187 : UInt<2>[2]
    T_172187[0] := UInt<2>(1)
    T_172187[1] := UInt<2>(2)
    wire T_172188 : UInt<2>[1]
    T_172188[0] := UInt<2>(2)
    wire T_172189 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_172189.state := T_172178
    wire T_172190 : UInt<3>[3]
    T_172190[0] := UInt<3>(0)
    T_172190[1] := UInt<3>(1)
    T_172190[2] := UInt<3>(2)
    wire T_172191 : UInt<2>[2]
    T_172191[0] := UInt<2>(0)
    T_172191[1] := UInt<2>(1)
    wire T_172192 : UInt<2>[3]
    T_172192[0] := UInt<2>(1)
    T_172192[1] := UInt<2>(2)
    T_172192[2] := UInt<2>(3)
    wire T_172193 : UInt<2>[2]
    T_172193[0] := UInt<2>(2)
    T_172193[1] := UInt<2>(3)
    wire T_172194 : UInt<2>[1]
    T_172194[0] := UInt<2>(3)
    wire T_172195 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_172195 := xact_old_meta.coh.outer
    when T_172171 : T_172195 := T_172189
    meta.write.bits.data.coh.outer := T_172195
    
    
    node T_172196 = eq(state, UInt<3>(0))
    node T_172197 = and(T_172196, inner.release.valid)
    when T_172197 : 
      xact := inner.release.bits
      
      
      node T_172198 = eq(T_171849[0], inner.release.bits.r_type)
      node T_172199 = eq(T_171849[1], inner.release.bits.r_type)
      node T_172200 = eq(T_171849[2], inner.release.bits.r_type)
      node T_172201 = or(UInt<1>(0), T_172198)
      node T_172202 = or(T_172201, T_172199)
      node T_172203 = or(T_172202, T_172200)
      node T_172204 = and(UInt<1>(1), T_172203)
      when T_172204 : 
        node T_172205 = and(inner.release.ready, inner.release.valid)
        node T_172206 = eq(T_171849[0], inner.release.bits.r_type)
        node T_172207 = eq(T_171849[1], inner.release.bits.r_type)
        node T_172208 = eq(T_171849[2], inner.release.bits.r_type)
        node T_172209 = or(UInt<1>(0), T_172206)
        node T_172210 = or(T_172209, T_172207)
        node T_172211 = or(T_172210, T_172208)
        node T_172212 = and(T_172205, T_172211)
        node T_172213 = subw(UInt<4>(0), UInt<3>(4))
        node T_172214 = not(T_172213)
        node T_172215 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
        node T_172216 = not(T_172215)
        node T_172217 = or(T_172214, T_172216)
        pending_irels := T_172217
      else : 
        pending_irels := UInt<1>(0)
      node T_172218 = and(inner.release.ready, inner.release.valid)
      node T_172219 = eq(T_171849[0], inner.release.bits.r_type)
      node T_172220 = eq(T_171849[1], inner.release.bits.r_type)
      node T_172221 = eq(T_171849[2], inner.release.bits.r_type)
      node T_172222 = or(UInt<1>(0), T_172219)
      node T_172223 = or(T_172222, T_172220)
      node T_172224 = or(T_172223, T_172221)
      node T_172225 = and(T_172218, T_172224)
      node T_172226 = subw(UInt<4>(0), UInt<3>(4))
      node T_172227 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
      node T_172228 = and(T_172226, T_172227)
      pending_writes := T_172228
      node T_172229 = eq(UInt<1>(0), UInt<1>(0))
      pending_ignt := T_172229
      state := UInt<3>(1)
    
    
    node T_172230 = eq(state, UInt<3>(1))
    node T_172231 = and(T_172230, meta.read.ready)
    when T_172231 : state := UInt<3>(2)
    
    
    node T_172232 = eq(state, UInt<3>(2))
    node T_172233 = and(T_172232, meta.resp.valid)
    when T_172233 : 
      xact_old_meta := meta.resp.bits.meta
      xact_way_en := meta.resp.bits.way_en
      state := UInt<3>(3)
    
    
    node T_172234 = eq(state, UInt<3>(3))
    node T_172235 = and(T_172234, all_pending_done)
    when T_172235 : state := UInt<3>(4)
    
    
    node T_172236 = eq(state, UInt<3>(4))
    node T_172237 = and(T_172236, meta.write.ready)
    when T_172237 : state := UInt<3>(0)
    has_release_match := inner.release.bits.voluntary
    has_acquire_match := UInt<1>(0)
    has_acquire_conflict := UInt<1>(0)
    node T_172238 = eq(state, UInt<3>(2))
    node T_172239 = and(T_172238, meta.resp.valid)
    node T_172240 = eq(meta.resp.bits.tag_match, UInt<1>(0))
    node T_172241 = and(T_172239, T_172240)
    node T_172242 = eq(T_172241, UInt<1>(0))
    node T_172243 = eq(state, UInt<3>(0))
    node T_172244 = and(inner.release.ready, inner.release.valid)
    node T_172245 = and(T_172243, T_172244)
    node T_172246 = eq(inner.release.bits.voluntary, UInt<1>(0))
    node T_172247 = and(T_172245, T_172246)
    node T_172248 = eq(T_172247, UInt<1>(0))
  module Queue_76584 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<1>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<1>}}
    output count : UInt<3>
    
    wire T_172249 : UInt<3>[3]
    T_172249[0] := UInt<3>(0)
    T_172249[1] := UInt<3>(1)
    T_172249[2] := UInt<3>(2)
    wire T_172250 : UInt<2>[2]
    T_172250[0] := UInt<2>(0)
    T_172250[1] := UInt<2>(1)
    wire T_172251 : UInt<2>[3]
    T_172251[0] := UInt<2>(1)
    T_172251[1] := UInt<2>(2)
    T_172251[2] := UInt<2>(3)
    wire T_172252 : UInt<2>[2]
    T_172252[0] := UInt<2>(2)
    T_172252[1] := UInt<2>(3)
    wire T_172253 : UInt<2>[1]
    T_172253[0] := UInt<2>(3)
    wire T_172254 : UInt<3>[3]
    T_172254[0] := UInt<3>(0)
    T_172254[1] := UInt<3>(1)
    T_172254[2] := UInt<3>(2)
    wire T_172255 : UInt<2>[2]
    T_172255[0] := UInt<2>(0)
    T_172255[1] := UInt<2>(1)
    wire T_172256 : UInt<2>[3]
    T_172256[0] := UInt<2>(1)
    T_172256[1] := UInt<2>(2)
    T_172256[2] := UInt<2>(3)
    wire T_172257 : UInt<2>[2]
    T_172257[0] := UInt<2>(2)
    T_172257[1] := UInt<2>(3)
    wire T_172258 : UInt<2>[1]
    T_172258[0] := UInt<2>(3)
    wire T_172259 : UInt<3>[3]
    T_172259[0] := UInt<3>(0)
    T_172259[1] := UInt<3>(1)
    T_172259[2] := UInt<3>(2)
    wire T_172260 : UInt<2>[2]
    T_172260[0] := UInt<2>(0)
    T_172260[1] := UInt<2>(1)
    wire T_172261 : UInt<2>[3]
    T_172261[0] := UInt<2>(1)
    T_172261[1] := UInt<2>(2)
    T_172261[2] := UInt<2>(3)
    wire T_172262 : UInt<2>[2]
    T_172262[0] := UInt<2>(2)
    T_172262[1] := UInt<2>(3)
    wire T_172263 : UInt<2>[1]
    T_172263[0] := UInt<2>(3)
    wire T_172264 : UInt<3>[3]
    T_172264[0] := UInt<3>(0)
    T_172264[1] := UInt<3>(1)
    T_172264[2] := UInt<3>(2)
    wire T_172265 : UInt<2>[2]
    T_172265[0] := UInt<2>(0)
    T_172265[1] := UInt<2>(1)
    wire T_172266 : UInt<2>[3]
    T_172266[0] := UInt<2>(1)
    T_172266[1] := UInt<2>(2)
    T_172266[2] := UInt<2>(3)
    wire T_172267 : UInt<2>[2]
    T_172267[0] := UInt<2>(2)
    T_172267[1] := UInt<2>(3)
    wire T_172268 : UInt<2>[1]
    T_172268[0] := UInt<2>(3)
    wire T_172269 : UInt<3>[3]
    T_172269[0] := UInt<3>(0)
    T_172269[1] := UInt<3>(1)
    T_172269[2] := UInt<3>(2)
    wire T_172270 : UInt<2>[2]
    T_172270[0] := UInt<2>(0)
    T_172270[1] := UInt<2>(1)
    wire T_172271 : UInt<2>[3]
    T_172271[0] := UInt<2>(1)
    T_172271[1] := UInt<2>(2)
    T_172271[2] := UInt<2>(3)
    wire T_172272 : UInt<2>[2]
    T_172272[0] := UInt<2>(2)
    T_172272[1] := UInt<2>(3)
    wire T_172273 : UInt<2>[1]
    T_172273[0] := UInt<2>(3)
    cmem ram : {addr_beat : UInt<2>, client_xact_id : UInt<1>}[4]
    reg T_172274 : UInt<2>
    onreset T_172274 := UInt<2>(0)
    reg T_172275 : UInt<2>
    onreset T_172275 := UInt<2>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_172274, T_172275)
    node T_172276 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_172276)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_172277 = and(enq.ready, enq.valid)
    node T_172278 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_172277, T_172278)
    node T_172279 = and(deq.ready, deq.valid)
    node T_172280 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_172279, T_172280)
    when do_enq : 
      wire T_172281 : UInt<3>[3]
      T_172281[0] := UInt<3>(0)
      T_172281[1] := UInt<3>(1)
      T_172281[2] := UInt<3>(2)
      wire T_172282 : UInt<2>[2]
      T_172282[0] := UInt<2>(0)
      T_172282[1] := UInt<2>(1)
      wire T_172283 : UInt<2>[3]
      T_172283[0] := UInt<2>(1)
      T_172283[1] := UInt<2>(2)
      T_172283[2] := UInt<2>(3)
      wire T_172284 : UInt<2>[2]
      T_172284[0] := UInt<2>(2)
      T_172284[1] := UInt<2>(3)
      wire T_172285 : UInt<2>[1]
      T_172285[0] := UInt<2>(3)
      accessor T_172286 = ram[T_172274]
      T_172286 := enq.bits
      node T_172287 = eq(T_172274, UInt<2>(3))
      node T_172288 = and(UInt<1>(0), T_172287)
      node T_172289 = addw(T_172274, UInt<1>(1))
      wire T_172290 : UInt<2>
      T_172290 := T_172289
      when T_172288 : T_172290 := UInt<1>(0)
      T_172274 := T_172290
    when do_deq : 
      node T_172291 = eq(T_172275, UInt<2>(3))
      node T_172292 = and(UInt<1>(0), T_172291)
      node T_172293 = addw(T_172275, UInt<1>(1))
      wire T_172294 : UInt<2>
      T_172294 := T_172293
      when T_172292 : T_172294 := UInt<1>(0)
      T_172275 := T_172294
    
    node T_172295 = neq(do_enq, do_deq)
    when T_172295 : maybe_full := do_enq
    node T_172296 = eq(empty, UInt<1>(0))
    node T_172297 = and(UInt<1>(0), enq.valid)
    node T_172298 = or(T_172296, T_172297)
    deq.valid := T_172298
    node T_172299 = eq(full, UInt<1>(0))
    node T_172300 = and(UInt<1>(0), deq.ready)
    node T_172301 = or(T_172299, T_172300)
    enq.ready := T_172301
    wire T_172302 : UInt<3>[3]
    T_172302[0] := UInt<3>(0)
    T_172302[1] := UInt<3>(1)
    T_172302[2] := UInt<3>(2)
    wire T_172303 : UInt<2>[2]
    T_172303[0] := UInt<2>(0)
    T_172303[1] := UInt<2>(1)
    wire T_172304 : UInt<2>[3]
    T_172304[0] := UInt<2>(1)
    T_172304[1] := UInt<2>(2)
    T_172304[2] := UInt<2>(3)
    wire T_172305 : UInt<2>[2]
    T_172305[0] := UInt<2>(2)
    T_172305[1] := UInt<2>(3)
    wire T_172306 : UInt<2>[1]
    T_172306[0] := UInt<2>(3)
    accessor T_172307 = ram[T_172275]
    wire T_172308 : UInt<3>[3]
    T_172308[0] := UInt<3>(0)
    T_172308[1] := UInt<3>(1)
    T_172308[2] := UInt<3>(2)
    wire T_172309 : UInt<2>[2]
    T_172309[0] := UInt<2>(0)
    T_172309[1] := UInt<2>(1)
    wire T_172310 : UInt<2>[3]
    T_172310[0] := UInt<2>(1)
    T_172310[1] := UInt<2>(2)
    T_172310[2] := UInt<2>(3)
    wire T_172311 : UInt<2>[2]
    T_172311[0] := UInt<2>(2)
    T_172311[1] := UInt<2>(3)
    wire T_172312 : UInt<2>[1]
    T_172312[0] := UInt<2>(3)
    wire T_172313 : {addr_beat : UInt<2>, client_xact_id : UInt<1>}
    T_172313 := T_172307
    when maybe_flow : T_172313 := enq.bits
    deq.bits := T_172313
    node ptr_diff = subw(T_172274, T_172275)
    node T_172314 = and(maybe_full, ptr_match)
    node T_172315 = cat(T_172314, ptr_diff)
    count := T_172315
  module AMOALU : 
    input addr : UInt<6>
    input cmd : UInt<5>
    input typ : UInt<3>
    input lhs : UInt<64>
    input rhs : UInt<64>
    output out : UInt<64>
    
    node T_172316 = eq(typ, UInt<3>(0))
    node T_172317 = eq(typ, UInt<3>(4))
    node T_172318 = or(T_172316, T_172317)
    node T_172319 = eq(typ, UInt<3>(1))
    node T_172320 = eq(typ, UInt<3>(5))
    node T_172321 = or(T_172319, T_172320)
    node T_172322 = eq(typ, UInt<3>(2))
    node T_172323 = eq(typ, UInt<3>(6))
    node T_172324 = or(T_172322, T_172323)
    node T_172325 = bits(rhs, 31, 0)
    node T_172326 = cat(T_172325, T_172325)
    wire rhs : UInt<64>
    rhs := rhs
    when T_172324 : rhs := T_172326
    node T_172327 = eq(cmd, UInt<5>(12))
    node T_172328 = eq(cmd, UInt<5>(13))
    node sgned = or(T_172327, T_172328)
    node T_172329 = eq(cmd, UInt<5>(13))
    node T_172330 = eq(cmd, UInt<5>(15))
    node max = or(T_172329, T_172330)
    node T_172331 = eq(cmd, UInt<5>(12))
    node T_172332 = eq(cmd, UInt<5>(14))
    node min = or(T_172331, T_172332)
    node T_172333 = eq(typ, UInt<3>(2))
    node T_172334 = eq(typ, UInt<3>(6))
    node T_172335 = or(T_172333, T_172334)
    node T_172336 = eq(typ, UInt<3>(0))
    node T_172337 = or(T_172335, T_172336)
    node T_172338 = eq(typ, UInt<3>(4))
    node word = or(T_172337, T_172338)
    node T_172339 = not(UInt<64>(0))
    node T_172340 = bit(addr, 2)
    node T_172341 = dshl(T_172340, UInt<5>(31))
    node mask = xor(T_172339, T_172341)
    node T_172342 = and(lhs, mask)
    node T_172343 = and(rhs, mask)
    node adder_out = addw(T_172342, T_172343)
    node T_172344 = bit(addr, 2)
    node T_172345 = eq(T_172344, UInt<1>(0))
    node T_172346 = and(word, T_172345)
    node T_172347 = bit(lhs, 31)
    node T_172348 = bit(lhs, 63)
    wire cmp_lhs : UInt<1>
    cmp_lhs := T_172348
    when T_172346 : cmp_lhs := T_172347
    node T_172349 = bit(addr, 2)
    node T_172350 = eq(T_172349, UInt<1>(0))
    node T_172351 = and(word, T_172350)
    node T_172352 = bit(rhs, 31)
    node T_172353 = bit(rhs, 63)
    wire cmp_rhs : UInt<1>
    cmp_rhs := T_172353
    when T_172351 : cmp_rhs := T_172352
    node T_172354 = bits(lhs, 31, 0)
    node T_172355 = bits(rhs, 31, 0)
    node lt_lo = lt(T_172354, T_172355)
    node T_172356 = bits(lhs, 63, 32)
    node T_172357 = bits(rhs, 63, 32)
    node lt_hi = lt(T_172356, T_172357)
    node T_172358 = bits(lhs, 63, 32)
    node T_172359 = bits(rhs, 63, 32)
    node eq_hi = eq(T_172358, T_172359)
    node T_172360 = bit(addr, 2)
    wire T_172361 : UInt<1>
    T_172361 := lt_lo
    when T_172360 : T_172361 := lt_hi
    node T_172362 = and(eq_hi, lt_lo)
    node T_172363 = or(lt_hi, T_172362)
    wire lt : UInt<1>
    lt := T_172363
    when word : lt := T_172361
    node T_172364 = eq(cmp_lhs, cmp_rhs)
    wire T_172365 : UInt<1>
    T_172365 := cmp_rhs
    when sgned : T_172365 := cmp_lhs
    wire less : UInt<1>
    less := T_172365
    when T_172364 : less := lt
    node T_172366 = eq(cmd, UInt<5>(8))
    node T_172367 = eq(cmd, UInt<5>(11))
    node T_172368 = and(lhs, rhs)
    node T_172369 = eq(cmd, UInt<5>(10))
    node T_172370 = or(lhs, rhs)
    node T_172371 = eq(cmd, UInt<5>(9))
    node T_172372 = xor(lhs, rhs)
    wire T_172373 : UInt<1>
    T_172373 := max
    when less : T_172373 := min
    node T_172374 = bits(rhs, 7, 0)
    node T_172375 = cat(T_172374, T_172374)
    node T_172376 = cat(T_172375, T_172375)
    node T_172377 = cat(T_172376, T_172376)
    node T_172378 = bits(rhs, 15, 0)
    node T_172379 = cat(T_172378, T_172378)
    node T_172380 = cat(T_172379, T_172379)
    wire T_172381 : UInt<64>
    T_172381 := rhs
    when T_172321 : T_172381 := T_172380
    wire T_172382 : UInt<64>
    T_172382 := T_172381
    when T_172318 : T_172382 := T_172377
    wire T_172383 : UInt<64>
    T_172383 := T_172382
    when T_172373 : T_172383 := lhs
    wire T_172384 : UInt<64>
    T_172384 := T_172383
    when T_172371 : T_172384 := T_172372
    wire T_172385 : UInt<64>
    T_172385 := T_172384
    when T_172369 : T_172385 := T_172370
    wire T_172386 : UInt<64>
    T_172386 := T_172385
    when T_172367 : T_172386 := T_172368
    wire out : UInt<64>
    out := T_172386
    when T_172366 : out := adder_out
    node T_172387 = bits(addr, 2, 0)
    node T_172388 = dshl(UInt<1>(1), T_172387)
    node T_172389 = bits(addr, 2, 1)
    node T_172390 = cat(T_172389, UInt<1>(0))
    node T_172391 = dshl(UInt<2>(3), T_172390)
    node T_172392 = bit(addr, 2)
    node T_172393 = cat(T_172392, UInt<2>(0))
    node T_172394 = dshl(UInt<4>(15), T_172393)
    wire T_172395 : UInt<8>
    T_172395 := UInt<8>(255)
    when T_172324 : T_172395 := T_172394
    wire T_172396 : UInt<8>
    T_172396 := T_172395
    when T_172321 : T_172396 := T_172391
    wire T_172397 : UInt<8>
    T_172397 := T_172396
    when T_172318 : T_172397 := T_172388
    node T_172398 = bit(T_172397, 0)
    node T_172399 = bit(T_172397, 1)
    node T_172400 = bit(T_172397, 2)
    node T_172401 = bit(T_172397, 3)
    node T_172402 = bit(T_172397, 4)
    node T_172403 = bit(T_172397, 5)
    node T_172404 = bit(T_172397, 6)
    node T_172405 = bit(T_172397, 7)
    wire T_172406 : UInt<1>[8]
    T_172406[0] := T_172398
    T_172406[1] := T_172399
    T_172406[2] := T_172400
    T_172406[3] := T_172401
    T_172406[4] := T_172402
    T_172406[5] := T_172403
    T_172406[6] := T_172404
    T_172406[7] := T_172405
    node T_172407 = subw(UInt<8>(0), UInt<4>(8))
    node T_172408 = subw(UInt<8>(0), UInt<4>(8))
    node T_172409 = subw(UInt<8>(0), UInt<4>(8))
    node T_172410 = subw(UInt<8>(0), UInt<4>(8))
    node T_172411 = subw(UInt<8>(0), UInt<4>(8))
    node T_172412 = subw(UInt<8>(0), UInt<4>(8))
    node T_172413 = subw(UInt<8>(0), UInt<4>(8))
    node T_172414 = subw(UInt<8>(0), UInt<4>(8))
    wire T_172415 : UInt<8>[8]
    T_172415[0] := T_172407
    T_172415[1] := T_172408
    T_172415[2] := T_172409
    T_172415[3] := T_172410
    T_172415[4] := T_172411
    T_172415[5] := T_172412
    T_172415[6] := T_172413
    T_172415[7] := T_172414
    node T_172416 = cat(T_172415[7], T_172415[6])
    node T_172417 = cat(T_172415[5], T_172415[4])
    node T_172418 = cat(T_172416, T_172417)
    node T_172419 = cat(T_172415[3], T_172415[2])
    node T_172420 = cat(T_172415[1], T_172415[0])
    node T_172421 = cat(T_172419, T_172420)
    node wmask = cat(T_172418, T_172421)
    node T_172422 = and(wmask, out)
    node T_172423 = not(wmask)
    node T_172424 = and(T_172423, lhs)
    node T_172425 = or(T_172422, T_172424)
    out := T_172425
  module L2AcquireTracker : 
    output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input incoherent : UInt<1>[1]
    output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output has_acquire_conflict : UInt<1>
    output has_acquire_match : UInt<1>
    output has_release_match : UInt<1>
    output data : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}}
    output meta : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, tag_match : UInt<1>, meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, way_en : UInt<8>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}}
    output wb : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>}}}
    
    wire T_172426 : UInt<3>[3]
    T_172426[0] := UInt<3>(0)
    T_172426[1] := UInt<3>(1)
    T_172426[2] := UInt<3>(2)
    wire T_172427 : UInt<2>[2]
    T_172427[0] := UInt<2>(0)
    T_172427[1] := UInt<2>(1)
    wire T_172428 : UInt<2>[3]
    T_172428[0] := UInt<2>(1)
    T_172428[1] := UInt<2>(2)
    T_172428[2] := UInt<2>(3)
    wire T_172429 : UInt<2>[2]
    T_172429[0] := UInt<2>(2)
    T_172429[1] := UInt<2>(3)
    wire T_172430 : UInt<2>[1]
    T_172430[0] := UInt<2>(3)
    wire T_172431 : UInt<3>[3]
    T_172431[0] := UInt<3>(0)
    T_172431[1] := UInt<3>(1)
    T_172431[2] := UInt<3>(2)
    wire T_172432 : UInt<2>[2]
    T_172432[0] := UInt<2>(0)
    T_172432[1] := UInt<2>(1)
    wire T_172433 : UInt<2>[3]
    T_172433[0] := UInt<2>(1)
    T_172433[1] := UInt<2>(2)
    T_172433[2] := UInt<2>(3)
    wire T_172434 : UInt<2>[2]
    T_172434[0] := UInt<2>(2)
    T_172434[1] := UInt<2>(3)
    wire T_172435 : UInt<2>[1]
    T_172435[0] := UInt<2>(3)
    wire T_172436 : UInt<3>[3]
    T_172436[0] := UInt<3>(0)
    T_172436[1] := UInt<3>(1)
    T_172436[2] := UInt<3>(2)
    wire T_172437 : UInt<2>[2]
    T_172437[0] := UInt<2>(0)
    T_172437[1] := UInt<2>(1)
    wire T_172438 : UInt<2>[3]
    T_172438[0] := UInt<2>(1)
    T_172438[1] := UInt<2>(2)
    T_172438[2] := UInt<2>(3)
    wire T_172439 : UInt<2>[2]
    T_172439[0] := UInt<2>(2)
    T_172439[1] := UInt<2>(3)
    wire T_172440 : UInt<2>[1]
    T_172440[0] := UInt<2>(3)
    wire T_172441 : UInt<3>[3]
    T_172441[0] := UInt<3>(0)
    T_172441[1] := UInt<3>(1)
    T_172441[2] := UInt<3>(2)
    wire T_172442 : UInt<2>[2]
    T_172442[0] := UInt<2>(0)
    T_172442[1] := UInt<2>(1)
    wire T_172443 : UInt<2>[3]
    T_172443[0] := UInt<2>(1)
    T_172443[1] := UInt<2>(2)
    T_172443[2] := UInt<2>(3)
    wire T_172444 : UInt<2>[2]
    T_172444[0] := UInt<2>(2)
    T_172444[1] := UInt<2>(3)
    wire T_172445 : UInt<2>[1]
    T_172445[0] := UInt<2>(3)
    wire T_172446 : UInt<3>[3]
    T_172446[0] := UInt<3>(0)
    T_172446[1] := UInt<3>(1)
    T_172446[2] := UInt<3>(2)
    wire T_172447 : UInt<2>[2]
    T_172447[0] := UInt<2>(0)
    T_172447[1] := UInt<2>(1)
    wire T_172448 : UInt<2>[3]
    T_172448[0] := UInt<2>(1)
    T_172448[1] := UInt<2>(2)
    T_172448[2] := UInt<2>(3)
    wire T_172449 : UInt<2>[2]
    T_172449[0] := UInt<2>(2)
    T_172449[1] := UInt<2>(3)
    wire T_172450 : UInt<2>[1]
    T_172450[0] := UInt<2>(3)
    wire T_172451 : UInt<3>[3]
    T_172451[0] := UInt<3>(0)
    T_172451[1] := UInt<3>(1)
    T_172451[2] := UInt<3>(2)
    wire T_172452 : UInt<2>[2]
    T_172452[0] := UInt<2>(0)
    T_172452[1] := UInt<2>(1)
    wire T_172453 : UInt<2>[3]
    T_172453[0] := UInt<2>(1)
    T_172453[1] := UInt<2>(2)
    T_172453[2] := UInt<2>(3)
    wire T_172454 : UInt<2>[2]
    T_172454[0] := UInt<2>(2)
    T_172454[1] := UInt<2>(3)
    wire T_172455 : UInt<2>[1]
    T_172455[0] := UInt<2>(3)
    wire T_172456 : UInt<3>[3]
    T_172456[0] := UInt<3>(0)
    T_172456[1] := UInt<3>(1)
    T_172456[2] := UInt<3>(2)
    wire T_172457 : UInt<2>[2]
    T_172457[0] := UInt<2>(0)
    T_172457[1] := UInt<2>(1)
    wire T_172458 : UInt<2>[3]
    T_172458[0] := UInt<2>(1)
    T_172458[1] := UInt<2>(2)
    T_172458[2] := UInt<2>(3)
    wire T_172459 : UInt<2>[2]
    T_172459[0] := UInt<2>(2)
    T_172459[1] := UInt<2>(3)
    wire T_172460 : UInt<2>[1]
    T_172460[0] := UInt<2>(3)
    wire T_172461 : UInt<3>[3]
    T_172461[0] := UInt<3>(0)
    T_172461[1] := UInt<3>(1)
    T_172461[2] := UInt<3>(2)
    wire T_172462 : UInt<2>[2]
    T_172462[0] := UInt<2>(0)
    T_172462[1] := UInt<2>(1)
    wire T_172463 : UInt<2>[3]
    T_172463[0] := UInt<2>(1)
    T_172463[1] := UInt<2>(2)
    T_172463[2] := UInt<2>(3)
    wire T_172464 : UInt<2>[2]
    T_172464[0] := UInt<2>(2)
    T_172464[1] := UInt<2>(3)
    wire T_172465 : UInt<2>[1]
    T_172465[0] := UInt<2>(3)
    wire T_172466 : UInt<3>[3]
    T_172466[0] := UInt<3>(0)
    T_172466[1] := UInt<3>(1)
    T_172466[2] := UInt<3>(2)
    wire T_172467 : UInt<2>[2]
    T_172467[0] := UInt<2>(0)
    T_172467[1] := UInt<2>(1)
    wire T_172468 : UInt<2>[3]
    T_172468[0] := UInt<2>(1)
    T_172468[1] := UInt<2>(2)
    T_172468[2] := UInt<2>(3)
    wire T_172469 : UInt<2>[2]
    T_172469[0] := UInt<2>(2)
    T_172469[1] := UInt<2>(3)
    wire T_172470 : UInt<2>[1]
    T_172470[0] := UInt<2>(3)
    wire T_172471 : UInt<3>[3]
    T_172471[0] := UInt<3>(0)
    T_172471[1] := UInt<3>(1)
    T_172471[2] := UInt<3>(2)
    wire T_172472 : UInt<2>[2]
    T_172472[0] := UInt<2>(0)
    T_172472[1] := UInt<2>(1)
    wire T_172473 : UInt<2>[3]
    T_172473[0] := UInt<2>(1)
    T_172473[1] := UInt<2>(2)
    T_172473[2] := UInt<2>(3)
    wire T_172474 : UInt<2>[2]
    T_172474[0] := UInt<2>(2)
    T_172474[1] := UInt<2>(3)
    wire T_172475 : UInt<2>[1]
    T_172475[0] := UInt<2>(3)
    wire T_172476 : UInt<3>[3]
    T_172476[0] := UInt<3>(0)
    T_172476[1] := UInt<3>(1)
    T_172476[2] := UInt<3>(2)
    wire T_172477 : UInt<2>[2]
    T_172477[0] := UInt<2>(0)
    T_172477[1] := UInt<2>(1)
    wire T_172478 : UInt<2>[3]
    T_172478[0] := UInt<2>(1)
    T_172478[1] := UInt<2>(2)
    T_172478[2] := UInt<2>(3)
    wire T_172479 : UInt<2>[2]
    T_172479[0] := UInt<2>(2)
    T_172479[1] := UInt<2>(3)
    wire T_172480 : UInt<2>[1]
    T_172480[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_172481
    wire T_172482 : UInt<3>[3]
    T_172482[0] := UInt<3>(0)
    T_172482[1] := UInt<3>(1)
    T_172482[2] := UInt<3>(2)
    wire T_172483 : UInt<0>[1]
    T_172483[0] := UInt<0>(0)
    wire T_172484 : UInt<2>[2]
    T_172484[0] := UInt<2>(1)
    T_172484[1] := UInt<2>(2)
    wire T_172485 : UInt<2>[2]
    T_172485[0] := UInt<2>(1)
    T_172485[1] := UInt<2>(2)
    wire T_172486 : UInt<2>[1]
    T_172486[0] := UInt<2>(2)
    wire T_172487 : UInt<3>[3]
    T_172487[0] := UInt<3>(0)
    T_172487[1] := UInt<3>(1)
    T_172487[2] := UInt<3>(2)
    wire T_172488 : UInt<0>[1]
    T_172488[0] := UInt<0>(0)
    wire T_172489 : UInt<2>[2]
    T_172489[0] := UInt<2>(1)
    T_172489[1] := UInt<2>(2)
    wire T_172490 : UInt<2>[2]
    T_172490[0] := UInt<2>(1)
    T_172490[1] := UInt<2>(2)
    wire T_172491 : UInt<2>[1]
    T_172491[0] := UInt<2>(2)
    wire T_172492 : UInt<3>[3]
    T_172492[0] := UInt<3>(0)
    T_172492[1] := UInt<3>(1)
    T_172492[2] := UInt<3>(2)
    wire T_172493 : UInt<0>[1]
    T_172493[0] := UInt<0>(0)
    wire T_172494 : UInt<2>[2]
    T_172494[0] := UInt<2>(1)
    T_172494[1] := UInt<2>(2)
    wire T_172495 : UInt<2>[2]
    T_172495[0] := UInt<2>(1)
    T_172495[1] := UInt<2>(2)
    wire T_172496 : UInt<2>[1]
    T_172496[0] := UInt<2>(2)
    wire T_172497 : UInt<3>[3]
    T_172497[0] := UInt<3>(0)
    T_172497[1] := UInt<3>(1)
    T_172497[2] := UInt<3>(2)
    wire T_172498 : UInt<0>[1]
    T_172498[0] := UInt<0>(0)
    wire T_172499 : UInt<2>[2]
    T_172499[0] := UInt<2>(1)
    T_172499[1] := UInt<2>(2)
    wire T_172500 : UInt<2>[2]
    T_172500[0] := UInt<2>(1)
    T_172500[1] := UInt<2>(2)
    wire T_172501 : UInt<2>[1]
    T_172501[0] := UInt<2>(2)
    wire T_172502 : UInt<3>[3]
    T_172502[0] := UInt<3>(0)
    T_172502[1] := UInt<3>(1)
    T_172502[2] := UInt<3>(2)
    wire T_172503 : UInt<0>[1]
    T_172503[0] := UInt<0>(0)
    wire T_172504 : UInt<2>[2]
    T_172504[0] := UInt<2>(1)
    T_172504[1] := UInt<2>(2)
    wire T_172505 : UInt<2>[2]
    T_172505[0] := UInt<2>(1)
    T_172505[1] := UInt<2>(2)
    wire T_172506 : UInt<2>[1]
    T_172506[0] := UInt<2>(2)
    wire T_172507 : UInt<3>[3]
    T_172507[0] := UInt<3>(0)
    T_172507[1] := UInt<3>(1)
    T_172507[2] := UInt<3>(2)
    wire T_172508 : UInt<0>[1]
    T_172508[0] := UInt<0>(0)
    wire T_172509 : UInt<2>[2]
    T_172509[0] := UInt<2>(1)
    T_172509[1] := UInt<2>(2)
    wire T_172510 : UInt<2>[2]
    T_172510[0] := UInt<2>(1)
    T_172510[1] := UInt<2>(2)
    wire T_172511 : UInt<2>[1]
    T_172511[0] := UInt<2>(2)
    wire T_172512 : UInt<3>[3]
    T_172512[0] := UInt<3>(0)
    T_172512[1] := UInt<3>(1)
    T_172512[2] := UInt<3>(2)
    wire T_172513 : UInt<0>[1]
    T_172513[0] := UInt<0>(0)
    wire T_172514 : UInt<2>[2]
    T_172514[0] := UInt<2>(1)
    T_172514[1] := UInt<2>(2)
    wire T_172515 : UInt<2>[2]
    T_172515[0] := UInt<2>(1)
    T_172515[1] := UInt<2>(2)
    wire T_172516 : UInt<2>[1]
    T_172516[0] := UInt<2>(2)
    wire T_172517 : UInt<3>[3]
    T_172517[0] := UInt<3>(0)
    T_172517[1] := UInt<3>(1)
    T_172517[2] := UInt<3>(2)
    wire T_172518 : UInt<0>[1]
    T_172518[0] := UInt<0>(0)
    wire T_172519 : UInt<2>[2]
    T_172519[0] := UInt<2>(1)
    T_172519[1] := UInt<2>(2)
    wire T_172520 : UInt<2>[2]
    T_172520[0] := UInt<2>(1)
    T_172520[1] := UInt<2>(2)
    wire T_172521 : UInt<2>[1]
    T_172521[0] := UInt<2>(2)
    wire T_172522 : UInt<3>[3]
    T_172522[0] := UInt<3>(0)
    T_172522[1] := UInt<3>(1)
    T_172522[2] := UInt<3>(2)
    wire T_172523 : UInt<0>[1]
    T_172523[0] := UInt<0>(0)
    wire T_172524 : UInt<2>[2]
    T_172524[0] := UInt<2>(1)
    T_172524[1] := UInt<2>(2)
    wire T_172525 : UInt<2>[2]
    T_172525[0] := UInt<2>(1)
    T_172525[1] := UInt<2>(2)
    wire T_172526 : UInt<2>[1]
    T_172526[0] := UInt<2>(2)
    wire T_172527 : UInt<3>[3]
    T_172527[0] := UInt<3>(0)
    T_172527[1] := UInt<3>(1)
    T_172527[2] := UInt<3>(2)
    wire T_172528 : UInt<2>[2]
    T_172528[0] := UInt<2>(0)
    T_172528[1] := UInt<2>(1)
    wire T_172529 : UInt<2>[3]
    T_172529[0] := UInt<2>(1)
    T_172529[1] := UInt<2>(2)
    T_172529[2] := UInt<2>(3)
    wire T_172530 : UInt<2>[2]
    T_172530[0] := UInt<2>(2)
    T_172530[1] := UInt<2>(3)
    wire T_172531 : UInt<2>[1]
    T_172531[0] := UInt<2>(3)
    wire T_172532 : UInt<3>[3]
    T_172532[0] := UInt<3>(0)
    T_172532[1] := UInt<3>(1)
    T_172532[2] := UInt<3>(2)
    wire T_172533 : UInt<2>[2]
    T_172533[0] := UInt<2>(0)
    T_172533[1] := UInt<2>(1)
    wire T_172534 : UInt<2>[3]
    T_172534[0] := UInt<2>(1)
    T_172534[1] := UInt<2>(2)
    T_172534[2] := UInt<2>(3)
    wire T_172535 : UInt<2>[2]
    T_172535[0] := UInt<2>(2)
    T_172535[1] := UInt<2>(3)
    wire T_172536 : UInt<2>[1]
    T_172536[0] := UInt<2>(3)
    wire T_172537 : UInt<3>[3]
    T_172537[0] := UInt<3>(0)
    T_172537[1] := UInt<3>(1)
    T_172537[2] := UInt<3>(2)
    wire T_172538 : UInt<0>[1]
    T_172538[0] := UInt<0>(0)
    wire T_172539 : UInt<2>[2]
    T_172539[0] := UInt<2>(1)
    T_172539[1] := UInt<2>(2)
    wire T_172540 : UInt<2>[2]
    T_172540[0] := UInt<2>(1)
    T_172540[1] := UInt<2>(2)
    wire T_172541 : UInt<2>[1]
    T_172541[0] := UInt<2>(2)
    wire T_172542 : UInt<3>[3]
    T_172542[0] := UInt<3>(0)
    T_172542[1] := UInt<3>(1)
    T_172542[2] := UInt<3>(2)
    wire T_172543 : UInt<2>[2]
    T_172543[0] := UInt<2>(0)
    T_172543[1] := UInt<2>(1)
    wire T_172544 : UInt<2>[3]
    T_172544[0] := UInt<2>(1)
    T_172544[1] := UInt<2>(2)
    T_172544[2] := UInt<2>(3)
    wire T_172545 : UInt<2>[2]
    T_172545[0] := UInt<2>(2)
    T_172545[1] := UInt<2>(3)
    wire T_172546 : UInt<2>[1]
    T_172546[0] := UInt<2>(3)
    wire T_172547 : UInt<3>[3]
    T_172547[0] := UInt<3>(0)
    T_172547[1] := UInt<3>(1)
    T_172547[2] := UInt<3>(2)
    wire T_172548 : UInt<2>[2]
    T_172548[0] := UInt<2>(0)
    T_172548[1] := UInt<2>(1)
    wire T_172549 : UInt<2>[3]
    T_172549[0] := UInt<2>(1)
    T_172549[1] := UInt<2>(2)
    T_172549[2] := UInt<2>(3)
    wire T_172550 : UInt<2>[2]
    T_172550[0] := UInt<2>(2)
    T_172550[1] := UInt<2>(3)
    wire T_172551 : UInt<2>[1]
    T_172551[0] := UInt<2>(3)
    wire T_172552 : UInt<3>[3]
    T_172552[0] := UInt<3>(0)
    T_172552[1] := UInt<3>(1)
    T_172552[2] := UInt<3>(2)
    wire T_172553 : UInt<0>[1]
    T_172553[0] := UInt<0>(0)
    wire T_172554 : UInt<2>[2]
    T_172554[0] := UInt<2>(1)
    T_172554[1] := UInt<2>(2)
    wire T_172555 : UInt<2>[2]
    T_172555[0] := UInt<2>(1)
    T_172555[1] := UInt<2>(2)
    wire T_172556 : UInt<2>[1]
    T_172556[0] := UInt<2>(2)
    wire T_172557 : UInt<3>[3]
    T_172557[0] := UInt<3>(0)
    T_172557[1] := UInt<3>(1)
    T_172557[2] := UInt<3>(2)
    wire T_172558 : UInt<2>[2]
    T_172558[0] := UInt<2>(0)
    T_172558[1] := UInt<2>(1)
    wire T_172559 : UInt<2>[3]
    T_172559[0] := UInt<2>(1)
    T_172559[1] := UInt<2>(2)
    T_172559[2] := UInt<2>(3)
    wire T_172560 : UInt<2>[2]
    T_172560[0] := UInt<2>(2)
    T_172560[1] := UInt<2>(3)
    wire T_172561 : UInt<2>[1]
    T_172561[0] := UInt<2>(3)
    wire T_172562 : UInt<3>[3]
    T_172562[0] := UInt<3>(0)
    T_172562[1] := UInt<3>(1)
    T_172562[2] := UInt<3>(2)
    wire T_172563 : UInt<2>[2]
    T_172563[0] := UInt<2>(0)
    T_172563[1] := UInt<2>(1)
    wire T_172564 : UInt<2>[3]
    T_172564[0] := UInt<2>(1)
    T_172564[1] := UInt<2>(2)
    T_172564[2] := UInt<2>(3)
    wire T_172565 : UInt<2>[2]
    T_172565[0] := UInt<2>(2)
    T_172565[1] := UInt<2>(3)
    wire T_172566 : UInt<2>[1]
    T_172566[0] := UInt<2>(3)
    wire T_172567 : UInt<3>[3]
    T_172567[0] := UInt<3>(0)
    T_172567[1] := UInt<3>(1)
    T_172567[2] := UInt<3>(2)
    wire T_172568 : UInt<0>[1]
    T_172568[0] := UInt<0>(0)
    wire T_172569 : UInt<2>[2]
    T_172569[0] := UInt<2>(1)
    T_172569[1] := UInt<2>(2)
    wire T_172570 : UInt<2>[2]
    T_172570[0] := UInt<2>(1)
    T_172570[1] := UInt<2>(2)
    wire T_172571 : UInt<2>[1]
    T_172571[0] := UInt<2>(2)
    wire T_172572 : UInt<3>[3]
    T_172572[0] := UInt<3>(0)
    T_172572[1] := UInt<3>(1)
    T_172572[2] := UInt<3>(2)
    wire T_172573 : UInt<2>[2]
    T_172573[0] := UInt<2>(0)
    T_172573[1] := UInt<2>(1)
    wire T_172574 : UInt<2>[3]
    T_172574[0] := UInt<2>(1)
    T_172574[1] := UInt<2>(2)
    T_172574[2] := UInt<2>(3)
    wire T_172575 : UInt<2>[2]
    T_172575[0] := UInt<2>(2)
    T_172575[1] := UInt<2>(3)
    wire T_172576 : UInt<2>[1]
    T_172576[0] := UInt<2>(3)
    wire T_172577 : UInt<3>[3]
    T_172577[0] := UInt<3>(0)
    T_172577[1] := UInt<3>(1)
    T_172577[2] := UInt<3>(2)
    wire T_172578 : UInt<2>[2]
    T_172578[0] := UInt<2>(0)
    T_172578[1] := UInt<2>(1)
    wire T_172579 : UInt<2>[3]
    T_172579[0] := UInt<2>(1)
    T_172579[1] := UInt<2>(2)
    T_172579[2] := UInt<2>(3)
    wire T_172580 : UInt<2>[2]
    T_172580[0] := UInt<2>(2)
    T_172580[1] := UInt<2>(3)
    wire T_172581 : UInt<2>[1]
    T_172581[0] := UInt<2>(3)
    wire T_172582 : UInt<3>[3]
    T_172582[0] := UInt<3>(0)
    T_172582[1] := UInt<3>(1)
    T_172582[2] := UInt<3>(2)
    wire T_172583 : UInt<0>[1]
    T_172583[0] := UInt<0>(0)
    wire T_172584 : UInt<2>[2]
    T_172584[0] := UInt<2>(1)
    T_172584[1] := UInt<2>(2)
    wire T_172585 : UInt<2>[2]
    T_172585[0] := UInt<2>(1)
    T_172585[1] := UInt<2>(2)
    wire T_172586 : UInt<2>[1]
    T_172586[0] := UInt<2>(2)
    wire T_172587 : UInt<3>[3]
    T_172587[0] := UInt<3>(0)
    T_172587[1] := UInt<3>(1)
    T_172587[2] := UInt<3>(2)
    wire T_172588 : UInt<2>[2]
    T_172588[0] := UInt<2>(0)
    T_172588[1] := UInt<2>(1)
    wire T_172589 : UInt<2>[3]
    T_172589[0] := UInt<2>(1)
    T_172589[1] := UInt<2>(2)
    T_172589[2] := UInt<2>(3)
    wire T_172590 : UInt<2>[2]
    T_172590[0] := UInt<2>(2)
    T_172590[1] := UInt<2>(3)
    wire T_172591 : UInt<2>[1]
    T_172591[0] := UInt<2>(3)
    wire T_172592 : UInt<3>[3]
    T_172592[0] := UInt<3>(0)
    T_172592[1] := UInt<3>(1)
    T_172592[2] := UInt<3>(2)
    wire T_172593 : UInt<2>[2]
    T_172593[0] := UInt<2>(0)
    T_172593[1] := UInt<2>(1)
    wire T_172594 : UInt<2>[3]
    T_172594[0] := UInt<2>(1)
    T_172594[1] := UInt<2>(2)
    T_172594[2] := UInt<2>(3)
    wire T_172595 : UInt<2>[2]
    T_172595[0] := UInt<2>(2)
    T_172595[1] := UInt<2>(3)
    wire T_172596 : UInt<2>[1]
    T_172596[0] := UInt<2>(3)
    wire T_172597 : UInt<3>[3]
    T_172597[0] := UInt<3>(0)
    T_172597[1] := UInt<3>(1)
    T_172597[2] := UInt<3>(2)
    wire T_172598 : UInt<0>[1]
    T_172598[0] := UInt<0>(0)
    wire T_172599 : UInt<2>[2]
    T_172599[0] := UInt<2>(1)
    T_172599[1] := UInt<2>(2)
    wire T_172600 : UInt<2>[2]
    T_172600[0] := UInt<2>(1)
    T_172600[1] := UInt<2>(2)
    wire T_172601 : UInt<2>[1]
    T_172601[0] := UInt<2>(2)
    wire T_172602 : UInt<3>[3]
    T_172602[0] := UInt<3>(0)
    T_172602[1] := UInt<3>(1)
    T_172602[2] := UInt<3>(2)
    wire T_172603 : UInt<2>[2]
    T_172603[0] := UInt<2>(0)
    T_172603[1] := UInt<2>(1)
    wire T_172604 : UInt<2>[3]
    T_172604[0] := UInt<2>(1)
    T_172604[1] := UInt<2>(2)
    T_172604[2] := UInt<2>(3)
    wire T_172605 : UInt<2>[2]
    T_172605[0] := UInt<2>(2)
    T_172605[1] := UInt<2>(3)
    wire T_172606 : UInt<2>[1]
    T_172606[0] := UInt<2>(3)
    wire T_172607 : UInt<3>[3]
    T_172607[0] := UInt<3>(0)
    T_172607[1] := UInt<3>(1)
    T_172607[2] := UInt<3>(2)
    wire T_172608 : UInt<2>[2]
    T_172608[0] := UInt<2>(0)
    T_172608[1] := UInt<2>(1)
    wire T_172609 : UInt<2>[3]
    T_172609[0] := UInt<2>(1)
    T_172609[1] := UInt<2>(2)
    T_172609[2] := UInt<2>(3)
    wire T_172610 : UInt<2>[2]
    T_172610[0] := UInt<2>(2)
    T_172610[1] := UInt<2>(3)
    wire T_172611 : UInt<2>[1]
    T_172611[0] := UInt<2>(3)
    wire T_172612 : UInt<3>[3]
    T_172612[0] := UInt<3>(0)
    T_172612[1] := UInt<3>(1)
    T_172612[2] := UInt<3>(2)
    wire T_172613 : UInt<0>[1]
    T_172613[0] := UInt<0>(0)
    wire T_172614 : UInt<2>[2]
    T_172614[0] := UInt<2>(1)
    T_172614[1] := UInt<2>(2)
    wire T_172615 : UInt<2>[2]
    T_172615[0] := UInt<2>(1)
    T_172615[1] := UInt<2>(2)
    wire T_172616 : UInt<2>[1]
    T_172616[0] := UInt<2>(2)
    wire T_172617 : UInt<3>[3]
    T_172617[0] := UInt<3>(0)
    T_172617[1] := UInt<3>(1)
    T_172617[2] := UInt<3>(2)
    wire T_172618 : UInt<2>[2]
    T_172618[0] := UInt<2>(0)
    T_172618[1] := UInt<2>(1)
    wire T_172619 : UInt<2>[3]
    T_172619[0] := UInt<2>(1)
    T_172619[1] := UInt<2>(2)
    T_172619[2] := UInt<2>(3)
    wire T_172620 : UInt<2>[2]
    T_172620[0] := UInt<2>(2)
    T_172620[1] := UInt<2>(3)
    wire T_172621 : UInt<2>[1]
    T_172621[0] := UInt<2>(3)
    wire T_172622 : UInt<3>[3]
    T_172622[0] := UInt<3>(0)
    T_172622[1] := UInt<3>(1)
    T_172622[2] := UInt<3>(2)
    wire T_172623 : UInt<2>[2]
    T_172623[0] := UInt<2>(0)
    T_172623[1] := UInt<2>(1)
    wire T_172624 : UInt<2>[3]
    T_172624[0] := UInt<2>(1)
    T_172624[1] := UInt<2>(2)
    T_172624[2] := UInt<2>(3)
    wire T_172625 : UInt<2>[2]
    T_172625[0] := UInt<2>(2)
    T_172625[1] := UInt<2>(3)
    wire T_172626 : UInt<2>[1]
    T_172626[0] := UInt<2>(3)
    wire T_172627 : UInt<3>[3]
    T_172627[0] := UInt<3>(0)
    T_172627[1] := UInt<3>(1)
    T_172627[2] := UInt<3>(2)
    wire T_172628 : UInt<0>[1]
    T_172628[0] := UInt<0>(0)
    wire T_172629 : UInt<2>[2]
    T_172629[0] := UInt<2>(1)
    T_172629[1] := UInt<2>(2)
    wire T_172630 : UInt<2>[2]
    T_172630[0] := UInt<2>(1)
    T_172630[1] := UInt<2>(2)
    wire T_172631 : UInt<2>[1]
    T_172631[0] := UInt<2>(2)
    wire T_172632 : UInt<3>[3]
    T_172632[0] := UInt<3>(0)
    T_172632[1] := UInt<3>(1)
    T_172632[2] := UInt<3>(2)
    wire T_172633 : UInt<2>[2]
    T_172633[0] := UInt<2>(0)
    T_172633[1] := UInt<2>(1)
    wire T_172634 : UInt<2>[3]
    T_172634[0] := UInt<2>(1)
    T_172634[1] := UInt<2>(2)
    T_172634[2] := UInt<2>(3)
    wire T_172635 : UInt<2>[2]
    T_172635[0] := UInt<2>(2)
    T_172635[1] := UInt<2>(3)
    wire T_172636 : UInt<2>[1]
    T_172636[0] := UInt<2>(3)
    wire T_172637 : UInt<3>[3]
    T_172637[0] := UInt<3>(0)
    T_172637[1] := UInt<3>(1)
    T_172637[2] := UInt<3>(2)
    wire T_172638 : UInt<2>[2]
    T_172638[0] := UInt<2>(0)
    T_172638[1] := UInt<2>(1)
    wire T_172639 : UInt<2>[3]
    T_172639[0] := UInt<2>(1)
    T_172639[1] := UInt<2>(2)
    T_172639[2] := UInt<2>(3)
    wire T_172640 : UInt<2>[2]
    T_172640[0] := UInt<2>(2)
    T_172640[1] := UInt<2>(3)
    wire T_172641 : UInt<2>[1]
    T_172641[0] := UInt<2>(3)
    wire T_172642 : UInt<3>[3]
    T_172642[0] := UInt<3>(0)
    T_172642[1] := UInt<3>(1)
    T_172642[2] := UInt<3>(2)
    wire T_172643 : UInt<0>[1]
    T_172643[0] := UInt<0>(0)
    wire T_172644 : UInt<2>[2]
    T_172644[0] := UInt<2>(1)
    T_172644[1] := UInt<2>(2)
    wire T_172645 : UInt<2>[2]
    T_172645[0] := UInt<2>(1)
    T_172645[1] := UInt<2>(2)
    wire T_172646 : UInt<2>[1]
    T_172646[0] := UInt<2>(2)
    wb.resp.valid := UInt<1>(0)
    wb.req.valid := UInt<1>(0)
    meta.write.valid := UInt<1>(0)
    meta.resp.valid := UInt<1>(0)
    meta.read.valid := UInt<1>(0)
    data.write.valid := UInt<1>(0)
    data.resp.valid := UInt<1>(0)
    data.read.valid := UInt<1>(0)
    outer.release.valid := UInt<1>(0)
    outer.probe.valid := UInt<1>(0)
    outer.grant.valid := UInt<1>(0)
    outer.acquire.valid := UInt<1>(0)
    inner.release.valid := UInt<1>(0)
    inner.probe.valid := UInt<1>(0)
    inner.finish.valid := UInt<1>(0)
    inner.grant.valid := UInt<1>(0)
    inner.acquire.valid := UInt<1>(0)
    reg state : UInt<4>
    onreset state := UInt<4>(0)
    wire T_172647 : UInt<3>[3]
    T_172647[0] := UInt<3>(0)
    T_172647[1] := UInt<3>(1)
    T_172647[2] := UInt<3>(2)
    wire T_172648 : UInt<2>[2]
    T_172648[0] := UInt<2>(0)
    T_172648[1] := UInt<2>(1)
    wire T_172649 : UInt<2>[3]
    T_172649[0] := UInt<2>(1)
    T_172649[1] := UInt<2>(2)
    T_172649[2] := UInt<2>(3)
    wire T_172650 : UInt<2>[2]
    T_172650[0] := UInt<2>(2)
    T_172650[1] := UInt<2>(3)
    wire T_172651 : UInt<2>[1]
    T_172651[0] := UInt<2>(3)
    wire T_172652 : UInt<3>[3]
    T_172652[0] := UInt<3>(0)
    T_172652[1] := UInt<3>(1)
    T_172652[2] := UInt<3>(2)
    wire T_172653 : UInt<2>[2]
    T_172653[0] := UInt<2>(0)
    T_172653[1] := UInt<2>(1)
    wire T_172654 : UInt<2>[3]
    T_172654[0] := UInt<2>(1)
    T_172654[1] := UInt<2>(2)
    T_172654[2] := UInt<2>(3)
    wire T_172655 : UInt<2>[2]
    T_172655[0] := UInt<2>(2)
    T_172655[1] := UInt<2>(3)
    wire T_172656 : UInt<2>[1]
    T_172656[0] := UInt<2>(3)
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}
    wire T_172657 : UInt<128>[4]
    T_172657[0] := UInt<128>(0)
    T_172657[1] := UInt<128>(0)
    T_172657[2] := UInt<128>(0)
    T_172657[3] := UInt<128>(0)
    reg data_buffer : UInt<128>[4]
    onreset data_buffer := T_172657
    wire T_172658 : UInt<16>[4]
    T_172658[0] := UInt<16>(0)
    T_172658[1] := UInt<16>(0)
    T_172658[2] := UInt<16>(0)
    T_172658[3] := UInt<16>(0)
    reg wmask_buffer : UInt<16>[4]
    onreset wmask_buffer := T_172658
    reg xact_tag_match : UInt<1>
    reg xact_way_en : UInt<8>
    wire T_172659 : UInt<3>[3]
    T_172659[0] := UInt<3>(0)
    T_172659[1] := UInt<3>(1)
    T_172659[2] := UInt<3>(2)
    wire T_172660 : UInt<2>[2]
    T_172660[0] := UInt<2>(0)
    T_172660[1] := UInt<2>(1)
    wire T_172661 : UInt<2>[3]
    T_172661[0] := UInt<2>(1)
    T_172661[1] := UInt<2>(2)
    T_172661[2] := UInt<2>(3)
    wire T_172662 : UInt<2>[2]
    T_172662[0] := UInt<2>(2)
    T_172662[1] := UInt<2>(3)
    wire T_172663 : UInt<2>[1]
    T_172663[0] := UInt<2>(3)
    wire T_172664 : UInt<3>[3]
    T_172664[0] := UInt<3>(0)
    T_172664[1] := UInt<3>(1)
    T_172664[2] := UInt<3>(2)
    wire T_172665 : UInt<2>[2]
    T_172665[0] := UInt<2>(0)
    T_172665[1] := UInt<2>(1)
    wire T_172666 : UInt<2>[3]
    T_172666[0] := UInt<2>(1)
    T_172666[1] := UInt<2>(2)
    T_172666[2] := UInt<2>(3)
    wire T_172667 : UInt<2>[2]
    T_172667[0] := UInt<2>(2)
    T_172667[1] := UInt<2>(3)
    wire T_172668 : UInt<2>[1]
    T_172668[0] := UInt<2>(3)
    wire T_172669 : UInt<3>[3]
    T_172669[0] := UInt<3>(0)
    T_172669[1] := UInt<3>(1)
    T_172669[2] := UInt<3>(2)
    wire T_172670 : UInt<0>[1]
    T_172670[0] := UInt<0>(0)
    wire T_172671 : UInt<2>[2]
    T_172671[0] := UInt<2>(1)
    T_172671[1] := UInt<2>(2)
    wire T_172672 : UInt<2>[2]
    T_172672[0] := UInt<2>(1)
    T_172672[1] := UInt<2>(2)
    wire T_172673 : UInt<2>[1]
    T_172673[0] := UInt<2>(2)
    wire T_172674 : UInt<3>[3]
    T_172674[0] := UInt<3>(0)
    T_172674[1] := UInt<3>(1)
    T_172674[2] := UInt<3>(2)
    wire T_172675 : UInt<2>[2]
    T_172675[0] := UInt<2>(0)
    T_172675[1] := UInt<2>(1)
    wire T_172676 : UInt<2>[3]
    T_172676[0] := UInt<2>(1)
    T_172676[1] := UInt<2>(2)
    T_172676[2] := UInt<2>(3)
    wire T_172677 : UInt<2>[2]
    T_172677[0] := UInt<2>(2)
    T_172677[1] := UInt<2>(3)
    wire T_172678 : UInt<2>[1]
    T_172678[0] := UInt<2>(3)
    wire T_172679 : UInt<3>[3]
    T_172679[0] := UInt<3>(0)
    T_172679[1] := UInt<3>(1)
    T_172679[2] := UInt<3>(2)
    wire T_172680 : UInt<2>[2]
    T_172680[0] := UInt<2>(0)
    T_172680[1] := UInt<2>(1)
    wire T_172681 : UInt<2>[3]
    T_172681[0] := UInt<2>(1)
    T_172681[1] := UInt<2>(2)
    T_172681[2] := UInt<2>(3)
    wire T_172682 : UInt<2>[2]
    T_172682[0] := UInt<2>(2)
    T_172682[1] := UInt<2>(3)
    wire T_172683 : UInt<2>[1]
    T_172683[0] := UInt<2>(3)
    wire T_172684 : UInt<3>[3]
    T_172684[0] := UInt<3>(0)
    T_172684[1] := UInt<3>(1)
    T_172684[2] := UInt<3>(2)
    wire T_172685 : UInt<0>[1]
    T_172685[0] := UInt<0>(0)
    wire T_172686 : UInt<2>[2]
    T_172686[0] := UInt<2>(1)
    T_172686[1] := UInt<2>(2)
    wire T_172687 : UInt<2>[2]
    T_172687[0] := UInt<2>(1)
    T_172687[1] := UInt<2>(2)
    wire T_172688 : UInt<2>[1]
    T_172688[0] := UInt<2>(2)
    reg xact_old_meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    wire T_172689 : UInt<3>[3]
    T_172689[0] := UInt<3>(0)
    T_172689[1] := UInt<3>(1)
    T_172689[2] := UInt<3>(2)
    wire T_172690 : UInt<2>[2]
    T_172690[0] := UInt<2>(0)
    T_172690[1] := UInt<2>(1)
    wire T_172691 : UInt<2>[3]
    T_172691[0] := UInt<2>(1)
    T_172691[1] := UInt<2>(2)
    T_172691[2] := UInt<2>(3)
    wire T_172692 : UInt<2>[2]
    T_172692[0] := UInt<2>(2)
    T_172692[1] := UInt<2>(3)
    wire T_172693 : UInt<2>[1]
    T_172693[0] := UInt<2>(3)
    wire T_172694 : UInt<3>[3]
    T_172694[0] := UInt<3>(0)
    T_172694[1] := UInt<3>(1)
    T_172694[2] := UInt<3>(2)
    wire T_172695 : UInt<2>[2]
    T_172695[0] := UInt<2>(0)
    T_172695[1] := UInt<2>(1)
    wire T_172696 : UInt<2>[3]
    T_172696[0] := UInt<2>(1)
    T_172696[1] := UInt<2>(2)
    T_172696[2] := UInt<2>(3)
    wire T_172697 : UInt<2>[2]
    T_172697[0] := UInt<2>(2)
    T_172697[1] := UInt<2>(3)
    wire T_172698 : UInt<2>[1]
    T_172698[0] := UInt<2>(3)
    wire T_172699 : UInt<3>[3]
    T_172699[0] := UInt<3>(0)
    T_172699[1] := UInt<3>(1)
    T_172699[2] := UInt<3>(2)
    wire T_172700 : UInt<0>[1]
    T_172700[0] := UInt<0>(0)
    wire T_172701 : UInt<2>[2]
    T_172701[0] := UInt<2>(1)
    T_172701[1] := UInt<2>(2)
    wire T_172702 : UInt<2>[2]
    T_172702[0] := UInt<2>(1)
    T_172702[1] := UInt<2>(2)
    wire T_172703 : UInt<2>[1]
    T_172703[0] := UInt<2>(2)
    reg pending_coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    wire T_172704 : UInt<3>[3]
    T_172704[0] := UInt<3>(0)
    T_172704[1] := UInt<3>(1)
    T_172704[2] := UInt<3>(2)
    wire T_172705 : UInt<2>[2]
    T_172705[0] := UInt<2>(0)
    T_172705[1] := UInt<2>(1)
    wire T_172706 : UInt<2>[3]
    T_172706[0] := UInt<2>(1)
    T_172706[1] := UInt<2>(2)
    T_172706[2] := UInt<2>(3)
    wire T_172707 : UInt<2>[2]
    T_172707[0] := UInt<2>(2)
    T_172707[1] := UInt<2>(3)
    wire T_172708 : UInt<2>[1]
    T_172708[0] := UInt<2>(3)
    inst ignt_q of Queue_76584
    node T_172709 = and(inner.acquire.ready, inner.acquire.valid)
    node T_172710 = and(UInt<1>(1), inner.acquire.bits.is_builtin_type)
    wire T_172711 : UInt<3>[1]
    T_172711[0] := UInt<3>(3)
    node T_172712 = eq(T_172711[0], inner.acquire.bits.a_type)
    node T_172713 = or(UInt<1>(0), T_172712)
    node T_172714 = and(T_172710, T_172713)
    node T_172715 = and(T_172709, T_172714)
    reg T_172716 : UInt<2>
    onreset T_172716 := UInt<2>(0)
    when T_172715 : 
      node T_172717 = eq(T_172716, UInt<2>(3))
      node T_172718 = and(UInt<1>(0), T_172717)
      node T_172719 = addw(T_172716, UInt<1>(1))
      wire T_172720 : UInt<2>
      T_172720 := T_172719
      when T_172718 : T_172720 := UInt<1>(0)
      T_172716 := T_172720
    node T_172721 = and(T_172715, T_172717)
    wire T_172722 : UInt<1>
    T_172722 := UInt<1>(0)
    when T_172714 : T_172722 := T_172716
    wire iacq_data_done : UInt<1>
    iacq_data_done := T_172709
    when T_172714 : iacq_data_done := T_172721
    reg T_172723 : UInt<1>
    onreset T_172723 := UInt<1>(0)
    node T_172724 = and(inner.probe.ready, inner.probe.valid)
    node T_172725 = and(T_172724, UInt<1>(0))
    reg T_172726 : UInt<2>
    onreset T_172726 := UInt<2>(0)
    when T_172725 : 
      node T_172727 = eq(T_172726, UInt<2>(3))
      node T_172728 = and(UInt<1>(0), T_172727)
      node T_172729 = addw(T_172726, UInt<1>(1))
      wire T_172730 : UInt<2>
      T_172730 := T_172729
      when T_172728 : T_172730 := UInt<1>(0)
      T_172726 := T_172730
    node T_172731 = and(T_172725, T_172727)
    wire T_172732 : UInt<1>
    T_172732 := UInt<1>(0)
    when UInt<1>(0) : T_172732 := T_172726
    wire T_172733 : UInt<1>
    T_172733 := T_172724
    when UInt<1>(0) : T_172733 := T_172731
    node T_172734 = and(inner.release.ready, inner.release.valid)
    node T_172735 = eq(T_172476[0], inner.release.bits.r_type)
    node T_172736 = eq(T_172476[1], inner.release.bits.r_type)
    node T_172737 = eq(T_172476[2], inner.release.bits.r_type)
    node T_172738 = or(UInt<1>(0), T_172735)
    node T_172739 = or(T_172738, T_172736)
    node T_172740 = or(T_172739, T_172737)
    node T_172741 = and(UInt<1>(1), T_172740)
    node T_172742 = and(T_172734, T_172741)
    reg T_172743 : UInt<2>
    onreset T_172743 := UInt<2>(0)
    when T_172742 : 
      node T_172744 = eq(T_172743, UInt<2>(3))
      node T_172745 = and(UInt<1>(0), T_172744)
      node T_172746 = addw(T_172743, UInt<1>(1))
      wire T_172747 : UInt<2>
      T_172747 := T_172746
      when T_172745 : T_172747 := UInt<1>(0)
      T_172743 := T_172747
    node T_172748 = and(T_172742, T_172744)
    wire T_172749 : UInt<1>
    T_172749 := UInt<1>(0)
    when T_172741 : T_172749 := T_172743
    wire T_172750 : UInt<1>
    T_172750 := T_172734
    when T_172741 : T_172750 := T_172748
    node T_172751 = and(T_172733, UInt<1>(1))
    node T_172752 = subw(T_172723, UInt<1>(1))
    wire T_172753 : UInt<1>
    T_172753 := T_172752
    when T_172751 : T_172753 := T_172723
    node T_172754 = addw(T_172723, UInt<1>(1))
    wire T_172755 : UInt<1>
    T_172755 := T_172723
    when T_172751 : T_172755 := T_172754
    wire T_172756 : UInt<1>
    T_172756 := T_172755
    when T_172750 : T_172756 := T_172753
    T_172723 := T_172756
    node pending_irels = gt(T_172723, UInt<1>(0))
    reg T_172757 : UInt<1>
    onreset T_172757 := UInt<1>(0)
    node T_172758 = and(outer.acquire.ready, outer.acquire.valid)
    node T_172759 = and(UInt<1>(1), outer.acquire.bits.is_builtin_type)
    wire T_172760 : UInt<3>[1]
    T_172760[0] := UInt<3>(3)
    node T_172761 = eq(T_172760[0], outer.acquire.bits.a_type)
    node T_172762 = or(UInt<1>(0), T_172761)
    node T_172763 = and(T_172759, T_172762)
    node T_172764 = and(T_172758, T_172763)
    reg T_172765 : UInt<2>
    onreset T_172765 := UInt<2>(0)
    when T_172764 : 
      node T_172766 = eq(T_172765, UInt<2>(3))
      node T_172767 = and(UInt<1>(0), T_172766)
      node T_172768 = addw(T_172765, UInt<1>(1))
      wire T_172769 : UInt<2>
      T_172769 := T_172768
      when T_172767 : T_172769 := UInt<1>(0)
      T_172765 := T_172769
    node T_172770 = and(T_172764, T_172766)
    wire oacq_data_idx : UInt<2>
    oacq_data_idx := xact.addr_beat
    when T_172763 : oacq_data_idx := T_172765
    wire oacq_data_done : UInt<1>
    oacq_data_done := T_172758
    when T_172763 : oacq_data_done := T_172770
    node T_172771 = and(outer.grant.ready, outer.grant.valid)
    wire T_172772 : UInt<3>[1]
    T_172772[0] := UInt<3>(5)
    node T_172773 = eq(T_172772[0], outer.grant.bits.g_type)
    node T_172774 = or(UInt<1>(0), T_172773)
    node T_172775 = eq(T_172503[0], outer.grant.bits.g_type)
    node T_172776 = or(UInt<1>(0), T_172775)
    wire T_172777 : UInt<1>
    T_172777 := T_172776
    when outer.grant.bits.is_builtin_type : T_172777 := T_172774
    node T_172778 = and(UInt<1>(1), T_172777)
    node T_172779 = and(T_172771, T_172778)
    reg T_172780 : UInt<2>
    onreset T_172780 := UInt<2>(0)
    when T_172779 : 
      node T_172781 = eq(T_172780, UInt<2>(3))
      node T_172782 = and(UInt<1>(0), T_172781)
      node T_172783 = addw(T_172780, UInt<1>(1))
      wire T_172784 : UInt<2>
      T_172784 := T_172783
      when T_172782 : T_172784 := UInt<1>(0)
      T_172780 := T_172784
    node T_172785 = and(T_172779, T_172781)
    wire ognt_data_idx : UInt<2>
    ognt_data_idx := xact.addr_beat
    when T_172778 : ognt_data_idx := T_172780
    wire ognt_data_done : UInt<1>
    ognt_data_done := T_172771
    when T_172778 : ognt_data_done := T_172785
    node T_172786 = and(oacq_data_done, UInt<1>(1))
    node T_172787 = subw(T_172757, UInt<1>(1))
    wire T_172788 : UInt<1>
    T_172788 := T_172787
    when T_172786 : T_172788 := T_172757
    node T_172789 = addw(T_172757, UInt<1>(1))
    wire T_172790 : UInt<1>
    T_172790 := T_172757
    when T_172786 : T_172790 := T_172789
    wire T_172791 : UInt<1>
    T_172791 := T_172790
    when ognt_data_done : T_172791 := T_172788
    T_172757 := T_172791
    node pending_ognt = gt(T_172757, UInt<1>(0))
    node T_172792 = and(inner.grant.ready, inner.grant.valid)
    wire T_172793 : UInt<3>[1]
    T_172793[0] := UInt<3>(5)
    node T_172794 = eq(T_172793[0], inner.grant.bits.g_type)
    node T_172795 = or(UInt<1>(0), T_172794)
    node T_172796 = eq(T_172447[0], inner.grant.bits.g_type)
    node T_172797 = eq(T_172447[1], inner.grant.bits.g_type)
    node T_172798 = or(UInt<1>(0), T_172796)
    node T_172799 = or(T_172798, T_172797)
    wire T_172800 : UInt<1>
    T_172800 := T_172799
    when inner.grant.bits.is_builtin_type : T_172800 := T_172795
    node T_172801 = and(UInt<1>(1), T_172800)
    node T_172802 = and(T_172792, T_172801)
    reg T_172803 : UInt<2>
    onreset T_172803 := UInt<2>(0)
    when T_172802 : 
      node T_172804 = eq(T_172803, UInt<2>(3))
      node T_172805 = and(UInt<1>(0), T_172804)
      node T_172806 = addw(T_172803, UInt<1>(1))
      wire T_172807 : UInt<2>
      T_172807 := T_172806
      when T_172805 : T_172807 := UInt<1>(0)
      T_172803 := T_172807
    node T_172808 = and(T_172802, T_172804)
    wire ignt_data_idx : UInt<2>
    ignt_data_idx := ignt_q.deq.bits.addr_beat
    when T_172801 : ignt_data_idx := T_172803
    wire ignt_data_done : UInt<1>
    ignt_data_done := T_172792
    when T_172801 : ignt_data_done := T_172808
    reg T_172809 : UInt<3>
    onreset T_172809 := UInt<3>(0)
    node T_172810 = and(inner.grant.ready, inner.grant.valid)
    wire T_172811 : UInt<3>[1]
    T_172811[0] := UInt<3>(5)
    node T_172812 = eq(T_172811[0], inner.grant.bits.g_type)
    node T_172813 = or(UInt<1>(0), T_172812)
    node T_172814 = eq(T_172447[0], inner.grant.bits.g_type)
    node T_172815 = eq(T_172447[1], inner.grant.bits.g_type)
    node T_172816 = or(UInt<1>(0), T_172814)
    node T_172817 = or(T_172816, T_172815)
    wire T_172818 : UInt<1>
    T_172818 := T_172817
    when inner.grant.bits.is_builtin_type : T_172818 := T_172813
    node T_172819 = and(UInt<1>(1), T_172818)
    node T_172820 = and(T_172810, T_172819)
    reg T_172821 : UInt<2>
    onreset T_172821 := UInt<2>(0)
    when T_172820 : 
      node T_172822 = eq(T_172821, UInt<2>(3))
      node T_172823 = and(UInt<1>(0), T_172822)
      node T_172824 = addw(T_172821, UInt<1>(1))
      wire T_172825 : UInt<2>
      T_172825 := T_172824
      when T_172823 : T_172825 := UInt<1>(0)
      T_172821 := T_172825
    node T_172826 = and(T_172820, T_172822)
    wire T_172827 : UInt<1>
    T_172827 := UInt<1>(0)
    when T_172819 : T_172827 := T_172821
    wire T_172828 : UInt<1>
    T_172828 := T_172810
    when T_172819 : T_172828 := T_172826
    node T_172829 = and(inner.finish.ready, inner.finish.valid)
    node T_172830 = and(T_172829, UInt<1>(0))
    reg T_172831 : UInt<2>
    onreset T_172831 := UInt<2>(0)
    when T_172830 : 
      node T_172832 = eq(T_172831, UInt<2>(3))
      node T_172833 = and(UInt<1>(0), T_172832)
      node T_172834 = addw(T_172831, UInt<1>(1))
      wire T_172835 : UInt<2>
      T_172835 := T_172834
      when T_172833 : T_172835 := UInt<1>(0)
      T_172831 := T_172835
    node T_172836 = and(T_172830, T_172832)
    wire T_172837 : UInt<1>
    T_172837 := UInt<1>(0)
    when UInt<1>(0) : T_172837 := T_172831
    wire T_172838 : UInt<1>
    T_172838 := T_172829
    when UInt<1>(0) : T_172838 := T_172836
    node T_172839 = eq(UInt<1>(0), UInt<1>(0))
    node T_172840 = eq(inner.grant.bits.g_type, UInt<3>(0))
    node T_172841 = and(inner.grant.bits.is_builtin_type, T_172840)
    node T_172842 = eq(T_172841, UInt<1>(0))
    node T_172843 = and(T_172839, T_172842)
    node T_172844 = and(T_172828, T_172843)
    node T_172845 = subw(T_172809, UInt<1>(1))
    wire T_172846 : UInt<3>
    T_172846 := T_172845
    when T_172844 : T_172846 := T_172809
    node T_172847 = addw(T_172809, UInt<1>(1))
    wire T_172848 : UInt<3>
    T_172848 := T_172809
    when T_172844 : T_172848 := T_172847
    wire T_172849 : UInt<3>
    T_172849 := T_172848
    when T_172838 : T_172849 := T_172846
    T_172809 := T_172849
    node pending_ifins = gt(T_172809, UInt<1>(0))
    reg pending_puts : UInt<4>
    onreset pending_puts := UInt<4>(0)
    reg pending_iprbs : UInt<1>
    onreset pending_iprbs := UInt<1>(0)
    reg pending_reads : UInt<4>
    onreset pending_reads := UInt<4>(0)
    reg pending_writes : UInt<4>
    onreset pending_writes := UInt<4>(0)
    reg pending_resps : UInt<4>
    onreset pending_resps := UInt<4>(0)
    reg pending_ignt_data : UInt<4>
    onreset pending_ignt_data := UInt<4>(0)
    reg pending_meta_write : UInt<1>
    node T_172850 = eq(pending_reads, UInt<1>(0))
    node T_172851 = eq(T_172850, UInt<1>(0))
    node T_172852 = eq(pending_writes, UInt<1>(0))
    node T_172853 = eq(T_172852, UInt<1>(0))
    node T_172854 = or(T_172851, T_172853)
    node T_172855 = eq(pending_resps, UInt<1>(0))
    node T_172856 = eq(T_172855, UInt<1>(0))
    node T_172857 = or(T_172854, T_172856)
    node T_172858 = eq(pending_puts, UInt<1>(0))
    node T_172859 = eq(T_172858, UInt<1>(0))
    node T_172860 = or(T_172857, T_172859)
    node T_172861 = or(T_172860, pending_ognt)
    node T_172862 = gt(ignt_q.count, UInt<1>(0))
    node T_172863 = or(T_172861, T_172862)
    node T_172864 = or(T_172863, pending_ifins)
    node all_pending_done = eq(T_172864, UInt<1>(0))
    inst amoalu of AMOALU
    node T_172865 = bits(xact.union, 12, 9)
    node T_172866 = cat(xact.addr_beat, T_172865)
    node T_172867 = cat(xact.addr_block, T_172866)
    amoalu.addr := T_172867
    node T_172868 = eq(xact.a_type, UInt<3>(2))
    node T_172869 = and(xact.is_builtin_type, T_172868)
    node T_172870 = eq(xact.a_type, UInt<3>(3))
    node T_172871 = and(xact.is_builtin_type, T_172870)
    node T_172872 = or(T_172869, T_172871)
    node T_172873 = bits(xact.union, 5, 1)
    wire T_172874 : UInt<5>
    T_172874 := T_172873
    when T_172872 : T_172874 := UInt<5>(1)
    amoalu.cmd := T_172874
    node T_172875 = bits(xact.union, 8, 6)
    amoalu.typ := T_172875
    amoalu.lhs := data.resp.bits.data
    amoalu.rhs := data_buffer[0]
    node T_172876 = eq(xact.a_type, UInt<3>(0))
    node T_172877 = and(xact.is_builtin_type, T_172876)
    node T_172878 = eq(inner.acquire.bits.a_type, UInt<3>(0))
    node T_172879 = and(inner.acquire.bits.is_builtin_type, T_172878)
    node T_172880 = and(T_172877, T_172879)
    node T_172881 = eq(xact.client_id, inner.acquire.bits.client_id)
    node T_172882 = and(T_172880, T_172881)
    node T_172883 = eq(xact.addr_block, inner.acquire.bits.addr_block)
    node T_172884 = and(T_172882, T_172883)
    node T_172885 = neq(state, UInt<4>(0))
    node T_172886 = and(T_172884, T_172885)
    node T_172887 = neq(state, UInt<4>(8))
    node T_172888 = and(T_172886, T_172887)
    node T_172889 = eq(all_pending_done, UInt<1>(0))
    node T_172890 = and(T_172888, T_172889)
    node T_172891 = bit(xact.union, 0)
    node T_172892 = and(T_172890, T_172891)
    node T_172893 = and(inner.release.ready, inner.release.valid)
    node T_172894 = eq(T_172893, UInt<1>(0))
    node T_172895 = and(T_172892, T_172894)
    node T_172896 = and(outer.grant.ready, outer.grant.valid)
    node T_172897 = eq(T_172896, UInt<1>(0))
    node T_172898 = and(T_172895, T_172897)
    node T_172899 = eq(data.resp.valid, UInt<1>(0))
    node T_172900 = and(T_172898, T_172899)
    node can_merge_iacq_get = and(T_172900, ignt_q.enq.ready)
    node T_172901 = eq(xact.a_type, UInt<3>(2))
    node T_172902 = and(xact.is_builtin_type, T_172901)
    node T_172903 = eq(inner.acquire.bits.a_type, UInt<3>(2))
    node T_172904 = and(inner.acquire.bits.is_builtin_type, T_172903)
    node T_172905 = and(T_172902, T_172904)
    node T_172906 = eq(xact.a_type, UInt<3>(3))
    node T_172907 = and(xact.is_builtin_type, T_172906)
    node T_172908 = eq(inner.acquire.bits.a_type, UInt<3>(3))
    node T_172909 = and(inner.acquire.bits.is_builtin_type, T_172908)
    node T_172910 = and(T_172907, T_172909)
    node T_172911 = or(T_172905, T_172910)
    node T_172912 = eq(xact.client_id, inner.acquire.bits.client_id)
    node T_172913 = and(T_172911, T_172912)
    node T_172914 = eq(xact.addr_block, inner.acquire.bits.addr_block)
    node T_172915 = and(T_172913, T_172914)
    node T_172916 = neq(state, UInt<4>(0))
    node T_172917 = and(T_172915, T_172916)
    node T_172918 = neq(state, UInt<4>(8))
    node T_172919 = and(T_172917, T_172918)
    node T_172920 = eq(all_pending_done, UInt<1>(0))
    node T_172921 = and(T_172919, T_172920)
    node T_172922 = bit(xact.union, 0)
    node T_172923 = eq(xact.a_type, UInt<3>(3))
    node T_172924 = and(xact.is_builtin_type, T_172923)
    node T_172925 = or(T_172922, T_172924)
    node T_172926 = and(T_172921, T_172925)
    node T_172927 = and(inner.release.ready, inner.release.valid)
    node T_172928 = eq(T_172927, UInt<1>(0))
    node T_172929 = and(T_172926, T_172928)
    node T_172930 = and(outer.grant.ready, outer.grant.valid)
    node T_172931 = eq(T_172930, UInt<1>(0))
    node T_172932 = and(T_172929, T_172931)
    node T_172933 = eq(data.resp.valid, UInt<1>(0))
    node T_172934 = and(T_172932, T_172933)
    node can_merge_iacq_put = and(T_172934, ignt_q.enq.ready)
    node T_172935 = eq(state, UInt<4>(0))
    node T_172936 = or(T_172935, can_merge_iacq_put)
    node T_172937 = or(T_172936, can_merge_iacq_get)
    inner.acquire.ready := T_172937
    ignt_q.enq.valid := iacq_data_done
    ignt_q.enq.bits.client_xact_id := inner.acquire.bits.client_xact_id
    ignt_q.enq.bits.addr_beat := inner.acquire.bits.addr_beat
    node T_172938 = and(inner.acquire.ready, inner.acquire.valid)
    wire T_172939 : UInt<3>[3]
    T_172939[0] := UInt<3>(2)
    T_172939[1] := UInt<3>(3)
    T_172939[2] := UInt<3>(4)
    node T_172940 = eq(T_172939[0], inner.acquire.bits.a_type)
    node T_172941 = eq(T_172939[1], inner.acquire.bits.a_type)
    node T_172942 = eq(T_172939[2], inner.acquire.bits.a_type)
    node T_172943 = or(UInt<1>(0), T_172940)
    node T_172944 = or(T_172943, T_172941)
    node T_172945 = or(T_172944, T_172942)
    node T_172946 = and(inner.acquire.bits.is_builtin_type, T_172945)
    node T_172947 = and(T_172938, T_172946)
    node T_172948 = subw(UInt<4>(0), UInt<3>(4))
    node T_172949 = not(T_172948)
    node T_172950 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_172951 = not(T_172950)
    node T_172952 = or(T_172949, T_172951)
    node T_172953 = and(pending_puts, T_172952)
    pending_puts := T_172953
    node T_172954 = eq(state, UInt<4>(1))
    meta.read.valid := T_172954
    meta.read.bits.id := UInt<1>(1)
    node T_172955 = bits(xact.addr_block, 11, 0)
    meta.read.bits.idx := T_172955
    node T_172956 = dshr(xact.addr_block, UInt<4>(12))
    meta.read.bits.tag := T_172956
    node T_172957 = eq(state, UInt<4>(3))
    wb.req.valid := T_172957
    wb.req.bits.id := UInt<1>(1)
    node T_172958 = bits(xact.addr_block, 11, 0)
    wb.req.bits.idx := T_172958
    wb.req.bits.tag := xact_old_meta.tag
    wb.req.bits.coh := xact_old_meta.coh
    wb.req.bits.way_en := xact_way_en
    node T_172959 = and(inner.probe.ready, inner.probe.valid)
    node T_172960 = not(T_172959)
    node T_172961 = dshl(UInt<1>(1), inner.probe.bits.client_id)
    node T_172962 = not(T_172961)
    node T_172963 = or(T_172960, T_172962)
    node T_172964 = and(pending_iprbs, T_172963)
    pending_iprbs := T_172964
    node T_172965 = bit(pending_iprbs, 0)
    wire T_172966 : UInt<1>[1]
    T_172966[0] := T_172965
    node T_172967 = eq(state, UInt<4>(5))
    node T_172968 = eq(pending_iprbs, UInt<1>(0))
    node T_172969 = eq(T_172968, UInt<1>(0))
    node T_172970 = and(T_172967, T_172969)
    inner.probe.valid := T_172970
    node T_172971 = eq(UInt<3>(4), xact.a_type)
    wire T_172972 : UInt<2>
    T_172972 := UInt<2>(2)
    when T_172971 : T_172972 := UInt<2>(0)
    node T_172973 = eq(UInt<3>(2), xact.a_type)
    wire T_172974 : UInt<2>
    T_172974 := T_172972
    when T_172973 : T_172974 := UInt<2>(0)
    node T_172975 = eq(UInt<3>(0), xact.a_type)
    wire T_172976 : UInt<2>
    T_172976 := T_172974
    when T_172975 : T_172976 := UInt<2>(2)
    node T_172977 = eq(UInt<3>(3), xact.a_type)
    wire T_172978 : UInt<2>
    T_172978 := T_172976
    when T_172977 : T_172978 := UInt<2>(0)
    node T_172979 = eq(UInt<3>(1), xact.a_type)
    wire T_172980 : UInt<2>
    T_172980 := T_172978
    when T_172979 : T_172980 := UInt<2>(2)
    node T_172981 = eq(UInt<1>(1), xact.a_type)
    wire T_172982 : UInt<2>
    T_172982 := UInt<2>(2)
    when T_172981 : T_172982 := UInt<2>(0)
    node T_172983 = eq(UInt<1>(0), xact.a_type)
    wire T_172984 : UInt<2>
    T_172984 := T_172982
    when T_172983 : T_172984 := UInt<2>(1)
    wire T_172985 : UInt<2>
    T_172985 := T_172984
    when xact.is_builtin_type : T_172985 := T_172980
    wire T_172986 : UInt<3>[3]
    T_172986[0] := UInt<3>(0)
    T_172986[1] := UInt<3>(1)
    T_172986[2] := UInt<3>(2)
    wire T_172987 : UInt<2>[2]
    T_172987[0] := UInt<2>(0)
    T_172987[1] := UInt<2>(1)
    wire T_172988 : UInt<2>[3]
    T_172988[0] := UInt<2>(1)
    T_172988[1] := UInt<2>(2)
    T_172988[2] := UInt<2>(3)
    wire T_172989 : UInt<2>[2]
    T_172989[0] := UInt<2>(2)
    T_172989[1] := UInt<2>(3)
    wire T_172990 : UInt<2>[1]
    T_172990[0] := UInt<2>(3)
    wire T_172991 : UInt<3>[3]
    T_172991[0] := UInt<3>(0)
    T_172991[1] := UInt<3>(1)
    T_172991[2] := UInt<3>(2)
    wire T_172992 : UInt<2>[2]
    T_172992[0] := UInt<2>(0)
    T_172992[1] := UInt<2>(1)
    wire T_172993 : UInt<2>[3]
    T_172993[0] := UInt<2>(1)
    T_172993[1] := UInt<2>(2)
    T_172993[2] := UInt<2>(3)
    wire T_172994 : UInt<2>[2]
    T_172994[0] := UInt<2>(2)
    T_172994[1] := UInt<2>(3)
    wire T_172995 : UInt<2>[1]
    T_172995[0] := UInt<2>(3)
    wire T_172996 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_172996.client_id := UInt<1>(0)
    T_172996.p_type := T_172985
    T_172996.addr_block := xact.addr_block
    inner.probe.bits := T_172996
    node T_172997 = eq(state, UInt<4>(5))
    inner.release.ready := T_172997
    node T_172998 = dshl(UInt<1>(1), inner.release.bits.client_id)
    node T_172999 = not(T_172998)
    node T_173000 = and(pending_coh.inner.sharers, T_172999)
    wire T_173001 : UInt<3>[3]
    T_173001[0] := UInt<3>(0)
    T_173001[1] := UInt<3>(1)
    T_173001[2] := UInt<3>(2)
    wire T_173002 : UInt<2>[2]
    T_173002[0] := UInt<2>(0)
    T_173002[1] := UInt<2>(1)
    wire T_173003 : UInt<2>[3]
    T_173003[0] := UInt<2>(1)
    T_173003[1] := UInt<2>(2)
    T_173003[2] := UInt<2>(3)
    wire T_173004 : UInt<2>[2]
    T_173004[0] := UInt<2>(2)
    T_173004[1] := UInt<2>(3)
    wire T_173005 : UInt<2>[1]
    T_173005[0] := UInt<2>(3)
    wire T_173006 : UInt<3>[3]
    T_173006[0] := UInt<3>(0)
    T_173006[1] := UInt<3>(1)
    T_173006[2] := UInt<3>(2)
    wire T_173007 : UInt<2>[2]
    T_173007[0] := UInt<2>(0)
    T_173007[1] := UInt<2>(1)
    wire T_173008 : UInt<2>[3]
    T_173008[0] := UInt<2>(1)
    T_173008[1] := UInt<2>(2)
    T_173008[2] := UInt<2>(3)
    wire T_173009 : UInt<2>[2]
    T_173009[0] := UInt<2>(2)
    T_173009[1] := UInt<2>(3)
    wire T_173010 : UInt<2>[1]
    T_173010[0] := UInt<2>(3)
    wire T_173011 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_173011.sharers := T_173000
    node T_173012 = eq(inner.release.bits.r_type, UInt<3>(0))
    node T_173013 = eq(inner.release.bits.r_type, UInt<3>(3))
    wire T_173014 : UInt<3>[3]
    T_173014[0] := UInt<3>(0)
    T_173014[1] := UInt<3>(1)
    T_173014[2] := UInt<3>(2)
    wire T_173015 : UInt<2>[2]
    T_173015[0] := UInt<2>(0)
    T_173015[1] := UInt<2>(1)
    wire T_173016 : UInt<2>[3]
    T_173016[0] := UInt<2>(1)
    T_173016[1] := UInt<2>(2)
    T_173016[2] := UInt<2>(3)
    wire T_173017 : UInt<2>[2]
    T_173017[0] := UInt<2>(2)
    T_173017[1] := UInt<2>(3)
    wire T_173018 : UInt<2>[1]
    T_173018[0] := UInt<2>(3)
    wire T_173019 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_173019 := pending_coh.inner
    when T_173013 : T_173019 := T_173011
    wire T_173020 : UInt<3>[3]
    T_173020[0] := UInt<3>(0)
    T_173020[1] := UInt<3>(1)
    T_173020[2] := UInt<3>(2)
    wire T_173021 : UInt<2>[2]
    T_173021[0] := UInt<2>(0)
    T_173021[1] := UInt<2>(1)
    wire T_173022 : UInt<2>[3]
    T_173022[0] := UInt<2>(1)
    T_173022[1] := UInt<2>(2)
    T_173022[2] := UInt<2>(3)
    wire T_173023 : UInt<2>[2]
    T_173023[0] := UInt<2>(2)
    T_173023[1] := UInt<2>(3)
    wire T_173024 : UInt<2>[1]
    T_173024[0] := UInt<2>(3)
    wire T_173025 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_173025 := T_173019
    when T_173012 : T_173025 := T_173011
    node T_173026 = eq(T_172476[0], inner.release.bits.r_type)
    node T_173027 = eq(T_172476[1], inner.release.bits.r_type)
    node T_173028 = eq(T_172476[2], inner.release.bits.r_type)
    node T_173029 = or(UInt<1>(0), T_173026)
    node T_173030 = or(T_173029, T_173027)
    node T_173031 = or(T_173030, T_173028)
    node T_173032 = eq(UInt<5>(1), UInt<5>(1))
    node T_173033 = eq(UInt<5>(1), UInt<5>(7))
    node T_173034 = or(T_173032, T_173033)
    node T_173035 = eq(UInt<5>(1), UInt<5>(4))
    node T_173036 = or(UInt<1>(0), T_173035)
    node T_173037 = or(T_173034, T_173036)
    wire T_173038 : UInt<2>
    T_173038 := pending_coh.outer.state
    when T_173037 : T_173038 := UInt<2>(2)
    wire T_173039 : UInt<3>[3]
    T_173039[0] := UInt<3>(0)
    T_173039[1] := UInt<3>(1)
    T_173039[2] := UInt<3>(2)
    wire T_173040 : UInt<0>[1]
    T_173040[0] := UInt<0>(0)
    wire T_173041 : UInt<2>[2]
    T_173041[0] := UInt<2>(1)
    T_173041[1] := UInt<2>(2)
    wire T_173042 : UInt<2>[2]
    T_173042[0] := UInt<2>(1)
    T_173042[1] := UInt<2>(2)
    wire T_173043 : UInt<2>[1]
    T_173043[0] := UInt<2>(2)
    wire T_173044 : UInt<3>[3]
    T_173044[0] := UInt<3>(0)
    T_173044[1] := UInt<3>(1)
    T_173044[2] := UInt<3>(2)
    wire T_173045 : UInt<0>[1]
    T_173045[0] := UInt<0>(0)
    wire T_173046 : UInt<2>[2]
    T_173046[0] := UInt<2>(1)
    T_173046[1] := UInt<2>(2)
    wire T_173047 : UInt<2>[2]
    T_173047[0] := UInt<2>(1)
    T_173047[1] := UInt<2>(2)
    wire T_173048 : UInt<2>[1]
    T_173048[0] := UInt<2>(2)
    wire T_173049 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_173049.state := T_173038
    wire T_173050 : UInt<3>[3]
    T_173050[0] := UInt<3>(0)
    T_173050[1] := UInt<3>(1)
    T_173050[2] := UInt<3>(2)
    wire T_173051 : UInt<2>[2]
    T_173051[0] := UInt<2>(0)
    T_173051[1] := UInt<2>(1)
    wire T_173052 : UInt<2>[3]
    T_173052[0] := UInt<2>(1)
    T_173052[1] := UInt<2>(2)
    T_173052[2] := UInt<2>(3)
    wire T_173053 : UInt<2>[2]
    T_173053[0] := UInt<2>(2)
    T_173053[1] := UInt<2>(3)
    wire T_173054 : UInt<2>[1]
    T_173054[0] := UInt<2>(3)
    wire T_173055 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_173055 := pending_coh.outer
    when T_173031 : T_173055 := T_173049
    wire T_173056 : UInt<3>[3]
    T_173056[0] := UInt<3>(0)
    T_173056[1] := UInt<3>(1)
    T_173056[2] := UInt<3>(2)
    wire T_173057 : UInt<2>[2]
    T_173057[0] := UInt<2>(0)
    T_173057[1] := UInt<2>(1)
    wire T_173058 : UInt<2>[3]
    T_173058[0] := UInt<2>(1)
    T_173058[1] := UInt<2>(2)
    T_173058[2] := UInt<2>(3)
    wire T_173059 : UInt<2>[2]
    T_173059[0] := UInt<2>(2)
    T_173059[1] := UInt<2>(3)
    wire T_173060 : UInt<2>[1]
    T_173060[0] := UInt<2>(3)
    wire T_173061 : UInt<3>[3]
    T_173061[0] := UInt<3>(0)
    T_173061[1] := UInt<3>(1)
    T_173061[2] := UInt<3>(2)
    wire T_173062 : UInt<2>[2]
    T_173062[0] := UInt<2>(0)
    T_173062[1] := UInt<2>(1)
    wire T_173063 : UInt<2>[3]
    T_173063[0] := UInt<2>(1)
    T_173063[1] := UInt<2>(2)
    T_173063[2] := UInt<2>(3)
    wire T_173064 : UInt<2>[2]
    T_173064[0] := UInt<2>(2)
    T_173064[1] := UInt<2>(3)
    wire T_173065 : UInt<2>[1]
    T_173065[0] := UInt<2>(3)
    wire T_173066 : UInt<3>[3]
    T_173066[0] := UInt<3>(0)
    T_173066[1] := UInt<3>(1)
    T_173066[2] := UInt<3>(2)
    wire T_173067 : UInt<0>[1]
    T_173067[0] := UInt<0>(0)
    wire T_173068 : UInt<2>[2]
    T_173068[0] := UInt<2>(1)
    T_173068[1] := UInt<2>(2)
    wire T_173069 : UInt<2>[2]
    T_173069[0] := UInt<2>(1)
    T_173069[1] := UInt<2>(2)
    wire T_173070 : UInt<2>[1]
    T_173070[0] := UInt<2>(2)
    wire T_173071 : UInt<3>[3]
    T_173071[0] := UInt<3>(0)
    T_173071[1] := UInt<3>(1)
    T_173071[2] := UInt<3>(2)
    wire T_173072 : UInt<2>[2]
    T_173072[0] := UInt<2>(0)
    T_173072[1] := UInt<2>(1)
    wire T_173073 : UInt<2>[3]
    T_173073[0] := UInt<2>(1)
    T_173073[1] := UInt<2>(2)
    T_173073[2] := UInt<2>(3)
    wire T_173074 : UInt<2>[2]
    T_173074[0] := UInt<2>(2)
    T_173074[1] := UInt<2>(3)
    wire T_173075 : UInt<2>[1]
    T_173075[0] := UInt<2>(3)
    wire T_173076 : UInt<3>[3]
    T_173076[0] := UInt<3>(0)
    T_173076[1] := UInt<3>(1)
    T_173076[2] := UInt<3>(2)
    wire T_173077 : UInt<2>[2]
    T_173077[0] := UInt<2>(0)
    T_173077[1] := UInt<2>(1)
    wire T_173078 : UInt<2>[3]
    T_173078[0] := UInt<2>(1)
    T_173078[1] := UInt<2>(2)
    T_173078[2] := UInt<2>(3)
    wire T_173079 : UInt<2>[2]
    T_173079[0] := UInt<2>(2)
    T_173079[1] := UInt<2>(3)
    wire T_173080 : UInt<2>[1]
    T_173080[0] := UInt<2>(3)
    wire T_173081 : UInt<3>[3]
    T_173081[0] := UInt<3>(0)
    T_173081[1] := UInt<3>(1)
    T_173081[2] := UInt<3>(2)
    wire T_173082 : UInt<0>[1]
    T_173082[0] := UInt<0>(0)
    wire T_173083 : UInt<2>[2]
    T_173083[0] := UInt<2>(1)
    T_173083[1] := UInt<2>(2)
    wire T_173084 : UInt<2>[2]
    T_173084[0] := UInt<2>(1)
    T_173084[1] := UInt<2>(2)
    wire T_173085 : UInt<2>[1]
    T_173085[0] := UInt<2>(2)
    wire pending_coh_on_irel : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_irel.inner := T_173025
    pending_coh_on_irel.outer := T_173055
    node T_173086 = and(inner.release.ready, inner.release.valid)
    
    
    node T_173087 = eq(pending_coh.inner.sharers, pending_coh_on_irel.inner.sharers)
    node T_173088 = eq(pending_coh.outer.state, pending_coh_on_irel.outer.state)
    node T_173089 = and(T_173087, T_173088)
    node T_173090 = eq(T_173089, UInt<1>(0))
    node T_173091 = and(T_173086, T_173090)
    when T_173091 : 
      pending_meta_write := UInt<1>(1)
      pending_coh := pending_coh_on_irel
    
    
    node T_173092 = and(inner.release.ready, inner.release.valid)
    node T_173093 = eq(T_172476[0], inner.release.bits.r_type)
    node T_173094 = eq(T_172476[1], inner.release.bits.r_type)
    node T_173095 = eq(T_172476[2], inner.release.bits.r_type)
    node T_173096 = or(UInt<1>(0), T_173093)
    node T_173097 = or(T_173096, T_173094)
    node T_173098 = or(T_173097, T_173095)
    node T_173099 = and(T_173092, T_173098)
    when T_173099 : 
      accessor T_173100 = data_buffer[inner.release.bits.addr_beat]
      node T_173101 = bits(xact.union, 12, 9)
      node T_173102 = bits(T_173101, 3, 3)
      node T_173103 = mul(UInt<7>(64), T_173102)
      node T_173104 = dshr(inner.release.bits.data, T_173103)
      amoalu.lhs := T_173104
      node T_173105 = bits(xact.union, 12, 9)
      node T_173106 = bits(T_173105, 3, 3)
      node T_173107 = mul(UInt<7>(64), T_173106)
      node T_173108 = dshr(T_173100, T_173107)
      amoalu.rhs := T_173108
      accessor T_173109 = wmask_buffer[inner.release.bits.addr_beat]
      node T_173110 = bit(T_173109, 0)
      node T_173111 = bit(T_173109, 1)
      node T_173112 = bit(T_173109, 2)
      node T_173113 = bit(T_173109, 3)
      node T_173114 = bit(T_173109, 4)
      node T_173115 = bit(T_173109, 5)
      node T_173116 = bit(T_173109, 6)
      node T_173117 = bit(T_173109, 7)
      node T_173118 = bit(T_173109, 8)
      node T_173119 = bit(T_173109, 9)
      node T_173120 = bit(T_173109, 10)
      node T_173121 = bit(T_173109, 11)
      node T_173122 = bit(T_173109, 12)
      node T_173123 = bit(T_173109, 13)
      node T_173124 = bit(T_173109, 14)
      node T_173125 = bit(T_173109, 15)
      wire T_173126 : UInt<1>[16]
      T_173126[0] := T_173110
      T_173126[1] := T_173111
      T_173126[2] := T_173112
      T_173126[3] := T_173113
      T_173126[4] := T_173114
      T_173126[5] := T_173115
      T_173126[6] := T_173116
      T_173126[7] := T_173117
      T_173126[8] := T_173118
      T_173126[9] := T_173119
      T_173126[10] := T_173120
      T_173126[11] := T_173121
      T_173126[12] := T_173122
      T_173126[13] := T_173123
      T_173126[14] := T_173124
      T_173126[15] := T_173125
      node T_173127 = subw(UInt<8>(0), UInt<4>(8))
      node T_173128 = subw(UInt<8>(0), UInt<4>(8))
      node T_173129 = subw(UInt<8>(0), UInt<4>(8))
      node T_173130 = subw(UInt<8>(0), UInt<4>(8))
      node T_173131 = subw(UInt<8>(0), UInt<4>(8))
      node T_173132 = subw(UInt<8>(0), UInt<4>(8))
      node T_173133 = subw(UInt<8>(0), UInt<4>(8))
      node T_173134 = subw(UInt<8>(0), UInt<4>(8))
      node T_173135 = subw(UInt<8>(0), UInt<4>(8))
      node T_173136 = subw(UInt<8>(0), UInt<4>(8))
      node T_173137 = subw(UInt<8>(0), UInt<4>(8))
      node T_173138 = subw(UInt<8>(0), UInt<4>(8))
      node T_173139 = subw(UInt<8>(0), UInt<4>(8))
      node T_173140 = subw(UInt<8>(0), UInt<4>(8))
      node T_173141 = subw(UInt<8>(0), UInt<4>(8))
      node T_173142 = subw(UInt<8>(0), UInt<4>(8))
      wire T_173143 : UInt<8>[16]
      T_173143[0] := T_173127
      T_173143[1] := T_173128
      T_173143[2] := T_173129
      T_173143[3] := T_173130
      T_173143[4] := T_173131
      T_173143[5] := T_173132
      T_173143[6] := T_173133
      T_173143[7] := T_173134
      T_173143[8] := T_173135
      T_173143[9] := T_173136
      T_173143[10] := T_173137
      T_173143[11] := T_173138
      T_173143[12] := T_173139
      T_173143[13] := T_173140
      T_173143[14] := T_173141
      T_173143[15] := T_173142
      node T_173144 = cat(T_173143[15], T_173143[14])
      node T_173145 = cat(T_173143[13], T_173143[12])
      node T_173146 = cat(T_173144, T_173145)
      node T_173147 = cat(T_173143[11], T_173143[10])
      node T_173148 = cat(T_173143[9], T_173143[8])
      node T_173149 = cat(T_173147, T_173148)
      node T_173150 = cat(T_173146, T_173149)
      node T_173151 = cat(T_173143[7], T_173143[6])
      node T_173152 = cat(T_173143[5], T_173143[4])
      node T_173153 = cat(T_173151, T_173152)
      node T_173154 = cat(T_173143[3], T_173143[2])
      node T_173155 = cat(T_173143[1], T_173143[0])
      node T_173156 = cat(T_173154, T_173155)
      node T_173157 = cat(T_173153, T_173156)
      node T_173158 = cat(T_173150, T_173157)
      accessor T_173159 = data_buffer[inner.release.bits.addr_beat]
      node T_173160 = not(T_173158)
      node T_173161 = and(T_173160, inner.release.bits.data)
      node T_173162 = eq(xact.a_type, UInt<3>(4))
      node T_173163 = and(xact.is_builtin_type, T_173162)
      node T_173164 = bits(xact.union, 12, 9)
      node T_173165 = bits(T_173164, 3, 3)
      node T_173166 = mul(UInt<7>(64), T_173165)
      node T_173167 = dshl(amoalu.out, T_173166)
      wire T_173168 : UInt<128>
      T_173168 := T_173100
      when T_173163 : T_173168 := T_173167
      node T_173169 = and(T_173158, T_173168)
      node T_173170 = or(T_173161, T_173169)
      T_173159 := T_173170
      accessor T_173171 = wmask_buffer[inner.release.bits.addr_beat]
      T_173171 := SInt<1>(-1)
      
      
      node T_173172 = eq(xact.a_type, UInt<3>(4))
      node T_173173 = eq(xact.addr_beat, inner.release.bits.addr_beat)
      node T_173174 = and(T_173172, T_173173)
      when T_173174 : xact.data := inner.release.bits.data
    node T_173175 = eq(state, UInt<4>(6))
    node T_173176 = bit(xact.union, 0)
    node T_173177 = dshr(pending_puts, oacq_data_idx)
    node T_173178 = bit(T_173177, 0)
    node T_173179 = eq(T_173178, UInt<1>(0))
    node T_173180 = or(T_173176, T_173179)
    node T_173181 = and(T_173175, T_173180)
    outer.acquire.valid := T_173181
    node T_173182 = bit(xact.union, 0)
    node T_173183 = eq(xact.a_type, UInt<3>(2))
    node T_173184 = and(xact.is_builtin_type, T_173183)
    node T_173185 = eq(xact.a_type, UInt<3>(3))
    node T_173186 = and(xact.is_builtin_type, T_173185)
    node T_173187 = or(T_173184, T_173186)
    node T_173188 = bits(xact.union, 5, 1)
    wire T_173189 : UInt<5>
    T_173189 := T_173188
    when T_173187 : T_173189 := UInt<5>(1)
    node T_173190 = eq(T_173189, UInt<5>(1))
    node T_173191 = eq(T_173189, UInt<5>(7))
    node T_173192 = or(T_173190, T_173191)
    node T_173193 = bit(T_173189, 3)
    node T_173194 = eq(T_173189, UInt<5>(4))
    node T_173195 = or(T_173193, T_173194)
    node T_173196 = or(T_173192, T_173195)
    node T_173197 = eq(T_173189, UInt<5>(3))
    node T_173198 = or(T_173196, T_173197)
    node T_173199 = eq(T_173189, UInt<5>(6))
    node T_173200 = or(T_173198, T_173199)
    wire T_173201 : UInt<1>
    T_173201 := UInt<1>(0)
    when T_173200 : T_173201 := UInt<1>(1)
    node T_173202 = cat(T_173189, UInt<1>(1))
    wire T_173203 : UInt<3>[3]
    T_173203[0] := UInt<3>(0)
    T_173203[1] := UInt<3>(1)
    T_173203[2] := UInt<3>(2)
    wire T_173204 : UInt<0>[1]
    T_173204[0] := UInt<0>(0)
    wire T_173205 : UInt<2>[2]
    T_173205[0] := UInt<2>(1)
    T_173205[1] := UInt<2>(2)
    wire T_173206 : UInt<2>[2]
    T_173206[0] := UInt<2>(1)
    T_173206[1] := UInt<2>(2)
    wire T_173207 : UInt<2>[1]
    T_173207[0] := UInt<2>(2)
    wire T_173208 : UInt<3>[3]
    T_173208[0] := UInt<3>(0)
    T_173208[1] := UInt<3>(1)
    T_173208[2] := UInt<3>(2)
    wire T_173209 : UInt<0>[1]
    T_173209[0] := UInt<0>(0)
    wire T_173210 : UInt<2>[2]
    T_173210[0] := UInt<2>(1)
    T_173210[1] := UInt<2>(2)
    wire T_173211 : UInt<2>[2]
    T_173211[0] := UInt<2>(1)
    T_173211[1] := UInt<2>(2)
    wire T_173212 : UInt<2>[1]
    T_173212[0] := UInt<2>(2)
    wire T_173213 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_173213.is_builtin_type := UInt<1>(0)
    T_173213.a_type := T_173201
    T_173213.client_xact_id := UInt<1>(0)
    T_173213.addr_block := xact.addr_block
    T_173213.addr_beat := UInt<1>(0)
    T_173213.data := UInt<1>(0)
    T_173213.union := T_173202
    wire T_173214 : UInt<3>[3]
    T_173214[0] := UInt<3>(0)
    T_173214[1] := UInt<3>(1)
    T_173214[2] := UInt<3>(2)
    wire T_173215 : UInt<0>[1]
    T_173215[0] := UInt<0>(0)
    wire T_173216 : UInt<2>[2]
    T_173216[0] := UInt<2>(1)
    T_173216[1] := UInt<2>(2)
    wire T_173217 : UInt<2>[2]
    T_173217[0] := UInt<2>(1)
    T_173217[1] := UInt<2>(2)
    wire T_173218 : UInt<2>[1]
    T_173218[0] := UInt<2>(2)
    wire T_173219 : UInt<3>[3]
    T_173219[0] := UInt<3>(0)
    T_173219[1] := UInt<3>(1)
    T_173219[2] := UInt<3>(2)
    wire T_173220 : UInt<0>[1]
    T_173220[0] := UInt<0>(0)
    wire T_173221 : UInt<2>[2]
    T_173221[0] := UInt<2>(1)
    T_173221[1] := UInt<2>(2)
    wire T_173222 : UInt<2>[2]
    T_173222[0] := UInt<2>(1)
    T_173222[1] := UInt<2>(2)
    wire T_173223 : UInt<2>[1]
    T_173223[0] := UInt<2>(2)
    wire T_173224 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_173224 := xact
    wire T_173225 : UInt<3>[3]
    T_173225[0] := UInt<3>(0)
    T_173225[1] := UInt<3>(1)
    T_173225[2] := UInt<3>(2)
    wire T_173226 : UInt<2>[2]
    T_173226[0] := UInt<2>(0)
    T_173226[1] := UInt<2>(1)
    wire T_173227 : UInt<2>[3]
    T_173227[0] := UInt<2>(1)
    T_173227[1] := UInt<2>(2)
    T_173227[2] := UInt<2>(3)
    wire T_173228 : UInt<2>[2]
    T_173228[0] := UInt<2>(2)
    T_173228[1] := UInt<2>(3)
    wire T_173229 : UInt<2>[1]
    T_173229[0] := UInt<2>(3)
    wire T_173230 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_173230 := T_173224
    when T_173182 : T_173230 := T_173213
    outer.acquire.bits := T_173230
    accessor T_173231 = data_buffer[oacq_data_idx]
    outer.acquire.bits.data := T_173231
    node T_173232 = eq(state, UInt<4>(7))
    outer.grant.ready := T_173232
    wire T_173233 : UInt<3>[3]
    T_173233[0] := UInt<3>(0)
    T_173233[1] := UInt<3>(1)
    T_173233[2] := UInt<3>(2)
    wire T_173234 : UInt<2>[2]
    T_173234[0] := UInt<2>(0)
    T_173234[1] := UInt<2>(1)
    wire T_173235 : UInt<2>[3]
    T_173235[0] := UInt<2>(1)
    T_173235[1] := UInt<2>(2)
    T_173235[2] := UInt<2>(3)
    wire T_173236 : UInt<2>[2]
    T_173236[0] := UInt<2>(2)
    T_173236[1] := UInt<2>(3)
    wire T_173237 : UInt<2>[1]
    T_173237[0] := UInt<2>(3)
    wire T_173238 : UInt<3>[3]
    T_173238[0] := UInt<3>(0)
    T_173238[1] := UInt<3>(1)
    T_173238[2] := UInt<3>(2)
    wire T_173239 : UInt<2>[2]
    T_173239[0] := UInt<2>(0)
    T_173239[1] := UInt<2>(1)
    wire T_173240 : UInt<2>[3]
    T_173240[0] := UInt<2>(1)
    T_173240[1] := UInt<2>(2)
    T_173240[2] := UInt<2>(3)
    wire T_173241 : UInt<2>[2]
    T_173241[0] := UInt<2>(2)
    T_173241[1] := UInt<2>(3)
    wire T_173242 : UInt<2>[1]
    T_173242[0] := UInt<2>(3)
    wire T_173243 : UInt<3>[3]
    T_173243[0] := UInt<3>(0)
    T_173243[1] := UInt<3>(1)
    T_173243[2] := UInt<3>(2)
    wire T_173244 : UInt<2>[2]
    T_173244[0] := UInt<2>(0)
    T_173244[1] := UInt<2>(1)
    wire T_173245 : UInt<2>[3]
    T_173245[0] := UInt<2>(1)
    T_173245[1] := UInt<2>(2)
    T_173245[2] := UInt<2>(3)
    wire T_173246 : UInt<2>[2]
    T_173246[0] := UInt<2>(2)
    T_173246[1] := UInt<2>(3)
    wire T_173247 : UInt<2>[1]
    T_173247[0] := UInt<2>(3)
    wire T_173248 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_173248.sharers := UInt<1>(0)
    node T_173249 = eq(xact.a_type, UInt<3>(2))
    node T_173250 = and(xact.is_builtin_type, T_173249)
    node T_173251 = eq(xact.a_type, UInt<3>(3))
    node T_173252 = and(xact.is_builtin_type, T_173251)
    node T_173253 = or(T_173250, T_173252)
    node T_173254 = bits(xact.union, 5, 1)
    wire T_173255 : UInt<5>
    T_173255 := T_173254
    when T_173253 : T_173255 := UInt<5>(1)
    node T_173256 = eq(T_173255, UInt<5>(1))
    node T_173257 = eq(T_173255, UInt<5>(7))
    node T_173258 = or(T_173256, T_173257)
    node T_173259 = bit(T_173255, 3)
    node T_173260 = eq(T_173255, UInt<5>(4))
    node T_173261 = or(T_173259, T_173260)
    node T_173262 = or(T_173258, T_173261)
    wire T_173263 : UInt<2>
    T_173263 := UInt<2>(1)
    when T_173262 : T_173263 := UInt<2>(2)
    wire T_173264 : UInt<2>
    T_173264 := T_173263
    when outer.grant.bits.is_builtin_type : T_173264 := UInt<2>(0)
    wire T_173265 : UInt<3>[3]
    T_173265[0] := UInt<3>(0)
    T_173265[1] := UInt<3>(1)
    T_173265[2] := UInt<3>(2)
    wire T_173266 : UInt<0>[1]
    T_173266[0] := UInt<0>(0)
    wire T_173267 : UInt<2>[2]
    T_173267[0] := UInt<2>(1)
    T_173267[1] := UInt<2>(2)
    wire T_173268 : UInt<2>[2]
    T_173268[0] := UInt<2>(1)
    T_173268[1] := UInt<2>(2)
    wire T_173269 : UInt<2>[1]
    T_173269[0] := UInt<2>(2)
    wire T_173270 : UInt<3>[3]
    T_173270[0] := UInt<3>(0)
    T_173270[1] := UInt<3>(1)
    T_173270[2] := UInt<3>(2)
    wire T_173271 : UInt<0>[1]
    T_173271[0] := UInt<0>(0)
    wire T_173272 : UInt<2>[2]
    T_173272[0] := UInt<2>(1)
    T_173272[1] := UInt<2>(2)
    wire T_173273 : UInt<2>[2]
    T_173273[0] := UInt<2>(1)
    T_173273[1] := UInt<2>(2)
    wire T_173274 : UInt<2>[1]
    T_173274[0] := UInt<2>(2)
    wire T_173275 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_173275.state := T_173264
    wire T_173276 : UInt<3>[3]
    T_173276[0] := UInt<3>(0)
    T_173276[1] := UInt<3>(1)
    T_173276[2] := UInt<3>(2)
    wire T_173277 : UInt<2>[2]
    T_173277[0] := UInt<2>(0)
    T_173277[1] := UInt<2>(1)
    wire T_173278 : UInt<2>[3]
    T_173278[0] := UInt<2>(1)
    T_173278[1] := UInt<2>(2)
    T_173278[2] := UInt<2>(3)
    wire T_173279 : UInt<2>[2]
    T_173279[0] := UInt<2>(2)
    T_173279[1] := UInt<2>(3)
    wire T_173280 : UInt<2>[1]
    T_173280[0] := UInt<2>(3)
    wire T_173281 : UInt<3>[3]
    T_173281[0] := UInt<3>(0)
    T_173281[1] := UInt<3>(1)
    T_173281[2] := UInt<3>(2)
    wire T_173282 : UInt<2>[2]
    T_173282[0] := UInt<2>(0)
    T_173282[1] := UInt<2>(1)
    wire T_173283 : UInt<2>[3]
    T_173283[0] := UInt<2>(1)
    T_173283[1] := UInt<2>(2)
    T_173283[2] := UInt<2>(3)
    wire T_173284 : UInt<2>[2]
    T_173284[0] := UInt<2>(2)
    T_173284[1] := UInt<2>(3)
    wire T_173285 : UInt<2>[1]
    T_173285[0] := UInt<2>(3)
    wire T_173286 : UInt<3>[3]
    T_173286[0] := UInt<3>(0)
    T_173286[1] := UInt<3>(1)
    T_173286[2] := UInt<3>(2)
    wire T_173287 : UInt<0>[1]
    T_173287[0] := UInt<0>(0)
    wire T_173288 : UInt<2>[2]
    T_173288[0] := UInt<2>(1)
    T_173288[1] := UInt<2>(2)
    wire T_173289 : UInt<2>[2]
    T_173289[0] := UInt<2>(1)
    T_173289[1] := UInt<2>(2)
    wire T_173290 : UInt<2>[1]
    T_173290[0] := UInt<2>(2)
    wire T_173291 : UInt<3>[3]
    T_173291[0] := UInt<3>(0)
    T_173291[1] := UInt<3>(1)
    T_173291[2] := UInt<3>(2)
    wire T_173292 : UInt<2>[2]
    T_173292[0] := UInt<2>(0)
    T_173292[1] := UInt<2>(1)
    wire T_173293 : UInt<2>[3]
    T_173293[0] := UInt<2>(1)
    T_173293[1] := UInt<2>(2)
    T_173293[2] := UInt<2>(3)
    wire T_173294 : UInt<2>[2]
    T_173294[0] := UInt<2>(2)
    T_173294[1] := UInt<2>(3)
    wire T_173295 : UInt<2>[1]
    T_173295[0] := UInt<2>(3)
    wire T_173296 : UInt<3>[3]
    T_173296[0] := UInt<3>(0)
    T_173296[1] := UInt<3>(1)
    T_173296[2] := UInt<3>(2)
    wire T_173297 : UInt<2>[2]
    T_173297[0] := UInt<2>(0)
    T_173297[1] := UInt<2>(1)
    wire T_173298 : UInt<2>[3]
    T_173298[0] := UInt<2>(1)
    T_173298[1] := UInt<2>(2)
    T_173298[2] := UInt<2>(3)
    wire T_173299 : UInt<2>[2]
    T_173299[0] := UInt<2>(2)
    T_173299[1] := UInt<2>(3)
    wire T_173300 : UInt<2>[1]
    T_173300[0] := UInt<2>(3)
    wire T_173301 : UInt<3>[3]
    T_173301[0] := UInt<3>(0)
    T_173301[1] := UInt<3>(1)
    T_173301[2] := UInt<3>(2)
    wire T_173302 : UInt<0>[1]
    T_173302[0] := UInt<0>(0)
    wire T_173303 : UInt<2>[2]
    T_173303[0] := UInt<2>(1)
    T_173303[1] := UInt<2>(2)
    wire T_173304 : UInt<2>[2]
    T_173304[0] := UInt<2>(1)
    T_173304[1] := UInt<2>(2)
    wire T_173305 : UInt<2>[1]
    T_173305[0] := UInt<2>(2)
    wire pending_coh_on_ognt : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_ognt.inner := T_173248
    pending_coh_on_ognt.outer := T_173275
    
    
    node T_173306 = eq(pending_coh.inner.sharers, pending_coh_on_ognt.inner.sharers)
    node T_173307 = eq(pending_coh.outer.state, pending_coh_on_ognt.outer.state)
    node T_173308 = and(T_173306, T_173307)
    node T_173309 = eq(T_173308, UInt<1>(0))
    node T_173310 = and(ognt_data_done, T_173309)
    when T_173310 : 
      pending_meta_write := UInt<1>(1)
      pending_coh := pending_coh_on_ognt
    
    
    node T_173311 = and(outer.grant.ready, outer.grant.valid)
    wire T_173312 : UInt<3>[2]
    T_173312[0] := UInt<3>(5)
    T_173312[1] := UInt<3>(4)
    node T_173313 = eq(T_173312[0], outer.grant.bits.g_type)
    node T_173314 = eq(T_173312[1], outer.grant.bits.g_type)
    node T_173315 = or(UInt<1>(0), T_173313)
    node T_173316 = or(T_173315, T_173314)
    node T_173317 = eq(T_172503[0], outer.grant.bits.g_type)
    node T_173318 = or(UInt<1>(0), T_173317)
    wire T_173319 : UInt<1>
    T_173319 := T_173318
    when outer.grant.bits.is_builtin_type : T_173319 := T_173316
    node T_173320 = and(T_173311, T_173319)
    when T_173320 : 
      accessor T_173321 = data_buffer[outer.grant.bits.addr_beat]
      node T_173322 = bits(xact.union, 12, 9)
      node T_173323 = bits(T_173322, 3, 3)
      node T_173324 = mul(UInt<7>(64), T_173323)
      node T_173325 = dshr(outer.grant.bits.data, T_173324)
      amoalu.lhs := T_173325
      node T_173326 = bits(xact.union, 12, 9)
      node T_173327 = bits(T_173326, 3, 3)
      node T_173328 = mul(UInt<7>(64), T_173327)
      node T_173329 = dshr(T_173321, T_173328)
      amoalu.rhs := T_173329
      accessor T_173330 = wmask_buffer[outer.grant.bits.addr_beat]
      node T_173331 = bit(T_173330, 0)
      node T_173332 = bit(T_173330, 1)
      node T_173333 = bit(T_173330, 2)
      node T_173334 = bit(T_173330, 3)
      node T_173335 = bit(T_173330, 4)
      node T_173336 = bit(T_173330, 5)
      node T_173337 = bit(T_173330, 6)
      node T_173338 = bit(T_173330, 7)
      node T_173339 = bit(T_173330, 8)
      node T_173340 = bit(T_173330, 9)
      node T_173341 = bit(T_173330, 10)
      node T_173342 = bit(T_173330, 11)
      node T_173343 = bit(T_173330, 12)
      node T_173344 = bit(T_173330, 13)
      node T_173345 = bit(T_173330, 14)
      node T_173346 = bit(T_173330, 15)
      wire T_173347 : UInt<1>[16]
      T_173347[0] := T_173331
      T_173347[1] := T_173332
      T_173347[2] := T_173333
      T_173347[3] := T_173334
      T_173347[4] := T_173335
      T_173347[5] := T_173336
      T_173347[6] := T_173337
      T_173347[7] := T_173338
      T_173347[8] := T_173339
      T_173347[9] := T_173340
      T_173347[10] := T_173341
      T_173347[11] := T_173342
      T_173347[12] := T_173343
      T_173347[13] := T_173344
      T_173347[14] := T_173345
      T_173347[15] := T_173346
      node T_173348 = subw(UInt<8>(0), UInt<4>(8))
      node T_173349 = subw(UInt<8>(0), UInt<4>(8))
      node T_173350 = subw(UInt<8>(0), UInt<4>(8))
      node T_173351 = subw(UInt<8>(0), UInt<4>(8))
      node T_173352 = subw(UInt<8>(0), UInt<4>(8))
      node T_173353 = subw(UInt<8>(0), UInt<4>(8))
      node T_173354 = subw(UInt<8>(0), UInt<4>(8))
      node T_173355 = subw(UInt<8>(0), UInt<4>(8))
      node T_173356 = subw(UInt<8>(0), UInt<4>(8))
      node T_173357 = subw(UInt<8>(0), UInt<4>(8))
      node T_173358 = subw(UInt<8>(0), UInt<4>(8))
      node T_173359 = subw(UInt<8>(0), UInt<4>(8))
      node T_173360 = subw(UInt<8>(0), UInt<4>(8))
      node T_173361 = subw(UInt<8>(0), UInt<4>(8))
      node T_173362 = subw(UInt<8>(0), UInt<4>(8))
      node T_173363 = subw(UInt<8>(0), UInt<4>(8))
      wire T_173364 : UInt<8>[16]
      T_173364[0] := T_173348
      T_173364[1] := T_173349
      T_173364[2] := T_173350
      T_173364[3] := T_173351
      T_173364[4] := T_173352
      T_173364[5] := T_173353
      T_173364[6] := T_173354
      T_173364[7] := T_173355
      T_173364[8] := T_173356
      T_173364[9] := T_173357
      T_173364[10] := T_173358
      T_173364[11] := T_173359
      T_173364[12] := T_173360
      T_173364[13] := T_173361
      T_173364[14] := T_173362
      T_173364[15] := T_173363
      node T_173365 = cat(T_173364[15], T_173364[14])
      node T_173366 = cat(T_173364[13], T_173364[12])
      node T_173367 = cat(T_173365, T_173366)
      node T_173368 = cat(T_173364[11], T_173364[10])
      node T_173369 = cat(T_173364[9], T_173364[8])
      node T_173370 = cat(T_173368, T_173369)
      node T_173371 = cat(T_173367, T_173370)
      node T_173372 = cat(T_173364[7], T_173364[6])
      node T_173373 = cat(T_173364[5], T_173364[4])
      node T_173374 = cat(T_173372, T_173373)
      node T_173375 = cat(T_173364[3], T_173364[2])
      node T_173376 = cat(T_173364[1], T_173364[0])
      node T_173377 = cat(T_173375, T_173376)
      node T_173378 = cat(T_173374, T_173377)
      node T_173379 = cat(T_173371, T_173378)
      accessor T_173380 = data_buffer[outer.grant.bits.addr_beat]
      node T_173381 = not(T_173379)
      node T_173382 = and(T_173381, outer.grant.bits.data)
      node T_173383 = eq(xact.a_type, UInt<3>(4))
      node T_173384 = and(xact.is_builtin_type, T_173383)
      node T_173385 = bits(xact.union, 12, 9)
      node T_173386 = bits(T_173385, 3, 3)
      node T_173387 = mul(UInt<7>(64), T_173386)
      node T_173388 = dshl(amoalu.out, T_173387)
      wire T_173389 : UInt<128>
      T_173389 := T_173321
      when T_173384 : T_173389 := T_173388
      node T_173390 = and(T_173379, T_173389)
      node T_173391 = or(T_173382, T_173390)
      T_173380 := T_173391
      accessor T_173392 = wmask_buffer[outer.grant.bits.addr_beat]
      T_173392 := SInt<1>(-1)
      
      
      node T_173393 = eq(xact.a_type, UInt<3>(4))
      node T_173394 = eq(xact.addr_beat, outer.grant.bits.addr_beat)
      node T_173395 = and(T_173393, T_173394)
      when T_173395 : xact.data := outer.grant.bits.data
    node T_173396 = and(inner.release.ready, inner.release.valid)
    node T_173397 = eq(T_172476[0], inner.release.bits.r_type)
    node T_173398 = eq(T_172476[1], inner.release.bits.r_type)
    node T_173399 = eq(T_172476[2], inner.release.bits.r_type)
    node T_173400 = or(UInt<1>(0), T_173397)
    node T_173401 = or(T_173400, T_173398)
    node T_173402 = or(T_173401, T_173399)
    node T_173403 = and(T_173396, T_173402)
    node T_173404 = subw(UInt<4>(0), UInt<3>(4))
    node T_173405 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_173406 = and(T_173404, T_173405)
    node T_173407 = or(pending_ignt_data, T_173406)
    node T_173408 = and(outer.grant.ready, outer.grant.valid)
    wire T_173409 : UInt<3>[2]
    T_173409[0] := UInt<3>(5)
    T_173409[1] := UInt<3>(4)
    node T_173410 = eq(T_173409[0], outer.grant.bits.g_type)
    node T_173411 = eq(T_173409[1], outer.grant.bits.g_type)
    node T_173412 = or(UInt<1>(0), T_173410)
    node T_173413 = or(T_173412, T_173411)
    node T_173414 = eq(T_172503[0], outer.grant.bits.g_type)
    node T_173415 = or(UInt<1>(0), T_173414)
    wire T_173416 : UInt<1>
    T_173416 := T_173415
    when outer.grant.bits.is_builtin_type : T_173416 := T_173413
    node T_173417 = and(T_173408, T_173416)
    node T_173418 = subw(UInt<4>(0), UInt<3>(4))
    node T_173419 = dshl(UInt<1>(1), outer.grant.bits.addr_beat)
    node T_173420 = and(T_173418, T_173419)
    node T_173421 = or(T_173407, T_173420)
    node T_173422 = subw(UInt<4>(0), UInt<3>(4))
    node T_173423 = dshl(UInt<1>(1), data.resp.bits.addr_beat)
    node T_173424 = and(T_173422, T_173423)
    node T_173425 = or(T_173421, T_173424)
    pending_ignt_data := T_173425
    ignt_q.deq.ready := ignt_data_done
    node T_173426 = eq(state, UInt<4>(7))
    node T_173427 = and(T_173426, ignt_q.deq.valid)
    wire T_173428 : UInt<3>[2]
    T_173428[0] := UInt<3>(5)
    T_173428[1] := UInt<3>(4)
    node T_173429 = eq(T_173428[0], inner.grant.bits.g_type)
    node T_173430 = eq(T_173428[1], inner.grant.bits.g_type)
    node T_173431 = or(UInt<1>(0), T_173429)
    node T_173432 = or(T_173431, T_173430)
    node T_173433 = eq(T_172447[0], inner.grant.bits.g_type)
    node T_173434 = eq(T_172447[1], inner.grant.bits.g_type)
    node T_173435 = or(UInt<1>(0), T_173433)
    node T_173436 = or(T_173435, T_173434)
    wire T_173437 : UInt<1>
    T_173437 := T_173436
    when inner.grant.bits.is_builtin_type : T_173437 := T_173432
    node T_173438 = eq(T_173437, UInt<1>(0))
    node T_173439 = dshr(pending_ignt_data, ignt_data_idx)
    node T_173440 = bit(T_173439, 0)
    node T_173441 = or(T_173438, T_173440)
    node T_173442 = and(T_173427, T_173441)
    inner.grant.valid := T_173442
    node T_173443 = eq(xact.a_type, UInt<3>(4))
    accessor T_173444 = data_buffer[ignt_data_idx]
    wire T_173445 : UInt<128>
    T_173445 := T_173444
    when T_173443 : T_173445 := xact.data
    node T_173446 = eq(UInt<3>(5), xact.a_type)
    wire T_173447 : UInt<3>
    T_173447 := UInt<3>(3)
    when T_173446 : T_173447 := UInt<3>(1)
    node T_173448 = eq(UInt<3>(4), xact.a_type)
    wire T_173449 : UInt<3>
    T_173449 := T_173447
    when T_173448 : T_173449 := UInt<3>(4)
    node T_173450 = eq(UInt<3>(3), xact.a_type)
    wire T_173451 : UInt<3>
    T_173451 := T_173449
    when T_173450 : T_173451 := UInt<3>(3)
    node T_173452 = eq(UInt<3>(2), xact.a_type)
    wire T_173453 : UInt<3>
    T_173453 := T_173451
    when T_173452 : T_173453 := UInt<3>(3)
    node T_173454 = eq(UInt<3>(1), xact.a_type)
    wire T_173455 : UInt<3>
    T_173455 := T_173453
    when T_173454 : T_173455 := UInt<3>(5)
    node T_173456 = eq(UInt<3>(0), xact.a_type)
    wire T_173457 : UInt<3>
    T_173457 := T_173455
    when T_173456 : T_173457 := UInt<3>(4)
    node T_173458 = eq(xact.a_type, UInt<1>(0))
    node T_173459 = eq(pending_coh.inner.sharers, UInt<1>(0))
    node T_173460 = eq(T_173459, UInt<1>(0))
    wire T_173461 : UInt<2>
    T_173461 := UInt<2>(1)
    when T_173460 : T_173461 := UInt<2>(0)
    wire T_173462 : UInt<2>
    T_173462 := UInt<2>(1)
    when T_173458 : T_173462 := T_173461
    wire T_173463 : UInt<2>
    T_173463 := T_173462
    when xact.is_builtin_type : T_173463 := T_173457
    wire T_173464 : UInt<3>[3]
    T_173464[0] := UInt<3>(0)
    T_173464[1] := UInt<3>(1)
    T_173464[2] := UInt<3>(2)
    wire T_173465 : UInt<2>[2]
    T_173465[0] := UInt<2>(0)
    T_173465[1] := UInt<2>(1)
    wire T_173466 : UInt<2>[3]
    T_173466[0] := UInt<2>(1)
    T_173466[1] := UInt<2>(2)
    T_173466[2] := UInt<2>(3)
    wire T_173467 : UInt<2>[2]
    T_173467[0] := UInt<2>(2)
    T_173467[1] := UInt<2>(3)
    wire T_173468 : UInt<2>[1]
    T_173468[0] := UInt<2>(3)
    wire T_173469 : UInt<3>[3]
    T_173469[0] := UInt<3>(0)
    T_173469[1] := UInt<3>(1)
    T_173469[2] := UInt<3>(2)
    wire T_173470 : UInt<2>[2]
    T_173470[0] := UInt<2>(0)
    T_173470[1] := UInt<2>(1)
    wire T_173471 : UInt<2>[3]
    T_173471[0] := UInt<2>(1)
    T_173471[1] := UInt<2>(2)
    T_173471[2] := UInt<2>(3)
    wire T_173472 : UInt<2>[2]
    T_173472[0] := UInt<2>(2)
    T_173472[1] := UInt<2>(3)
    wire T_173473 : UInt<2>[1]
    T_173473[0] := UInt<2>(3)
    wire T_173474 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}
    T_173474.client_id := xact.client_id
    T_173474.is_builtin_type := xact.is_builtin_type
    T_173474.g_type := T_173463
    T_173474.client_xact_id := xact.client_xact_id
    T_173474.manager_xact_id := UInt<1>(1)
    T_173474.addr_beat := ignt_q.deq.bits.addr_beat
    T_173474.data := T_173445
    T_173474.client_xact_id := ignt_q.deq.bits.client_xact_id
    inner.grant.bits := T_173474
    inner.grant.bits.addr_beat := ignt_data_idx
    node T_173475 = dshl(UInt<1>(1), inner.grant.bits.client_id)
    node T_173476 = or(pending_coh.inner.sharers, T_173475)
    wire T_173477 : UInt<5>
    T_173477 := T_173476
    when inner.grant.bits.is_builtin_type : T_173477 := pending_coh.inner.sharers
    wire T_173478 : UInt<3>[3]
    T_173478[0] := UInt<3>(0)
    T_173478[1] := UInt<3>(1)
    T_173478[2] := UInt<3>(2)
    wire T_173479 : UInt<2>[2]
    T_173479[0] := UInt<2>(0)
    T_173479[1] := UInt<2>(1)
    wire T_173480 : UInt<2>[3]
    T_173480[0] := UInt<2>(1)
    T_173480[1] := UInt<2>(2)
    T_173480[2] := UInt<2>(3)
    wire T_173481 : UInt<2>[2]
    T_173481[0] := UInt<2>(2)
    T_173481[1] := UInt<2>(3)
    wire T_173482 : UInt<2>[1]
    T_173482[0] := UInt<2>(3)
    wire T_173483 : UInt<3>[3]
    T_173483[0] := UInt<3>(0)
    T_173483[1] := UInt<3>(1)
    T_173483[2] := UInt<3>(2)
    wire T_173484 : UInt<2>[2]
    T_173484[0] := UInt<2>(0)
    T_173484[1] := UInt<2>(1)
    wire T_173485 : UInt<2>[3]
    T_173485[0] := UInt<2>(1)
    T_173485[1] := UInt<2>(2)
    T_173485[2] := UInt<2>(3)
    wire T_173486 : UInt<2>[2]
    T_173486[0] := UInt<2>(2)
    T_173486[1] := UInt<2>(3)
    wire T_173487 : UInt<2>[1]
    T_173487[0] := UInt<2>(3)
    wire T_173488 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_173488.sharers := T_173477
    wire T_173489 : UInt<3>[3]
    T_173489[0] := UInt<3>(0)
    T_173489[1] := UInt<3>(1)
    T_173489[2] := UInt<3>(2)
    wire T_173490 : UInt<2>[2]
    T_173490[0] := UInt<2>(0)
    T_173490[1] := UInt<2>(1)
    wire T_173491 : UInt<2>[3]
    T_173491[0] := UInt<2>(1)
    T_173491[1] := UInt<2>(2)
    T_173491[2] := UInt<2>(3)
    wire T_173492 : UInt<2>[2]
    T_173492[0] := UInt<2>(2)
    T_173492[1] := UInt<2>(3)
    wire T_173493 : UInt<2>[1]
    T_173493[0] := UInt<2>(3)
    wire T_173494 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_173494 := pending_coh.outer
    when ognt_data_done : T_173494 := pending_coh_on_ognt.outer
    wire T_173495 : UInt<3>[3]
    T_173495[0] := UInt<3>(0)
    T_173495[1] := UInt<3>(1)
    T_173495[2] := UInt<3>(2)
    wire T_173496 : UInt<2>[2]
    T_173496[0] := UInt<2>(0)
    T_173496[1] := UInt<2>(1)
    wire T_173497 : UInt<2>[3]
    T_173497[0] := UInt<2>(1)
    T_173497[1] := UInt<2>(2)
    T_173497[2] := UInt<2>(3)
    wire T_173498 : UInt<2>[2]
    T_173498[0] := UInt<2>(2)
    T_173498[1] := UInt<2>(3)
    wire T_173499 : UInt<2>[1]
    T_173499[0] := UInt<2>(3)
    wire T_173500 : UInt<3>[3]
    T_173500[0] := UInt<3>(0)
    T_173500[1] := UInt<3>(1)
    T_173500[2] := UInt<3>(2)
    wire T_173501 : UInt<2>[2]
    T_173501[0] := UInt<2>(0)
    T_173501[1] := UInt<2>(1)
    wire T_173502 : UInt<2>[3]
    T_173502[0] := UInt<2>(1)
    T_173502[1] := UInt<2>(2)
    T_173502[2] := UInt<2>(3)
    wire T_173503 : UInt<2>[2]
    T_173503[0] := UInt<2>(2)
    T_173503[1] := UInt<2>(3)
    wire T_173504 : UInt<2>[1]
    T_173504[0] := UInt<2>(3)
    wire T_173505 : UInt<3>[3]
    T_173505[0] := UInt<3>(0)
    T_173505[1] := UInt<3>(1)
    T_173505[2] := UInt<3>(2)
    wire T_173506 : UInt<0>[1]
    T_173506[0] := UInt<0>(0)
    wire T_173507 : UInt<2>[2]
    T_173507[0] := UInt<2>(1)
    T_173507[1] := UInt<2>(2)
    wire T_173508 : UInt<2>[2]
    T_173508[0] := UInt<2>(1)
    T_173508[1] := UInt<2>(2)
    wire T_173509 : UInt<2>[1]
    T_173509[0] := UInt<2>(2)
    wire T_173510 : UInt<3>[3]
    T_173510[0] := UInt<3>(0)
    T_173510[1] := UInt<3>(1)
    T_173510[2] := UInt<3>(2)
    wire T_173511 : UInt<2>[2]
    T_173511[0] := UInt<2>(0)
    T_173511[1] := UInt<2>(1)
    wire T_173512 : UInt<2>[3]
    T_173512[0] := UInt<2>(1)
    T_173512[1] := UInt<2>(2)
    T_173512[2] := UInt<2>(3)
    wire T_173513 : UInt<2>[2]
    T_173513[0] := UInt<2>(2)
    T_173513[1] := UInt<2>(3)
    wire T_173514 : UInt<2>[1]
    T_173514[0] := UInt<2>(3)
    wire T_173515 : UInt<3>[3]
    T_173515[0] := UInt<3>(0)
    T_173515[1] := UInt<3>(1)
    T_173515[2] := UInt<3>(2)
    wire T_173516 : UInt<2>[2]
    T_173516[0] := UInt<2>(0)
    T_173516[1] := UInt<2>(1)
    wire T_173517 : UInt<2>[3]
    T_173517[0] := UInt<2>(1)
    T_173517[1] := UInt<2>(2)
    T_173517[2] := UInt<2>(3)
    wire T_173518 : UInt<2>[2]
    T_173518[0] := UInt<2>(2)
    T_173518[1] := UInt<2>(3)
    wire T_173519 : UInt<2>[1]
    T_173519[0] := UInt<2>(3)
    wire T_173520 : UInt<3>[3]
    T_173520[0] := UInt<3>(0)
    T_173520[1] := UInt<3>(1)
    T_173520[2] := UInt<3>(2)
    wire T_173521 : UInt<0>[1]
    T_173521[0] := UInt<0>(0)
    wire T_173522 : UInt<2>[2]
    T_173522[0] := UInt<2>(1)
    T_173522[1] := UInt<2>(2)
    wire T_173523 : UInt<2>[2]
    T_173523[0] := UInt<2>(1)
    T_173523[1] := UInt<2>(2)
    wire T_173524 : UInt<2>[1]
    T_173524[0] := UInt<2>(2)
    wire pending_coh_on_ignt : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_ignt.inner := T_173488
    pending_coh_on_ignt.outer := T_173494
    node T_173525 = and(inner.grant.ready, inner.grant.valid)
    
    
    node T_173526 = eq(pending_coh.inner.sharers, pending_coh_on_ignt.inner.sharers)
    node T_173527 = eq(pending_coh.outer.state, pending_coh_on_ignt.outer.state)
    node T_173528 = and(T_173526, T_173527)
    node T_173529 = eq(T_173528, UInt<1>(0))
    node T_173530 = and(T_173525, T_173529)
    when T_173530 : 
      pending_meta_write := UInt<1>(1)
      pending_coh := pending_coh_on_ignt
    node T_173531 = eq(state, UInt<4>(7))
    inner.finish.ready := T_173531
    node T_173532 = and(data.read.ready, data.read.valid)
    node T_173533 = subw(UInt<4>(0), UInt<3>(4))
    node T_173534 = not(T_173533)
    node T_173535 = dshl(UInt<1>(1), data.read.bits.addr_beat)
    node T_173536 = not(T_173535)
    node T_173537 = or(T_173534, T_173536)
    node T_173538 = and(pending_reads, T_173537)
    node T_173539 = and(inner.release.ready, inner.release.valid)
    node T_173540 = eq(T_172476[0], inner.release.bits.r_type)
    node T_173541 = eq(T_172476[1], inner.release.bits.r_type)
    node T_173542 = eq(T_172476[2], inner.release.bits.r_type)
    node T_173543 = or(UInt<1>(0), T_173540)
    node T_173544 = or(T_173543, T_173541)
    node T_173545 = or(T_173544, T_173542)
    node T_173546 = and(T_173539, T_173545)
    node T_173547 = subw(UInt<4>(0), UInt<3>(4))
    node T_173548 = not(T_173547)
    node T_173549 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_173550 = not(T_173549)
    node T_173551 = or(T_173548, T_173550)
    node T_173552 = and(T_173538, T_173551)
    node T_173553 = and(outer.grant.ready, outer.grant.valid)
    wire T_173554 : UInt<3>[2]
    T_173554[0] := UInt<3>(5)
    T_173554[1] := UInt<3>(4)
    node T_173555 = eq(T_173554[0], outer.grant.bits.g_type)
    node T_173556 = eq(T_173554[1], outer.grant.bits.g_type)
    node T_173557 = or(UInt<1>(0), T_173555)
    node T_173558 = or(T_173557, T_173556)
    node T_173559 = eq(T_172503[0], outer.grant.bits.g_type)
    node T_173560 = or(UInt<1>(0), T_173559)
    wire T_173561 : UInt<1>
    T_173561 := T_173560
    when outer.grant.bits.is_builtin_type : T_173561 := T_173558
    node T_173562 = and(T_173553, T_173561)
    node T_173563 = subw(UInt<4>(0), UInt<3>(4))
    node T_173564 = not(T_173563)
    node T_173565 = dshl(UInt<1>(1), outer.grant.bits.addr_beat)
    node T_173566 = not(T_173565)
    node T_173567 = or(T_173564, T_173566)
    node T_173568 = and(T_173552, T_173567)
    wire T_173569 : UInt<3>[3]
    T_173569[0] := UInt<3>(0)
    T_173569[1] := UInt<3>(1)
    T_173569[2] := UInt<3>(4)
    node T_173570 = eq(T_173569[0], inner.acquire.bits.a_type)
    node T_173571 = eq(T_173569[1], inner.acquire.bits.a_type)
    node T_173572 = eq(T_173569[2], inner.acquire.bits.a_type)
    node T_173573 = or(UInt<1>(0), T_173570)
    node T_173574 = or(T_173573, T_173571)
    node T_173575 = or(T_173574, T_173572)
    node T_173576 = and(inner.acquire.bits.is_builtin_type, T_173575)
    node T_173577 = and(inner.acquire.ready, inner.acquire.valid)
    node T_173578 = and(T_173577, T_173576)
    node T_173579 = subw(UInt<4>(0), UInt<3>(4))
    node T_173580 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_173581 = and(T_173579, T_173580)
    node T_173582 = or(T_173568, T_173581)
    node T_173583 = eq(inner.acquire.bits.a_type, UInt<3>(4))
    node T_173584 = and(inner.acquire.bits.is_builtin_type, T_173583)
    node T_173585 = bits(inner.acquire.bits.union, 12, 9)
    node T_173586 = bits(T_173585, 3, 3)
    node T_173587 = dshl(UInt<1>(1), T_173586)
    node T_173588 = bit(T_173587, 0)
    node T_173589 = bit(T_173587, 1)
    node T_173590 = bit(T_173587, 2)
    wire T_173591 : UInt<1>[3]
    T_173591[0] := T_173588
    T_173591[1] := T_173589
    T_173591[2] := T_173590
    node T_173592 = subw(UInt<8>(0), UInt<4>(8))
    node T_173593 = subw(UInt<8>(0), UInt<4>(8))
    node T_173594 = subw(UInt<8>(0), UInt<4>(8))
    wire T_173595 : UInt<8>[3]
    T_173595[0] := T_173592
    T_173595[1] := T_173593
    T_173595[2] := T_173594
    node T_173596 = cat(T_173595[1], T_173595[0])
    node T_173597 = cat(T_173595[2], T_173596)
    node T_173598 = eq(inner.acquire.bits.a_type, UInt<3>(3))
    node T_173599 = and(inner.acquire.bits.is_builtin_type, T_173598)
    node T_173600 = eq(inner.acquire.bits.a_type, UInt<3>(2))
    node T_173601 = and(inner.acquire.bits.is_builtin_type, T_173600)
    node T_173602 = or(T_173599, T_173601)
    node T_173603 = bits(inner.acquire.bits.union, 16, 1)
    wire T_173604 : UInt<16>
    T_173604 := UInt<16>(0)
    when T_173602 : T_173604 := T_173603
    wire T_173605 : UInt<16>
    T_173605 := T_173604
    when T_173584 : T_173605 := T_173597
    wire T_173606 : UInt<3>[3]
    T_173606[0] := UInt<3>(0)
    T_173606[1] := UInt<3>(1)
    T_173606[2] := UInt<3>(2)
    wire T_173607 : UInt<2>[2]
    T_173607[0] := UInt<2>(0)
    T_173607[1] := UInt<2>(1)
    wire T_173608 : UInt<2>[3]
    T_173608[0] := UInt<2>(1)
    T_173608[1] := UInt<2>(2)
    T_173608[2] := UInt<2>(3)
    wire T_173609 : UInt<2>[2]
    T_173609[0] := UInt<2>(2)
    T_173609[1] := UInt<2>(3)
    wire T_173610 : UInt<2>[1]
    T_173610[0] := UInt<2>(3)
    node T_173611 = asUInt(SInt<16>(-1))
    node T_173612 = neq(T_173605, T_173611)
    node T_173613 = and(inner.acquire.ready, inner.acquire.valid)
    node T_173614 = and(T_173613, T_173612)
    node T_173615 = and(T_173614, UInt<1>(0))
    node T_173616 = subw(UInt<4>(0), UInt<3>(4))
    node T_173617 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_173618 = and(T_173616, T_173617)
    node T_173619 = or(T_173582, T_173618)
    pending_reads := T_173619
    node T_173620 = bit(pending_reads, 0)
    node T_173621 = bit(pending_reads, 1)
    node T_173622 = bit(pending_reads, 2)
    node T_173623 = bit(pending_reads, 3)
    wire T_173624 : UInt<1>[4]
    T_173624[0] := T_173620
    T_173624[1] := T_173621
    T_173624[2] := T_173622
    T_173624[3] := T_173623
    wire T_173625 : UInt<2>
    T_173625 := UInt<2>(3)
    when T_173624[2] : T_173625 := UInt<2>(2)
    wire T_173626 : UInt<2>
    T_173626 := T_173625
    when T_173624[1] : T_173626 := UInt<1>(1)
    wire curr_read_beat : UInt<2>
    curr_read_beat := T_173626
    when T_173624[0] : curr_read_beat := UInt<1>(0)
    node T_173627 = eq(state, UInt<4>(7))
    node T_173628 = eq(pending_reads, UInt<1>(0))
    node T_173629 = eq(T_173628, UInt<1>(0))
    node T_173630 = and(T_173627, T_173629)
    node T_173631 = eq(pending_ognt, UInt<1>(0))
    node T_173632 = and(T_173630, T_173631)
    data.read.valid := T_173632
    data.read.bits.id := UInt<1>(1)
    data.read.bits.way_en := xact_way_en
    node T_173633 = bits(xact.addr_block, 11, 0)
    data.read.bits.addr_idx := T_173633
    data.read.bits.addr_beat := curr_read_beat
    node T_173634 = subw(UInt<4>(0), UInt<3>(4))
    node T_173635 = not(T_173634)
    node T_173636 = dshl(UInt<1>(1), data.resp.bits.addr_beat)
    node T_173637 = not(T_173636)
    node T_173638 = or(T_173635, T_173637)
    node T_173639 = and(pending_resps, T_173638)
    node T_173640 = and(data.read.ready, data.read.valid)
    node T_173641 = subw(UInt<4>(0), UInt<3>(4))
    node T_173642 = dshl(UInt<1>(1), data.read.bits.addr_beat)
    node T_173643 = and(T_173641, T_173642)
    node T_173644 = or(T_173639, T_173643)
    pending_resps := T_173644
    when data.resp.valid : 
      accessor T_173645 = data_buffer[data.resp.bits.addr_beat]
      node T_173646 = bits(xact.union, 12, 9)
      node T_173647 = bits(T_173646, 3, 3)
      node T_173648 = mul(UInt<7>(64), T_173647)
      node T_173649 = dshr(data.resp.bits.data, T_173648)
      amoalu.lhs := T_173649
      node T_173650 = bits(xact.union, 12, 9)
      node T_173651 = bits(T_173650, 3, 3)
      node T_173652 = mul(UInt<7>(64), T_173651)
      node T_173653 = dshr(T_173645, T_173652)
      amoalu.rhs := T_173653
      accessor T_173654 = wmask_buffer[data.resp.bits.addr_beat]
      node T_173655 = bit(T_173654, 0)
      node T_173656 = bit(T_173654, 1)
      node T_173657 = bit(T_173654, 2)
      node T_173658 = bit(T_173654, 3)
      node T_173659 = bit(T_173654, 4)
      node T_173660 = bit(T_173654, 5)
      node T_173661 = bit(T_173654, 6)
      node T_173662 = bit(T_173654, 7)
      node T_173663 = bit(T_173654, 8)
      node T_173664 = bit(T_173654, 9)
      node T_173665 = bit(T_173654, 10)
      node T_173666 = bit(T_173654, 11)
      node T_173667 = bit(T_173654, 12)
      node T_173668 = bit(T_173654, 13)
      node T_173669 = bit(T_173654, 14)
      node T_173670 = bit(T_173654, 15)
      wire T_173671 : UInt<1>[16]
      T_173671[0] := T_173655
      T_173671[1] := T_173656
      T_173671[2] := T_173657
      T_173671[3] := T_173658
      T_173671[4] := T_173659
      T_173671[5] := T_173660
      T_173671[6] := T_173661
      T_173671[7] := T_173662
      T_173671[8] := T_173663
      T_173671[9] := T_173664
      T_173671[10] := T_173665
      T_173671[11] := T_173666
      T_173671[12] := T_173667
      T_173671[13] := T_173668
      T_173671[14] := T_173669
      T_173671[15] := T_173670
      node T_173672 = subw(UInt<8>(0), UInt<4>(8))
      node T_173673 = subw(UInt<8>(0), UInt<4>(8))
      node T_173674 = subw(UInt<8>(0), UInt<4>(8))
      node T_173675 = subw(UInt<8>(0), UInt<4>(8))
      node T_173676 = subw(UInt<8>(0), UInt<4>(8))
      node T_173677 = subw(UInt<8>(0), UInt<4>(8))
      node T_173678 = subw(UInt<8>(0), UInt<4>(8))
      node T_173679 = subw(UInt<8>(0), UInt<4>(8))
      node T_173680 = subw(UInt<8>(0), UInt<4>(8))
      node T_173681 = subw(UInt<8>(0), UInt<4>(8))
      node T_173682 = subw(UInt<8>(0), UInt<4>(8))
      node T_173683 = subw(UInt<8>(0), UInt<4>(8))
      node T_173684 = subw(UInt<8>(0), UInt<4>(8))
      node T_173685 = subw(UInt<8>(0), UInt<4>(8))
      node T_173686 = subw(UInt<8>(0), UInt<4>(8))
      node T_173687 = subw(UInt<8>(0), UInt<4>(8))
      wire T_173688 : UInt<8>[16]
      T_173688[0] := T_173672
      T_173688[1] := T_173673
      T_173688[2] := T_173674
      T_173688[3] := T_173675
      T_173688[4] := T_173676
      T_173688[5] := T_173677
      T_173688[6] := T_173678
      T_173688[7] := T_173679
      T_173688[8] := T_173680
      T_173688[9] := T_173681
      T_173688[10] := T_173682
      T_173688[11] := T_173683
      T_173688[12] := T_173684
      T_173688[13] := T_173685
      T_173688[14] := T_173686
      T_173688[15] := T_173687
      node T_173689 = cat(T_173688[15], T_173688[14])
      node T_173690 = cat(T_173688[13], T_173688[12])
      node T_173691 = cat(T_173689, T_173690)
      node T_173692 = cat(T_173688[11], T_173688[10])
      node T_173693 = cat(T_173688[9], T_173688[8])
      node T_173694 = cat(T_173692, T_173693)
      node T_173695 = cat(T_173691, T_173694)
      node T_173696 = cat(T_173688[7], T_173688[6])
      node T_173697 = cat(T_173688[5], T_173688[4])
      node T_173698 = cat(T_173696, T_173697)
      node T_173699 = cat(T_173688[3], T_173688[2])
      node T_173700 = cat(T_173688[1], T_173688[0])
      node T_173701 = cat(T_173699, T_173700)
      node T_173702 = cat(T_173698, T_173701)
      node T_173703 = cat(T_173695, T_173702)
      accessor T_173704 = data_buffer[data.resp.bits.addr_beat]
      node T_173705 = not(T_173703)
      node T_173706 = and(T_173705, data.resp.bits.data)
      node T_173707 = eq(xact.a_type, UInt<3>(4))
      node T_173708 = and(xact.is_builtin_type, T_173707)
      node T_173709 = bits(xact.union, 12, 9)
      node T_173710 = bits(T_173709, 3, 3)
      node T_173711 = mul(UInt<7>(64), T_173710)
      node T_173712 = dshl(amoalu.out, T_173711)
      wire T_173713 : UInt<128>
      T_173713 := T_173645
      when T_173708 : T_173713 := T_173712
      node T_173714 = and(T_173703, T_173713)
      node T_173715 = or(T_173706, T_173714)
      T_173704 := T_173715
      accessor T_173716 = wmask_buffer[data.resp.bits.addr_beat]
      T_173716 := SInt<1>(-1)
      
      
      node T_173717 = eq(xact.a_type, UInt<3>(4))
      node T_173718 = eq(xact.addr_beat, data.resp.bits.addr_beat)
      node T_173719 = and(T_173717, T_173718)
      when T_173719 : xact.data := data.resp.bits.data
    node T_173720 = and(data.write.ready, data.write.valid)
    node T_173721 = subw(UInt<4>(0), UInt<3>(4))
    node T_173722 = not(T_173721)
    node T_173723 = dshl(UInt<1>(1), data.write.bits.addr_beat)
    node T_173724 = not(T_173723)
    node T_173725 = or(T_173722, T_173724)
    node T_173726 = and(pending_writes, T_173725)
    node T_173727 = and(inner.acquire.ready, inner.acquire.valid)
    wire T_173728 : UInt<3>[3]
    T_173728[0] := UInt<3>(2)
    T_173728[1] := UInt<3>(3)
    T_173728[2] := UInt<3>(4)
    node T_173729 = eq(T_173728[0], inner.acquire.bits.a_type)
    node T_173730 = eq(T_173728[1], inner.acquire.bits.a_type)
    node T_173731 = eq(T_173728[2], inner.acquire.bits.a_type)
    node T_173732 = or(UInt<1>(0), T_173729)
    node T_173733 = or(T_173732, T_173730)
    node T_173734 = or(T_173733, T_173731)
    node T_173735 = and(inner.acquire.bits.is_builtin_type, T_173734)
    node T_173736 = and(T_173727, T_173735)
    node T_173737 = bit(inner.acquire.bits.union, 0)
    node T_173738 = and(T_173736, T_173737)
    node T_173739 = subw(UInt<4>(0), UInt<3>(4))
    node T_173740 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_173741 = and(T_173739, T_173740)
    node T_173742 = or(T_173726, T_173741)
    node T_173743 = and(inner.release.ready, inner.release.valid)
    node T_173744 = eq(T_172476[0], inner.release.bits.r_type)
    node T_173745 = eq(T_172476[1], inner.release.bits.r_type)
    node T_173746 = eq(T_172476[2], inner.release.bits.r_type)
    node T_173747 = or(UInt<1>(0), T_173744)
    node T_173748 = or(T_173747, T_173745)
    node T_173749 = or(T_173748, T_173746)
    node T_173750 = and(T_173743, T_173749)
    node T_173751 = subw(UInt<4>(0), UInt<3>(4))
    node T_173752 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_173753 = and(T_173751, T_173752)
    node T_173754 = or(T_173742, T_173753)
    node T_173755 = and(outer.grant.ready, outer.grant.valid)
    wire T_173756 : UInt<3>[2]
    T_173756[0] := UInt<3>(5)
    T_173756[1] := UInt<3>(4)
    node T_173757 = eq(T_173756[0], outer.grant.bits.g_type)
    node T_173758 = eq(T_173756[1], outer.grant.bits.g_type)
    node T_173759 = or(UInt<1>(0), T_173757)
    node T_173760 = or(T_173759, T_173758)
    node T_173761 = eq(T_172503[0], outer.grant.bits.g_type)
    node T_173762 = or(UInt<1>(0), T_173761)
    wire T_173763 : UInt<1>
    T_173763 := T_173762
    when outer.grant.bits.is_builtin_type : T_173763 := T_173760
    node T_173764 = and(T_173755, T_173763)
    node T_173765 = subw(UInt<4>(0), UInt<3>(4))
    node T_173766 = dshl(UInt<1>(1), outer.grant.bits.addr_beat)
    node T_173767 = and(T_173765, T_173766)
    node T_173768 = or(T_173754, T_173767)
    pending_writes := T_173768
    node T_173769 = bit(pending_writes, 0)
    node T_173770 = bit(pending_writes, 1)
    node T_173771 = bit(pending_writes, 2)
    node T_173772 = bit(pending_writes, 3)
    wire T_173773 : UInt<1>[4]
    T_173773[0] := T_173769
    T_173773[1] := T_173770
    T_173773[2] := T_173771
    T_173773[3] := T_173772
    wire T_173774 : UInt<2>
    T_173774 := UInt<2>(3)
    when T_173773[2] : T_173774 := UInt<2>(2)
    wire T_173775 : UInt<2>
    T_173775 := T_173774
    when T_173773[1] : T_173775 := UInt<1>(1)
    wire curr_write_beat : UInt<2>
    curr_write_beat := T_173775
    when T_173773[0] : curr_write_beat := UInt<1>(0)
    node T_173776 = eq(state, UInt<4>(7))
    node T_173777 = eq(pending_writes, UInt<1>(0))
    node T_173778 = eq(T_173777, UInt<1>(0))
    node T_173779 = and(T_173776, T_173778)
    node T_173780 = eq(pending_ognt, UInt<1>(0))
    node T_173781 = and(T_173779, T_173780)
    node T_173782 = dshr(pending_reads, curr_write_beat)
    node T_173783 = bit(T_173782, 0)
    node T_173784 = eq(T_173783, UInt<1>(0))
    node T_173785 = and(T_173781, T_173784)
    node T_173786 = dshr(pending_resps, curr_write_beat)
    node T_173787 = bit(T_173786, 0)
    node T_173788 = eq(T_173787, UInt<1>(0))
    node T_173789 = and(T_173785, T_173788)
    data.write.valid := T_173789
    data.write.bits.id := UInt<1>(1)
    data.write.bits.way_en := xact_way_en
    node T_173790 = bits(xact.addr_block, 11, 0)
    data.write.bits.addr_idx := T_173790
    data.write.bits.addr_beat := curr_write_beat
    accessor T_173791 = wmask_buffer[curr_write_beat]
    data.write.bits.wmask := T_173791
    accessor T_173792 = data_buffer[curr_write_beat]
    data.write.bits.data := T_173792
    node T_173793 = eq(state, UInt<4>(8))
    meta.write.valid := T_173793
    meta.write.bits.id := UInt<1>(1)
    node T_173794 = bits(xact.addr_block, 11, 0)
    meta.write.bits.idx := T_173794
    meta.write.bits.way_en := xact_way_en
    node T_173795 = dshr(xact.addr_block, UInt<4>(12))
    meta.write.bits.data.tag := T_173795
    meta.write.bits.data.coh := pending_coh
    
    
    node T_173796 = and(inner.acquire.ready, inner.acquire.valid)
    wire T_173797 : UInt<3>[3]
    T_173797[0] := UInt<3>(2)
    T_173797[1] := UInt<3>(3)
    T_173797[2] := UInt<3>(4)
    node T_173798 = eq(T_173797[0], inner.acquire.bits.a_type)
    node T_173799 = eq(T_173797[1], inner.acquire.bits.a_type)
    node T_173800 = eq(T_173797[2], inner.acquire.bits.a_type)
    node T_173801 = or(UInt<1>(0), T_173798)
    node T_173802 = or(T_173801, T_173799)
    node T_173803 = or(T_173802, T_173800)
    node T_173804 = and(inner.acquire.bits.is_builtin_type, T_173803)
    node T_173805 = and(T_173796, T_173804)
    when T_173805 : 
      node T_173806 = eq(inner.acquire.bits.a_type, UInt<3>(4))
      node T_173807 = and(inner.acquire.bits.is_builtin_type, T_173806)
      node T_173808 = bits(inner.acquire.bits.union, 12, 9)
      node T_173809 = bits(T_173808, 3, 3)
      node T_173810 = dshl(UInt<1>(1), T_173809)
      node T_173811 = bit(T_173810, 0)
      node T_173812 = bit(T_173810, 1)
      node T_173813 = bit(T_173810, 2)
      wire T_173814 : UInt<1>[3]
      T_173814[0] := T_173811
      T_173814[1] := T_173812
      T_173814[2] := T_173813
      node T_173815 = subw(UInt<8>(0), UInt<4>(8))
      node T_173816 = subw(UInt<8>(0), UInt<4>(8))
      node T_173817 = subw(UInt<8>(0), UInt<4>(8))
      wire T_173818 : UInt<8>[3]
      T_173818[0] := T_173815
      T_173818[1] := T_173816
      T_173818[2] := T_173817
      node T_173819 = cat(T_173818[1], T_173818[0])
      node T_173820 = cat(T_173818[2], T_173819)
      node T_173821 = eq(inner.acquire.bits.a_type, UInt<3>(3))
      node T_173822 = and(inner.acquire.bits.is_builtin_type, T_173821)
      node T_173823 = eq(inner.acquire.bits.a_type, UInt<3>(2))
      node T_173824 = and(inner.acquire.bits.is_builtin_type, T_173823)
      node T_173825 = or(T_173822, T_173824)
      node T_173826 = bits(inner.acquire.bits.union, 16, 1)
      wire T_173827 : UInt<16>
      T_173827 := UInt<16>(0)
      when T_173825 : T_173827 := T_173826
      wire T_173828 : UInt<16>
      T_173828 := T_173827
      when T_173807 : T_173828 := T_173820
      node T_173829 = bit(T_173828, 0)
      node T_173830 = bit(T_173828, 1)
      node T_173831 = bit(T_173828, 2)
      node T_173832 = bit(T_173828, 3)
      node T_173833 = bit(T_173828, 4)
      node T_173834 = bit(T_173828, 5)
      node T_173835 = bit(T_173828, 6)
      node T_173836 = bit(T_173828, 7)
      node T_173837 = bit(T_173828, 8)
      node T_173838 = bit(T_173828, 9)
      node T_173839 = bit(T_173828, 10)
      node T_173840 = bit(T_173828, 11)
      node T_173841 = bit(T_173828, 12)
      node T_173842 = bit(T_173828, 13)
      node T_173843 = bit(T_173828, 14)
      node T_173844 = bit(T_173828, 15)
      wire T_173845 : UInt<1>[16]
      T_173845[0] := T_173829
      T_173845[1] := T_173830
      T_173845[2] := T_173831
      T_173845[3] := T_173832
      T_173845[4] := T_173833
      T_173845[5] := T_173834
      T_173845[6] := T_173835
      T_173845[7] := T_173836
      T_173845[8] := T_173837
      T_173845[9] := T_173838
      T_173845[10] := T_173839
      T_173845[11] := T_173840
      T_173845[12] := T_173841
      T_173845[13] := T_173842
      T_173845[14] := T_173843
      T_173845[15] := T_173844
      node T_173846 = subw(UInt<8>(0), UInt<4>(8))
      node T_173847 = subw(UInt<8>(0), UInt<4>(8))
      node T_173848 = subw(UInt<8>(0), UInt<4>(8))
      node T_173849 = subw(UInt<8>(0), UInt<4>(8))
      node T_173850 = subw(UInt<8>(0), UInt<4>(8))
      node T_173851 = subw(UInt<8>(0), UInt<4>(8))
      node T_173852 = subw(UInt<8>(0), UInt<4>(8))
      node T_173853 = subw(UInt<8>(0), UInt<4>(8))
      node T_173854 = subw(UInt<8>(0), UInt<4>(8))
      node T_173855 = subw(UInt<8>(0), UInt<4>(8))
      node T_173856 = subw(UInt<8>(0), UInt<4>(8))
      node T_173857 = subw(UInt<8>(0), UInt<4>(8))
      node T_173858 = subw(UInt<8>(0), UInt<4>(8))
      node T_173859 = subw(UInt<8>(0), UInt<4>(8))
      node T_173860 = subw(UInt<8>(0), UInt<4>(8))
      node T_173861 = subw(UInt<8>(0), UInt<4>(8))
      wire T_173862 : UInt<8>[16]
      T_173862[0] := T_173846
      T_173862[1] := T_173847
      T_173862[2] := T_173848
      T_173862[3] := T_173849
      T_173862[4] := T_173850
      T_173862[5] := T_173851
      T_173862[6] := T_173852
      T_173862[7] := T_173853
      T_173862[8] := T_173854
      T_173862[9] := T_173855
      T_173862[10] := T_173856
      T_173862[11] := T_173857
      T_173862[12] := T_173858
      T_173862[13] := T_173859
      T_173862[14] := T_173860
      T_173862[15] := T_173861
      node T_173863 = cat(T_173862[15], T_173862[14])
      node T_173864 = cat(T_173862[13], T_173862[12])
      node T_173865 = cat(T_173863, T_173864)
      node T_173866 = cat(T_173862[11], T_173862[10])
      node T_173867 = cat(T_173862[9], T_173862[8])
      node T_173868 = cat(T_173866, T_173867)
      node T_173869 = cat(T_173865, T_173868)
      node T_173870 = cat(T_173862[7], T_173862[6])
      node T_173871 = cat(T_173862[5], T_173862[4])
      node T_173872 = cat(T_173870, T_173871)
      node T_173873 = cat(T_173862[3], T_173862[2])
      node T_173874 = cat(T_173862[1], T_173862[0])
      node T_173875 = cat(T_173873, T_173874)
      node T_173876 = cat(T_173872, T_173875)
      node T_173877 = cat(T_173869, T_173876)
      accessor T_173878 = data_buffer[inner.acquire.bits.addr_beat]
      node T_173879 = not(T_173877)
      accessor T_173880 = data_buffer[inner.acquire.bits.addr_beat]
      node T_173881 = and(T_173879, T_173880)
      node T_173882 = and(T_173877, inner.acquire.bits.data)
      node T_173883 = or(T_173881, T_173882)
      T_173878 := T_173883
      accessor T_173884 = wmask_buffer[inner.acquire.bits.addr_beat]
      node T_173885 = eq(state, UInt<4>(0))
      accessor T_173886 = wmask_buffer[inner.acquire.bits.addr_beat]
      wire T_173887 : UInt<16>
      T_173887 := T_173886
      when T_173885 : T_173887 := UInt<1>(0)
      node T_173888 = or(T_173828, T_173887)
      T_173884 := T_173888
    node T_173889 = eq(xact.a_type, UInt<3>(2))
    node T_173890 = and(xact.is_builtin_type, T_173889)
    node T_173891 = eq(xact.a_type, UInt<3>(3))
    node T_173892 = and(xact.is_builtin_type, T_173891)
    node T_173893 = or(T_173890, T_173892)
    node T_173894 = bits(xact.union, 5, 1)
    wire T_173895 : UInt<5>
    T_173895 := T_173894
    when T_173893 : T_173895 := UInt<5>(1)
    node T_173896 = eq(T_173895, UInt<5>(1))
    node T_173897 = eq(T_173895, UInt<5>(7))
    node T_173898 = or(T_173896, T_173897)
    node T_173899 = bit(T_173895, 3)
    node T_173900 = eq(T_173895, UInt<5>(4))
    node T_173901 = or(T_173899, T_173900)
    node T_173902 = or(T_173898, T_173901)
    wire T_173903 : UInt<2>
    T_173903 := meta.resp.bits.meta.coh.outer.state
    when T_173902 : T_173903 := UInt<2>(2)
    wire T_173904 : UInt<3>[3]
    T_173904[0] := UInt<3>(0)
    T_173904[1] := UInt<3>(1)
    T_173904[2] := UInt<3>(2)
    wire T_173905 : UInt<0>[1]
    T_173905[0] := UInt<0>(0)
    wire T_173906 : UInt<2>[2]
    T_173906[0] := UInt<2>(1)
    T_173906[1] := UInt<2>(2)
    wire T_173907 : UInt<2>[2]
    T_173907[0] := UInt<2>(1)
    T_173907[1] := UInt<2>(2)
    wire T_173908 : UInt<2>[1]
    T_173908[0] := UInt<2>(2)
    wire T_173909 : UInt<3>[3]
    T_173909[0] := UInt<3>(0)
    T_173909[1] := UInt<3>(1)
    T_173909[2] := UInt<3>(2)
    wire T_173910 : UInt<0>[1]
    T_173910[0] := UInt<0>(0)
    wire T_173911 : UInt<2>[2]
    T_173911[0] := UInt<2>(1)
    T_173911[1] := UInt<2>(2)
    wire T_173912 : UInt<2>[2]
    T_173912[0] := UInt<2>(1)
    T_173912[1] := UInt<2>(2)
    wire T_173913 : UInt<2>[1]
    T_173913[0] := UInt<2>(2)
    wire T_173914 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_173914.state := T_173903
    wire T_173915 : UInt<3>[3]
    T_173915[0] := UInt<3>(0)
    T_173915[1] := UInt<3>(1)
    T_173915[2] := UInt<3>(2)
    wire T_173916 : UInt<2>[2]
    T_173916[0] := UInt<2>(0)
    T_173916[1] := UInt<2>(1)
    wire T_173917 : UInt<2>[3]
    T_173917[0] := UInt<2>(1)
    T_173917[1] := UInt<2>(2)
    T_173917[2] := UInt<2>(3)
    wire T_173918 : UInt<2>[2]
    T_173918[0] := UInt<2>(2)
    T_173918[1] := UInt<2>(3)
    wire T_173919 : UInt<2>[1]
    T_173919[0] := UInt<2>(3)
    wire T_173920 : UInt<3>[3]
    T_173920[0] := UInt<3>(0)
    T_173920[1] := UInt<3>(1)
    T_173920[2] := UInt<3>(2)
    wire T_173921 : UInt<2>[2]
    T_173921[0] := UInt<2>(0)
    T_173921[1] := UInt<2>(1)
    wire T_173922 : UInt<2>[3]
    T_173922[0] := UInt<2>(1)
    T_173922[1] := UInt<2>(2)
    T_173922[2] := UInt<2>(3)
    wire T_173923 : UInt<2>[2]
    T_173923[0] := UInt<2>(2)
    T_173923[1] := UInt<2>(3)
    wire T_173924 : UInt<2>[1]
    T_173924[0] := UInt<2>(3)
    wire T_173925 : UInt<3>[3]
    T_173925[0] := UInt<3>(0)
    T_173925[1] := UInt<3>(1)
    T_173925[2] := UInt<3>(2)
    wire T_173926 : UInt<0>[1]
    T_173926[0] := UInt<0>(0)
    wire T_173927 : UInt<2>[2]
    T_173927[0] := UInt<2>(1)
    T_173927[1] := UInt<2>(2)
    wire T_173928 : UInt<2>[2]
    T_173928[0] := UInt<2>(1)
    T_173928[1] := UInt<2>(2)
    wire T_173929 : UInt<2>[1]
    T_173929[0] := UInt<2>(2)
    wire T_173930 : UInt<3>[3]
    T_173930[0] := UInt<3>(0)
    T_173930[1] := UInt<3>(1)
    T_173930[2] := UInt<3>(2)
    wire T_173931 : UInt<2>[2]
    T_173931[0] := UInt<2>(0)
    T_173931[1] := UInt<2>(1)
    wire T_173932 : UInt<2>[3]
    T_173932[0] := UInt<2>(1)
    T_173932[1] := UInt<2>(2)
    T_173932[2] := UInt<2>(3)
    wire T_173933 : UInt<2>[2]
    T_173933[0] := UInt<2>(2)
    T_173933[1] := UInt<2>(3)
    wire T_173934 : UInt<2>[1]
    T_173934[0] := UInt<2>(3)
    wire T_173935 : UInt<3>[3]
    T_173935[0] := UInt<3>(0)
    T_173935[1] := UInt<3>(1)
    T_173935[2] := UInt<3>(2)
    wire T_173936 : UInt<2>[2]
    T_173936[0] := UInt<2>(0)
    T_173936[1] := UInt<2>(1)
    wire T_173937 : UInt<2>[3]
    T_173937[0] := UInt<2>(1)
    T_173937[1] := UInt<2>(2)
    T_173937[2] := UInt<2>(3)
    wire T_173938 : UInt<2>[2]
    T_173938[0] := UInt<2>(2)
    T_173938[1] := UInt<2>(3)
    wire T_173939 : UInt<2>[1]
    T_173939[0] := UInt<2>(3)
    wire T_173940 : UInt<3>[3]
    T_173940[0] := UInt<3>(0)
    T_173940[1] := UInt<3>(1)
    T_173940[2] := UInt<3>(2)
    wire T_173941 : UInt<0>[1]
    T_173941[0] := UInt<0>(0)
    wire T_173942 : UInt<2>[2]
    T_173942[0] := UInt<2>(1)
    T_173942[1] := UInt<2>(2)
    wire T_173943 : UInt<2>[2]
    T_173943[0] := UInt<2>(1)
    T_173943[1] := UInt<2>(2)
    wire T_173944 : UInt<2>[1]
    T_173944[0] := UInt<2>(2)
    wire pending_coh_on_hit : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_hit.inner := meta.resp.bits.meta.coh.inner
    pending_coh_on_hit.outer := T_173914
    wire T_173945 : UInt<3>[3]
    T_173945[0] := UInt<3>(0)
    T_173945[1] := UInt<3>(1)
    T_173945[2] := UInt<3>(2)
    wire T_173946 : UInt<2>[2]
    T_173946[0] := UInt<2>(0)
    T_173946[1] := UInt<2>(1)
    wire T_173947 : UInt<2>[3]
    T_173947[0] := UInt<2>(1)
    T_173947[1] := UInt<2>(2)
    T_173947[2] := UInt<2>(3)
    wire T_173948 : UInt<2>[2]
    T_173948[0] := UInt<2>(2)
    T_173948[1] := UInt<2>(3)
    wire T_173949 : UInt<2>[1]
    T_173949[0] := UInt<2>(3)
    wire T_173950 : UInt<3>[3]
    T_173950[0] := UInt<3>(0)
    T_173950[1] := UInt<3>(1)
    T_173950[2] := UInt<3>(2)
    wire T_173951 : UInt<2>[2]
    T_173951[0] := UInt<2>(0)
    T_173951[1] := UInt<2>(1)
    wire T_173952 : UInt<2>[3]
    T_173952[0] := UInt<2>(1)
    T_173952[1] := UInt<2>(2)
    T_173952[2] := UInt<2>(3)
    wire T_173953 : UInt<2>[2]
    T_173953[0] := UInt<2>(2)
    T_173953[1] := UInt<2>(3)
    wire T_173954 : UInt<2>[1]
    T_173954[0] := UInt<2>(3)
    wire T_173955 : UInt<3>[3]
    T_173955[0] := UInt<3>(0)
    T_173955[1] := UInt<3>(1)
    T_173955[2] := UInt<3>(2)
    wire T_173956 : UInt<2>[2]
    T_173956[0] := UInt<2>(0)
    T_173956[1] := UInt<2>(1)
    wire T_173957 : UInt<2>[3]
    T_173957[0] := UInt<2>(1)
    T_173957[1] := UInt<2>(2)
    T_173957[2] := UInt<2>(3)
    wire T_173958 : UInt<2>[2]
    T_173958[0] := UInt<2>(2)
    T_173958[1] := UInt<2>(3)
    wire T_173959 : UInt<2>[1]
    T_173959[0] := UInt<2>(3)
    wire T_173960 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_173960.sharers := UInt<1>(0)
    wire T_173961 : UInt<3>[3]
    T_173961[0] := UInt<3>(0)
    T_173961[1] := UInt<3>(1)
    T_173961[2] := UInt<3>(2)
    wire T_173962 : UInt<2>[2]
    T_173962[0] := UInt<2>(0)
    T_173962[1] := UInt<2>(1)
    wire T_173963 : UInt<2>[3]
    T_173963[0] := UInt<2>(1)
    T_173963[1] := UInt<2>(2)
    T_173963[2] := UInt<2>(3)
    wire T_173964 : UInt<2>[2]
    T_173964[0] := UInt<2>(2)
    T_173964[1] := UInt<2>(3)
    wire T_173965 : UInt<2>[1]
    T_173965[0] := UInt<2>(3)
    wire T_173966 : UInt<3>[3]
    T_173966[0] := UInt<3>(0)
    T_173966[1] := UInt<3>(1)
    T_173966[2] := UInt<3>(2)
    wire T_173967 : UInt<2>[2]
    T_173967[0] := UInt<2>(0)
    T_173967[1] := UInt<2>(1)
    wire T_173968 : UInt<2>[3]
    T_173968[0] := UInt<2>(1)
    T_173968[1] := UInt<2>(2)
    T_173968[2] := UInt<2>(3)
    wire T_173969 : UInt<2>[2]
    T_173969[0] := UInt<2>(2)
    T_173969[1] := UInt<2>(3)
    wire T_173970 : UInt<2>[1]
    T_173970[0] := UInt<2>(3)
    wire T_173971 : UInt<3>[3]
    T_173971[0] := UInt<3>(0)
    T_173971[1] := UInt<3>(1)
    T_173971[2] := UInt<3>(2)
    wire T_173972 : UInt<2>[2]
    T_173972[0] := UInt<2>(0)
    T_173972[1] := UInt<2>(1)
    wire T_173973 : UInt<2>[3]
    T_173973[0] := UInt<2>(1)
    T_173973[1] := UInt<2>(2)
    T_173973[2] := UInt<2>(3)
    wire T_173974 : UInt<2>[2]
    T_173974[0] := UInt<2>(2)
    T_173974[1] := UInt<2>(3)
    wire T_173975 : UInt<2>[1]
    T_173975[0] := UInt<2>(3)
    wire T_173976 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_173976.state := UInt<2>(0)
    wire T_173977 : UInt<3>[3]
    T_173977[0] := UInt<3>(0)
    T_173977[1] := UInt<3>(1)
    T_173977[2] := UInt<3>(2)
    wire T_173978 : UInt<2>[2]
    T_173978[0] := UInt<2>(0)
    T_173978[1] := UInt<2>(1)
    wire T_173979 : UInt<2>[3]
    T_173979[0] := UInt<2>(1)
    T_173979[1] := UInt<2>(2)
    T_173979[2] := UInt<2>(3)
    wire T_173980 : UInt<2>[2]
    T_173980[0] := UInt<2>(2)
    T_173980[1] := UInt<2>(3)
    wire T_173981 : UInt<2>[1]
    T_173981[0] := UInt<2>(3)
    wire T_173982 : UInt<3>[3]
    T_173982[0] := UInt<3>(0)
    T_173982[1] := UInt<3>(1)
    T_173982[2] := UInt<3>(2)
    wire T_173983 : UInt<2>[2]
    T_173983[0] := UInt<2>(0)
    T_173983[1] := UInt<2>(1)
    wire T_173984 : UInt<2>[3]
    T_173984[0] := UInt<2>(1)
    T_173984[1] := UInt<2>(2)
    T_173984[2] := UInt<2>(3)
    wire T_173985 : UInt<2>[2]
    T_173985[0] := UInt<2>(2)
    T_173985[1] := UInt<2>(3)
    wire T_173986 : UInt<2>[1]
    T_173986[0] := UInt<2>(3)
    wire T_173987 : UInt<3>[3]
    T_173987[0] := UInt<3>(0)
    T_173987[1] := UInt<3>(1)
    T_173987[2] := UInt<3>(2)
    wire T_173988 : UInt<0>[1]
    T_173988[0] := UInt<0>(0)
    wire T_173989 : UInt<2>[2]
    T_173989[0] := UInt<2>(1)
    T_173989[1] := UInt<2>(2)
    wire T_173990 : UInt<2>[2]
    T_173990[0] := UInt<2>(1)
    T_173990[1] := UInt<2>(2)
    wire T_173991 : UInt<2>[1]
    T_173991[0] := UInt<2>(2)
    wire T_173992 : UInt<3>[3]
    T_173992[0] := UInt<3>(0)
    T_173992[1] := UInt<3>(1)
    T_173992[2] := UInt<3>(2)
    wire T_173993 : UInt<2>[2]
    T_173993[0] := UInt<2>(0)
    T_173993[1] := UInt<2>(1)
    wire T_173994 : UInt<2>[3]
    T_173994[0] := UInt<2>(1)
    T_173994[1] := UInt<2>(2)
    T_173994[2] := UInt<2>(3)
    wire T_173995 : UInt<2>[2]
    T_173995[0] := UInt<2>(2)
    T_173995[1] := UInt<2>(3)
    wire T_173996 : UInt<2>[1]
    T_173996[0] := UInt<2>(3)
    wire T_173997 : UInt<3>[3]
    T_173997[0] := UInt<3>(0)
    T_173997[1] := UInt<3>(1)
    T_173997[2] := UInt<3>(2)
    wire T_173998 : UInt<2>[2]
    T_173998[0] := UInt<2>(0)
    T_173998[1] := UInt<2>(1)
    wire T_173999 : UInt<2>[3]
    T_173999[0] := UInt<2>(1)
    T_173999[1] := UInt<2>(2)
    T_173999[2] := UInt<2>(3)
    wire T_174000 : UInt<2>[2]
    T_174000[0] := UInt<2>(2)
    T_174000[1] := UInt<2>(3)
    wire T_174001 : UInt<2>[1]
    T_174001[0] := UInt<2>(3)
    wire T_174002 : UInt<3>[3]
    T_174002[0] := UInt<3>(0)
    T_174002[1] := UInt<3>(1)
    T_174002[2] := UInt<3>(2)
    wire T_174003 : UInt<0>[1]
    T_174003[0] := UInt<0>(0)
    wire T_174004 : UInt<2>[2]
    T_174004[0] := UInt<2>(1)
    T_174004[1] := UInt<2>(2)
    wire T_174005 : UInt<2>[2]
    T_174005[0] := UInt<2>(1)
    T_174005[1] := UInt<2>(2)
    wire T_174006 : UInt<2>[1]
    T_174006[0] := UInt<2>(2)
    wire pending_coh_on_miss : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_miss.inner := T_173960
    pending_coh_on_miss.outer := T_173976
    
    
    node T_174007 = eq(state, UInt<4>(0))
    node T_174008 = and(T_174007, inner.acquire.valid)
    when T_174008 : 
      xact := inner.acquire.bits
      xact.data := UInt<1>(0)
      node T_174009 = eq(inner.acquire.bits.a_type, UInt<3>(3))
      node T_174010 = and(inner.acquire.bits.is_builtin_type, T_174009)
      node T_174011 = and(inner.acquire.ready, inner.acquire.valid)
      wire T_174012 : UInt<3>[3]
      T_174012[0] := UInt<3>(2)
      T_174012[1] := UInt<3>(3)
      T_174012[2] := UInt<3>(4)
      node T_174013 = eq(T_174012[0], inner.acquire.bits.a_type)
      node T_174014 = eq(T_174012[1], inner.acquire.bits.a_type)
      node T_174015 = eq(T_174012[2], inner.acquire.bits.a_type)
      node T_174016 = or(UInt<1>(0), T_174013)
      node T_174017 = or(T_174016, T_174014)
      node T_174018 = or(T_174017, T_174015)
      node T_174019 = and(inner.acquire.bits.is_builtin_type, T_174018)
      node T_174020 = and(T_174011, T_174019)
      node T_174021 = subw(UInt<4>(0), UInt<3>(4))
      node T_174022 = not(T_174021)
      node T_174023 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_174024 = not(T_174023)
      node T_174025 = or(T_174022, T_174024)
      wire T_174026 : UInt<1>
      T_174026 := UInt<1>(0)
      when T_174010 : T_174026 := T_174025
      pending_puts := T_174026
      node T_174027 = eq(inner.acquire.bits.a_type, UInt<3>(1))
      node T_174028 = and(inner.acquire.bits.is_builtin_type, T_174027)
      node T_174029 = eq(inner.acquire.bits.is_builtin_type, UInt<1>(0))
      node T_174030 = or(T_174028, T_174029)
      wire T_174031 : UInt<3>[3]
      T_174031[0] := UInt<3>(0)
      T_174031[1] := UInt<3>(1)
      T_174031[2] := UInt<3>(4)
      node T_174032 = eq(T_174031[0], inner.acquire.bits.a_type)
      node T_174033 = eq(T_174031[1], inner.acquire.bits.a_type)
      node T_174034 = eq(T_174031[2], inner.acquire.bits.a_type)
      node T_174035 = or(UInt<1>(0), T_174032)
      node T_174036 = or(T_174035, T_174033)
      node T_174037 = or(T_174036, T_174034)
      node T_174038 = and(inner.acquire.bits.is_builtin_type, T_174037)
      node T_174039 = and(inner.acquire.ready, inner.acquire.valid)
      node T_174040 = and(T_174039, T_174038)
      node T_174041 = subw(UInt<4>(0), UInt<3>(4))
      node T_174042 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_174043 = and(T_174041, T_174042)
      node T_174044 = eq(inner.acquire.bits.a_type, UInt<3>(4))
      node T_174045 = and(inner.acquire.bits.is_builtin_type, T_174044)
      node T_174046 = bits(inner.acquire.bits.union, 12, 9)
      node T_174047 = bits(T_174046, 3, 3)
      node T_174048 = dshl(UInt<1>(1), T_174047)
      node T_174049 = bit(T_174048, 0)
      node T_174050 = bit(T_174048, 1)
      node T_174051 = bit(T_174048, 2)
      wire T_174052 : UInt<1>[3]
      T_174052[0] := T_174049
      T_174052[1] := T_174050
      T_174052[2] := T_174051
      node T_174053 = subw(UInt<8>(0), UInt<4>(8))
      node T_174054 = subw(UInt<8>(0), UInt<4>(8))
      node T_174055 = subw(UInt<8>(0), UInt<4>(8))
      wire T_174056 : UInt<8>[3]
      T_174056[0] := T_174053
      T_174056[1] := T_174054
      T_174056[2] := T_174055
      node T_174057 = cat(T_174056[1], T_174056[0])
      node T_174058 = cat(T_174056[2], T_174057)
      node T_174059 = eq(inner.acquire.bits.a_type, UInt<3>(3))
      node T_174060 = and(inner.acquire.bits.is_builtin_type, T_174059)
      node T_174061 = eq(inner.acquire.bits.a_type, UInt<3>(2))
      node T_174062 = and(inner.acquire.bits.is_builtin_type, T_174061)
      node T_174063 = or(T_174060, T_174062)
      node T_174064 = bits(inner.acquire.bits.union, 16, 1)
      wire T_174065 : UInt<16>
      T_174065 := UInt<16>(0)
      when T_174063 : T_174065 := T_174064
      wire T_174066 : UInt<16>
      T_174066 := T_174065
      when T_174045 : T_174066 := T_174058
      wire T_174067 : UInt<3>[3]
      T_174067[0] := UInt<3>(0)
      T_174067[1] := UInt<3>(1)
      T_174067[2] := UInt<3>(2)
      wire T_174068 : UInt<2>[2]
      T_174068[0] := UInt<2>(0)
      T_174068[1] := UInt<2>(1)
      wire T_174069 : UInt<2>[3]
      T_174069[0] := UInt<2>(1)
      T_174069[1] := UInt<2>(2)
      T_174069[2] := UInt<2>(3)
      wire T_174070 : UInt<2>[2]
      T_174070[0] := UInt<2>(2)
      T_174070[1] := UInt<2>(3)
      wire T_174071 : UInt<2>[1]
      T_174071[0] := UInt<2>(3)
      node T_174072 = asUInt(SInt<16>(-1))
      node T_174073 = neq(T_174066, T_174072)
      node T_174074 = and(inner.acquire.ready, inner.acquire.valid)
      node T_174075 = and(T_174074, T_174073)
      node T_174076 = and(T_174075, UInt<1>(0))
      node T_174077 = subw(UInt<4>(0), UInt<3>(4))
      node T_174078 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_174079 = and(T_174077, T_174078)
      node T_174080 = or(T_174043, T_174079)
      node T_174081 = asSInt(T_174080)
      wire T_174082 : SInt<5>
      T_174082 := T_174081
      when T_174030 : T_174082 := SInt<1>(-1)
      node T_174083 = asUInt(T_174082)
      pending_reads := T_174083
      node T_174084 = and(inner.acquire.ready, inner.acquire.valid)
      wire T_174085 : UInt<3>[3]
      T_174085[0] := UInt<3>(2)
      T_174085[1] := UInt<3>(3)
      T_174085[2] := UInt<3>(4)
      node T_174086 = eq(T_174085[0], inner.acquire.bits.a_type)
      node T_174087 = eq(T_174085[1], inner.acquire.bits.a_type)
      node T_174088 = eq(T_174085[2], inner.acquire.bits.a_type)
      node T_174089 = or(UInt<1>(0), T_174086)
      node T_174090 = or(T_174089, T_174087)
      node T_174091 = or(T_174090, T_174088)
      node T_174092 = and(inner.acquire.bits.is_builtin_type, T_174091)
      node T_174093 = and(T_174084, T_174092)
      node T_174094 = bit(inner.acquire.bits.union, 0)
      node T_174095 = and(T_174093, T_174094)
      node T_174096 = subw(UInt<4>(0), UInt<3>(4))
      node T_174097 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_174098 = and(T_174096, T_174097)
      pending_writes := T_174098
      pending_resps := UInt<1>(0)
      pending_ignt_data := UInt<1>(0)
      pending_meta_write := UInt<1>(0)
      state := UInt<4>(1)
    
    
    node T_174099 = eq(state, UInt<4>(1))
    node T_174100 = and(T_174099, meta.read.ready)
    when T_174100 : state := UInt<4>(2)
    
    
    node T_174101 = eq(state, UInt<4>(2))
    node T_174102 = and(T_174101, meta.resp.valid)
    when T_174102 : 
      xact_tag_match := meta.resp.bits.tag_match
      xact_old_meta := meta.resp.bits.meta
      xact_way_en := meta.resp.bits.way_en
      node T_174103 = eq(xact.a_type, UInt<3>(3))
      node T_174104 = and(xact.is_builtin_type, T_174103)
      node T_174105 = neq(meta.resp.bits.meta.coh.outer.state, UInt<2>(0))
      node T_174106 = and(meta.resp.bits.tag_match, T_174105)
      node T_174107 = or(T_174104, T_174106)
      node T_174108 = eq(meta.resp.bits.tag_match, UInt<1>(0))
      node T_174109 = bit(xact.union, 0)
      node T_174110 = and(T_174108, T_174109)
      node T_174111 = eq(T_172556[0], meta.resp.bits.meta.coh.outer.state)
      node T_174112 = or(UInt<1>(0), T_174111)
      node T_174113 = eq(meta.resp.bits.meta.coh.inner.sharers, UInt<1>(0))
      node T_174114 = eq(T_174113, UInt<1>(0))
      node T_174115 = or(T_174112, T_174114)
      node T_174116 = and(T_174110, T_174115)
      node T_174117 = eq(meta.resp.bits.meta.coh.inner.sharers, UInt<1>(0))
      node T_174118 = bit(meta.resp.bits.meta.coh.inner.sharers, 0)
      node T_174119 = eq(T_174118, UInt<1>(1))
      wire T_174120 : UInt<3>[3]
      T_174120[0] := UInt<3>(2)
      T_174120[1] := UInt<3>(3)
      T_174120[2] := UInt<3>(4)
      node T_174121 = eq(T_174120[0], xact.a_type)
      node T_174122 = eq(T_174120[1], xact.a_type)
      node T_174123 = eq(T_174120[2], xact.a_type)
      node T_174124 = or(UInt<1>(0), T_174121)
      node T_174125 = or(T_174124, T_174122)
      node T_174126 = or(T_174125, T_174123)
      node T_174127 = and(xact.is_builtin_type, T_174126)
      node T_174128 = neq(xact.a_type, UInt<1>(0))
      wire T_174129 : UInt<1>
      T_174129 := T_174128
      when xact.is_builtin_type : T_174129 := T_174127
      wire T_174130 : UInt<1>
      T_174130 := T_174129
      when T_174119 : T_174130 := UInt<1>(1)
      wire T_174131 : UInt<1>
      T_174131 := T_174130
      when T_174117 : T_174131 := UInt<1>(0)
      node T_174132 = and(meta.resp.bits.tag_match, T_174131)
      
      
      node T_174133 = eq(meta.resp.bits.tag_match, UInt<1>(0))
      node T_174134 = eq(pending_coh_on_hit.inner.sharers, meta.resp.bits.meta.coh.inner.sharers)
      node T_174135 = eq(pending_coh_on_hit.outer.state, meta.resp.bits.meta.coh.outer.state)
      node T_174136 = and(T_174134, T_174135)
      node T_174137 = eq(T_174136, UInt<1>(0))
      node T_174138 = and(T_174107, T_174137)
      node T_174139 = or(T_174133, T_174138)
      when T_174139 : pending_meta_write := UInt<1>(1)
      wire T_174140 : UInt<3>[3]
      T_174140[0] := UInt<3>(0)
      T_174140[1] := UInt<3>(1)
      T_174140[2] := UInt<3>(2)
      wire T_174141 : UInt<2>[2]
      T_174141[0] := UInt<2>(0)
      T_174141[1] := UInt<2>(1)
      wire T_174142 : UInt<2>[3]
      T_174142[0] := UInt<2>(1)
      T_174142[1] := UInt<2>(2)
      T_174142[2] := UInt<2>(3)
      wire T_174143 : UInt<2>[2]
      T_174143[0] := UInt<2>(2)
      T_174143[1] := UInt<2>(3)
      wire T_174144 : UInt<2>[1]
      T_174144[0] := UInt<2>(3)
      wire T_174145 : UInt<3>[3]
      T_174145[0] := UInt<3>(0)
      T_174145[1] := UInt<3>(1)
      T_174145[2] := UInt<3>(2)
      wire T_174146 : UInt<2>[2]
      T_174146[0] := UInt<2>(0)
      T_174146[1] := UInt<2>(1)
      wire T_174147 : UInt<2>[3]
      T_174147[0] := UInt<2>(1)
      T_174147[1] := UInt<2>(2)
      T_174147[2] := UInt<2>(3)
      wire T_174148 : UInt<2>[2]
      T_174148[0] := UInt<2>(2)
      T_174148[1] := UInt<2>(3)
      wire T_174149 : UInt<2>[1]
      T_174149[0] := UInt<2>(3)
      wire T_174150 : UInt<3>[3]
      T_174150[0] := UInt<3>(0)
      T_174150[1] := UInt<3>(1)
      T_174150[2] := UInt<3>(2)
      wire T_174151 : UInt<0>[1]
      T_174151[0] := UInt<0>(0)
      wire T_174152 : UInt<2>[2]
      T_174152[0] := UInt<2>(1)
      T_174152[1] := UInt<2>(2)
      wire T_174153 : UInt<2>[2]
      T_174153[0] := UInt<2>(1)
      T_174153[1] := UInt<2>(2)
      wire T_174154 : UInt<2>[1]
      T_174154[0] := UInt<2>(2)
      wire T_174155 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
      T_174155 := pending_coh_on_miss
      when meta.resp.bits.tag_match : T_174155 := meta.resp.bits.meta.coh
      wire T_174156 : UInt<3>[3]
      T_174156[0] := UInt<3>(0)
      T_174156[1] := UInt<3>(1)
      T_174156[2] := UInt<3>(2)
      wire T_174157 : UInt<2>[2]
      T_174157[0] := UInt<2>(0)
      T_174157[1] := UInt<2>(1)
      wire T_174158 : UInt<2>[3]
      T_174158[0] := UInt<2>(1)
      T_174158[1] := UInt<2>(2)
      T_174158[2] := UInt<2>(3)
      wire T_174159 : UInt<2>[2]
      T_174159[0] := UInt<2>(2)
      T_174159[1] := UInt<2>(3)
      wire T_174160 : UInt<2>[1]
      T_174160[0] := UInt<2>(3)
      wire T_174161 : UInt<3>[3]
      T_174161[0] := UInt<3>(0)
      T_174161[1] := UInt<3>(1)
      T_174161[2] := UInt<3>(2)
      wire T_174162 : UInt<2>[2]
      T_174162[0] := UInt<2>(0)
      T_174162[1] := UInt<2>(1)
      wire T_174163 : UInt<2>[3]
      T_174163[0] := UInt<2>(1)
      T_174163[1] := UInt<2>(2)
      T_174163[2] := UInt<2>(3)
      wire T_174164 : UInt<2>[2]
      T_174164[0] := UInt<2>(2)
      T_174164[1] := UInt<2>(3)
      wire T_174165 : UInt<2>[1]
      T_174165[0] := UInt<2>(3)
      wire T_174166 : UInt<3>[3]
      T_174166[0] := UInt<3>(0)
      T_174166[1] := UInt<3>(1)
      T_174166[2] := UInt<3>(2)
      wire T_174167 : UInt<0>[1]
      T_174167[0] := UInt<0>(0)
      wire T_174168 : UInt<2>[2]
      T_174168[0] := UInt<2>(1)
      T_174168[1] := UInt<2>(2)
      wire T_174169 : UInt<2>[2]
      T_174169[0] := UInt<2>(1)
      T_174169[1] := UInt<2>(2)
      wire T_174170 : UInt<2>[1]
      T_174170[0] := UInt<2>(2)
      wire T_174171 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
      T_174171 := T_174155
      when T_174107 : T_174171 := pending_coh_on_hit
      pending_coh := T_174171
      when T_174132 : 
        node T_174172 = dshl(UInt<1>(1), xact.client_id)
        node T_174173 = or(meta.resp.bits.meta.coh.inner.sharers, T_174172)
        node T_174174 = dshl(UInt<1>(1), xact.client_id)
        node T_174175 = not(T_174174)
        node T_174176 = and(meta.resp.bits.meta.coh.inner.sharers, T_174175)
        wire T_174177 : UInt<5>
        T_174177 := T_174176
        when UInt<1>(0) : T_174177 := T_174173
        node T_174178 = not(incoherent[0])
        node T_174179 = and(T_174177, T_174178)
        pending_iprbs := T_174179
      node T_174180 = eq(T_174107, UInt<1>(0))
      wire T_174181 : UInt<4>
      T_174181 := UInt<4>(7)
      when T_174180 : T_174181 := UInt<4>(6)
      wire T_174182 : UInt<4>
      T_174182 := T_174181
      when T_174132 : T_174182 := UInt<4>(5)
      wire T_174183 : UInt<4>
      T_174183 := T_174182
      when T_174116 : T_174183 := UInt<4>(3)
      state := T_174183
    
    
    node T_174184 = eq(state, UInt<4>(3))
    node T_174185 = and(T_174184, wb.req.ready)
    when T_174185 : state := UInt<4>(4)
    
    
    node T_174186 = eq(state, UInt<4>(4))
    node T_174187 = and(T_174186, wb.resp.valid)
    when T_174187 : 
      node T_174188 = eq(xact.a_type, UInt<3>(3))
      node T_174189 = and(xact.is_builtin_type, T_174188)
      node T_174190 = and(UInt<1>(1), T_174189)
      node T_174191 = eq(T_174190, UInt<1>(0))
      wire T_174192 : UInt<4>
      T_174192 := UInt<4>(7)
      when T_174191 : T_174192 := UInt<4>(6)
      state := T_174192
    
    
    node T_174193 = eq(state, UInt<4>(5))
    node T_174194 = eq(pending_iprbs, UInt<1>(0))
    node T_174195 = eq(T_174194, UInt<1>(0))
    node T_174196 = or(T_174195, pending_irels)
    node T_174197 = eq(T_174196, UInt<1>(0))
    node T_174198 = and(T_174193, T_174197)
    when T_174198 : 
      node T_174199 = eq(xact.a_type, UInt<3>(3))
      node T_174200 = and(xact.is_builtin_type, T_174199)
      node T_174201 = neq(xact_old_meta.coh.outer.state, UInt<2>(0))
      node T_174202 = or(T_174200, T_174201)
      node T_174203 = eq(T_174202, UInt<1>(0))
      wire T_174204 : UInt<4>
      T_174204 := UInt<4>(7)
      when T_174203 : T_174204 := UInt<4>(6)
      state := T_174204
    
    
    node T_174205 = eq(state, UInt<4>(6))
    node T_174206 = and(T_174205, oacq_data_done)
    when T_174206 : state := UInt<4>(7)
    
    
    node T_174207 = eq(state, UInt<4>(7))
    node T_174208 = and(T_174207, all_pending_done)
    when T_174208 : state := UInt<4>(8)
    
    
    node T_174209 = eq(state, UInt<4>(8))
    node T_174210 = eq(pending_meta_write, UInt<1>(0))
    node T_174211 = or(meta.write.ready, T_174210)
    node T_174212 = and(T_174209, T_174211)
    when T_174212 : 
      wmask_buffer[0] := UInt<1>(0)
      wmask_buffer[1] := UInt<1>(0)
      wmask_buffer[2] := UInt<1>(0)
      wmask_buffer[3] := UInt<1>(0)
      state := UInt<4>(0)
    node T_174213 = bits(xact.addr_block, 11, 0)
    node T_174214 = bits(inner.acquire.bits.addr_block, 11, 0)
    node in_same_set = eq(T_174213, T_174214)
    node T_174215 = eq(xact.addr_block, inner.release.bits.addr_block)
    node T_174216 = eq(inner.release.bits.voluntary, UInt<1>(0))
    node T_174217 = and(T_174215, T_174216)
    node T_174218 = and(T_174217, inner.release.ready)
    has_release_match := T_174218
    node T_174219 = or(can_merge_iacq_put, can_merge_iacq_get)
    has_acquire_match := T_174219
    node T_174220 = neq(state, UInt<4>(0))
    node T_174221 = and(in_same_set, T_174220)
    node T_174222 = eq(has_acquire_match, UInt<1>(0))
    node T_174223 = and(T_174221, T_174222)
    has_acquire_conflict := T_174223
    node T_174224 = neq(state, UInt<4>(0))
    node T_174225 = and(inner.acquire.ready, inner.acquire.valid)
    node T_174226 = and(T_174224, T_174225)
    node T_174227 = neq(inner.acquire.bits.client_id, xact.client_id)
    node T_174228 = and(T_174226, T_174227)
    node T_174229 = eq(T_174228, UInt<1>(0))
  module Queue_86917 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<1>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<1>}}
    output count : UInt<3>
    
    wire T_174230 : UInt<3>[3]
    T_174230[0] := UInt<3>(0)
    T_174230[1] := UInt<3>(1)
    T_174230[2] := UInt<3>(2)
    wire T_174231 : UInt<2>[2]
    T_174231[0] := UInt<2>(0)
    T_174231[1] := UInt<2>(1)
    wire T_174232 : UInt<2>[3]
    T_174232[0] := UInt<2>(1)
    T_174232[1] := UInt<2>(2)
    T_174232[2] := UInt<2>(3)
    wire T_174233 : UInt<2>[2]
    T_174233[0] := UInt<2>(2)
    T_174233[1] := UInt<2>(3)
    wire T_174234 : UInt<2>[1]
    T_174234[0] := UInt<2>(3)
    wire T_174235 : UInt<3>[3]
    T_174235[0] := UInt<3>(0)
    T_174235[1] := UInt<3>(1)
    T_174235[2] := UInt<3>(2)
    wire T_174236 : UInt<2>[2]
    T_174236[0] := UInt<2>(0)
    T_174236[1] := UInt<2>(1)
    wire T_174237 : UInt<2>[3]
    T_174237[0] := UInt<2>(1)
    T_174237[1] := UInt<2>(2)
    T_174237[2] := UInt<2>(3)
    wire T_174238 : UInt<2>[2]
    T_174238[0] := UInt<2>(2)
    T_174238[1] := UInt<2>(3)
    wire T_174239 : UInt<2>[1]
    T_174239[0] := UInt<2>(3)
    wire T_174240 : UInt<3>[3]
    T_174240[0] := UInt<3>(0)
    T_174240[1] := UInt<3>(1)
    T_174240[2] := UInt<3>(2)
    wire T_174241 : UInt<2>[2]
    T_174241[0] := UInt<2>(0)
    T_174241[1] := UInt<2>(1)
    wire T_174242 : UInt<2>[3]
    T_174242[0] := UInt<2>(1)
    T_174242[1] := UInt<2>(2)
    T_174242[2] := UInt<2>(3)
    wire T_174243 : UInt<2>[2]
    T_174243[0] := UInt<2>(2)
    T_174243[1] := UInt<2>(3)
    wire T_174244 : UInt<2>[1]
    T_174244[0] := UInt<2>(3)
    wire T_174245 : UInt<3>[3]
    T_174245[0] := UInt<3>(0)
    T_174245[1] := UInt<3>(1)
    T_174245[2] := UInt<3>(2)
    wire T_174246 : UInt<2>[2]
    T_174246[0] := UInt<2>(0)
    T_174246[1] := UInt<2>(1)
    wire T_174247 : UInt<2>[3]
    T_174247[0] := UInt<2>(1)
    T_174247[1] := UInt<2>(2)
    T_174247[2] := UInt<2>(3)
    wire T_174248 : UInt<2>[2]
    T_174248[0] := UInt<2>(2)
    T_174248[1] := UInt<2>(3)
    wire T_174249 : UInt<2>[1]
    T_174249[0] := UInt<2>(3)
    wire T_174250 : UInt<3>[3]
    T_174250[0] := UInt<3>(0)
    T_174250[1] := UInt<3>(1)
    T_174250[2] := UInt<3>(2)
    wire T_174251 : UInt<2>[2]
    T_174251[0] := UInt<2>(0)
    T_174251[1] := UInt<2>(1)
    wire T_174252 : UInt<2>[3]
    T_174252[0] := UInt<2>(1)
    T_174252[1] := UInt<2>(2)
    T_174252[2] := UInt<2>(3)
    wire T_174253 : UInt<2>[2]
    T_174253[0] := UInt<2>(2)
    T_174253[1] := UInt<2>(3)
    wire T_174254 : UInt<2>[1]
    T_174254[0] := UInt<2>(3)
    cmem ram : {addr_beat : UInt<2>, client_xact_id : UInt<1>}[4]
    reg T_174255 : UInt<2>
    onreset T_174255 := UInt<2>(0)
    reg T_174256 : UInt<2>
    onreset T_174256 := UInt<2>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_174255, T_174256)
    node T_174257 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_174257)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_174258 = and(enq.ready, enq.valid)
    node T_174259 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_174258, T_174259)
    node T_174260 = and(deq.ready, deq.valid)
    node T_174261 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_174260, T_174261)
    when do_enq : 
      wire T_174262 : UInt<3>[3]
      T_174262[0] := UInt<3>(0)
      T_174262[1] := UInt<3>(1)
      T_174262[2] := UInt<3>(2)
      wire T_174263 : UInt<2>[2]
      T_174263[0] := UInt<2>(0)
      T_174263[1] := UInt<2>(1)
      wire T_174264 : UInt<2>[3]
      T_174264[0] := UInt<2>(1)
      T_174264[1] := UInt<2>(2)
      T_174264[2] := UInt<2>(3)
      wire T_174265 : UInt<2>[2]
      T_174265[0] := UInt<2>(2)
      T_174265[1] := UInt<2>(3)
      wire T_174266 : UInt<2>[1]
      T_174266[0] := UInt<2>(3)
      accessor T_174267 = ram[T_174255]
      T_174267 := enq.bits
      node T_174268 = eq(T_174255, UInt<2>(3))
      node T_174269 = and(UInt<1>(0), T_174268)
      node T_174270 = addw(T_174255, UInt<1>(1))
      wire T_174271 : UInt<2>
      T_174271 := T_174270
      when T_174269 : T_174271 := UInt<1>(0)
      T_174255 := T_174271
    when do_deq : 
      node T_174272 = eq(T_174256, UInt<2>(3))
      node T_174273 = and(UInt<1>(0), T_174272)
      node T_174274 = addw(T_174256, UInt<1>(1))
      wire T_174275 : UInt<2>
      T_174275 := T_174274
      when T_174273 : T_174275 := UInt<1>(0)
      T_174256 := T_174275
    
    node T_174276 = neq(do_enq, do_deq)
    when T_174276 : maybe_full := do_enq
    node T_174277 = eq(empty, UInt<1>(0))
    node T_174278 = and(UInt<1>(0), enq.valid)
    node T_174279 = or(T_174277, T_174278)
    deq.valid := T_174279
    node T_174280 = eq(full, UInt<1>(0))
    node T_174281 = and(UInt<1>(0), deq.ready)
    node T_174282 = or(T_174280, T_174281)
    enq.ready := T_174282
    wire T_174283 : UInt<3>[3]
    T_174283[0] := UInt<3>(0)
    T_174283[1] := UInt<3>(1)
    T_174283[2] := UInt<3>(2)
    wire T_174284 : UInt<2>[2]
    T_174284[0] := UInt<2>(0)
    T_174284[1] := UInt<2>(1)
    wire T_174285 : UInt<2>[3]
    T_174285[0] := UInt<2>(1)
    T_174285[1] := UInt<2>(2)
    T_174285[2] := UInt<2>(3)
    wire T_174286 : UInt<2>[2]
    T_174286[0] := UInt<2>(2)
    T_174286[1] := UInt<2>(3)
    wire T_174287 : UInt<2>[1]
    T_174287[0] := UInt<2>(3)
    accessor T_174288 = ram[T_174256]
    wire T_174289 : UInt<3>[3]
    T_174289[0] := UInt<3>(0)
    T_174289[1] := UInt<3>(1)
    T_174289[2] := UInt<3>(2)
    wire T_174290 : UInt<2>[2]
    T_174290[0] := UInt<2>(0)
    T_174290[1] := UInt<2>(1)
    wire T_174291 : UInt<2>[3]
    T_174291[0] := UInt<2>(1)
    T_174291[1] := UInt<2>(2)
    T_174291[2] := UInt<2>(3)
    wire T_174292 : UInt<2>[2]
    T_174292[0] := UInt<2>(2)
    T_174292[1] := UInt<2>(3)
    wire T_174293 : UInt<2>[1]
    T_174293[0] := UInt<2>(3)
    wire T_174294 : {addr_beat : UInt<2>, client_xact_id : UInt<1>}
    T_174294 := T_174288
    when maybe_flow : T_174294 := enq.bits
    deq.bits := T_174294
    node ptr_diff = subw(T_174255, T_174256)
    node T_174295 = and(maybe_full, ptr_match)
    node T_174296 = cat(T_174295, ptr_diff)
    count := T_174296
  module AMOALU_87374 : 
    input addr : UInt<6>
    input cmd : UInt<5>
    input typ : UInt<3>
    input lhs : UInt<64>
    input rhs : UInt<64>
    output out : UInt<64>
    
    node T_174297 = eq(typ, UInt<3>(0))
    node T_174298 = eq(typ, UInt<3>(4))
    node T_174299 = or(T_174297, T_174298)
    node T_174300 = eq(typ, UInt<3>(1))
    node T_174301 = eq(typ, UInt<3>(5))
    node T_174302 = or(T_174300, T_174301)
    node T_174303 = eq(typ, UInt<3>(2))
    node T_174304 = eq(typ, UInt<3>(6))
    node T_174305 = or(T_174303, T_174304)
    node T_174306 = bits(rhs, 31, 0)
    node T_174307 = cat(T_174306, T_174306)
    wire rhs : UInt<64>
    rhs := rhs
    when T_174305 : rhs := T_174307
    node T_174308 = eq(cmd, UInt<5>(12))
    node T_174309 = eq(cmd, UInt<5>(13))
    node sgned = or(T_174308, T_174309)
    node T_174310 = eq(cmd, UInt<5>(13))
    node T_174311 = eq(cmd, UInt<5>(15))
    node max = or(T_174310, T_174311)
    node T_174312 = eq(cmd, UInt<5>(12))
    node T_174313 = eq(cmd, UInt<5>(14))
    node min = or(T_174312, T_174313)
    node T_174314 = eq(typ, UInt<3>(2))
    node T_174315 = eq(typ, UInt<3>(6))
    node T_174316 = or(T_174314, T_174315)
    node T_174317 = eq(typ, UInt<3>(0))
    node T_174318 = or(T_174316, T_174317)
    node T_174319 = eq(typ, UInt<3>(4))
    node word = or(T_174318, T_174319)
    node T_174320 = not(UInt<64>(0))
    node T_174321 = bit(addr, 2)
    node T_174322 = dshl(T_174321, UInt<5>(31))
    node mask = xor(T_174320, T_174322)
    node T_174323 = and(lhs, mask)
    node T_174324 = and(rhs, mask)
    node adder_out = addw(T_174323, T_174324)
    node T_174325 = bit(addr, 2)
    node T_174326 = eq(T_174325, UInt<1>(0))
    node T_174327 = and(word, T_174326)
    node T_174328 = bit(lhs, 31)
    node T_174329 = bit(lhs, 63)
    wire cmp_lhs : UInt<1>
    cmp_lhs := T_174329
    when T_174327 : cmp_lhs := T_174328
    node T_174330 = bit(addr, 2)
    node T_174331 = eq(T_174330, UInt<1>(0))
    node T_174332 = and(word, T_174331)
    node T_174333 = bit(rhs, 31)
    node T_174334 = bit(rhs, 63)
    wire cmp_rhs : UInt<1>
    cmp_rhs := T_174334
    when T_174332 : cmp_rhs := T_174333
    node T_174335 = bits(lhs, 31, 0)
    node T_174336 = bits(rhs, 31, 0)
    node lt_lo = lt(T_174335, T_174336)
    node T_174337 = bits(lhs, 63, 32)
    node T_174338 = bits(rhs, 63, 32)
    node lt_hi = lt(T_174337, T_174338)
    node T_174339 = bits(lhs, 63, 32)
    node T_174340 = bits(rhs, 63, 32)
    node eq_hi = eq(T_174339, T_174340)
    node T_174341 = bit(addr, 2)
    wire T_174342 : UInt<1>
    T_174342 := lt_lo
    when T_174341 : T_174342 := lt_hi
    node T_174343 = and(eq_hi, lt_lo)
    node T_174344 = or(lt_hi, T_174343)
    wire lt : UInt<1>
    lt := T_174344
    when word : lt := T_174342
    node T_174345 = eq(cmp_lhs, cmp_rhs)
    wire T_174346 : UInt<1>
    T_174346 := cmp_rhs
    when sgned : T_174346 := cmp_lhs
    wire less : UInt<1>
    less := T_174346
    when T_174345 : less := lt
    node T_174347 = eq(cmd, UInt<5>(8))
    node T_174348 = eq(cmd, UInt<5>(11))
    node T_174349 = and(lhs, rhs)
    node T_174350 = eq(cmd, UInt<5>(10))
    node T_174351 = or(lhs, rhs)
    node T_174352 = eq(cmd, UInt<5>(9))
    node T_174353 = xor(lhs, rhs)
    wire T_174354 : UInt<1>
    T_174354 := max
    when less : T_174354 := min
    node T_174355 = bits(rhs, 7, 0)
    node T_174356 = cat(T_174355, T_174355)
    node T_174357 = cat(T_174356, T_174356)
    node T_174358 = cat(T_174357, T_174357)
    node T_174359 = bits(rhs, 15, 0)
    node T_174360 = cat(T_174359, T_174359)
    node T_174361 = cat(T_174360, T_174360)
    wire T_174362 : UInt<64>
    T_174362 := rhs
    when T_174302 : T_174362 := T_174361
    wire T_174363 : UInt<64>
    T_174363 := T_174362
    when T_174299 : T_174363 := T_174358
    wire T_174364 : UInt<64>
    T_174364 := T_174363
    when T_174354 : T_174364 := lhs
    wire T_174365 : UInt<64>
    T_174365 := T_174364
    when T_174352 : T_174365 := T_174353
    wire T_174366 : UInt<64>
    T_174366 := T_174365
    when T_174350 : T_174366 := T_174351
    wire T_174367 : UInt<64>
    T_174367 := T_174366
    when T_174348 : T_174367 := T_174349
    wire out : UInt<64>
    out := T_174367
    when T_174347 : out := adder_out
    node T_174368 = bits(addr, 2, 0)
    node T_174369 = dshl(UInt<1>(1), T_174368)
    node T_174370 = bits(addr, 2, 1)
    node T_174371 = cat(T_174370, UInt<1>(0))
    node T_174372 = dshl(UInt<2>(3), T_174371)
    node T_174373 = bit(addr, 2)
    node T_174374 = cat(T_174373, UInt<2>(0))
    node T_174375 = dshl(UInt<4>(15), T_174374)
    wire T_174376 : UInt<8>
    T_174376 := UInt<8>(255)
    when T_174305 : T_174376 := T_174375
    wire T_174377 : UInt<8>
    T_174377 := T_174376
    when T_174302 : T_174377 := T_174372
    wire T_174378 : UInt<8>
    T_174378 := T_174377
    when T_174299 : T_174378 := T_174369
    node T_174379 = bit(T_174378, 0)
    node T_174380 = bit(T_174378, 1)
    node T_174381 = bit(T_174378, 2)
    node T_174382 = bit(T_174378, 3)
    node T_174383 = bit(T_174378, 4)
    node T_174384 = bit(T_174378, 5)
    node T_174385 = bit(T_174378, 6)
    node T_174386 = bit(T_174378, 7)
    wire T_174387 : UInt<1>[8]
    T_174387[0] := T_174379
    T_174387[1] := T_174380
    T_174387[2] := T_174381
    T_174387[3] := T_174382
    T_174387[4] := T_174383
    T_174387[5] := T_174384
    T_174387[6] := T_174385
    T_174387[7] := T_174386
    node T_174388 = subw(UInt<8>(0), UInt<4>(8))
    node T_174389 = subw(UInt<8>(0), UInt<4>(8))
    node T_174390 = subw(UInt<8>(0), UInt<4>(8))
    node T_174391 = subw(UInt<8>(0), UInt<4>(8))
    node T_174392 = subw(UInt<8>(0), UInt<4>(8))
    node T_174393 = subw(UInt<8>(0), UInt<4>(8))
    node T_174394 = subw(UInt<8>(0), UInt<4>(8))
    node T_174395 = subw(UInt<8>(0), UInt<4>(8))
    wire T_174396 : UInt<8>[8]
    T_174396[0] := T_174388
    T_174396[1] := T_174389
    T_174396[2] := T_174390
    T_174396[3] := T_174391
    T_174396[4] := T_174392
    T_174396[5] := T_174393
    T_174396[6] := T_174394
    T_174396[7] := T_174395
    node T_174397 = cat(T_174396[7], T_174396[6])
    node T_174398 = cat(T_174396[5], T_174396[4])
    node T_174399 = cat(T_174397, T_174398)
    node T_174400 = cat(T_174396[3], T_174396[2])
    node T_174401 = cat(T_174396[1], T_174396[0])
    node T_174402 = cat(T_174400, T_174401)
    node wmask = cat(T_174399, T_174402)
    node T_174403 = and(wmask, out)
    node T_174404 = not(wmask)
    node T_174405 = and(T_174404, lhs)
    node T_174406 = or(T_174403, T_174405)
    out := T_174406
  module L2AcquireTracker_93254 : 
    output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input incoherent : UInt<1>[1]
    output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output has_acquire_conflict : UInt<1>
    output has_acquire_match : UInt<1>
    output has_release_match : UInt<1>
    output data : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}}
    output meta : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, tag_match : UInt<1>, meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, way_en : UInt<8>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}}
    output wb : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>}}}
    
    wire T_174407 : UInt<3>[3]
    T_174407[0] := UInt<3>(0)
    T_174407[1] := UInt<3>(1)
    T_174407[2] := UInt<3>(2)
    wire T_174408 : UInt<2>[2]
    T_174408[0] := UInt<2>(0)
    T_174408[1] := UInt<2>(1)
    wire T_174409 : UInt<2>[3]
    T_174409[0] := UInt<2>(1)
    T_174409[1] := UInt<2>(2)
    T_174409[2] := UInt<2>(3)
    wire T_174410 : UInt<2>[2]
    T_174410[0] := UInt<2>(2)
    T_174410[1] := UInt<2>(3)
    wire T_174411 : UInt<2>[1]
    T_174411[0] := UInt<2>(3)
    wire T_174412 : UInt<3>[3]
    T_174412[0] := UInt<3>(0)
    T_174412[1] := UInt<3>(1)
    T_174412[2] := UInt<3>(2)
    wire T_174413 : UInt<2>[2]
    T_174413[0] := UInt<2>(0)
    T_174413[1] := UInt<2>(1)
    wire T_174414 : UInt<2>[3]
    T_174414[0] := UInt<2>(1)
    T_174414[1] := UInt<2>(2)
    T_174414[2] := UInt<2>(3)
    wire T_174415 : UInt<2>[2]
    T_174415[0] := UInt<2>(2)
    T_174415[1] := UInt<2>(3)
    wire T_174416 : UInt<2>[1]
    T_174416[0] := UInt<2>(3)
    wire T_174417 : UInt<3>[3]
    T_174417[0] := UInt<3>(0)
    T_174417[1] := UInt<3>(1)
    T_174417[2] := UInt<3>(2)
    wire T_174418 : UInt<2>[2]
    T_174418[0] := UInt<2>(0)
    T_174418[1] := UInt<2>(1)
    wire T_174419 : UInt<2>[3]
    T_174419[0] := UInt<2>(1)
    T_174419[1] := UInt<2>(2)
    T_174419[2] := UInt<2>(3)
    wire T_174420 : UInt<2>[2]
    T_174420[0] := UInt<2>(2)
    T_174420[1] := UInt<2>(3)
    wire T_174421 : UInt<2>[1]
    T_174421[0] := UInt<2>(3)
    wire T_174422 : UInt<3>[3]
    T_174422[0] := UInt<3>(0)
    T_174422[1] := UInt<3>(1)
    T_174422[2] := UInt<3>(2)
    wire T_174423 : UInt<2>[2]
    T_174423[0] := UInt<2>(0)
    T_174423[1] := UInt<2>(1)
    wire T_174424 : UInt<2>[3]
    T_174424[0] := UInt<2>(1)
    T_174424[1] := UInt<2>(2)
    T_174424[2] := UInt<2>(3)
    wire T_174425 : UInt<2>[2]
    T_174425[0] := UInt<2>(2)
    T_174425[1] := UInt<2>(3)
    wire T_174426 : UInt<2>[1]
    T_174426[0] := UInt<2>(3)
    wire T_174427 : UInt<3>[3]
    T_174427[0] := UInt<3>(0)
    T_174427[1] := UInt<3>(1)
    T_174427[2] := UInt<3>(2)
    wire T_174428 : UInt<2>[2]
    T_174428[0] := UInt<2>(0)
    T_174428[1] := UInt<2>(1)
    wire T_174429 : UInt<2>[3]
    T_174429[0] := UInt<2>(1)
    T_174429[1] := UInt<2>(2)
    T_174429[2] := UInt<2>(3)
    wire T_174430 : UInt<2>[2]
    T_174430[0] := UInt<2>(2)
    T_174430[1] := UInt<2>(3)
    wire T_174431 : UInt<2>[1]
    T_174431[0] := UInt<2>(3)
    wire T_174432 : UInt<3>[3]
    T_174432[0] := UInt<3>(0)
    T_174432[1] := UInt<3>(1)
    T_174432[2] := UInt<3>(2)
    wire T_174433 : UInt<2>[2]
    T_174433[0] := UInt<2>(0)
    T_174433[1] := UInt<2>(1)
    wire T_174434 : UInt<2>[3]
    T_174434[0] := UInt<2>(1)
    T_174434[1] := UInt<2>(2)
    T_174434[2] := UInt<2>(3)
    wire T_174435 : UInt<2>[2]
    T_174435[0] := UInt<2>(2)
    T_174435[1] := UInt<2>(3)
    wire T_174436 : UInt<2>[1]
    T_174436[0] := UInt<2>(3)
    wire T_174437 : UInt<3>[3]
    T_174437[0] := UInt<3>(0)
    T_174437[1] := UInt<3>(1)
    T_174437[2] := UInt<3>(2)
    wire T_174438 : UInt<2>[2]
    T_174438[0] := UInt<2>(0)
    T_174438[1] := UInt<2>(1)
    wire T_174439 : UInt<2>[3]
    T_174439[0] := UInt<2>(1)
    T_174439[1] := UInt<2>(2)
    T_174439[2] := UInt<2>(3)
    wire T_174440 : UInt<2>[2]
    T_174440[0] := UInt<2>(2)
    T_174440[1] := UInt<2>(3)
    wire T_174441 : UInt<2>[1]
    T_174441[0] := UInt<2>(3)
    wire T_174442 : UInt<3>[3]
    T_174442[0] := UInt<3>(0)
    T_174442[1] := UInt<3>(1)
    T_174442[2] := UInt<3>(2)
    wire T_174443 : UInt<2>[2]
    T_174443[0] := UInt<2>(0)
    T_174443[1] := UInt<2>(1)
    wire T_174444 : UInt<2>[3]
    T_174444[0] := UInt<2>(1)
    T_174444[1] := UInt<2>(2)
    T_174444[2] := UInt<2>(3)
    wire T_174445 : UInt<2>[2]
    T_174445[0] := UInt<2>(2)
    T_174445[1] := UInt<2>(3)
    wire T_174446 : UInt<2>[1]
    T_174446[0] := UInt<2>(3)
    wire T_174447 : UInt<3>[3]
    T_174447[0] := UInt<3>(0)
    T_174447[1] := UInt<3>(1)
    T_174447[2] := UInt<3>(2)
    wire T_174448 : UInt<2>[2]
    T_174448[0] := UInt<2>(0)
    T_174448[1] := UInt<2>(1)
    wire T_174449 : UInt<2>[3]
    T_174449[0] := UInt<2>(1)
    T_174449[1] := UInt<2>(2)
    T_174449[2] := UInt<2>(3)
    wire T_174450 : UInt<2>[2]
    T_174450[0] := UInt<2>(2)
    T_174450[1] := UInt<2>(3)
    wire T_174451 : UInt<2>[1]
    T_174451[0] := UInt<2>(3)
    wire T_174452 : UInt<3>[3]
    T_174452[0] := UInt<3>(0)
    T_174452[1] := UInt<3>(1)
    T_174452[2] := UInt<3>(2)
    wire T_174453 : UInt<2>[2]
    T_174453[0] := UInt<2>(0)
    T_174453[1] := UInt<2>(1)
    wire T_174454 : UInt<2>[3]
    T_174454[0] := UInt<2>(1)
    T_174454[1] := UInt<2>(2)
    T_174454[2] := UInt<2>(3)
    wire T_174455 : UInt<2>[2]
    T_174455[0] := UInt<2>(2)
    T_174455[1] := UInt<2>(3)
    wire T_174456 : UInt<2>[1]
    T_174456[0] := UInt<2>(3)
    wire T_174457 : UInt<3>[3]
    T_174457[0] := UInt<3>(0)
    T_174457[1] := UInt<3>(1)
    T_174457[2] := UInt<3>(2)
    wire T_174458 : UInt<2>[2]
    T_174458[0] := UInt<2>(0)
    T_174458[1] := UInt<2>(1)
    wire T_174459 : UInt<2>[3]
    T_174459[0] := UInt<2>(1)
    T_174459[1] := UInt<2>(2)
    T_174459[2] := UInt<2>(3)
    wire T_174460 : UInt<2>[2]
    T_174460[0] := UInt<2>(2)
    T_174460[1] := UInt<2>(3)
    wire T_174461 : UInt<2>[1]
    T_174461[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_174462
    wire T_174463 : UInt<3>[3]
    T_174463[0] := UInt<3>(0)
    T_174463[1] := UInt<3>(1)
    T_174463[2] := UInt<3>(2)
    wire T_174464 : UInt<0>[1]
    T_174464[0] := UInt<0>(0)
    wire T_174465 : UInt<2>[2]
    T_174465[0] := UInt<2>(1)
    T_174465[1] := UInt<2>(2)
    wire T_174466 : UInt<2>[2]
    T_174466[0] := UInt<2>(1)
    T_174466[1] := UInt<2>(2)
    wire T_174467 : UInt<2>[1]
    T_174467[0] := UInt<2>(2)
    wire T_174468 : UInt<3>[3]
    T_174468[0] := UInt<3>(0)
    T_174468[1] := UInt<3>(1)
    T_174468[2] := UInt<3>(2)
    wire T_174469 : UInt<0>[1]
    T_174469[0] := UInt<0>(0)
    wire T_174470 : UInt<2>[2]
    T_174470[0] := UInt<2>(1)
    T_174470[1] := UInt<2>(2)
    wire T_174471 : UInt<2>[2]
    T_174471[0] := UInt<2>(1)
    T_174471[1] := UInt<2>(2)
    wire T_174472 : UInt<2>[1]
    T_174472[0] := UInt<2>(2)
    wire T_174473 : UInt<3>[3]
    T_174473[0] := UInt<3>(0)
    T_174473[1] := UInt<3>(1)
    T_174473[2] := UInt<3>(2)
    wire T_174474 : UInt<0>[1]
    T_174474[0] := UInt<0>(0)
    wire T_174475 : UInt<2>[2]
    T_174475[0] := UInt<2>(1)
    T_174475[1] := UInt<2>(2)
    wire T_174476 : UInt<2>[2]
    T_174476[0] := UInt<2>(1)
    T_174476[1] := UInt<2>(2)
    wire T_174477 : UInt<2>[1]
    T_174477[0] := UInt<2>(2)
    wire T_174478 : UInt<3>[3]
    T_174478[0] := UInt<3>(0)
    T_174478[1] := UInt<3>(1)
    T_174478[2] := UInt<3>(2)
    wire T_174479 : UInt<0>[1]
    T_174479[0] := UInt<0>(0)
    wire T_174480 : UInt<2>[2]
    T_174480[0] := UInt<2>(1)
    T_174480[1] := UInt<2>(2)
    wire T_174481 : UInt<2>[2]
    T_174481[0] := UInt<2>(1)
    T_174481[1] := UInt<2>(2)
    wire T_174482 : UInt<2>[1]
    T_174482[0] := UInt<2>(2)
    wire T_174483 : UInt<3>[3]
    T_174483[0] := UInt<3>(0)
    T_174483[1] := UInt<3>(1)
    T_174483[2] := UInt<3>(2)
    wire T_174484 : UInt<0>[1]
    T_174484[0] := UInt<0>(0)
    wire T_174485 : UInt<2>[2]
    T_174485[0] := UInt<2>(1)
    T_174485[1] := UInt<2>(2)
    wire T_174486 : UInt<2>[2]
    T_174486[0] := UInt<2>(1)
    T_174486[1] := UInt<2>(2)
    wire T_174487 : UInt<2>[1]
    T_174487[0] := UInt<2>(2)
    wire T_174488 : UInt<3>[3]
    T_174488[0] := UInt<3>(0)
    T_174488[1] := UInt<3>(1)
    T_174488[2] := UInt<3>(2)
    wire T_174489 : UInt<0>[1]
    T_174489[0] := UInt<0>(0)
    wire T_174490 : UInt<2>[2]
    T_174490[0] := UInt<2>(1)
    T_174490[1] := UInt<2>(2)
    wire T_174491 : UInt<2>[2]
    T_174491[0] := UInt<2>(1)
    T_174491[1] := UInt<2>(2)
    wire T_174492 : UInt<2>[1]
    T_174492[0] := UInt<2>(2)
    wire T_174493 : UInt<3>[3]
    T_174493[0] := UInt<3>(0)
    T_174493[1] := UInt<3>(1)
    T_174493[2] := UInt<3>(2)
    wire T_174494 : UInt<0>[1]
    T_174494[0] := UInt<0>(0)
    wire T_174495 : UInt<2>[2]
    T_174495[0] := UInt<2>(1)
    T_174495[1] := UInt<2>(2)
    wire T_174496 : UInt<2>[2]
    T_174496[0] := UInt<2>(1)
    T_174496[1] := UInt<2>(2)
    wire T_174497 : UInt<2>[1]
    T_174497[0] := UInt<2>(2)
    wire T_174498 : UInt<3>[3]
    T_174498[0] := UInt<3>(0)
    T_174498[1] := UInt<3>(1)
    T_174498[2] := UInt<3>(2)
    wire T_174499 : UInt<0>[1]
    T_174499[0] := UInt<0>(0)
    wire T_174500 : UInt<2>[2]
    T_174500[0] := UInt<2>(1)
    T_174500[1] := UInt<2>(2)
    wire T_174501 : UInt<2>[2]
    T_174501[0] := UInt<2>(1)
    T_174501[1] := UInt<2>(2)
    wire T_174502 : UInt<2>[1]
    T_174502[0] := UInt<2>(2)
    wire T_174503 : UInt<3>[3]
    T_174503[0] := UInt<3>(0)
    T_174503[1] := UInt<3>(1)
    T_174503[2] := UInt<3>(2)
    wire T_174504 : UInt<0>[1]
    T_174504[0] := UInt<0>(0)
    wire T_174505 : UInt<2>[2]
    T_174505[0] := UInt<2>(1)
    T_174505[1] := UInt<2>(2)
    wire T_174506 : UInt<2>[2]
    T_174506[0] := UInt<2>(1)
    T_174506[1] := UInt<2>(2)
    wire T_174507 : UInt<2>[1]
    T_174507[0] := UInt<2>(2)
    wire T_174508 : UInt<3>[3]
    T_174508[0] := UInt<3>(0)
    T_174508[1] := UInt<3>(1)
    T_174508[2] := UInt<3>(2)
    wire T_174509 : UInt<2>[2]
    T_174509[0] := UInt<2>(0)
    T_174509[1] := UInt<2>(1)
    wire T_174510 : UInt<2>[3]
    T_174510[0] := UInt<2>(1)
    T_174510[1] := UInt<2>(2)
    T_174510[2] := UInt<2>(3)
    wire T_174511 : UInt<2>[2]
    T_174511[0] := UInt<2>(2)
    T_174511[1] := UInt<2>(3)
    wire T_174512 : UInt<2>[1]
    T_174512[0] := UInt<2>(3)
    wire T_174513 : UInt<3>[3]
    T_174513[0] := UInt<3>(0)
    T_174513[1] := UInt<3>(1)
    T_174513[2] := UInt<3>(2)
    wire T_174514 : UInt<2>[2]
    T_174514[0] := UInt<2>(0)
    T_174514[1] := UInt<2>(1)
    wire T_174515 : UInt<2>[3]
    T_174515[0] := UInt<2>(1)
    T_174515[1] := UInt<2>(2)
    T_174515[2] := UInt<2>(3)
    wire T_174516 : UInt<2>[2]
    T_174516[0] := UInt<2>(2)
    T_174516[1] := UInt<2>(3)
    wire T_174517 : UInt<2>[1]
    T_174517[0] := UInt<2>(3)
    wire T_174518 : UInt<3>[3]
    T_174518[0] := UInt<3>(0)
    T_174518[1] := UInt<3>(1)
    T_174518[2] := UInt<3>(2)
    wire T_174519 : UInt<0>[1]
    T_174519[0] := UInt<0>(0)
    wire T_174520 : UInt<2>[2]
    T_174520[0] := UInt<2>(1)
    T_174520[1] := UInt<2>(2)
    wire T_174521 : UInt<2>[2]
    T_174521[0] := UInt<2>(1)
    T_174521[1] := UInt<2>(2)
    wire T_174522 : UInt<2>[1]
    T_174522[0] := UInt<2>(2)
    wire T_174523 : UInt<3>[3]
    T_174523[0] := UInt<3>(0)
    T_174523[1] := UInt<3>(1)
    T_174523[2] := UInt<3>(2)
    wire T_174524 : UInt<2>[2]
    T_174524[0] := UInt<2>(0)
    T_174524[1] := UInt<2>(1)
    wire T_174525 : UInt<2>[3]
    T_174525[0] := UInt<2>(1)
    T_174525[1] := UInt<2>(2)
    T_174525[2] := UInt<2>(3)
    wire T_174526 : UInt<2>[2]
    T_174526[0] := UInt<2>(2)
    T_174526[1] := UInt<2>(3)
    wire T_174527 : UInt<2>[1]
    T_174527[0] := UInt<2>(3)
    wire T_174528 : UInt<3>[3]
    T_174528[0] := UInt<3>(0)
    T_174528[1] := UInt<3>(1)
    T_174528[2] := UInt<3>(2)
    wire T_174529 : UInt<2>[2]
    T_174529[0] := UInt<2>(0)
    T_174529[1] := UInt<2>(1)
    wire T_174530 : UInt<2>[3]
    T_174530[0] := UInt<2>(1)
    T_174530[1] := UInt<2>(2)
    T_174530[2] := UInt<2>(3)
    wire T_174531 : UInt<2>[2]
    T_174531[0] := UInt<2>(2)
    T_174531[1] := UInt<2>(3)
    wire T_174532 : UInt<2>[1]
    T_174532[0] := UInt<2>(3)
    wire T_174533 : UInt<3>[3]
    T_174533[0] := UInt<3>(0)
    T_174533[1] := UInt<3>(1)
    T_174533[2] := UInt<3>(2)
    wire T_174534 : UInt<0>[1]
    T_174534[0] := UInt<0>(0)
    wire T_174535 : UInt<2>[2]
    T_174535[0] := UInt<2>(1)
    T_174535[1] := UInt<2>(2)
    wire T_174536 : UInt<2>[2]
    T_174536[0] := UInt<2>(1)
    T_174536[1] := UInt<2>(2)
    wire T_174537 : UInt<2>[1]
    T_174537[0] := UInt<2>(2)
    wire T_174538 : UInt<3>[3]
    T_174538[0] := UInt<3>(0)
    T_174538[1] := UInt<3>(1)
    T_174538[2] := UInt<3>(2)
    wire T_174539 : UInt<2>[2]
    T_174539[0] := UInt<2>(0)
    T_174539[1] := UInt<2>(1)
    wire T_174540 : UInt<2>[3]
    T_174540[0] := UInt<2>(1)
    T_174540[1] := UInt<2>(2)
    T_174540[2] := UInt<2>(3)
    wire T_174541 : UInt<2>[2]
    T_174541[0] := UInt<2>(2)
    T_174541[1] := UInt<2>(3)
    wire T_174542 : UInt<2>[1]
    T_174542[0] := UInt<2>(3)
    wire T_174543 : UInt<3>[3]
    T_174543[0] := UInt<3>(0)
    T_174543[1] := UInt<3>(1)
    T_174543[2] := UInt<3>(2)
    wire T_174544 : UInt<2>[2]
    T_174544[0] := UInt<2>(0)
    T_174544[1] := UInt<2>(1)
    wire T_174545 : UInt<2>[3]
    T_174545[0] := UInt<2>(1)
    T_174545[1] := UInt<2>(2)
    T_174545[2] := UInt<2>(3)
    wire T_174546 : UInt<2>[2]
    T_174546[0] := UInt<2>(2)
    T_174546[1] := UInt<2>(3)
    wire T_174547 : UInt<2>[1]
    T_174547[0] := UInt<2>(3)
    wire T_174548 : UInt<3>[3]
    T_174548[0] := UInt<3>(0)
    T_174548[1] := UInt<3>(1)
    T_174548[2] := UInt<3>(2)
    wire T_174549 : UInt<0>[1]
    T_174549[0] := UInt<0>(0)
    wire T_174550 : UInt<2>[2]
    T_174550[0] := UInt<2>(1)
    T_174550[1] := UInt<2>(2)
    wire T_174551 : UInt<2>[2]
    T_174551[0] := UInt<2>(1)
    T_174551[1] := UInt<2>(2)
    wire T_174552 : UInt<2>[1]
    T_174552[0] := UInt<2>(2)
    wire T_174553 : UInt<3>[3]
    T_174553[0] := UInt<3>(0)
    T_174553[1] := UInt<3>(1)
    T_174553[2] := UInt<3>(2)
    wire T_174554 : UInt<2>[2]
    T_174554[0] := UInt<2>(0)
    T_174554[1] := UInt<2>(1)
    wire T_174555 : UInt<2>[3]
    T_174555[0] := UInt<2>(1)
    T_174555[1] := UInt<2>(2)
    T_174555[2] := UInt<2>(3)
    wire T_174556 : UInt<2>[2]
    T_174556[0] := UInt<2>(2)
    T_174556[1] := UInt<2>(3)
    wire T_174557 : UInt<2>[1]
    T_174557[0] := UInt<2>(3)
    wire T_174558 : UInt<3>[3]
    T_174558[0] := UInt<3>(0)
    T_174558[1] := UInt<3>(1)
    T_174558[2] := UInt<3>(2)
    wire T_174559 : UInt<2>[2]
    T_174559[0] := UInt<2>(0)
    T_174559[1] := UInt<2>(1)
    wire T_174560 : UInt<2>[3]
    T_174560[0] := UInt<2>(1)
    T_174560[1] := UInt<2>(2)
    T_174560[2] := UInt<2>(3)
    wire T_174561 : UInt<2>[2]
    T_174561[0] := UInt<2>(2)
    T_174561[1] := UInt<2>(3)
    wire T_174562 : UInt<2>[1]
    T_174562[0] := UInt<2>(3)
    wire T_174563 : UInt<3>[3]
    T_174563[0] := UInt<3>(0)
    T_174563[1] := UInt<3>(1)
    T_174563[2] := UInt<3>(2)
    wire T_174564 : UInt<0>[1]
    T_174564[0] := UInt<0>(0)
    wire T_174565 : UInt<2>[2]
    T_174565[0] := UInt<2>(1)
    T_174565[1] := UInt<2>(2)
    wire T_174566 : UInt<2>[2]
    T_174566[0] := UInt<2>(1)
    T_174566[1] := UInt<2>(2)
    wire T_174567 : UInt<2>[1]
    T_174567[0] := UInt<2>(2)
    wire T_174568 : UInt<3>[3]
    T_174568[0] := UInt<3>(0)
    T_174568[1] := UInt<3>(1)
    T_174568[2] := UInt<3>(2)
    wire T_174569 : UInt<2>[2]
    T_174569[0] := UInt<2>(0)
    T_174569[1] := UInt<2>(1)
    wire T_174570 : UInt<2>[3]
    T_174570[0] := UInt<2>(1)
    T_174570[1] := UInt<2>(2)
    T_174570[2] := UInt<2>(3)
    wire T_174571 : UInt<2>[2]
    T_174571[0] := UInt<2>(2)
    T_174571[1] := UInt<2>(3)
    wire T_174572 : UInt<2>[1]
    T_174572[0] := UInt<2>(3)
    wire T_174573 : UInt<3>[3]
    T_174573[0] := UInt<3>(0)
    T_174573[1] := UInt<3>(1)
    T_174573[2] := UInt<3>(2)
    wire T_174574 : UInt<2>[2]
    T_174574[0] := UInt<2>(0)
    T_174574[1] := UInt<2>(1)
    wire T_174575 : UInt<2>[3]
    T_174575[0] := UInt<2>(1)
    T_174575[1] := UInt<2>(2)
    T_174575[2] := UInt<2>(3)
    wire T_174576 : UInt<2>[2]
    T_174576[0] := UInt<2>(2)
    T_174576[1] := UInt<2>(3)
    wire T_174577 : UInt<2>[1]
    T_174577[0] := UInt<2>(3)
    wire T_174578 : UInt<3>[3]
    T_174578[0] := UInt<3>(0)
    T_174578[1] := UInt<3>(1)
    T_174578[2] := UInt<3>(2)
    wire T_174579 : UInt<0>[1]
    T_174579[0] := UInt<0>(0)
    wire T_174580 : UInt<2>[2]
    T_174580[0] := UInt<2>(1)
    T_174580[1] := UInt<2>(2)
    wire T_174581 : UInt<2>[2]
    T_174581[0] := UInt<2>(1)
    T_174581[1] := UInt<2>(2)
    wire T_174582 : UInt<2>[1]
    T_174582[0] := UInt<2>(2)
    wire T_174583 : UInt<3>[3]
    T_174583[0] := UInt<3>(0)
    T_174583[1] := UInt<3>(1)
    T_174583[2] := UInt<3>(2)
    wire T_174584 : UInt<2>[2]
    T_174584[0] := UInt<2>(0)
    T_174584[1] := UInt<2>(1)
    wire T_174585 : UInt<2>[3]
    T_174585[0] := UInt<2>(1)
    T_174585[1] := UInt<2>(2)
    T_174585[2] := UInt<2>(3)
    wire T_174586 : UInt<2>[2]
    T_174586[0] := UInt<2>(2)
    T_174586[1] := UInt<2>(3)
    wire T_174587 : UInt<2>[1]
    T_174587[0] := UInt<2>(3)
    wire T_174588 : UInt<3>[3]
    T_174588[0] := UInt<3>(0)
    T_174588[1] := UInt<3>(1)
    T_174588[2] := UInt<3>(2)
    wire T_174589 : UInt<2>[2]
    T_174589[0] := UInt<2>(0)
    T_174589[1] := UInt<2>(1)
    wire T_174590 : UInt<2>[3]
    T_174590[0] := UInt<2>(1)
    T_174590[1] := UInt<2>(2)
    T_174590[2] := UInt<2>(3)
    wire T_174591 : UInt<2>[2]
    T_174591[0] := UInt<2>(2)
    T_174591[1] := UInt<2>(3)
    wire T_174592 : UInt<2>[1]
    T_174592[0] := UInt<2>(3)
    wire T_174593 : UInt<3>[3]
    T_174593[0] := UInt<3>(0)
    T_174593[1] := UInt<3>(1)
    T_174593[2] := UInt<3>(2)
    wire T_174594 : UInt<0>[1]
    T_174594[0] := UInt<0>(0)
    wire T_174595 : UInt<2>[2]
    T_174595[0] := UInt<2>(1)
    T_174595[1] := UInt<2>(2)
    wire T_174596 : UInt<2>[2]
    T_174596[0] := UInt<2>(1)
    T_174596[1] := UInt<2>(2)
    wire T_174597 : UInt<2>[1]
    T_174597[0] := UInt<2>(2)
    wire T_174598 : UInt<3>[3]
    T_174598[0] := UInt<3>(0)
    T_174598[1] := UInt<3>(1)
    T_174598[2] := UInt<3>(2)
    wire T_174599 : UInt<2>[2]
    T_174599[0] := UInt<2>(0)
    T_174599[1] := UInt<2>(1)
    wire T_174600 : UInt<2>[3]
    T_174600[0] := UInt<2>(1)
    T_174600[1] := UInt<2>(2)
    T_174600[2] := UInt<2>(3)
    wire T_174601 : UInt<2>[2]
    T_174601[0] := UInt<2>(2)
    T_174601[1] := UInt<2>(3)
    wire T_174602 : UInt<2>[1]
    T_174602[0] := UInt<2>(3)
    wire T_174603 : UInt<3>[3]
    T_174603[0] := UInt<3>(0)
    T_174603[1] := UInt<3>(1)
    T_174603[2] := UInt<3>(2)
    wire T_174604 : UInt<2>[2]
    T_174604[0] := UInt<2>(0)
    T_174604[1] := UInt<2>(1)
    wire T_174605 : UInt<2>[3]
    T_174605[0] := UInt<2>(1)
    T_174605[1] := UInt<2>(2)
    T_174605[2] := UInt<2>(3)
    wire T_174606 : UInt<2>[2]
    T_174606[0] := UInt<2>(2)
    T_174606[1] := UInt<2>(3)
    wire T_174607 : UInt<2>[1]
    T_174607[0] := UInt<2>(3)
    wire T_174608 : UInt<3>[3]
    T_174608[0] := UInt<3>(0)
    T_174608[1] := UInt<3>(1)
    T_174608[2] := UInt<3>(2)
    wire T_174609 : UInt<0>[1]
    T_174609[0] := UInt<0>(0)
    wire T_174610 : UInt<2>[2]
    T_174610[0] := UInt<2>(1)
    T_174610[1] := UInt<2>(2)
    wire T_174611 : UInt<2>[2]
    T_174611[0] := UInt<2>(1)
    T_174611[1] := UInt<2>(2)
    wire T_174612 : UInt<2>[1]
    T_174612[0] := UInt<2>(2)
    wire T_174613 : UInt<3>[3]
    T_174613[0] := UInt<3>(0)
    T_174613[1] := UInt<3>(1)
    T_174613[2] := UInt<3>(2)
    wire T_174614 : UInt<2>[2]
    T_174614[0] := UInt<2>(0)
    T_174614[1] := UInt<2>(1)
    wire T_174615 : UInt<2>[3]
    T_174615[0] := UInt<2>(1)
    T_174615[1] := UInt<2>(2)
    T_174615[2] := UInt<2>(3)
    wire T_174616 : UInt<2>[2]
    T_174616[0] := UInt<2>(2)
    T_174616[1] := UInt<2>(3)
    wire T_174617 : UInt<2>[1]
    T_174617[0] := UInt<2>(3)
    wire T_174618 : UInt<3>[3]
    T_174618[0] := UInt<3>(0)
    T_174618[1] := UInt<3>(1)
    T_174618[2] := UInt<3>(2)
    wire T_174619 : UInt<2>[2]
    T_174619[0] := UInt<2>(0)
    T_174619[1] := UInt<2>(1)
    wire T_174620 : UInt<2>[3]
    T_174620[0] := UInt<2>(1)
    T_174620[1] := UInt<2>(2)
    T_174620[2] := UInt<2>(3)
    wire T_174621 : UInt<2>[2]
    T_174621[0] := UInt<2>(2)
    T_174621[1] := UInt<2>(3)
    wire T_174622 : UInt<2>[1]
    T_174622[0] := UInt<2>(3)
    wire T_174623 : UInt<3>[3]
    T_174623[0] := UInt<3>(0)
    T_174623[1] := UInt<3>(1)
    T_174623[2] := UInt<3>(2)
    wire T_174624 : UInt<0>[1]
    T_174624[0] := UInt<0>(0)
    wire T_174625 : UInt<2>[2]
    T_174625[0] := UInt<2>(1)
    T_174625[1] := UInt<2>(2)
    wire T_174626 : UInt<2>[2]
    T_174626[0] := UInt<2>(1)
    T_174626[1] := UInt<2>(2)
    wire T_174627 : UInt<2>[1]
    T_174627[0] := UInt<2>(2)
    wb.resp.valid := UInt<1>(0)
    wb.req.valid := UInt<1>(0)
    meta.write.valid := UInt<1>(0)
    meta.resp.valid := UInt<1>(0)
    meta.read.valid := UInt<1>(0)
    data.write.valid := UInt<1>(0)
    data.resp.valid := UInt<1>(0)
    data.read.valid := UInt<1>(0)
    outer.release.valid := UInt<1>(0)
    outer.probe.valid := UInt<1>(0)
    outer.grant.valid := UInt<1>(0)
    outer.acquire.valid := UInt<1>(0)
    inner.release.valid := UInt<1>(0)
    inner.probe.valid := UInt<1>(0)
    inner.finish.valid := UInt<1>(0)
    inner.grant.valid := UInt<1>(0)
    inner.acquire.valid := UInt<1>(0)
    reg state : UInt<4>
    onreset state := UInt<4>(0)
    wire T_174628 : UInt<3>[3]
    T_174628[0] := UInt<3>(0)
    T_174628[1] := UInt<3>(1)
    T_174628[2] := UInt<3>(2)
    wire T_174629 : UInt<2>[2]
    T_174629[0] := UInt<2>(0)
    T_174629[1] := UInt<2>(1)
    wire T_174630 : UInt<2>[3]
    T_174630[0] := UInt<2>(1)
    T_174630[1] := UInt<2>(2)
    T_174630[2] := UInt<2>(3)
    wire T_174631 : UInt<2>[2]
    T_174631[0] := UInt<2>(2)
    T_174631[1] := UInt<2>(3)
    wire T_174632 : UInt<2>[1]
    T_174632[0] := UInt<2>(3)
    wire T_174633 : UInt<3>[3]
    T_174633[0] := UInt<3>(0)
    T_174633[1] := UInt<3>(1)
    T_174633[2] := UInt<3>(2)
    wire T_174634 : UInt<2>[2]
    T_174634[0] := UInt<2>(0)
    T_174634[1] := UInt<2>(1)
    wire T_174635 : UInt<2>[3]
    T_174635[0] := UInt<2>(1)
    T_174635[1] := UInt<2>(2)
    T_174635[2] := UInt<2>(3)
    wire T_174636 : UInt<2>[2]
    T_174636[0] := UInt<2>(2)
    T_174636[1] := UInt<2>(3)
    wire T_174637 : UInt<2>[1]
    T_174637[0] := UInt<2>(3)
    reg xact : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}
    wire T_174638 : UInt<128>[4]
    T_174638[0] := UInt<128>(0)
    T_174638[1] := UInt<128>(0)
    T_174638[2] := UInt<128>(0)
    T_174638[3] := UInt<128>(0)
    reg data_buffer : UInt<128>[4]
    onreset data_buffer := T_174638
    wire T_174639 : UInt<16>[4]
    T_174639[0] := UInt<16>(0)
    T_174639[1] := UInt<16>(0)
    T_174639[2] := UInt<16>(0)
    T_174639[3] := UInt<16>(0)
    reg wmask_buffer : UInt<16>[4]
    onreset wmask_buffer := T_174639
    reg xact_tag_match : UInt<1>
    reg xact_way_en : UInt<8>
    wire T_174640 : UInt<3>[3]
    T_174640[0] := UInt<3>(0)
    T_174640[1] := UInt<3>(1)
    T_174640[2] := UInt<3>(2)
    wire T_174641 : UInt<2>[2]
    T_174641[0] := UInt<2>(0)
    T_174641[1] := UInt<2>(1)
    wire T_174642 : UInt<2>[3]
    T_174642[0] := UInt<2>(1)
    T_174642[1] := UInt<2>(2)
    T_174642[2] := UInt<2>(3)
    wire T_174643 : UInt<2>[2]
    T_174643[0] := UInt<2>(2)
    T_174643[1] := UInt<2>(3)
    wire T_174644 : UInt<2>[1]
    T_174644[0] := UInt<2>(3)
    wire T_174645 : UInt<3>[3]
    T_174645[0] := UInt<3>(0)
    T_174645[1] := UInt<3>(1)
    T_174645[2] := UInt<3>(2)
    wire T_174646 : UInt<2>[2]
    T_174646[0] := UInt<2>(0)
    T_174646[1] := UInt<2>(1)
    wire T_174647 : UInt<2>[3]
    T_174647[0] := UInt<2>(1)
    T_174647[1] := UInt<2>(2)
    T_174647[2] := UInt<2>(3)
    wire T_174648 : UInt<2>[2]
    T_174648[0] := UInt<2>(2)
    T_174648[1] := UInt<2>(3)
    wire T_174649 : UInt<2>[1]
    T_174649[0] := UInt<2>(3)
    wire T_174650 : UInt<3>[3]
    T_174650[0] := UInt<3>(0)
    T_174650[1] := UInt<3>(1)
    T_174650[2] := UInt<3>(2)
    wire T_174651 : UInt<0>[1]
    T_174651[0] := UInt<0>(0)
    wire T_174652 : UInt<2>[2]
    T_174652[0] := UInt<2>(1)
    T_174652[1] := UInt<2>(2)
    wire T_174653 : UInt<2>[2]
    T_174653[0] := UInt<2>(1)
    T_174653[1] := UInt<2>(2)
    wire T_174654 : UInt<2>[1]
    T_174654[0] := UInt<2>(2)
    wire T_174655 : UInt<3>[3]
    T_174655[0] := UInt<3>(0)
    T_174655[1] := UInt<3>(1)
    T_174655[2] := UInt<3>(2)
    wire T_174656 : UInt<2>[2]
    T_174656[0] := UInt<2>(0)
    T_174656[1] := UInt<2>(1)
    wire T_174657 : UInt<2>[3]
    T_174657[0] := UInt<2>(1)
    T_174657[1] := UInt<2>(2)
    T_174657[2] := UInt<2>(3)
    wire T_174658 : UInt<2>[2]
    T_174658[0] := UInt<2>(2)
    T_174658[1] := UInt<2>(3)
    wire T_174659 : UInt<2>[1]
    T_174659[0] := UInt<2>(3)
    wire T_174660 : UInt<3>[3]
    T_174660[0] := UInt<3>(0)
    T_174660[1] := UInt<3>(1)
    T_174660[2] := UInt<3>(2)
    wire T_174661 : UInt<2>[2]
    T_174661[0] := UInt<2>(0)
    T_174661[1] := UInt<2>(1)
    wire T_174662 : UInt<2>[3]
    T_174662[0] := UInt<2>(1)
    T_174662[1] := UInt<2>(2)
    T_174662[2] := UInt<2>(3)
    wire T_174663 : UInt<2>[2]
    T_174663[0] := UInt<2>(2)
    T_174663[1] := UInt<2>(3)
    wire T_174664 : UInt<2>[1]
    T_174664[0] := UInt<2>(3)
    wire T_174665 : UInt<3>[3]
    T_174665[0] := UInt<3>(0)
    T_174665[1] := UInt<3>(1)
    T_174665[2] := UInt<3>(2)
    wire T_174666 : UInt<0>[1]
    T_174666[0] := UInt<0>(0)
    wire T_174667 : UInt<2>[2]
    T_174667[0] := UInt<2>(1)
    T_174667[1] := UInt<2>(2)
    wire T_174668 : UInt<2>[2]
    T_174668[0] := UInt<2>(1)
    T_174668[1] := UInt<2>(2)
    wire T_174669 : UInt<2>[1]
    T_174669[0] := UInt<2>(2)
    reg xact_old_meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}
    wire T_174670 : UInt<3>[3]
    T_174670[0] := UInt<3>(0)
    T_174670[1] := UInt<3>(1)
    T_174670[2] := UInt<3>(2)
    wire T_174671 : UInt<2>[2]
    T_174671[0] := UInt<2>(0)
    T_174671[1] := UInt<2>(1)
    wire T_174672 : UInt<2>[3]
    T_174672[0] := UInt<2>(1)
    T_174672[1] := UInt<2>(2)
    T_174672[2] := UInt<2>(3)
    wire T_174673 : UInt<2>[2]
    T_174673[0] := UInt<2>(2)
    T_174673[1] := UInt<2>(3)
    wire T_174674 : UInt<2>[1]
    T_174674[0] := UInt<2>(3)
    wire T_174675 : UInt<3>[3]
    T_174675[0] := UInt<3>(0)
    T_174675[1] := UInt<3>(1)
    T_174675[2] := UInt<3>(2)
    wire T_174676 : UInt<2>[2]
    T_174676[0] := UInt<2>(0)
    T_174676[1] := UInt<2>(1)
    wire T_174677 : UInt<2>[3]
    T_174677[0] := UInt<2>(1)
    T_174677[1] := UInt<2>(2)
    T_174677[2] := UInt<2>(3)
    wire T_174678 : UInt<2>[2]
    T_174678[0] := UInt<2>(2)
    T_174678[1] := UInt<2>(3)
    wire T_174679 : UInt<2>[1]
    T_174679[0] := UInt<2>(3)
    wire T_174680 : UInt<3>[3]
    T_174680[0] := UInt<3>(0)
    T_174680[1] := UInt<3>(1)
    T_174680[2] := UInt<3>(2)
    wire T_174681 : UInt<0>[1]
    T_174681[0] := UInt<0>(0)
    wire T_174682 : UInt<2>[2]
    T_174682[0] := UInt<2>(1)
    T_174682[1] := UInt<2>(2)
    wire T_174683 : UInt<2>[2]
    T_174683[0] := UInt<2>(1)
    T_174683[1] := UInt<2>(2)
    wire T_174684 : UInt<2>[1]
    T_174684[0] := UInt<2>(2)
    reg pending_coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    wire T_174685 : UInt<3>[3]
    T_174685[0] := UInt<3>(0)
    T_174685[1] := UInt<3>(1)
    T_174685[2] := UInt<3>(2)
    wire T_174686 : UInt<2>[2]
    T_174686[0] := UInt<2>(0)
    T_174686[1] := UInt<2>(1)
    wire T_174687 : UInt<2>[3]
    T_174687[0] := UInt<2>(1)
    T_174687[1] := UInt<2>(2)
    T_174687[2] := UInt<2>(3)
    wire T_174688 : UInt<2>[2]
    T_174688[0] := UInt<2>(2)
    T_174688[1] := UInt<2>(3)
    wire T_174689 : UInt<2>[1]
    T_174689[0] := UInt<2>(3)
    inst ignt_q of Queue_86917
    node T_174690 = and(inner.acquire.ready, inner.acquire.valid)
    node T_174691 = and(UInt<1>(1), inner.acquire.bits.is_builtin_type)
    wire T_174692 : UInt<3>[1]
    T_174692[0] := UInt<3>(3)
    node T_174693 = eq(T_174692[0], inner.acquire.bits.a_type)
    node T_174694 = or(UInt<1>(0), T_174693)
    node T_174695 = and(T_174691, T_174694)
    node T_174696 = and(T_174690, T_174695)
    reg T_174697 : UInt<2>
    onreset T_174697 := UInt<2>(0)
    when T_174696 : 
      node T_174698 = eq(T_174697, UInt<2>(3))
      node T_174699 = and(UInt<1>(0), T_174698)
      node T_174700 = addw(T_174697, UInt<1>(1))
      wire T_174701 : UInt<2>
      T_174701 := T_174700
      when T_174699 : T_174701 := UInt<1>(0)
      T_174697 := T_174701
    node T_174702 = and(T_174696, T_174698)
    wire T_174703 : UInt<1>
    T_174703 := UInt<1>(0)
    when T_174695 : T_174703 := T_174697
    wire iacq_data_done : UInt<1>
    iacq_data_done := T_174690
    when T_174695 : iacq_data_done := T_174702
    reg T_174704 : UInt<1>
    onreset T_174704 := UInt<1>(0)
    node T_174705 = and(inner.probe.ready, inner.probe.valid)
    node T_174706 = and(T_174705, UInt<1>(0))
    reg T_174707 : UInt<2>
    onreset T_174707 := UInt<2>(0)
    when T_174706 : 
      node T_174708 = eq(T_174707, UInt<2>(3))
      node T_174709 = and(UInt<1>(0), T_174708)
      node T_174710 = addw(T_174707, UInt<1>(1))
      wire T_174711 : UInt<2>
      T_174711 := T_174710
      when T_174709 : T_174711 := UInt<1>(0)
      T_174707 := T_174711
    node T_174712 = and(T_174706, T_174708)
    wire T_174713 : UInt<1>
    T_174713 := UInt<1>(0)
    when UInt<1>(0) : T_174713 := T_174707
    wire T_174714 : UInt<1>
    T_174714 := T_174705
    when UInt<1>(0) : T_174714 := T_174712
    node T_174715 = and(inner.release.ready, inner.release.valid)
    node T_174716 = eq(T_174457[0], inner.release.bits.r_type)
    node T_174717 = eq(T_174457[1], inner.release.bits.r_type)
    node T_174718 = eq(T_174457[2], inner.release.bits.r_type)
    node T_174719 = or(UInt<1>(0), T_174716)
    node T_174720 = or(T_174719, T_174717)
    node T_174721 = or(T_174720, T_174718)
    node T_174722 = and(UInt<1>(1), T_174721)
    node T_174723 = and(T_174715, T_174722)
    reg T_174724 : UInt<2>
    onreset T_174724 := UInt<2>(0)
    when T_174723 : 
      node T_174725 = eq(T_174724, UInt<2>(3))
      node T_174726 = and(UInt<1>(0), T_174725)
      node T_174727 = addw(T_174724, UInt<1>(1))
      wire T_174728 : UInt<2>
      T_174728 := T_174727
      when T_174726 : T_174728 := UInt<1>(0)
      T_174724 := T_174728
    node T_174729 = and(T_174723, T_174725)
    wire T_174730 : UInt<1>
    T_174730 := UInt<1>(0)
    when T_174722 : T_174730 := T_174724
    wire T_174731 : UInt<1>
    T_174731 := T_174715
    when T_174722 : T_174731 := T_174729
    node T_174732 = and(T_174714, UInt<1>(1))
    node T_174733 = subw(T_174704, UInt<1>(1))
    wire T_174734 : UInt<1>
    T_174734 := T_174733
    when T_174732 : T_174734 := T_174704
    node T_174735 = addw(T_174704, UInt<1>(1))
    wire T_174736 : UInt<1>
    T_174736 := T_174704
    when T_174732 : T_174736 := T_174735
    wire T_174737 : UInt<1>
    T_174737 := T_174736
    when T_174731 : T_174737 := T_174734
    T_174704 := T_174737
    node pending_irels = gt(T_174704, UInt<1>(0))
    reg T_174738 : UInt<1>
    onreset T_174738 := UInt<1>(0)
    node T_174739 = and(outer.acquire.ready, outer.acquire.valid)
    node T_174740 = and(UInt<1>(1), outer.acquire.bits.is_builtin_type)
    wire T_174741 : UInt<3>[1]
    T_174741[0] := UInt<3>(3)
    node T_174742 = eq(T_174741[0], outer.acquire.bits.a_type)
    node T_174743 = or(UInt<1>(0), T_174742)
    node T_174744 = and(T_174740, T_174743)
    node T_174745 = and(T_174739, T_174744)
    reg T_174746 : UInt<2>
    onreset T_174746 := UInt<2>(0)
    when T_174745 : 
      node T_174747 = eq(T_174746, UInt<2>(3))
      node T_174748 = and(UInt<1>(0), T_174747)
      node T_174749 = addw(T_174746, UInt<1>(1))
      wire T_174750 : UInt<2>
      T_174750 := T_174749
      when T_174748 : T_174750 := UInt<1>(0)
      T_174746 := T_174750
    node T_174751 = and(T_174745, T_174747)
    wire oacq_data_idx : UInt<2>
    oacq_data_idx := xact.addr_beat
    when T_174744 : oacq_data_idx := T_174746
    wire oacq_data_done : UInt<1>
    oacq_data_done := T_174739
    when T_174744 : oacq_data_done := T_174751
    node T_174752 = and(outer.grant.ready, outer.grant.valid)
    wire T_174753 : UInt<3>[1]
    T_174753[0] := UInt<3>(5)
    node T_174754 = eq(T_174753[0], outer.grant.bits.g_type)
    node T_174755 = or(UInt<1>(0), T_174754)
    node T_174756 = eq(T_174484[0], outer.grant.bits.g_type)
    node T_174757 = or(UInt<1>(0), T_174756)
    wire T_174758 : UInt<1>
    T_174758 := T_174757
    when outer.grant.bits.is_builtin_type : T_174758 := T_174755
    node T_174759 = and(UInt<1>(1), T_174758)
    node T_174760 = and(T_174752, T_174759)
    reg T_174761 : UInt<2>
    onreset T_174761 := UInt<2>(0)
    when T_174760 : 
      node T_174762 = eq(T_174761, UInt<2>(3))
      node T_174763 = and(UInt<1>(0), T_174762)
      node T_174764 = addw(T_174761, UInt<1>(1))
      wire T_174765 : UInt<2>
      T_174765 := T_174764
      when T_174763 : T_174765 := UInt<1>(0)
      T_174761 := T_174765
    node T_174766 = and(T_174760, T_174762)
    wire ognt_data_idx : UInt<2>
    ognt_data_idx := xact.addr_beat
    when T_174759 : ognt_data_idx := T_174761
    wire ognt_data_done : UInt<1>
    ognt_data_done := T_174752
    when T_174759 : ognt_data_done := T_174766
    node T_174767 = and(oacq_data_done, UInt<1>(1))
    node T_174768 = subw(T_174738, UInt<1>(1))
    wire T_174769 : UInt<1>
    T_174769 := T_174768
    when T_174767 : T_174769 := T_174738
    node T_174770 = addw(T_174738, UInt<1>(1))
    wire T_174771 : UInt<1>
    T_174771 := T_174738
    when T_174767 : T_174771 := T_174770
    wire T_174772 : UInt<1>
    T_174772 := T_174771
    when ognt_data_done : T_174772 := T_174769
    T_174738 := T_174772
    node pending_ognt = gt(T_174738, UInt<1>(0))
    node T_174773 = and(inner.grant.ready, inner.grant.valid)
    wire T_174774 : UInt<3>[1]
    T_174774[0] := UInt<3>(5)
    node T_174775 = eq(T_174774[0], inner.grant.bits.g_type)
    node T_174776 = or(UInt<1>(0), T_174775)
    node T_174777 = eq(T_174428[0], inner.grant.bits.g_type)
    node T_174778 = eq(T_174428[1], inner.grant.bits.g_type)
    node T_174779 = or(UInt<1>(0), T_174777)
    node T_174780 = or(T_174779, T_174778)
    wire T_174781 : UInt<1>
    T_174781 := T_174780
    when inner.grant.bits.is_builtin_type : T_174781 := T_174776
    node T_174782 = and(UInt<1>(1), T_174781)
    node T_174783 = and(T_174773, T_174782)
    reg T_174784 : UInt<2>
    onreset T_174784 := UInt<2>(0)
    when T_174783 : 
      node T_174785 = eq(T_174784, UInt<2>(3))
      node T_174786 = and(UInt<1>(0), T_174785)
      node T_174787 = addw(T_174784, UInt<1>(1))
      wire T_174788 : UInt<2>
      T_174788 := T_174787
      when T_174786 : T_174788 := UInt<1>(0)
      T_174784 := T_174788
    node T_174789 = and(T_174783, T_174785)
    wire ignt_data_idx : UInt<2>
    ignt_data_idx := ignt_q.deq.bits.addr_beat
    when T_174782 : ignt_data_idx := T_174784
    wire ignt_data_done : UInt<1>
    ignt_data_done := T_174773
    when T_174782 : ignt_data_done := T_174789
    reg T_174790 : UInt<3>
    onreset T_174790 := UInt<3>(0)
    node T_174791 = and(inner.grant.ready, inner.grant.valid)
    wire T_174792 : UInt<3>[1]
    T_174792[0] := UInt<3>(5)
    node T_174793 = eq(T_174792[0], inner.grant.bits.g_type)
    node T_174794 = or(UInt<1>(0), T_174793)
    node T_174795 = eq(T_174428[0], inner.grant.bits.g_type)
    node T_174796 = eq(T_174428[1], inner.grant.bits.g_type)
    node T_174797 = or(UInt<1>(0), T_174795)
    node T_174798 = or(T_174797, T_174796)
    wire T_174799 : UInt<1>
    T_174799 := T_174798
    when inner.grant.bits.is_builtin_type : T_174799 := T_174794
    node T_174800 = and(UInt<1>(1), T_174799)
    node T_174801 = and(T_174791, T_174800)
    reg T_174802 : UInt<2>
    onreset T_174802 := UInt<2>(0)
    when T_174801 : 
      node T_174803 = eq(T_174802, UInt<2>(3))
      node T_174804 = and(UInt<1>(0), T_174803)
      node T_174805 = addw(T_174802, UInt<1>(1))
      wire T_174806 : UInt<2>
      T_174806 := T_174805
      when T_174804 : T_174806 := UInt<1>(0)
      T_174802 := T_174806
    node T_174807 = and(T_174801, T_174803)
    wire T_174808 : UInt<1>
    T_174808 := UInt<1>(0)
    when T_174800 : T_174808 := T_174802
    wire T_174809 : UInt<1>
    T_174809 := T_174791
    when T_174800 : T_174809 := T_174807
    node T_174810 = and(inner.finish.ready, inner.finish.valid)
    node T_174811 = and(T_174810, UInt<1>(0))
    reg T_174812 : UInt<2>
    onreset T_174812 := UInt<2>(0)
    when T_174811 : 
      node T_174813 = eq(T_174812, UInt<2>(3))
      node T_174814 = and(UInt<1>(0), T_174813)
      node T_174815 = addw(T_174812, UInt<1>(1))
      wire T_174816 : UInt<2>
      T_174816 := T_174815
      when T_174814 : T_174816 := UInt<1>(0)
      T_174812 := T_174816
    node T_174817 = and(T_174811, T_174813)
    wire T_174818 : UInt<1>
    T_174818 := UInt<1>(0)
    when UInt<1>(0) : T_174818 := T_174812
    wire T_174819 : UInt<1>
    T_174819 := T_174810
    when UInt<1>(0) : T_174819 := T_174817
    node T_174820 = eq(UInt<1>(0), UInt<1>(0))
    node T_174821 = eq(inner.grant.bits.g_type, UInt<3>(0))
    node T_174822 = and(inner.grant.bits.is_builtin_type, T_174821)
    node T_174823 = eq(T_174822, UInt<1>(0))
    node T_174824 = and(T_174820, T_174823)
    node T_174825 = and(T_174809, T_174824)
    node T_174826 = subw(T_174790, UInt<1>(1))
    wire T_174827 : UInt<3>
    T_174827 := T_174826
    when T_174825 : T_174827 := T_174790
    node T_174828 = addw(T_174790, UInt<1>(1))
    wire T_174829 : UInt<3>
    T_174829 := T_174790
    when T_174825 : T_174829 := T_174828
    wire T_174830 : UInt<3>
    T_174830 := T_174829
    when T_174819 : T_174830 := T_174827
    T_174790 := T_174830
    node pending_ifins = gt(T_174790, UInt<1>(0))
    reg pending_puts : UInt<4>
    onreset pending_puts := UInt<4>(0)
    reg pending_iprbs : UInt<1>
    onreset pending_iprbs := UInt<1>(0)
    reg pending_reads : UInt<4>
    onreset pending_reads := UInt<4>(0)
    reg pending_writes : UInt<4>
    onreset pending_writes := UInt<4>(0)
    reg pending_resps : UInt<4>
    onreset pending_resps := UInt<4>(0)
    reg pending_ignt_data : UInt<4>
    onreset pending_ignt_data := UInt<4>(0)
    reg pending_meta_write : UInt<1>
    node T_174831 = eq(pending_reads, UInt<1>(0))
    node T_174832 = eq(T_174831, UInt<1>(0))
    node T_174833 = eq(pending_writes, UInt<1>(0))
    node T_174834 = eq(T_174833, UInt<1>(0))
    node T_174835 = or(T_174832, T_174834)
    node T_174836 = eq(pending_resps, UInt<1>(0))
    node T_174837 = eq(T_174836, UInt<1>(0))
    node T_174838 = or(T_174835, T_174837)
    node T_174839 = eq(pending_puts, UInt<1>(0))
    node T_174840 = eq(T_174839, UInt<1>(0))
    node T_174841 = or(T_174838, T_174840)
    node T_174842 = or(T_174841, pending_ognt)
    node T_174843 = gt(ignt_q.count, UInt<1>(0))
    node T_174844 = or(T_174842, T_174843)
    node T_174845 = or(T_174844, pending_ifins)
    node all_pending_done = eq(T_174845, UInt<1>(0))
    inst amoalu of AMOALU_87374
    node T_174846 = bits(xact.union, 12, 9)
    node T_174847 = cat(xact.addr_beat, T_174846)
    node T_174848 = cat(xact.addr_block, T_174847)
    amoalu.addr := T_174848
    node T_174849 = eq(xact.a_type, UInt<3>(2))
    node T_174850 = and(xact.is_builtin_type, T_174849)
    node T_174851 = eq(xact.a_type, UInt<3>(3))
    node T_174852 = and(xact.is_builtin_type, T_174851)
    node T_174853 = or(T_174850, T_174852)
    node T_174854 = bits(xact.union, 5, 1)
    wire T_174855 : UInt<5>
    T_174855 := T_174854
    when T_174853 : T_174855 := UInt<5>(1)
    amoalu.cmd := T_174855
    node T_174856 = bits(xact.union, 8, 6)
    amoalu.typ := T_174856
    amoalu.lhs := data.resp.bits.data
    amoalu.rhs := data_buffer[0]
    node T_174857 = eq(xact.a_type, UInt<3>(0))
    node T_174858 = and(xact.is_builtin_type, T_174857)
    node T_174859 = eq(inner.acquire.bits.a_type, UInt<3>(0))
    node T_174860 = and(inner.acquire.bits.is_builtin_type, T_174859)
    node T_174861 = and(T_174858, T_174860)
    node T_174862 = eq(xact.client_id, inner.acquire.bits.client_id)
    node T_174863 = and(T_174861, T_174862)
    node T_174864 = eq(xact.addr_block, inner.acquire.bits.addr_block)
    node T_174865 = and(T_174863, T_174864)
    node T_174866 = neq(state, UInt<4>(0))
    node T_174867 = and(T_174865, T_174866)
    node T_174868 = neq(state, UInt<4>(8))
    node T_174869 = and(T_174867, T_174868)
    node T_174870 = eq(all_pending_done, UInt<1>(0))
    node T_174871 = and(T_174869, T_174870)
    node T_174872 = bit(xact.union, 0)
    node T_174873 = and(T_174871, T_174872)
    node T_174874 = and(inner.release.ready, inner.release.valid)
    node T_174875 = eq(T_174874, UInt<1>(0))
    node T_174876 = and(T_174873, T_174875)
    node T_174877 = and(outer.grant.ready, outer.grant.valid)
    node T_174878 = eq(T_174877, UInt<1>(0))
    node T_174879 = and(T_174876, T_174878)
    node T_174880 = eq(data.resp.valid, UInt<1>(0))
    node T_174881 = and(T_174879, T_174880)
    node can_merge_iacq_get = and(T_174881, ignt_q.enq.ready)
    node T_174882 = eq(xact.a_type, UInt<3>(2))
    node T_174883 = and(xact.is_builtin_type, T_174882)
    node T_174884 = eq(inner.acquire.bits.a_type, UInt<3>(2))
    node T_174885 = and(inner.acquire.bits.is_builtin_type, T_174884)
    node T_174886 = and(T_174883, T_174885)
    node T_174887 = eq(xact.a_type, UInt<3>(3))
    node T_174888 = and(xact.is_builtin_type, T_174887)
    node T_174889 = eq(inner.acquire.bits.a_type, UInt<3>(3))
    node T_174890 = and(inner.acquire.bits.is_builtin_type, T_174889)
    node T_174891 = and(T_174888, T_174890)
    node T_174892 = or(T_174886, T_174891)
    node T_174893 = eq(xact.client_id, inner.acquire.bits.client_id)
    node T_174894 = and(T_174892, T_174893)
    node T_174895 = eq(xact.addr_block, inner.acquire.bits.addr_block)
    node T_174896 = and(T_174894, T_174895)
    node T_174897 = neq(state, UInt<4>(0))
    node T_174898 = and(T_174896, T_174897)
    node T_174899 = neq(state, UInt<4>(8))
    node T_174900 = and(T_174898, T_174899)
    node T_174901 = eq(all_pending_done, UInt<1>(0))
    node T_174902 = and(T_174900, T_174901)
    node T_174903 = bit(xact.union, 0)
    node T_174904 = eq(xact.a_type, UInt<3>(3))
    node T_174905 = and(xact.is_builtin_type, T_174904)
    node T_174906 = or(T_174903, T_174905)
    node T_174907 = and(T_174902, T_174906)
    node T_174908 = and(inner.release.ready, inner.release.valid)
    node T_174909 = eq(T_174908, UInt<1>(0))
    node T_174910 = and(T_174907, T_174909)
    node T_174911 = and(outer.grant.ready, outer.grant.valid)
    node T_174912 = eq(T_174911, UInt<1>(0))
    node T_174913 = and(T_174910, T_174912)
    node T_174914 = eq(data.resp.valid, UInt<1>(0))
    node T_174915 = and(T_174913, T_174914)
    node can_merge_iacq_put = and(T_174915, ignt_q.enq.ready)
    node T_174916 = eq(state, UInt<4>(0))
    node T_174917 = or(T_174916, can_merge_iacq_put)
    node T_174918 = or(T_174917, can_merge_iacq_get)
    inner.acquire.ready := T_174918
    ignt_q.enq.valid := iacq_data_done
    ignt_q.enq.bits.client_xact_id := inner.acquire.bits.client_xact_id
    ignt_q.enq.bits.addr_beat := inner.acquire.bits.addr_beat
    node T_174919 = and(inner.acquire.ready, inner.acquire.valid)
    wire T_174920 : UInt<3>[3]
    T_174920[0] := UInt<3>(2)
    T_174920[1] := UInt<3>(3)
    T_174920[2] := UInt<3>(4)
    node T_174921 = eq(T_174920[0], inner.acquire.bits.a_type)
    node T_174922 = eq(T_174920[1], inner.acquire.bits.a_type)
    node T_174923 = eq(T_174920[2], inner.acquire.bits.a_type)
    node T_174924 = or(UInt<1>(0), T_174921)
    node T_174925 = or(T_174924, T_174922)
    node T_174926 = or(T_174925, T_174923)
    node T_174927 = and(inner.acquire.bits.is_builtin_type, T_174926)
    node T_174928 = and(T_174919, T_174927)
    node T_174929 = subw(UInt<4>(0), UInt<3>(4))
    node T_174930 = not(T_174929)
    node T_174931 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_174932 = not(T_174931)
    node T_174933 = or(T_174930, T_174932)
    node T_174934 = and(pending_puts, T_174933)
    pending_puts := T_174934
    node T_174935 = eq(state, UInt<4>(1))
    meta.read.valid := T_174935
    meta.read.bits.id := UInt<2>(2)
    node T_174936 = bits(xact.addr_block, 11, 0)
    meta.read.bits.idx := T_174936
    node T_174937 = dshr(xact.addr_block, UInt<4>(12))
    meta.read.bits.tag := T_174937
    node T_174938 = eq(state, UInt<4>(3))
    wb.req.valid := T_174938
    wb.req.bits.id := UInt<2>(2)
    node T_174939 = bits(xact.addr_block, 11, 0)
    wb.req.bits.idx := T_174939
    wb.req.bits.tag := xact_old_meta.tag
    wb.req.bits.coh := xact_old_meta.coh
    wb.req.bits.way_en := xact_way_en
    node T_174940 = and(inner.probe.ready, inner.probe.valid)
    node T_174941 = not(T_174940)
    node T_174942 = dshl(UInt<1>(1), inner.probe.bits.client_id)
    node T_174943 = not(T_174942)
    node T_174944 = or(T_174941, T_174943)
    node T_174945 = and(pending_iprbs, T_174944)
    pending_iprbs := T_174945
    node T_174946 = bit(pending_iprbs, 0)
    wire T_174947 : UInt<1>[1]
    T_174947[0] := T_174946
    node T_174948 = eq(state, UInt<4>(5))
    node T_174949 = eq(pending_iprbs, UInt<1>(0))
    node T_174950 = eq(T_174949, UInt<1>(0))
    node T_174951 = and(T_174948, T_174950)
    inner.probe.valid := T_174951
    node T_174952 = eq(UInt<3>(4), xact.a_type)
    wire T_174953 : UInt<2>
    T_174953 := UInt<2>(2)
    when T_174952 : T_174953 := UInt<2>(0)
    node T_174954 = eq(UInt<3>(2), xact.a_type)
    wire T_174955 : UInt<2>
    T_174955 := T_174953
    when T_174954 : T_174955 := UInt<2>(0)
    node T_174956 = eq(UInt<3>(0), xact.a_type)
    wire T_174957 : UInt<2>
    T_174957 := T_174955
    when T_174956 : T_174957 := UInt<2>(2)
    node T_174958 = eq(UInt<3>(3), xact.a_type)
    wire T_174959 : UInt<2>
    T_174959 := T_174957
    when T_174958 : T_174959 := UInt<2>(0)
    node T_174960 = eq(UInt<3>(1), xact.a_type)
    wire T_174961 : UInt<2>
    T_174961 := T_174959
    when T_174960 : T_174961 := UInt<2>(2)
    node T_174962 = eq(UInt<1>(1), xact.a_type)
    wire T_174963 : UInt<2>
    T_174963 := UInt<2>(2)
    when T_174962 : T_174963 := UInt<2>(0)
    node T_174964 = eq(UInt<1>(0), xact.a_type)
    wire T_174965 : UInt<2>
    T_174965 := T_174963
    when T_174964 : T_174965 := UInt<2>(1)
    wire T_174966 : UInt<2>
    T_174966 := T_174965
    when xact.is_builtin_type : T_174966 := T_174961
    wire T_174967 : UInt<3>[3]
    T_174967[0] := UInt<3>(0)
    T_174967[1] := UInt<3>(1)
    T_174967[2] := UInt<3>(2)
    wire T_174968 : UInt<2>[2]
    T_174968[0] := UInt<2>(0)
    T_174968[1] := UInt<2>(1)
    wire T_174969 : UInt<2>[3]
    T_174969[0] := UInt<2>(1)
    T_174969[1] := UInt<2>(2)
    T_174969[2] := UInt<2>(3)
    wire T_174970 : UInt<2>[2]
    T_174970[0] := UInt<2>(2)
    T_174970[1] := UInt<2>(3)
    wire T_174971 : UInt<2>[1]
    T_174971[0] := UInt<2>(3)
    wire T_174972 : UInt<3>[3]
    T_174972[0] := UInt<3>(0)
    T_174972[1] := UInt<3>(1)
    T_174972[2] := UInt<3>(2)
    wire T_174973 : UInt<2>[2]
    T_174973[0] := UInt<2>(0)
    T_174973[1] := UInt<2>(1)
    wire T_174974 : UInt<2>[3]
    T_174974[0] := UInt<2>(1)
    T_174974[1] := UInt<2>(2)
    T_174974[2] := UInt<2>(3)
    wire T_174975 : UInt<2>[2]
    T_174975[0] := UInt<2>(2)
    T_174975[1] := UInt<2>(3)
    wire T_174976 : UInt<2>[1]
    T_174976[0] := UInt<2>(3)
    wire T_174977 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_174977.client_id := UInt<1>(0)
    T_174977.p_type := T_174966
    T_174977.addr_block := xact.addr_block
    inner.probe.bits := T_174977
    node T_174978 = eq(state, UInt<4>(5))
    inner.release.ready := T_174978
    node T_174979 = dshl(UInt<1>(1), inner.release.bits.client_id)
    node T_174980 = not(T_174979)
    node T_174981 = and(pending_coh.inner.sharers, T_174980)
    wire T_174982 : UInt<3>[3]
    T_174982[0] := UInt<3>(0)
    T_174982[1] := UInt<3>(1)
    T_174982[2] := UInt<3>(2)
    wire T_174983 : UInt<2>[2]
    T_174983[0] := UInt<2>(0)
    T_174983[1] := UInt<2>(1)
    wire T_174984 : UInt<2>[3]
    T_174984[0] := UInt<2>(1)
    T_174984[1] := UInt<2>(2)
    T_174984[2] := UInt<2>(3)
    wire T_174985 : UInt<2>[2]
    T_174985[0] := UInt<2>(2)
    T_174985[1] := UInt<2>(3)
    wire T_174986 : UInt<2>[1]
    T_174986[0] := UInt<2>(3)
    wire T_174987 : UInt<3>[3]
    T_174987[0] := UInt<3>(0)
    T_174987[1] := UInt<3>(1)
    T_174987[2] := UInt<3>(2)
    wire T_174988 : UInt<2>[2]
    T_174988[0] := UInt<2>(0)
    T_174988[1] := UInt<2>(1)
    wire T_174989 : UInt<2>[3]
    T_174989[0] := UInt<2>(1)
    T_174989[1] := UInt<2>(2)
    T_174989[2] := UInt<2>(3)
    wire T_174990 : UInt<2>[2]
    T_174990[0] := UInt<2>(2)
    T_174990[1] := UInt<2>(3)
    wire T_174991 : UInt<2>[1]
    T_174991[0] := UInt<2>(3)
    wire T_174992 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_174992.sharers := T_174981
    node T_174993 = eq(inner.release.bits.r_type, UInt<3>(0))
    node T_174994 = eq(inner.release.bits.r_type, UInt<3>(3))
    wire T_174995 : UInt<3>[3]
    T_174995[0] := UInt<3>(0)
    T_174995[1] := UInt<3>(1)
    T_174995[2] := UInt<3>(2)
    wire T_174996 : UInt<2>[2]
    T_174996[0] := UInt<2>(0)
    T_174996[1] := UInt<2>(1)
    wire T_174997 : UInt<2>[3]
    T_174997[0] := UInt<2>(1)
    T_174997[1] := UInt<2>(2)
    T_174997[2] := UInt<2>(3)
    wire T_174998 : UInt<2>[2]
    T_174998[0] := UInt<2>(2)
    T_174998[1] := UInt<2>(3)
    wire T_174999 : UInt<2>[1]
    T_174999[0] := UInt<2>(3)
    wire T_175000 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_175000 := pending_coh.inner
    when T_174994 : T_175000 := T_174992
    wire T_175001 : UInt<3>[3]
    T_175001[0] := UInt<3>(0)
    T_175001[1] := UInt<3>(1)
    T_175001[2] := UInt<3>(2)
    wire T_175002 : UInt<2>[2]
    T_175002[0] := UInt<2>(0)
    T_175002[1] := UInt<2>(1)
    wire T_175003 : UInt<2>[3]
    T_175003[0] := UInt<2>(1)
    T_175003[1] := UInt<2>(2)
    T_175003[2] := UInt<2>(3)
    wire T_175004 : UInt<2>[2]
    T_175004[0] := UInt<2>(2)
    T_175004[1] := UInt<2>(3)
    wire T_175005 : UInt<2>[1]
    T_175005[0] := UInt<2>(3)
    wire T_175006 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_175006 := T_175000
    when T_174993 : T_175006 := T_174992
    node T_175007 = eq(T_174457[0], inner.release.bits.r_type)
    node T_175008 = eq(T_174457[1], inner.release.bits.r_type)
    node T_175009 = eq(T_174457[2], inner.release.bits.r_type)
    node T_175010 = or(UInt<1>(0), T_175007)
    node T_175011 = or(T_175010, T_175008)
    node T_175012 = or(T_175011, T_175009)
    node T_175013 = eq(UInt<5>(1), UInt<5>(1))
    node T_175014 = eq(UInt<5>(1), UInt<5>(7))
    node T_175015 = or(T_175013, T_175014)
    node T_175016 = eq(UInt<5>(1), UInt<5>(4))
    node T_175017 = or(UInt<1>(0), T_175016)
    node T_175018 = or(T_175015, T_175017)
    wire T_175019 : UInt<2>
    T_175019 := pending_coh.outer.state
    when T_175018 : T_175019 := UInt<2>(2)
    wire T_175020 : UInt<3>[3]
    T_175020[0] := UInt<3>(0)
    T_175020[1] := UInt<3>(1)
    T_175020[2] := UInt<3>(2)
    wire T_175021 : UInt<0>[1]
    T_175021[0] := UInt<0>(0)
    wire T_175022 : UInt<2>[2]
    T_175022[0] := UInt<2>(1)
    T_175022[1] := UInt<2>(2)
    wire T_175023 : UInt<2>[2]
    T_175023[0] := UInt<2>(1)
    T_175023[1] := UInt<2>(2)
    wire T_175024 : UInt<2>[1]
    T_175024[0] := UInt<2>(2)
    wire T_175025 : UInt<3>[3]
    T_175025[0] := UInt<3>(0)
    T_175025[1] := UInt<3>(1)
    T_175025[2] := UInt<3>(2)
    wire T_175026 : UInt<0>[1]
    T_175026[0] := UInt<0>(0)
    wire T_175027 : UInt<2>[2]
    T_175027[0] := UInt<2>(1)
    T_175027[1] := UInt<2>(2)
    wire T_175028 : UInt<2>[2]
    T_175028[0] := UInt<2>(1)
    T_175028[1] := UInt<2>(2)
    wire T_175029 : UInt<2>[1]
    T_175029[0] := UInt<2>(2)
    wire T_175030 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_175030.state := T_175019
    wire T_175031 : UInt<3>[3]
    T_175031[0] := UInt<3>(0)
    T_175031[1] := UInt<3>(1)
    T_175031[2] := UInt<3>(2)
    wire T_175032 : UInt<2>[2]
    T_175032[0] := UInt<2>(0)
    T_175032[1] := UInt<2>(1)
    wire T_175033 : UInt<2>[3]
    T_175033[0] := UInt<2>(1)
    T_175033[1] := UInt<2>(2)
    T_175033[2] := UInt<2>(3)
    wire T_175034 : UInt<2>[2]
    T_175034[0] := UInt<2>(2)
    T_175034[1] := UInt<2>(3)
    wire T_175035 : UInt<2>[1]
    T_175035[0] := UInt<2>(3)
    wire T_175036 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_175036 := pending_coh.outer
    when T_175012 : T_175036 := T_175030
    wire T_175037 : UInt<3>[3]
    T_175037[0] := UInt<3>(0)
    T_175037[1] := UInt<3>(1)
    T_175037[2] := UInt<3>(2)
    wire T_175038 : UInt<2>[2]
    T_175038[0] := UInt<2>(0)
    T_175038[1] := UInt<2>(1)
    wire T_175039 : UInt<2>[3]
    T_175039[0] := UInt<2>(1)
    T_175039[1] := UInt<2>(2)
    T_175039[2] := UInt<2>(3)
    wire T_175040 : UInt<2>[2]
    T_175040[0] := UInt<2>(2)
    T_175040[1] := UInt<2>(3)
    wire T_175041 : UInt<2>[1]
    T_175041[0] := UInt<2>(3)
    wire T_175042 : UInt<3>[3]
    T_175042[0] := UInt<3>(0)
    T_175042[1] := UInt<3>(1)
    T_175042[2] := UInt<3>(2)
    wire T_175043 : UInt<2>[2]
    T_175043[0] := UInt<2>(0)
    T_175043[1] := UInt<2>(1)
    wire T_175044 : UInt<2>[3]
    T_175044[0] := UInt<2>(1)
    T_175044[1] := UInt<2>(2)
    T_175044[2] := UInt<2>(3)
    wire T_175045 : UInt<2>[2]
    T_175045[0] := UInt<2>(2)
    T_175045[1] := UInt<2>(3)
    wire T_175046 : UInt<2>[1]
    T_175046[0] := UInt<2>(3)
    wire T_175047 : UInt<3>[3]
    T_175047[0] := UInt<3>(0)
    T_175047[1] := UInt<3>(1)
    T_175047[2] := UInt<3>(2)
    wire T_175048 : UInt<0>[1]
    T_175048[0] := UInt<0>(0)
    wire T_175049 : UInt<2>[2]
    T_175049[0] := UInt<2>(1)
    T_175049[1] := UInt<2>(2)
    wire T_175050 : UInt<2>[2]
    T_175050[0] := UInt<2>(1)
    T_175050[1] := UInt<2>(2)
    wire T_175051 : UInt<2>[1]
    T_175051[0] := UInt<2>(2)
    wire T_175052 : UInt<3>[3]
    T_175052[0] := UInt<3>(0)
    T_175052[1] := UInt<3>(1)
    T_175052[2] := UInt<3>(2)
    wire T_175053 : UInt<2>[2]
    T_175053[0] := UInt<2>(0)
    T_175053[1] := UInt<2>(1)
    wire T_175054 : UInt<2>[3]
    T_175054[0] := UInt<2>(1)
    T_175054[1] := UInt<2>(2)
    T_175054[2] := UInt<2>(3)
    wire T_175055 : UInt<2>[2]
    T_175055[0] := UInt<2>(2)
    T_175055[1] := UInt<2>(3)
    wire T_175056 : UInt<2>[1]
    T_175056[0] := UInt<2>(3)
    wire T_175057 : UInt<3>[3]
    T_175057[0] := UInt<3>(0)
    T_175057[1] := UInt<3>(1)
    T_175057[2] := UInt<3>(2)
    wire T_175058 : UInt<2>[2]
    T_175058[0] := UInt<2>(0)
    T_175058[1] := UInt<2>(1)
    wire T_175059 : UInt<2>[3]
    T_175059[0] := UInt<2>(1)
    T_175059[1] := UInt<2>(2)
    T_175059[2] := UInt<2>(3)
    wire T_175060 : UInt<2>[2]
    T_175060[0] := UInt<2>(2)
    T_175060[1] := UInt<2>(3)
    wire T_175061 : UInt<2>[1]
    T_175061[0] := UInt<2>(3)
    wire T_175062 : UInt<3>[3]
    T_175062[0] := UInt<3>(0)
    T_175062[1] := UInt<3>(1)
    T_175062[2] := UInt<3>(2)
    wire T_175063 : UInt<0>[1]
    T_175063[0] := UInt<0>(0)
    wire T_175064 : UInt<2>[2]
    T_175064[0] := UInt<2>(1)
    T_175064[1] := UInt<2>(2)
    wire T_175065 : UInt<2>[2]
    T_175065[0] := UInt<2>(1)
    T_175065[1] := UInt<2>(2)
    wire T_175066 : UInt<2>[1]
    T_175066[0] := UInt<2>(2)
    wire pending_coh_on_irel : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_irel.inner := T_175006
    pending_coh_on_irel.outer := T_175036
    node T_175067 = and(inner.release.ready, inner.release.valid)
    
    
    node T_175068 = eq(pending_coh.inner.sharers, pending_coh_on_irel.inner.sharers)
    node T_175069 = eq(pending_coh.outer.state, pending_coh_on_irel.outer.state)
    node T_175070 = and(T_175068, T_175069)
    node T_175071 = eq(T_175070, UInt<1>(0))
    node T_175072 = and(T_175067, T_175071)
    when T_175072 : 
      pending_meta_write := UInt<1>(1)
      pending_coh := pending_coh_on_irel
    
    
    node T_175073 = and(inner.release.ready, inner.release.valid)
    node T_175074 = eq(T_174457[0], inner.release.bits.r_type)
    node T_175075 = eq(T_174457[1], inner.release.bits.r_type)
    node T_175076 = eq(T_174457[2], inner.release.bits.r_type)
    node T_175077 = or(UInt<1>(0), T_175074)
    node T_175078 = or(T_175077, T_175075)
    node T_175079 = or(T_175078, T_175076)
    node T_175080 = and(T_175073, T_175079)
    when T_175080 : 
      accessor T_175081 = data_buffer[inner.release.bits.addr_beat]
      node T_175082 = bits(xact.union, 12, 9)
      node T_175083 = bits(T_175082, 3, 3)
      node T_175084 = mul(UInt<7>(64), T_175083)
      node T_175085 = dshr(inner.release.bits.data, T_175084)
      amoalu.lhs := T_175085
      node T_175086 = bits(xact.union, 12, 9)
      node T_175087 = bits(T_175086, 3, 3)
      node T_175088 = mul(UInt<7>(64), T_175087)
      node T_175089 = dshr(T_175081, T_175088)
      amoalu.rhs := T_175089
      accessor T_175090 = wmask_buffer[inner.release.bits.addr_beat]
      node T_175091 = bit(T_175090, 0)
      node T_175092 = bit(T_175090, 1)
      node T_175093 = bit(T_175090, 2)
      node T_175094 = bit(T_175090, 3)
      node T_175095 = bit(T_175090, 4)
      node T_175096 = bit(T_175090, 5)
      node T_175097 = bit(T_175090, 6)
      node T_175098 = bit(T_175090, 7)
      node T_175099 = bit(T_175090, 8)
      node T_175100 = bit(T_175090, 9)
      node T_175101 = bit(T_175090, 10)
      node T_175102 = bit(T_175090, 11)
      node T_175103 = bit(T_175090, 12)
      node T_175104 = bit(T_175090, 13)
      node T_175105 = bit(T_175090, 14)
      node T_175106 = bit(T_175090, 15)
      wire T_175107 : UInt<1>[16]
      T_175107[0] := T_175091
      T_175107[1] := T_175092
      T_175107[2] := T_175093
      T_175107[3] := T_175094
      T_175107[4] := T_175095
      T_175107[5] := T_175096
      T_175107[6] := T_175097
      T_175107[7] := T_175098
      T_175107[8] := T_175099
      T_175107[9] := T_175100
      T_175107[10] := T_175101
      T_175107[11] := T_175102
      T_175107[12] := T_175103
      T_175107[13] := T_175104
      T_175107[14] := T_175105
      T_175107[15] := T_175106
      node T_175108 = subw(UInt<8>(0), UInt<4>(8))
      node T_175109 = subw(UInt<8>(0), UInt<4>(8))
      node T_175110 = subw(UInt<8>(0), UInt<4>(8))
      node T_175111 = subw(UInt<8>(0), UInt<4>(8))
      node T_175112 = subw(UInt<8>(0), UInt<4>(8))
      node T_175113 = subw(UInt<8>(0), UInt<4>(8))
      node T_175114 = subw(UInt<8>(0), UInt<4>(8))
      node T_175115 = subw(UInt<8>(0), UInt<4>(8))
      node T_175116 = subw(UInt<8>(0), UInt<4>(8))
      node T_175117 = subw(UInt<8>(0), UInt<4>(8))
      node T_175118 = subw(UInt<8>(0), UInt<4>(8))
      node T_175119 = subw(UInt<8>(0), UInt<4>(8))
      node T_175120 = subw(UInt<8>(0), UInt<4>(8))
      node T_175121 = subw(UInt<8>(0), UInt<4>(8))
      node T_175122 = subw(UInt<8>(0), UInt<4>(8))
      node T_175123 = subw(UInt<8>(0), UInt<4>(8))
      wire T_175124 : UInt<8>[16]
      T_175124[0] := T_175108
      T_175124[1] := T_175109
      T_175124[2] := T_175110
      T_175124[3] := T_175111
      T_175124[4] := T_175112
      T_175124[5] := T_175113
      T_175124[6] := T_175114
      T_175124[7] := T_175115
      T_175124[8] := T_175116
      T_175124[9] := T_175117
      T_175124[10] := T_175118
      T_175124[11] := T_175119
      T_175124[12] := T_175120
      T_175124[13] := T_175121
      T_175124[14] := T_175122
      T_175124[15] := T_175123
      node T_175125 = cat(T_175124[15], T_175124[14])
      node T_175126 = cat(T_175124[13], T_175124[12])
      node T_175127 = cat(T_175125, T_175126)
      node T_175128 = cat(T_175124[11], T_175124[10])
      node T_175129 = cat(T_175124[9], T_175124[8])
      node T_175130 = cat(T_175128, T_175129)
      node T_175131 = cat(T_175127, T_175130)
      node T_175132 = cat(T_175124[7], T_175124[6])
      node T_175133 = cat(T_175124[5], T_175124[4])
      node T_175134 = cat(T_175132, T_175133)
      node T_175135 = cat(T_175124[3], T_175124[2])
      node T_175136 = cat(T_175124[1], T_175124[0])
      node T_175137 = cat(T_175135, T_175136)
      node T_175138 = cat(T_175134, T_175137)
      node T_175139 = cat(T_175131, T_175138)
      accessor T_175140 = data_buffer[inner.release.bits.addr_beat]
      node T_175141 = not(T_175139)
      node T_175142 = and(T_175141, inner.release.bits.data)
      node T_175143 = eq(xact.a_type, UInt<3>(4))
      node T_175144 = and(xact.is_builtin_type, T_175143)
      node T_175145 = bits(xact.union, 12, 9)
      node T_175146 = bits(T_175145, 3, 3)
      node T_175147 = mul(UInt<7>(64), T_175146)
      node T_175148 = dshl(amoalu.out, T_175147)
      wire T_175149 : UInt<128>
      T_175149 := T_175081
      when T_175144 : T_175149 := T_175148
      node T_175150 = and(T_175139, T_175149)
      node T_175151 = or(T_175142, T_175150)
      T_175140 := T_175151
      accessor T_175152 = wmask_buffer[inner.release.bits.addr_beat]
      T_175152 := SInt<1>(-1)
      
      
      node T_175153 = eq(xact.a_type, UInt<3>(4))
      node T_175154 = eq(xact.addr_beat, inner.release.bits.addr_beat)
      node T_175155 = and(T_175153, T_175154)
      when T_175155 : xact.data := inner.release.bits.data
    node T_175156 = eq(state, UInt<4>(6))
    node T_175157 = bit(xact.union, 0)
    node T_175158 = dshr(pending_puts, oacq_data_idx)
    node T_175159 = bit(T_175158, 0)
    node T_175160 = eq(T_175159, UInt<1>(0))
    node T_175161 = or(T_175157, T_175160)
    node T_175162 = and(T_175156, T_175161)
    outer.acquire.valid := T_175162
    node T_175163 = bit(xact.union, 0)
    node T_175164 = eq(xact.a_type, UInt<3>(2))
    node T_175165 = and(xact.is_builtin_type, T_175164)
    node T_175166 = eq(xact.a_type, UInt<3>(3))
    node T_175167 = and(xact.is_builtin_type, T_175166)
    node T_175168 = or(T_175165, T_175167)
    node T_175169 = bits(xact.union, 5, 1)
    wire T_175170 : UInt<5>
    T_175170 := T_175169
    when T_175168 : T_175170 := UInt<5>(1)
    node T_175171 = eq(T_175170, UInt<5>(1))
    node T_175172 = eq(T_175170, UInt<5>(7))
    node T_175173 = or(T_175171, T_175172)
    node T_175174 = bit(T_175170, 3)
    node T_175175 = eq(T_175170, UInt<5>(4))
    node T_175176 = or(T_175174, T_175175)
    node T_175177 = or(T_175173, T_175176)
    node T_175178 = eq(T_175170, UInt<5>(3))
    node T_175179 = or(T_175177, T_175178)
    node T_175180 = eq(T_175170, UInt<5>(6))
    node T_175181 = or(T_175179, T_175180)
    wire T_175182 : UInt<1>
    T_175182 := UInt<1>(0)
    when T_175181 : T_175182 := UInt<1>(1)
    node T_175183 = cat(T_175170, UInt<1>(1))
    wire T_175184 : UInt<3>[3]
    T_175184[0] := UInt<3>(0)
    T_175184[1] := UInt<3>(1)
    T_175184[2] := UInt<3>(2)
    wire T_175185 : UInt<0>[1]
    T_175185[0] := UInt<0>(0)
    wire T_175186 : UInt<2>[2]
    T_175186[0] := UInt<2>(1)
    T_175186[1] := UInt<2>(2)
    wire T_175187 : UInt<2>[2]
    T_175187[0] := UInt<2>(1)
    T_175187[1] := UInt<2>(2)
    wire T_175188 : UInt<2>[1]
    T_175188[0] := UInt<2>(2)
    wire T_175189 : UInt<3>[3]
    T_175189[0] := UInt<3>(0)
    T_175189[1] := UInt<3>(1)
    T_175189[2] := UInt<3>(2)
    wire T_175190 : UInt<0>[1]
    T_175190[0] := UInt<0>(0)
    wire T_175191 : UInt<2>[2]
    T_175191[0] := UInt<2>(1)
    T_175191[1] := UInt<2>(2)
    wire T_175192 : UInt<2>[2]
    T_175192[0] := UInt<2>(1)
    T_175192[1] := UInt<2>(2)
    wire T_175193 : UInt<2>[1]
    T_175193[0] := UInt<2>(2)
    wire T_175194 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_175194.is_builtin_type := UInt<1>(0)
    T_175194.a_type := T_175182
    T_175194.client_xact_id := UInt<1>(0)
    T_175194.addr_block := xact.addr_block
    T_175194.addr_beat := UInt<1>(0)
    T_175194.data := UInt<1>(0)
    T_175194.union := T_175183
    wire T_175195 : UInt<3>[3]
    T_175195[0] := UInt<3>(0)
    T_175195[1] := UInt<3>(1)
    T_175195[2] := UInt<3>(2)
    wire T_175196 : UInt<0>[1]
    T_175196[0] := UInt<0>(0)
    wire T_175197 : UInt<2>[2]
    T_175197[0] := UInt<2>(1)
    T_175197[1] := UInt<2>(2)
    wire T_175198 : UInt<2>[2]
    T_175198[0] := UInt<2>(1)
    T_175198[1] := UInt<2>(2)
    wire T_175199 : UInt<2>[1]
    T_175199[0] := UInt<2>(2)
    wire T_175200 : UInt<3>[3]
    T_175200[0] := UInt<3>(0)
    T_175200[1] := UInt<3>(1)
    T_175200[2] := UInt<3>(2)
    wire T_175201 : UInt<0>[1]
    T_175201[0] := UInt<0>(0)
    wire T_175202 : UInt<2>[2]
    T_175202[0] := UInt<2>(1)
    T_175202[1] := UInt<2>(2)
    wire T_175203 : UInt<2>[2]
    T_175203[0] := UInt<2>(1)
    T_175203[1] := UInt<2>(2)
    wire T_175204 : UInt<2>[1]
    T_175204[0] := UInt<2>(2)
    wire T_175205 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_175205 := xact
    wire T_175206 : UInt<3>[3]
    T_175206[0] := UInt<3>(0)
    T_175206[1] := UInt<3>(1)
    T_175206[2] := UInt<3>(2)
    wire T_175207 : UInt<2>[2]
    T_175207[0] := UInt<2>(0)
    T_175207[1] := UInt<2>(1)
    wire T_175208 : UInt<2>[3]
    T_175208[0] := UInt<2>(1)
    T_175208[1] := UInt<2>(2)
    T_175208[2] := UInt<2>(3)
    wire T_175209 : UInt<2>[2]
    T_175209[0] := UInt<2>(2)
    T_175209[1] := UInt<2>(3)
    wire T_175210 : UInt<2>[1]
    T_175210[0] := UInt<2>(3)
    wire T_175211 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_175211 := T_175205
    when T_175163 : T_175211 := T_175194
    outer.acquire.bits := T_175211
    accessor T_175212 = data_buffer[oacq_data_idx]
    outer.acquire.bits.data := T_175212
    node T_175213 = eq(state, UInt<4>(7))
    outer.grant.ready := T_175213
    wire T_175214 : UInt<3>[3]
    T_175214[0] := UInt<3>(0)
    T_175214[1] := UInt<3>(1)
    T_175214[2] := UInt<3>(2)
    wire T_175215 : UInt<2>[2]
    T_175215[0] := UInt<2>(0)
    T_175215[1] := UInt<2>(1)
    wire T_175216 : UInt<2>[3]
    T_175216[0] := UInt<2>(1)
    T_175216[1] := UInt<2>(2)
    T_175216[2] := UInt<2>(3)
    wire T_175217 : UInt<2>[2]
    T_175217[0] := UInt<2>(2)
    T_175217[1] := UInt<2>(3)
    wire T_175218 : UInt<2>[1]
    T_175218[0] := UInt<2>(3)
    wire T_175219 : UInt<3>[3]
    T_175219[0] := UInt<3>(0)
    T_175219[1] := UInt<3>(1)
    T_175219[2] := UInt<3>(2)
    wire T_175220 : UInt<2>[2]
    T_175220[0] := UInt<2>(0)
    T_175220[1] := UInt<2>(1)
    wire T_175221 : UInt<2>[3]
    T_175221[0] := UInt<2>(1)
    T_175221[1] := UInt<2>(2)
    T_175221[2] := UInt<2>(3)
    wire T_175222 : UInt<2>[2]
    T_175222[0] := UInt<2>(2)
    T_175222[1] := UInt<2>(3)
    wire T_175223 : UInt<2>[1]
    T_175223[0] := UInt<2>(3)
    wire T_175224 : UInt<3>[3]
    T_175224[0] := UInt<3>(0)
    T_175224[1] := UInt<3>(1)
    T_175224[2] := UInt<3>(2)
    wire T_175225 : UInt<2>[2]
    T_175225[0] := UInt<2>(0)
    T_175225[1] := UInt<2>(1)
    wire T_175226 : UInt<2>[3]
    T_175226[0] := UInt<2>(1)
    T_175226[1] := UInt<2>(2)
    T_175226[2] := UInt<2>(3)
    wire T_175227 : UInt<2>[2]
    T_175227[0] := UInt<2>(2)
    T_175227[1] := UInt<2>(3)
    wire T_175228 : UInt<2>[1]
    T_175228[0] := UInt<2>(3)
    wire T_175229 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_175229.sharers := UInt<1>(0)
    node T_175230 = eq(xact.a_type, UInt<3>(2))
    node T_175231 = and(xact.is_builtin_type, T_175230)
    node T_175232 = eq(xact.a_type, UInt<3>(3))
    node T_175233 = and(xact.is_builtin_type, T_175232)
    node T_175234 = or(T_175231, T_175233)
    node T_175235 = bits(xact.union, 5, 1)
    wire T_175236 : UInt<5>
    T_175236 := T_175235
    when T_175234 : T_175236 := UInt<5>(1)
    node T_175237 = eq(T_175236, UInt<5>(1))
    node T_175238 = eq(T_175236, UInt<5>(7))
    node T_175239 = or(T_175237, T_175238)
    node T_175240 = bit(T_175236, 3)
    node T_175241 = eq(T_175236, UInt<5>(4))
    node T_175242 = or(T_175240, T_175241)
    node T_175243 = or(T_175239, T_175242)
    wire T_175244 : UInt<2>
    T_175244 := UInt<2>(1)
    when T_175243 : T_175244 := UInt<2>(2)
    wire T_175245 : UInt<2>
    T_175245 := T_175244
    when outer.grant.bits.is_builtin_type : T_175245 := UInt<2>(0)
    wire T_175246 : UInt<3>[3]
    T_175246[0] := UInt<3>(0)
    T_175246[1] := UInt<3>(1)
    T_175246[2] := UInt<3>(2)
    wire T_175247 : UInt<0>[1]
    T_175247[0] := UInt<0>(0)
    wire T_175248 : UInt<2>[2]
    T_175248[0] := UInt<2>(1)
    T_175248[1] := UInt<2>(2)
    wire T_175249 : UInt<2>[2]
    T_175249[0] := UInt<2>(1)
    T_175249[1] := UInt<2>(2)
    wire T_175250 : UInt<2>[1]
    T_175250[0] := UInt<2>(2)
    wire T_175251 : UInt<3>[3]
    T_175251[0] := UInt<3>(0)
    T_175251[1] := UInt<3>(1)
    T_175251[2] := UInt<3>(2)
    wire T_175252 : UInt<0>[1]
    T_175252[0] := UInt<0>(0)
    wire T_175253 : UInt<2>[2]
    T_175253[0] := UInt<2>(1)
    T_175253[1] := UInt<2>(2)
    wire T_175254 : UInt<2>[2]
    T_175254[0] := UInt<2>(1)
    T_175254[1] := UInt<2>(2)
    wire T_175255 : UInt<2>[1]
    T_175255[0] := UInt<2>(2)
    wire T_175256 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_175256.state := T_175245
    wire T_175257 : UInt<3>[3]
    T_175257[0] := UInt<3>(0)
    T_175257[1] := UInt<3>(1)
    T_175257[2] := UInt<3>(2)
    wire T_175258 : UInt<2>[2]
    T_175258[0] := UInt<2>(0)
    T_175258[1] := UInt<2>(1)
    wire T_175259 : UInt<2>[3]
    T_175259[0] := UInt<2>(1)
    T_175259[1] := UInt<2>(2)
    T_175259[2] := UInt<2>(3)
    wire T_175260 : UInt<2>[2]
    T_175260[0] := UInt<2>(2)
    T_175260[1] := UInt<2>(3)
    wire T_175261 : UInt<2>[1]
    T_175261[0] := UInt<2>(3)
    wire T_175262 : UInt<3>[3]
    T_175262[0] := UInt<3>(0)
    T_175262[1] := UInt<3>(1)
    T_175262[2] := UInt<3>(2)
    wire T_175263 : UInt<2>[2]
    T_175263[0] := UInt<2>(0)
    T_175263[1] := UInt<2>(1)
    wire T_175264 : UInt<2>[3]
    T_175264[0] := UInt<2>(1)
    T_175264[1] := UInt<2>(2)
    T_175264[2] := UInt<2>(3)
    wire T_175265 : UInt<2>[2]
    T_175265[0] := UInt<2>(2)
    T_175265[1] := UInt<2>(3)
    wire T_175266 : UInt<2>[1]
    T_175266[0] := UInt<2>(3)
    wire T_175267 : UInt<3>[3]
    T_175267[0] := UInt<3>(0)
    T_175267[1] := UInt<3>(1)
    T_175267[2] := UInt<3>(2)
    wire T_175268 : UInt<0>[1]
    T_175268[0] := UInt<0>(0)
    wire T_175269 : UInt<2>[2]
    T_175269[0] := UInt<2>(1)
    T_175269[1] := UInt<2>(2)
    wire T_175270 : UInt<2>[2]
    T_175270[0] := UInt<2>(1)
    T_175270[1] := UInt<2>(2)
    wire T_175271 : UInt<2>[1]
    T_175271[0] := UInt<2>(2)
    wire T_175272 : UInt<3>[3]
    T_175272[0] := UInt<3>(0)
    T_175272[1] := UInt<3>(1)
    T_175272[2] := UInt<3>(2)
    wire T_175273 : UInt<2>[2]
    T_175273[0] := UInt<2>(0)
    T_175273[1] := UInt<2>(1)
    wire T_175274 : UInt<2>[3]
    T_175274[0] := UInt<2>(1)
    T_175274[1] := UInt<2>(2)
    T_175274[2] := UInt<2>(3)
    wire T_175275 : UInt<2>[2]
    T_175275[0] := UInt<2>(2)
    T_175275[1] := UInt<2>(3)
    wire T_175276 : UInt<2>[1]
    T_175276[0] := UInt<2>(3)
    wire T_175277 : UInt<3>[3]
    T_175277[0] := UInt<3>(0)
    T_175277[1] := UInt<3>(1)
    T_175277[2] := UInt<3>(2)
    wire T_175278 : UInt<2>[2]
    T_175278[0] := UInt<2>(0)
    T_175278[1] := UInt<2>(1)
    wire T_175279 : UInt<2>[3]
    T_175279[0] := UInt<2>(1)
    T_175279[1] := UInt<2>(2)
    T_175279[2] := UInt<2>(3)
    wire T_175280 : UInt<2>[2]
    T_175280[0] := UInt<2>(2)
    T_175280[1] := UInt<2>(3)
    wire T_175281 : UInt<2>[1]
    T_175281[0] := UInt<2>(3)
    wire T_175282 : UInt<3>[3]
    T_175282[0] := UInt<3>(0)
    T_175282[1] := UInt<3>(1)
    T_175282[2] := UInt<3>(2)
    wire T_175283 : UInt<0>[1]
    T_175283[0] := UInt<0>(0)
    wire T_175284 : UInt<2>[2]
    T_175284[0] := UInt<2>(1)
    T_175284[1] := UInt<2>(2)
    wire T_175285 : UInt<2>[2]
    T_175285[0] := UInt<2>(1)
    T_175285[1] := UInt<2>(2)
    wire T_175286 : UInt<2>[1]
    T_175286[0] := UInt<2>(2)
    wire pending_coh_on_ognt : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_ognt.inner := T_175229
    pending_coh_on_ognt.outer := T_175256
    
    
    node T_175287 = eq(pending_coh.inner.sharers, pending_coh_on_ognt.inner.sharers)
    node T_175288 = eq(pending_coh.outer.state, pending_coh_on_ognt.outer.state)
    node T_175289 = and(T_175287, T_175288)
    node T_175290 = eq(T_175289, UInt<1>(0))
    node T_175291 = and(ognt_data_done, T_175290)
    when T_175291 : 
      pending_meta_write := UInt<1>(1)
      pending_coh := pending_coh_on_ognt
    
    
    node T_175292 = and(outer.grant.ready, outer.grant.valid)
    wire T_175293 : UInt<3>[2]
    T_175293[0] := UInt<3>(5)
    T_175293[1] := UInt<3>(4)
    node T_175294 = eq(T_175293[0], outer.grant.bits.g_type)
    node T_175295 = eq(T_175293[1], outer.grant.bits.g_type)
    node T_175296 = or(UInt<1>(0), T_175294)
    node T_175297 = or(T_175296, T_175295)
    node T_175298 = eq(T_174484[0], outer.grant.bits.g_type)
    node T_175299 = or(UInt<1>(0), T_175298)
    wire T_175300 : UInt<1>
    T_175300 := T_175299
    when outer.grant.bits.is_builtin_type : T_175300 := T_175297
    node T_175301 = and(T_175292, T_175300)
    when T_175301 : 
      accessor T_175302 = data_buffer[outer.grant.bits.addr_beat]
      node T_175303 = bits(xact.union, 12, 9)
      node T_175304 = bits(T_175303, 3, 3)
      node T_175305 = mul(UInt<7>(64), T_175304)
      node T_175306 = dshr(outer.grant.bits.data, T_175305)
      amoalu.lhs := T_175306
      node T_175307 = bits(xact.union, 12, 9)
      node T_175308 = bits(T_175307, 3, 3)
      node T_175309 = mul(UInt<7>(64), T_175308)
      node T_175310 = dshr(T_175302, T_175309)
      amoalu.rhs := T_175310
      accessor T_175311 = wmask_buffer[outer.grant.bits.addr_beat]
      node T_175312 = bit(T_175311, 0)
      node T_175313 = bit(T_175311, 1)
      node T_175314 = bit(T_175311, 2)
      node T_175315 = bit(T_175311, 3)
      node T_175316 = bit(T_175311, 4)
      node T_175317 = bit(T_175311, 5)
      node T_175318 = bit(T_175311, 6)
      node T_175319 = bit(T_175311, 7)
      node T_175320 = bit(T_175311, 8)
      node T_175321 = bit(T_175311, 9)
      node T_175322 = bit(T_175311, 10)
      node T_175323 = bit(T_175311, 11)
      node T_175324 = bit(T_175311, 12)
      node T_175325 = bit(T_175311, 13)
      node T_175326 = bit(T_175311, 14)
      node T_175327 = bit(T_175311, 15)
      wire T_175328 : UInt<1>[16]
      T_175328[0] := T_175312
      T_175328[1] := T_175313
      T_175328[2] := T_175314
      T_175328[3] := T_175315
      T_175328[4] := T_175316
      T_175328[5] := T_175317
      T_175328[6] := T_175318
      T_175328[7] := T_175319
      T_175328[8] := T_175320
      T_175328[9] := T_175321
      T_175328[10] := T_175322
      T_175328[11] := T_175323
      T_175328[12] := T_175324
      T_175328[13] := T_175325
      T_175328[14] := T_175326
      T_175328[15] := T_175327
      node T_175329 = subw(UInt<8>(0), UInt<4>(8))
      node T_175330 = subw(UInt<8>(0), UInt<4>(8))
      node T_175331 = subw(UInt<8>(0), UInt<4>(8))
      node T_175332 = subw(UInt<8>(0), UInt<4>(8))
      node T_175333 = subw(UInt<8>(0), UInt<4>(8))
      node T_175334 = subw(UInt<8>(0), UInt<4>(8))
      node T_175335 = subw(UInt<8>(0), UInt<4>(8))
      node T_175336 = subw(UInt<8>(0), UInt<4>(8))
      node T_175337 = subw(UInt<8>(0), UInt<4>(8))
      node T_175338 = subw(UInt<8>(0), UInt<4>(8))
      node T_175339 = subw(UInt<8>(0), UInt<4>(8))
      node T_175340 = subw(UInt<8>(0), UInt<4>(8))
      node T_175341 = subw(UInt<8>(0), UInt<4>(8))
      node T_175342 = subw(UInt<8>(0), UInt<4>(8))
      node T_175343 = subw(UInt<8>(0), UInt<4>(8))
      node T_175344 = subw(UInt<8>(0), UInt<4>(8))
      wire T_175345 : UInt<8>[16]
      T_175345[0] := T_175329
      T_175345[1] := T_175330
      T_175345[2] := T_175331
      T_175345[3] := T_175332
      T_175345[4] := T_175333
      T_175345[5] := T_175334
      T_175345[6] := T_175335
      T_175345[7] := T_175336
      T_175345[8] := T_175337
      T_175345[9] := T_175338
      T_175345[10] := T_175339
      T_175345[11] := T_175340
      T_175345[12] := T_175341
      T_175345[13] := T_175342
      T_175345[14] := T_175343
      T_175345[15] := T_175344
      node T_175346 = cat(T_175345[15], T_175345[14])
      node T_175347 = cat(T_175345[13], T_175345[12])
      node T_175348 = cat(T_175346, T_175347)
      node T_175349 = cat(T_175345[11], T_175345[10])
      node T_175350 = cat(T_175345[9], T_175345[8])
      node T_175351 = cat(T_175349, T_175350)
      node T_175352 = cat(T_175348, T_175351)
      node T_175353 = cat(T_175345[7], T_175345[6])
      node T_175354 = cat(T_175345[5], T_175345[4])
      node T_175355 = cat(T_175353, T_175354)
      node T_175356 = cat(T_175345[3], T_175345[2])
      node T_175357 = cat(T_175345[1], T_175345[0])
      node T_175358 = cat(T_175356, T_175357)
      node T_175359 = cat(T_175355, T_175358)
      node T_175360 = cat(T_175352, T_175359)
      accessor T_175361 = data_buffer[outer.grant.bits.addr_beat]
      node T_175362 = not(T_175360)
      node T_175363 = and(T_175362, outer.grant.bits.data)
      node T_175364 = eq(xact.a_type, UInt<3>(4))
      node T_175365 = and(xact.is_builtin_type, T_175364)
      node T_175366 = bits(xact.union, 12, 9)
      node T_175367 = bits(T_175366, 3, 3)
      node T_175368 = mul(UInt<7>(64), T_175367)
      node T_175369 = dshl(amoalu.out, T_175368)
      wire T_175370 : UInt<128>
      T_175370 := T_175302
      when T_175365 : T_175370 := T_175369
      node T_175371 = and(T_175360, T_175370)
      node T_175372 = or(T_175363, T_175371)
      T_175361 := T_175372
      accessor T_175373 = wmask_buffer[outer.grant.bits.addr_beat]
      T_175373 := SInt<1>(-1)
      
      
      node T_175374 = eq(xact.a_type, UInt<3>(4))
      node T_175375 = eq(xact.addr_beat, outer.grant.bits.addr_beat)
      node T_175376 = and(T_175374, T_175375)
      when T_175376 : xact.data := outer.grant.bits.data
    node T_175377 = and(inner.release.ready, inner.release.valid)
    node T_175378 = eq(T_174457[0], inner.release.bits.r_type)
    node T_175379 = eq(T_174457[1], inner.release.bits.r_type)
    node T_175380 = eq(T_174457[2], inner.release.bits.r_type)
    node T_175381 = or(UInt<1>(0), T_175378)
    node T_175382 = or(T_175381, T_175379)
    node T_175383 = or(T_175382, T_175380)
    node T_175384 = and(T_175377, T_175383)
    node T_175385 = subw(UInt<4>(0), UInt<3>(4))
    node T_175386 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_175387 = and(T_175385, T_175386)
    node T_175388 = or(pending_ignt_data, T_175387)
    node T_175389 = and(outer.grant.ready, outer.grant.valid)
    wire T_175390 : UInt<3>[2]
    T_175390[0] := UInt<3>(5)
    T_175390[1] := UInt<3>(4)
    node T_175391 = eq(T_175390[0], outer.grant.bits.g_type)
    node T_175392 = eq(T_175390[1], outer.grant.bits.g_type)
    node T_175393 = or(UInt<1>(0), T_175391)
    node T_175394 = or(T_175393, T_175392)
    node T_175395 = eq(T_174484[0], outer.grant.bits.g_type)
    node T_175396 = or(UInt<1>(0), T_175395)
    wire T_175397 : UInt<1>
    T_175397 := T_175396
    when outer.grant.bits.is_builtin_type : T_175397 := T_175394
    node T_175398 = and(T_175389, T_175397)
    node T_175399 = subw(UInt<4>(0), UInt<3>(4))
    node T_175400 = dshl(UInt<1>(1), outer.grant.bits.addr_beat)
    node T_175401 = and(T_175399, T_175400)
    node T_175402 = or(T_175388, T_175401)
    node T_175403 = subw(UInt<4>(0), UInt<3>(4))
    node T_175404 = dshl(UInt<1>(1), data.resp.bits.addr_beat)
    node T_175405 = and(T_175403, T_175404)
    node T_175406 = or(T_175402, T_175405)
    pending_ignt_data := T_175406
    ignt_q.deq.ready := ignt_data_done
    node T_175407 = eq(state, UInt<4>(7))
    node T_175408 = and(T_175407, ignt_q.deq.valid)
    wire T_175409 : UInt<3>[2]
    T_175409[0] := UInt<3>(5)
    T_175409[1] := UInt<3>(4)
    node T_175410 = eq(T_175409[0], inner.grant.bits.g_type)
    node T_175411 = eq(T_175409[1], inner.grant.bits.g_type)
    node T_175412 = or(UInt<1>(0), T_175410)
    node T_175413 = or(T_175412, T_175411)
    node T_175414 = eq(T_174428[0], inner.grant.bits.g_type)
    node T_175415 = eq(T_174428[1], inner.grant.bits.g_type)
    node T_175416 = or(UInt<1>(0), T_175414)
    node T_175417 = or(T_175416, T_175415)
    wire T_175418 : UInt<1>
    T_175418 := T_175417
    when inner.grant.bits.is_builtin_type : T_175418 := T_175413
    node T_175419 = eq(T_175418, UInt<1>(0))
    node T_175420 = dshr(pending_ignt_data, ignt_data_idx)
    node T_175421 = bit(T_175420, 0)
    node T_175422 = or(T_175419, T_175421)
    node T_175423 = and(T_175408, T_175422)
    inner.grant.valid := T_175423
    node T_175424 = eq(xact.a_type, UInt<3>(4))
    accessor T_175425 = data_buffer[ignt_data_idx]
    wire T_175426 : UInt<128>
    T_175426 := T_175425
    when T_175424 : T_175426 := xact.data
    node T_175427 = eq(UInt<3>(5), xact.a_type)
    wire T_175428 : UInt<3>
    T_175428 := UInt<3>(3)
    when T_175427 : T_175428 := UInt<3>(1)
    node T_175429 = eq(UInt<3>(4), xact.a_type)
    wire T_175430 : UInt<3>
    T_175430 := T_175428
    when T_175429 : T_175430 := UInt<3>(4)
    node T_175431 = eq(UInt<3>(3), xact.a_type)
    wire T_175432 : UInt<3>
    T_175432 := T_175430
    when T_175431 : T_175432 := UInt<3>(3)
    node T_175433 = eq(UInt<3>(2), xact.a_type)
    wire T_175434 : UInt<3>
    T_175434 := T_175432
    when T_175433 : T_175434 := UInt<3>(3)
    node T_175435 = eq(UInt<3>(1), xact.a_type)
    wire T_175436 : UInt<3>
    T_175436 := T_175434
    when T_175435 : T_175436 := UInt<3>(5)
    node T_175437 = eq(UInt<3>(0), xact.a_type)
    wire T_175438 : UInt<3>
    T_175438 := T_175436
    when T_175437 : T_175438 := UInt<3>(4)
    node T_175439 = eq(xact.a_type, UInt<1>(0))
    node T_175440 = eq(pending_coh.inner.sharers, UInt<1>(0))
    node T_175441 = eq(T_175440, UInt<1>(0))
    wire T_175442 : UInt<2>
    T_175442 := UInt<2>(1)
    when T_175441 : T_175442 := UInt<2>(0)
    wire T_175443 : UInt<2>
    T_175443 := UInt<2>(1)
    when T_175439 : T_175443 := T_175442
    wire T_175444 : UInt<2>
    T_175444 := T_175443
    when xact.is_builtin_type : T_175444 := T_175438
    wire T_175445 : UInt<3>[3]
    T_175445[0] := UInt<3>(0)
    T_175445[1] := UInt<3>(1)
    T_175445[2] := UInt<3>(2)
    wire T_175446 : UInt<2>[2]
    T_175446[0] := UInt<2>(0)
    T_175446[1] := UInt<2>(1)
    wire T_175447 : UInt<2>[3]
    T_175447[0] := UInt<2>(1)
    T_175447[1] := UInt<2>(2)
    T_175447[2] := UInt<2>(3)
    wire T_175448 : UInt<2>[2]
    T_175448[0] := UInt<2>(2)
    T_175448[1] := UInt<2>(3)
    wire T_175449 : UInt<2>[1]
    T_175449[0] := UInt<2>(3)
    wire T_175450 : UInt<3>[3]
    T_175450[0] := UInt<3>(0)
    T_175450[1] := UInt<3>(1)
    T_175450[2] := UInt<3>(2)
    wire T_175451 : UInt<2>[2]
    T_175451[0] := UInt<2>(0)
    T_175451[1] := UInt<2>(1)
    wire T_175452 : UInt<2>[3]
    T_175452[0] := UInt<2>(1)
    T_175452[1] := UInt<2>(2)
    T_175452[2] := UInt<2>(3)
    wire T_175453 : UInt<2>[2]
    T_175453[0] := UInt<2>(2)
    T_175453[1] := UInt<2>(3)
    wire T_175454 : UInt<2>[1]
    T_175454[0] := UInt<2>(3)
    wire T_175455 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}
    T_175455.client_id := xact.client_id
    T_175455.is_builtin_type := xact.is_builtin_type
    T_175455.g_type := T_175444
    T_175455.client_xact_id := xact.client_xact_id
    T_175455.manager_xact_id := UInt<2>(2)
    T_175455.addr_beat := ignt_q.deq.bits.addr_beat
    T_175455.data := T_175426
    T_175455.client_xact_id := ignt_q.deq.bits.client_xact_id
    inner.grant.bits := T_175455
    inner.grant.bits.addr_beat := ignt_data_idx
    node T_175456 = dshl(UInt<1>(1), inner.grant.bits.client_id)
    node T_175457 = or(pending_coh.inner.sharers, T_175456)
    wire T_175458 : UInt<5>
    T_175458 := T_175457
    when inner.grant.bits.is_builtin_type : T_175458 := pending_coh.inner.sharers
    wire T_175459 : UInt<3>[3]
    T_175459[0] := UInt<3>(0)
    T_175459[1] := UInt<3>(1)
    T_175459[2] := UInt<3>(2)
    wire T_175460 : UInt<2>[2]
    T_175460[0] := UInt<2>(0)
    T_175460[1] := UInt<2>(1)
    wire T_175461 : UInt<2>[3]
    T_175461[0] := UInt<2>(1)
    T_175461[1] := UInt<2>(2)
    T_175461[2] := UInt<2>(3)
    wire T_175462 : UInt<2>[2]
    T_175462[0] := UInt<2>(2)
    T_175462[1] := UInt<2>(3)
    wire T_175463 : UInt<2>[1]
    T_175463[0] := UInt<2>(3)
    wire T_175464 : UInt<3>[3]
    T_175464[0] := UInt<3>(0)
    T_175464[1] := UInt<3>(1)
    T_175464[2] := UInt<3>(2)
    wire T_175465 : UInt<2>[2]
    T_175465[0] := UInt<2>(0)
    T_175465[1] := UInt<2>(1)
    wire T_175466 : UInt<2>[3]
    T_175466[0] := UInt<2>(1)
    T_175466[1] := UInt<2>(2)
    T_175466[2] := UInt<2>(3)
    wire T_175467 : UInt<2>[2]
    T_175467[0] := UInt<2>(2)
    T_175467[1] := UInt<2>(3)
    wire T_175468 : UInt<2>[1]
    T_175468[0] := UInt<2>(3)
    wire T_175469 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_175469.sharers := T_175458
    wire T_175470 : UInt<3>[3]
    T_175470[0] := UInt<3>(0)
    T_175470[1] := UInt<3>(1)
    T_175470[2] := UInt<3>(2)
    wire T_175471 : UInt<2>[2]
    T_175471[0] := UInt<2>(0)
    T_175471[1] := UInt<2>(1)
    wire T_175472 : UInt<2>[3]
    T_175472[0] := UInt<2>(1)
    T_175472[1] := UInt<2>(2)
    T_175472[2] := UInt<2>(3)
    wire T_175473 : UInt<2>[2]
    T_175473[0] := UInt<2>(2)
    T_175473[1] := UInt<2>(3)
    wire T_175474 : UInt<2>[1]
    T_175474[0] := UInt<2>(3)
    wire T_175475 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_175475 := pending_coh.outer
    when ognt_data_done : T_175475 := pending_coh_on_ognt.outer
    wire T_175476 : UInt<3>[3]
    T_175476[0] := UInt<3>(0)
    T_175476[1] := UInt<3>(1)
    T_175476[2] := UInt<3>(2)
    wire T_175477 : UInt<2>[2]
    T_175477[0] := UInt<2>(0)
    T_175477[1] := UInt<2>(1)
    wire T_175478 : UInt<2>[3]
    T_175478[0] := UInt<2>(1)
    T_175478[1] := UInt<2>(2)
    T_175478[2] := UInt<2>(3)
    wire T_175479 : UInt<2>[2]
    T_175479[0] := UInt<2>(2)
    T_175479[1] := UInt<2>(3)
    wire T_175480 : UInt<2>[1]
    T_175480[0] := UInt<2>(3)
    wire T_175481 : UInt<3>[3]
    T_175481[0] := UInt<3>(0)
    T_175481[1] := UInt<3>(1)
    T_175481[2] := UInt<3>(2)
    wire T_175482 : UInt<2>[2]
    T_175482[0] := UInt<2>(0)
    T_175482[1] := UInt<2>(1)
    wire T_175483 : UInt<2>[3]
    T_175483[0] := UInt<2>(1)
    T_175483[1] := UInt<2>(2)
    T_175483[2] := UInt<2>(3)
    wire T_175484 : UInt<2>[2]
    T_175484[0] := UInt<2>(2)
    T_175484[1] := UInt<2>(3)
    wire T_175485 : UInt<2>[1]
    T_175485[0] := UInt<2>(3)
    wire T_175486 : UInt<3>[3]
    T_175486[0] := UInt<3>(0)
    T_175486[1] := UInt<3>(1)
    T_175486[2] := UInt<3>(2)
    wire T_175487 : UInt<0>[1]
    T_175487[0] := UInt<0>(0)
    wire T_175488 : UInt<2>[2]
    T_175488[0] := UInt<2>(1)
    T_175488[1] := UInt<2>(2)
    wire T_175489 : UInt<2>[2]
    T_175489[0] := UInt<2>(1)
    T_175489[1] := UInt<2>(2)
    wire T_175490 : UInt<2>[1]
    T_175490[0] := UInt<2>(2)
    wire T_175491 : UInt<3>[3]
    T_175491[0] := UInt<3>(0)
    T_175491[1] := UInt<3>(1)
    T_175491[2] := UInt<3>(2)
    wire T_175492 : UInt<2>[2]
    T_175492[0] := UInt<2>(0)
    T_175492[1] := UInt<2>(1)
    wire T_175493 : UInt<2>[3]
    T_175493[0] := UInt<2>(1)
    T_175493[1] := UInt<2>(2)
    T_175493[2] := UInt<2>(3)
    wire T_175494 : UInt<2>[2]
    T_175494[0] := UInt<2>(2)
    T_175494[1] := UInt<2>(3)
    wire T_175495 : UInt<2>[1]
    T_175495[0] := UInt<2>(3)
    wire T_175496 : UInt<3>[3]
    T_175496[0] := UInt<3>(0)
    T_175496[1] := UInt<3>(1)
    T_175496[2] := UInt<3>(2)
    wire T_175497 : UInt<2>[2]
    T_175497[0] := UInt<2>(0)
    T_175497[1] := UInt<2>(1)
    wire T_175498 : UInt<2>[3]
    T_175498[0] := UInt<2>(1)
    T_175498[1] := UInt<2>(2)
    T_175498[2] := UInt<2>(3)
    wire T_175499 : UInt<2>[2]
    T_175499[0] := UInt<2>(2)
    T_175499[1] := UInt<2>(3)
    wire T_175500 : UInt<2>[1]
    T_175500[0] := UInt<2>(3)
    wire T_175501 : UInt<3>[3]
    T_175501[0] := UInt<3>(0)
    T_175501[1] := UInt<3>(1)
    T_175501[2] := UInt<3>(2)
    wire T_175502 : UInt<0>[1]
    T_175502[0] := UInt<0>(0)
    wire T_175503 : UInt<2>[2]
    T_175503[0] := UInt<2>(1)
    T_175503[1] := UInt<2>(2)
    wire T_175504 : UInt<2>[2]
    T_175504[0] := UInt<2>(1)
    T_175504[1] := UInt<2>(2)
    wire T_175505 : UInt<2>[1]
    T_175505[0] := UInt<2>(2)
    wire pending_coh_on_ignt : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_ignt.inner := T_175469
    pending_coh_on_ignt.outer := T_175475
    node T_175506 = and(inner.grant.ready, inner.grant.valid)
    
    
    node T_175507 = eq(pending_coh.inner.sharers, pending_coh_on_ignt.inner.sharers)
    node T_175508 = eq(pending_coh.outer.state, pending_coh_on_ignt.outer.state)
    node T_175509 = and(T_175507, T_175508)
    node T_175510 = eq(T_175509, UInt<1>(0))
    node T_175511 = and(T_175506, T_175510)
    when T_175511 : 
      pending_meta_write := UInt<1>(1)
      pending_coh := pending_coh_on_ignt
    node T_175512 = eq(state, UInt<4>(7))
    inner.finish.ready := T_175512
    node T_175513 = and(data.read.ready, data.read.valid)
    node T_175514 = subw(UInt<4>(0), UInt<3>(4))
    node T_175515 = not(T_175514)
    node T_175516 = dshl(UInt<1>(1), data.read.bits.addr_beat)
    node T_175517 = not(T_175516)
    node T_175518 = or(T_175515, T_175517)
    node T_175519 = and(pending_reads, T_175518)
    node T_175520 = and(inner.release.ready, inner.release.valid)
    node T_175521 = eq(T_174457[0], inner.release.bits.r_type)
    node T_175522 = eq(T_174457[1], inner.release.bits.r_type)
    node T_175523 = eq(T_174457[2], inner.release.bits.r_type)
    node T_175524 = or(UInt<1>(0), T_175521)
    node T_175525 = or(T_175524, T_175522)
    node T_175526 = or(T_175525, T_175523)
    node T_175527 = and(T_175520, T_175526)
    node T_175528 = subw(UInt<4>(0), UInt<3>(4))
    node T_175529 = not(T_175528)
    node T_175530 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_175531 = not(T_175530)
    node T_175532 = or(T_175529, T_175531)
    node T_175533 = and(T_175519, T_175532)
    node T_175534 = and(outer.grant.ready, outer.grant.valid)
    wire T_175535 : UInt<3>[2]
    T_175535[0] := UInt<3>(5)
    T_175535[1] := UInt<3>(4)
    node T_175536 = eq(T_175535[0], outer.grant.bits.g_type)
    node T_175537 = eq(T_175535[1], outer.grant.bits.g_type)
    node T_175538 = or(UInt<1>(0), T_175536)
    node T_175539 = or(T_175538, T_175537)
    node T_175540 = eq(T_174484[0], outer.grant.bits.g_type)
    node T_175541 = or(UInt<1>(0), T_175540)
    wire T_175542 : UInt<1>
    T_175542 := T_175541
    when outer.grant.bits.is_builtin_type : T_175542 := T_175539
    node T_175543 = and(T_175534, T_175542)
    node T_175544 = subw(UInt<4>(0), UInt<3>(4))
    node T_175545 = not(T_175544)
    node T_175546 = dshl(UInt<1>(1), outer.grant.bits.addr_beat)
    node T_175547 = not(T_175546)
    node T_175548 = or(T_175545, T_175547)
    node T_175549 = and(T_175533, T_175548)
    wire T_175550 : UInt<3>[3]
    T_175550[0] := UInt<3>(0)
    T_175550[1] := UInt<3>(1)
    T_175550[2] := UInt<3>(4)
    node T_175551 = eq(T_175550[0], inner.acquire.bits.a_type)
    node T_175552 = eq(T_175550[1], inner.acquire.bits.a_type)
    node T_175553 = eq(T_175550[2], inner.acquire.bits.a_type)
    node T_175554 = or(UInt<1>(0), T_175551)
    node T_175555 = or(T_175554, T_175552)
    node T_175556 = or(T_175555, T_175553)
    node T_175557 = and(inner.acquire.bits.is_builtin_type, T_175556)
    node T_175558 = and(inner.acquire.ready, inner.acquire.valid)
    node T_175559 = and(T_175558, T_175557)
    node T_175560 = subw(UInt<4>(0), UInt<3>(4))
    node T_175561 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_175562 = and(T_175560, T_175561)
    node T_175563 = or(T_175549, T_175562)
    node T_175564 = eq(inner.acquire.bits.a_type, UInt<3>(4))
    node T_175565 = and(inner.acquire.bits.is_builtin_type, T_175564)
    node T_175566 = bits(inner.acquire.bits.union, 12, 9)
    node T_175567 = bits(T_175566, 3, 3)
    node T_175568 = dshl(UInt<1>(1), T_175567)
    node T_175569 = bit(T_175568, 0)
    node T_175570 = bit(T_175568, 1)
    node T_175571 = bit(T_175568, 2)
    wire T_175572 : UInt<1>[3]
    T_175572[0] := T_175569
    T_175572[1] := T_175570
    T_175572[2] := T_175571
    node T_175573 = subw(UInt<8>(0), UInt<4>(8))
    node T_175574 = subw(UInt<8>(0), UInt<4>(8))
    node T_175575 = subw(UInt<8>(0), UInt<4>(8))
    wire T_175576 : UInt<8>[3]
    T_175576[0] := T_175573
    T_175576[1] := T_175574
    T_175576[2] := T_175575
    node T_175577 = cat(T_175576[1], T_175576[0])
    node T_175578 = cat(T_175576[2], T_175577)
    node T_175579 = eq(inner.acquire.bits.a_type, UInt<3>(3))
    node T_175580 = and(inner.acquire.bits.is_builtin_type, T_175579)
    node T_175581 = eq(inner.acquire.bits.a_type, UInt<3>(2))
    node T_175582 = and(inner.acquire.bits.is_builtin_type, T_175581)
    node T_175583 = or(T_175580, T_175582)
    node T_175584 = bits(inner.acquire.bits.union, 16, 1)
    wire T_175585 : UInt<16>
    T_175585 := UInt<16>(0)
    when T_175583 : T_175585 := T_175584
    wire T_175586 : UInt<16>
    T_175586 := T_175585
    when T_175565 : T_175586 := T_175578
    wire T_175587 : UInt<3>[3]
    T_175587[0] := UInt<3>(0)
    T_175587[1] := UInt<3>(1)
    T_175587[2] := UInt<3>(2)
    wire T_175588 : UInt<2>[2]
    T_175588[0] := UInt<2>(0)
    T_175588[1] := UInt<2>(1)
    wire T_175589 : UInt<2>[3]
    T_175589[0] := UInt<2>(1)
    T_175589[1] := UInt<2>(2)
    T_175589[2] := UInt<2>(3)
    wire T_175590 : UInt<2>[2]
    T_175590[0] := UInt<2>(2)
    T_175590[1] := UInt<2>(3)
    wire T_175591 : UInt<2>[1]
    T_175591[0] := UInt<2>(3)
    node T_175592 = asUInt(SInt<16>(-1))
    node T_175593 = neq(T_175586, T_175592)
    node T_175594 = and(inner.acquire.ready, inner.acquire.valid)
    node T_175595 = and(T_175594, T_175593)
    node T_175596 = and(T_175595, UInt<1>(0))
    node T_175597 = subw(UInt<4>(0), UInt<3>(4))
    node T_175598 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_175599 = and(T_175597, T_175598)
    node T_175600 = or(T_175563, T_175599)
    pending_reads := T_175600
    node T_175601 = bit(pending_reads, 0)
    node T_175602 = bit(pending_reads, 1)
    node T_175603 = bit(pending_reads, 2)
    node T_175604 = bit(pending_reads, 3)
    wire T_175605 : UInt<1>[4]
    T_175605[0] := T_175601
    T_175605[1] := T_175602
    T_175605[2] := T_175603
    T_175605[3] := T_175604
    wire T_175606 : UInt<2>
    T_175606 := UInt<2>(3)
    when T_175605[2] : T_175606 := UInt<2>(2)
    wire T_175607 : UInt<2>
    T_175607 := T_175606
    when T_175605[1] : T_175607 := UInt<1>(1)
    wire curr_read_beat : UInt<2>
    curr_read_beat := T_175607
    when T_175605[0] : curr_read_beat := UInt<1>(0)
    node T_175608 = eq(state, UInt<4>(7))
    node T_175609 = eq(pending_reads, UInt<1>(0))
    node T_175610 = eq(T_175609, UInt<1>(0))
    node T_175611 = and(T_175608, T_175610)
    node T_175612 = eq(pending_ognt, UInt<1>(0))
    node T_175613 = and(T_175611, T_175612)
    data.read.valid := T_175613
    data.read.bits.id := UInt<2>(2)
    data.read.bits.way_en := xact_way_en
    node T_175614 = bits(xact.addr_block, 11, 0)
    data.read.bits.addr_idx := T_175614
    data.read.bits.addr_beat := curr_read_beat
    node T_175615 = subw(UInt<4>(0), UInt<3>(4))
    node T_175616 = not(T_175615)
    node T_175617 = dshl(UInt<1>(1), data.resp.bits.addr_beat)
    node T_175618 = not(T_175617)
    node T_175619 = or(T_175616, T_175618)
    node T_175620 = and(pending_resps, T_175619)
    node T_175621 = and(data.read.ready, data.read.valid)
    node T_175622 = subw(UInt<4>(0), UInt<3>(4))
    node T_175623 = dshl(UInt<1>(1), data.read.bits.addr_beat)
    node T_175624 = and(T_175622, T_175623)
    node T_175625 = or(T_175620, T_175624)
    pending_resps := T_175625
    when data.resp.valid : 
      accessor T_175626 = data_buffer[data.resp.bits.addr_beat]
      node T_175627 = bits(xact.union, 12, 9)
      node T_175628 = bits(T_175627, 3, 3)
      node T_175629 = mul(UInt<7>(64), T_175628)
      node T_175630 = dshr(data.resp.bits.data, T_175629)
      amoalu.lhs := T_175630
      node T_175631 = bits(xact.union, 12, 9)
      node T_175632 = bits(T_175631, 3, 3)
      node T_175633 = mul(UInt<7>(64), T_175632)
      node T_175634 = dshr(T_175626, T_175633)
      amoalu.rhs := T_175634
      accessor T_175635 = wmask_buffer[data.resp.bits.addr_beat]
      node T_175636 = bit(T_175635, 0)
      node T_175637 = bit(T_175635, 1)
      node T_175638 = bit(T_175635, 2)
      node T_175639 = bit(T_175635, 3)
      node T_175640 = bit(T_175635, 4)
      node T_175641 = bit(T_175635, 5)
      node T_175642 = bit(T_175635, 6)
      node T_175643 = bit(T_175635, 7)
      node T_175644 = bit(T_175635, 8)
      node T_175645 = bit(T_175635, 9)
      node T_175646 = bit(T_175635, 10)
      node T_175647 = bit(T_175635, 11)
      node T_175648 = bit(T_175635, 12)
      node T_175649 = bit(T_175635, 13)
      node T_175650 = bit(T_175635, 14)
      node T_175651 = bit(T_175635, 15)
      wire T_175652 : UInt<1>[16]
      T_175652[0] := T_175636
      T_175652[1] := T_175637
      T_175652[2] := T_175638
      T_175652[3] := T_175639
      T_175652[4] := T_175640
      T_175652[5] := T_175641
      T_175652[6] := T_175642
      T_175652[7] := T_175643
      T_175652[8] := T_175644
      T_175652[9] := T_175645
      T_175652[10] := T_175646
      T_175652[11] := T_175647
      T_175652[12] := T_175648
      T_175652[13] := T_175649
      T_175652[14] := T_175650
      T_175652[15] := T_175651
      node T_175653 = subw(UInt<8>(0), UInt<4>(8))
      node T_175654 = subw(UInt<8>(0), UInt<4>(8))
      node T_175655 = subw(UInt<8>(0), UInt<4>(8))
      node T_175656 = subw(UInt<8>(0), UInt<4>(8))
      node T_175657 = subw(UInt<8>(0), UInt<4>(8))
      node T_175658 = subw(UInt<8>(0), UInt<4>(8))
      node T_175659 = subw(UInt<8>(0), UInt<4>(8))
      node T_175660 = subw(UInt<8>(0), UInt<4>(8))
      node T_175661 = subw(UInt<8>(0), UInt<4>(8))
      node T_175662 = subw(UInt<8>(0), UInt<4>(8))
      node T_175663 = subw(UInt<8>(0), UInt<4>(8))
      node T_175664 = subw(UInt<8>(0), UInt<4>(8))
      node T_175665 = subw(UInt<8>(0), UInt<4>(8))
      node T_175666 = subw(UInt<8>(0), UInt<4>(8))
      node T_175667 = subw(UInt<8>(0), UInt<4>(8))
      node T_175668 = subw(UInt<8>(0), UInt<4>(8))
      wire T_175669 : UInt<8>[16]
      T_175669[0] := T_175653
      T_175669[1] := T_175654
      T_175669[2] := T_175655
      T_175669[3] := T_175656
      T_175669[4] := T_175657
      T_175669[5] := T_175658
      T_175669[6] := T_175659
      T_175669[7] := T_175660
      T_175669[8] := T_175661
      T_175669[9] := T_175662
      T_175669[10] := T_175663
      T_175669[11] := T_175664
      T_175669[12] := T_175665
      T_175669[13] := T_175666
      T_175669[14] := T_175667
      T_175669[15] := T_175668
      node T_175670 = cat(T_175669[15], T_175669[14])
      node T_175671 = cat(T_175669[13], T_175669[12])
      node T_175672 = cat(T_175670, T_175671)
      node T_175673 = cat(T_175669[11], T_175669[10])
      node T_175674 = cat(T_175669[9], T_175669[8])
      node T_175675 = cat(T_175673, T_175674)
      node T_175676 = cat(T_175672, T_175675)
      node T_175677 = cat(T_175669[7], T_175669[6])
      node T_175678 = cat(T_175669[5], T_175669[4])
      node T_175679 = cat(T_175677, T_175678)
      node T_175680 = cat(T_175669[3], T_175669[2])
      node T_175681 = cat(T_175669[1], T_175669[0])
      node T_175682 = cat(T_175680, T_175681)
      node T_175683 = cat(T_175679, T_175682)
      node T_175684 = cat(T_175676, T_175683)
      accessor T_175685 = data_buffer[data.resp.bits.addr_beat]
      node T_175686 = not(T_175684)
      node T_175687 = and(T_175686, data.resp.bits.data)
      node T_175688 = eq(xact.a_type, UInt<3>(4))
      node T_175689 = and(xact.is_builtin_type, T_175688)
      node T_175690 = bits(xact.union, 12, 9)
      node T_175691 = bits(T_175690, 3, 3)
      node T_175692 = mul(UInt<7>(64), T_175691)
      node T_175693 = dshl(amoalu.out, T_175692)
      wire T_175694 : UInt<128>
      T_175694 := T_175626
      when T_175689 : T_175694 := T_175693
      node T_175695 = and(T_175684, T_175694)
      node T_175696 = or(T_175687, T_175695)
      T_175685 := T_175696
      accessor T_175697 = wmask_buffer[data.resp.bits.addr_beat]
      T_175697 := SInt<1>(-1)
      
      
      node T_175698 = eq(xact.a_type, UInt<3>(4))
      node T_175699 = eq(xact.addr_beat, data.resp.bits.addr_beat)
      node T_175700 = and(T_175698, T_175699)
      when T_175700 : xact.data := data.resp.bits.data
    node T_175701 = and(data.write.ready, data.write.valid)
    node T_175702 = subw(UInt<4>(0), UInt<3>(4))
    node T_175703 = not(T_175702)
    node T_175704 = dshl(UInt<1>(1), data.write.bits.addr_beat)
    node T_175705 = not(T_175704)
    node T_175706 = or(T_175703, T_175705)
    node T_175707 = and(pending_writes, T_175706)
    node T_175708 = and(inner.acquire.ready, inner.acquire.valid)
    wire T_175709 : UInt<3>[3]
    T_175709[0] := UInt<3>(2)
    T_175709[1] := UInt<3>(3)
    T_175709[2] := UInt<3>(4)
    node T_175710 = eq(T_175709[0], inner.acquire.bits.a_type)
    node T_175711 = eq(T_175709[1], inner.acquire.bits.a_type)
    node T_175712 = eq(T_175709[2], inner.acquire.bits.a_type)
    node T_175713 = or(UInt<1>(0), T_175710)
    node T_175714 = or(T_175713, T_175711)
    node T_175715 = or(T_175714, T_175712)
    node T_175716 = and(inner.acquire.bits.is_builtin_type, T_175715)
    node T_175717 = and(T_175708, T_175716)
    node T_175718 = bit(inner.acquire.bits.union, 0)
    node T_175719 = and(T_175717, T_175718)
    node T_175720 = subw(UInt<4>(0), UInt<3>(4))
    node T_175721 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
    node T_175722 = and(T_175720, T_175721)
    node T_175723 = or(T_175707, T_175722)
    node T_175724 = and(inner.release.ready, inner.release.valid)
    node T_175725 = eq(T_174457[0], inner.release.bits.r_type)
    node T_175726 = eq(T_174457[1], inner.release.bits.r_type)
    node T_175727 = eq(T_174457[2], inner.release.bits.r_type)
    node T_175728 = or(UInt<1>(0), T_175725)
    node T_175729 = or(T_175728, T_175726)
    node T_175730 = or(T_175729, T_175727)
    node T_175731 = and(T_175724, T_175730)
    node T_175732 = subw(UInt<4>(0), UInt<3>(4))
    node T_175733 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_175734 = and(T_175732, T_175733)
    node T_175735 = or(T_175723, T_175734)
    node T_175736 = and(outer.grant.ready, outer.grant.valid)
    wire T_175737 : UInt<3>[2]
    T_175737[0] := UInt<3>(5)
    T_175737[1] := UInt<3>(4)
    node T_175738 = eq(T_175737[0], outer.grant.bits.g_type)
    node T_175739 = eq(T_175737[1], outer.grant.bits.g_type)
    node T_175740 = or(UInt<1>(0), T_175738)
    node T_175741 = or(T_175740, T_175739)
    node T_175742 = eq(T_174484[0], outer.grant.bits.g_type)
    node T_175743 = or(UInt<1>(0), T_175742)
    wire T_175744 : UInt<1>
    T_175744 := T_175743
    when outer.grant.bits.is_builtin_type : T_175744 := T_175741
    node T_175745 = and(T_175736, T_175744)
    node T_175746 = subw(UInt<4>(0), UInt<3>(4))
    node T_175747 = dshl(UInt<1>(1), outer.grant.bits.addr_beat)
    node T_175748 = and(T_175746, T_175747)
    node T_175749 = or(T_175735, T_175748)
    pending_writes := T_175749
    node T_175750 = bit(pending_writes, 0)
    node T_175751 = bit(pending_writes, 1)
    node T_175752 = bit(pending_writes, 2)
    node T_175753 = bit(pending_writes, 3)
    wire T_175754 : UInt<1>[4]
    T_175754[0] := T_175750
    T_175754[1] := T_175751
    T_175754[2] := T_175752
    T_175754[3] := T_175753
    wire T_175755 : UInt<2>
    T_175755 := UInt<2>(3)
    when T_175754[2] : T_175755 := UInt<2>(2)
    wire T_175756 : UInt<2>
    T_175756 := T_175755
    when T_175754[1] : T_175756 := UInt<1>(1)
    wire curr_write_beat : UInt<2>
    curr_write_beat := T_175756
    when T_175754[0] : curr_write_beat := UInt<1>(0)
    node T_175757 = eq(state, UInt<4>(7))
    node T_175758 = eq(pending_writes, UInt<1>(0))
    node T_175759 = eq(T_175758, UInt<1>(0))
    node T_175760 = and(T_175757, T_175759)
    node T_175761 = eq(pending_ognt, UInt<1>(0))
    node T_175762 = and(T_175760, T_175761)
    node T_175763 = dshr(pending_reads, curr_write_beat)
    node T_175764 = bit(T_175763, 0)
    node T_175765 = eq(T_175764, UInt<1>(0))
    node T_175766 = and(T_175762, T_175765)
    node T_175767 = dshr(pending_resps, curr_write_beat)
    node T_175768 = bit(T_175767, 0)
    node T_175769 = eq(T_175768, UInt<1>(0))
    node T_175770 = and(T_175766, T_175769)
    data.write.valid := T_175770
    data.write.bits.id := UInt<2>(2)
    data.write.bits.way_en := xact_way_en
    node T_175771 = bits(xact.addr_block, 11, 0)
    data.write.bits.addr_idx := T_175771
    data.write.bits.addr_beat := curr_write_beat
    accessor T_175772 = wmask_buffer[curr_write_beat]
    data.write.bits.wmask := T_175772
    accessor T_175773 = data_buffer[curr_write_beat]
    data.write.bits.data := T_175773
    node T_175774 = eq(state, UInt<4>(8))
    meta.write.valid := T_175774
    meta.write.bits.id := UInt<2>(2)
    node T_175775 = bits(xact.addr_block, 11, 0)
    meta.write.bits.idx := T_175775
    meta.write.bits.way_en := xact_way_en
    node T_175776 = dshr(xact.addr_block, UInt<4>(12))
    meta.write.bits.data.tag := T_175776
    meta.write.bits.data.coh := pending_coh
    
    
    node T_175777 = and(inner.acquire.ready, inner.acquire.valid)
    wire T_175778 : UInt<3>[3]
    T_175778[0] := UInt<3>(2)
    T_175778[1] := UInt<3>(3)
    T_175778[2] := UInt<3>(4)
    node T_175779 = eq(T_175778[0], inner.acquire.bits.a_type)
    node T_175780 = eq(T_175778[1], inner.acquire.bits.a_type)
    node T_175781 = eq(T_175778[2], inner.acquire.bits.a_type)
    node T_175782 = or(UInt<1>(0), T_175779)
    node T_175783 = or(T_175782, T_175780)
    node T_175784 = or(T_175783, T_175781)
    node T_175785 = and(inner.acquire.bits.is_builtin_type, T_175784)
    node T_175786 = and(T_175777, T_175785)
    when T_175786 : 
      node T_175787 = eq(inner.acquire.bits.a_type, UInt<3>(4))
      node T_175788 = and(inner.acquire.bits.is_builtin_type, T_175787)
      node T_175789 = bits(inner.acquire.bits.union, 12, 9)
      node T_175790 = bits(T_175789, 3, 3)
      node T_175791 = dshl(UInt<1>(1), T_175790)
      node T_175792 = bit(T_175791, 0)
      node T_175793 = bit(T_175791, 1)
      node T_175794 = bit(T_175791, 2)
      wire T_175795 : UInt<1>[3]
      T_175795[0] := T_175792
      T_175795[1] := T_175793
      T_175795[2] := T_175794
      node T_175796 = subw(UInt<8>(0), UInt<4>(8))
      node T_175797 = subw(UInt<8>(0), UInt<4>(8))
      node T_175798 = subw(UInt<8>(0), UInt<4>(8))
      wire T_175799 : UInt<8>[3]
      T_175799[0] := T_175796
      T_175799[1] := T_175797
      T_175799[2] := T_175798
      node T_175800 = cat(T_175799[1], T_175799[0])
      node T_175801 = cat(T_175799[2], T_175800)
      node T_175802 = eq(inner.acquire.bits.a_type, UInt<3>(3))
      node T_175803 = and(inner.acquire.bits.is_builtin_type, T_175802)
      node T_175804 = eq(inner.acquire.bits.a_type, UInt<3>(2))
      node T_175805 = and(inner.acquire.bits.is_builtin_type, T_175804)
      node T_175806 = or(T_175803, T_175805)
      node T_175807 = bits(inner.acquire.bits.union, 16, 1)
      wire T_175808 : UInt<16>
      T_175808 := UInt<16>(0)
      when T_175806 : T_175808 := T_175807
      wire T_175809 : UInt<16>
      T_175809 := T_175808
      when T_175788 : T_175809 := T_175801
      node T_175810 = bit(T_175809, 0)
      node T_175811 = bit(T_175809, 1)
      node T_175812 = bit(T_175809, 2)
      node T_175813 = bit(T_175809, 3)
      node T_175814 = bit(T_175809, 4)
      node T_175815 = bit(T_175809, 5)
      node T_175816 = bit(T_175809, 6)
      node T_175817 = bit(T_175809, 7)
      node T_175818 = bit(T_175809, 8)
      node T_175819 = bit(T_175809, 9)
      node T_175820 = bit(T_175809, 10)
      node T_175821 = bit(T_175809, 11)
      node T_175822 = bit(T_175809, 12)
      node T_175823 = bit(T_175809, 13)
      node T_175824 = bit(T_175809, 14)
      node T_175825 = bit(T_175809, 15)
      wire T_175826 : UInt<1>[16]
      T_175826[0] := T_175810
      T_175826[1] := T_175811
      T_175826[2] := T_175812
      T_175826[3] := T_175813
      T_175826[4] := T_175814
      T_175826[5] := T_175815
      T_175826[6] := T_175816
      T_175826[7] := T_175817
      T_175826[8] := T_175818
      T_175826[9] := T_175819
      T_175826[10] := T_175820
      T_175826[11] := T_175821
      T_175826[12] := T_175822
      T_175826[13] := T_175823
      T_175826[14] := T_175824
      T_175826[15] := T_175825
      node T_175827 = subw(UInt<8>(0), UInt<4>(8))
      node T_175828 = subw(UInt<8>(0), UInt<4>(8))
      node T_175829 = subw(UInt<8>(0), UInt<4>(8))
      node T_175830 = subw(UInt<8>(0), UInt<4>(8))
      node T_175831 = subw(UInt<8>(0), UInt<4>(8))
      node T_175832 = subw(UInt<8>(0), UInt<4>(8))
      node T_175833 = subw(UInt<8>(0), UInt<4>(8))
      node T_175834 = subw(UInt<8>(0), UInt<4>(8))
      node T_175835 = subw(UInt<8>(0), UInt<4>(8))
      node T_175836 = subw(UInt<8>(0), UInt<4>(8))
      node T_175837 = subw(UInt<8>(0), UInt<4>(8))
      node T_175838 = subw(UInt<8>(0), UInt<4>(8))
      node T_175839 = subw(UInt<8>(0), UInt<4>(8))
      node T_175840 = subw(UInt<8>(0), UInt<4>(8))
      node T_175841 = subw(UInt<8>(0), UInt<4>(8))
      node T_175842 = subw(UInt<8>(0), UInt<4>(8))
      wire T_175843 : UInt<8>[16]
      T_175843[0] := T_175827
      T_175843[1] := T_175828
      T_175843[2] := T_175829
      T_175843[3] := T_175830
      T_175843[4] := T_175831
      T_175843[5] := T_175832
      T_175843[6] := T_175833
      T_175843[7] := T_175834
      T_175843[8] := T_175835
      T_175843[9] := T_175836
      T_175843[10] := T_175837
      T_175843[11] := T_175838
      T_175843[12] := T_175839
      T_175843[13] := T_175840
      T_175843[14] := T_175841
      T_175843[15] := T_175842
      node T_175844 = cat(T_175843[15], T_175843[14])
      node T_175845 = cat(T_175843[13], T_175843[12])
      node T_175846 = cat(T_175844, T_175845)
      node T_175847 = cat(T_175843[11], T_175843[10])
      node T_175848 = cat(T_175843[9], T_175843[8])
      node T_175849 = cat(T_175847, T_175848)
      node T_175850 = cat(T_175846, T_175849)
      node T_175851 = cat(T_175843[7], T_175843[6])
      node T_175852 = cat(T_175843[5], T_175843[4])
      node T_175853 = cat(T_175851, T_175852)
      node T_175854 = cat(T_175843[3], T_175843[2])
      node T_175855 = cat(T_175843[1], T_175843[0])
      node T_175856 = cat(T_175854, T_175855)
      node T_175857 = cat(T_175853, T_175856)
      node T_175858 = cat(T_175850, T_175857)
      accessor T_175859 = data_buffer[inner.acquire.bits.addr_beat]
      node T_175860 = not(T_175858)
      accessor T_175861 = data_buffer[inner.acquire.bits.addr_beat]
      node T_175862 = and(T_175860, T_175861)
      node T_175863 = and(T_175858, inner.acquire.bits.data)
      node T_175864 = or(T_175862, T_175863)
      T_175859 := T_175864
      accessor T_175865 = wmask_buffer[inner.acquire.bits.addr_beat]
      node T_175866 = eq(state, UInt<4>(0))
      accessor T_175867 = wmask_buffer[inner.acquire.bits.addr_beat]
      wire T_175868 : UInt<16>
      T_175868 := T_175867
      when T_175866 : T_175868 := UInt<1>(0)
      node T_175869 = or(T_175809, T_175868)
      T_175865 := T_175869
    node T_175870 = eq(xact.a_type, UInt<3>(2))
    node T_175871 = and(xact.is_builtin_type, T_175870)
    node T_175872 = eq(xact.a_type, UInt<3>(3))
    node T_175873 = and(xact.is_builtin_type, T_175872)
    node T_175874 = or(T_175871, T_175873)
    node T_175875 = bits(xact.union, 5, 1)
    wire T_175876 : UInt<5>
    T_175876 := T_175875
    when T_175874 : T_175876 := UInt<5>(1)
    node T_175877 = eq(T_175876, UInt<5>(1))
    node T_175878 = eq(T_175876, UInt<5>(7))
    node T_175879 = or(T_175877, T_175878)
    node T_175880 = bit(T_175876, 3)
    node T_175881 = eq(T_175876, UInt<5>(4))
    node T_175882 = or(T_175880, T_175881)
    node T_175883 = or(T_175879, T_175882)
    wire T_175884 : UInt<2>
    T_175884 := meta.resp.bits.meta.coh.outer.state
    when T_175883 : T_175884 := UInt<2>(2)
    wire T_175885 : UInt<3>[3]
    T_175885[0] := UInt<3>(0)
    T_175885[1] := UInt<3>(1)
    T_175885[2] := UInt<3>(2)
    wire T_175886 : UInt<0>[1]
    T_175886[0] := UInt<0>(0)
    wire T_175887 : UInt<2>[2]
    T_175887[0] := UInt<2>(1)
    T_175887[1] := UInt<2>(2)
    wire T_175888 : UInt<2>[2]
    T_175888[0] := UInt<2>(1)
    T_175888[1] := UInt<2>(2)
    wire T_175889 : UInt<2>[1]
    T_175889[0] := UInt<2>(2)
    wire T_175890 : UInt<3>[3]
    T_175890[0] := UInt<3>(0)
    T_175890[1] := UInt<3>(1)
    T_175890[2] := UInt<3>(2)
    wire T_175891 : UInt<0>[1]
    T_175891[0] := UInt<0>(0)
    wire T_175892 : UInt<2>[2]
    T_175892[0] := UInt<2>(1)
    T_175892[1] := UInt<2>(2)
    wire T_175893 : UInt<2>[2]
    T_175893[0] := UInt<2>(1)
    T_175893[1] := UInt<2>(2)
    wire T_175894 : UInt<2>[1]
    T_175894[0] := UInt<2>(2)
    wire T_175895 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_175895.state := T_175884
    wire T_175896 : UInt<3>[3]
    T_175896[0] := UInt<3>(0)
    T_175896[1] := UInt<3>(1)
    T_175896[2] := UInt<3>(2)
    wire T_175897 : UInt<2>[2]
    T_175897[0] := UInt<2>(0)
    T_175897[1] := UInt<2>(1)
    wire T_175898 : UInt<2>[3]
    T_175898[0] := UInt<2>(1)
    T_175898[1] := UInt<2>(2)
    T_175898[2] := UInt<2>(3)
    wire T_175899 : UInt<2>[2]
    T_175899[0] := UInt<2>(2)
    T_175899[1] := UInt<2>(3)
    wire T_175900 : UInt<2>[1]
    T_175900[0] := UInt<2>(3)
    wire T_175901 : UInt<3>[3]
    T_175901[0] := UInt<3>(0)
    T_175901[1] := UInt<3>(1)
    T_175901[2] := UInt<3>(2)
    wire T_175902 : UInt<2>[2]
    T_175902[0] := UInt<2>(0)
    T_175902[1] := UInt<2>(1)
    wire T_175903 : UInt<2>[3]
    T_175903[0] := UInt<2>(1)
    T_175903[1] := UInt<2>(2)
    T_175903[2] := UInt<2>(3)
    wire T_175904 : UInt<2>[2]
    T_175904[0] := UInt<2>(2)
    T_175904[1] := UInt<2>(3)
    wire T_175905 : UInt<2>[1]
    T_175905[0] := UInt<2>(3)
    wire T_175906 : UInt<3>[3]
    T_175906[0] := UInt<3>(0)
    T_175906[1] := UInt<3>(1)
    T_175906[2] := UInt<3>(2)
    wire T_175907 : UInt<0>[1]
    T_175907[0] := UInt<0>(0)
    wire T_175908 : UInt<2>[2]
    T_175908[0] := UInt<2>(1)
    T_175908[1] := UInt<2>(2)
    wire T_175909 : UInt<2>[2]
    T_175909[0] := UInt<2>(1)
    T_175909[1] := UInt<2>(2)
    wire T_175910 : UInt<2>[1]
    T_175910[0] := UInt<2>(2)
    wire T_175911 : UInt<3>[3]
    T_175911[0] := UInt<3>(0)
    T_175911[1] := UInt<3>(1)
    T_175911[2] := UInt<3>(2)
    wire T_175912 : UInt<2>[2]
    T_175912[0] := UInt<2>(0)
    T_175912[1] := UInt<2>(1)
    wire T_175913 : UInt<2>[3]
    T_175913[0] := UInt<2>(1)
    T_175913[1] := UInt<2>(2)
    T_175913[2] := UInt<2>(3)
    wire T_175914 : UInt<2>[2]
    T_175914[0] := UInt<2>(2)
    T_175914[1] := UInt<2>(3)
    wire T_175915 : UInt<2>[1]
    T_175915[0] := UInt<2>(3)
    wire T_175916 : UInt<3>[3]
    T_175916[0] := UInt<3>(0)
    T_175916[1] := UInt<3>(1)
    T_175916[2] := UInt<3>(2)
    wire T_175917 : UInt<2>[2]
    T_175917[0] := UInt<2>(0)
    T_175917[1] := UInt<2>(1)
    wire T_175918 : UInt<2>[3]
    T_175918[0] := UInt<2>(1)
    T_175918[1] := UInt<2>(2)
    T_175918[2] := UInt<2>(3)
    wire T_175919 : UInt<2>[2]
    T_175919[0] := UInt<2>(2)
    T_175919[1] := UInt<2>(3)
    wire T_175920 : UInt<2>[1]
    T_175920[0] := UInt<2>(3)
    wire T_175921 : UInt<3>[3]
    T_175921[0] := UInt<3>(0)
    T_175921[1] := UInt<3>(1)
    T_175921[2] := UInt<3>(2)
    wire T_175922 : UInt<0>[1]
    T_175922[0] := UInt<0>(0)
    wire T_175923 : UInt<2>[2]
    T_175923[0] := UInt<2>(1)
    T_175923[1] := UInt<2>(2)
    wire T_175924 : UInt<2>[2]
    T_175924[0] := UInt<2>(1)
    T_175924[1] := UInt<2>(2)
    wire T_175925 : UInt<2>[1]
    T_175925[0] := UInt<2>(2)
    wire pending_coh_on_hit : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_hit.inner := meta.resp.bits.meta.coh.inner
    pending_coh_on_hit.outer := T_175895
    wire T_175926 : UInt<3>[3]
    T_175926[0] := UInt<3>(0)
    T_175926[1] := UInt<3>(1)
    T_175926[2] := UInt<3>(2)
    wire T_175927 : UInt<2>[2]
    T_175927[0] := UInt<2>(0)
    T_175927[1] := UInt<2>(1)
    wire T_175928 : UInt<2>[3]
    T_175928[0] := UInt<2>(1)
    T_175928[1] := UInt<2>(2)
    T_175928[2] := UInt<2>(3)
    wire T_175929 : UInt<2>[2]
    T_175929[0] := UInt<2>(2)
    T_175929[1] := UInt<2>(3)
    wire T_175930 : UInt<2>[1]
    T_175930[0] := UInt<2>(3)
    wire T_175931 : UInt<3>[3]
    T_175931[0] := UInt<3>(0)
    T_175931[1] := UInt<3>(1)
    T_175931[2] := UInt<3>(2)
    wire T_175932 : UInt<2>[2]
    T_175932[0] := UInt<2>(0)
    T_175932[1] := UInt<2>(1)
    wire T_175933 : UInt<2>[3]
    T_175933[0] := UInt<2>(1)
    T_175933[1] := UInt<2>(2)
    T_175933[2] := UInt<2>(3)
    wire T_175934 : UInt<2>[2]
    T_175934[0] := UInt<2>(2)
    T_175934[1] := UInt<2>(3)
    wire T_175935 : UInt<2>[1]
    T_175935[0] := UInt<2>(3)
    wire T_175936 : UInt<3>[3]
    T_175936[0] := UInt<3>(0)
    T_175936[1] := UInt<3>(1)
    T_175936[2] := UInt<3>(2)
    wire T_175937 : UInt<2>[2]
    T_175937[0] := UInt<2>(0)
    T_175937[1] := UInt<2>(1)
    wire T_175938 : UInt<2>[3]
    T_175938[0] := UInt<2>(1)
    T_175938[1] := UInt<2>(2)
    T_175938[2] := UInt<2>(3)
    wire T_175939 : UInt<2>[2]
    T_175939[0] := UInt<2>(2)
    T_175939[1] := UInt<2>(3)
    wire T_175940 : UInt<2>[1]
    T_175940[0] := UInt<2>(3)
    wire T_175941 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_175941.sharers := UInt<1>(0)
    wire T_175942 : UInt<3>[3]
    T_175942[0] := UInt<3>(0)
    T_175942[1] := UInt<3>(1)
    T_175942[2] := UInt<3>(2)
    wire T_175943 : UInt<2>[2]
    T_175943[0] := UInt<2>(0)
    T_175943[1] := UInt<2>(1)
    wire T_175944 : UInt<2>[3]
    T_175944[0] := UInt<2>(1)
    T_175944[1] := UInt<2>(2)
    T_175944[2] := UInt<2>(3)
    wire T_175945 : UInt<2>[2]
    T_175945[0] := UInt<2>(2)
    T_175945[1] := UInt<2>(3)
    wire T_175946 : UInt<2>[1]
    T_175946[0] := UInt<2>(3)
    wire T_175947 : UInt<3>[3]
    T_175947[0] := UInt<3>(0)
    T_175947[1] := UInt<3>(1)
    T_175947[2] := UInt<3>(2)
    wire T_175948 : UInt<2>[2]
    T_175948[0] := UInt<2>(0)
    T_175948[1] := UInt<2>(1)
    wire T_175949 : UInt<2>[3]
    T_175949[0] := UInt<2>(1)
    T_175949[1] := UInt<2>(2)
    T_175949[2] := UInt<2>(3)
    wire T_175950 : UInt<2>[2]
    T_175950[0] := UInt<2>(2)
    T_175950[1] := UInt<2>(3)
    wire T_175951 : UInt<2>[1]
    T_175951[0] := UInt<2>(3)
    wire T_175952 : UInt<3>[3]
    T_175952[0] := UInt<3>(0)
    T_175952[1] := UInt<3>(1)
    T_175952[2] := UInt<3>(2)
    wire T_175953 : UInt<2>[2]
    T_175953[0] := UInt<2>(0)
    T_175953[1] := UInt<2>(1)
    wire T_175954 : UInt<2>[3]
    T_175954[0] := UInt<2>(1)
    T_175954[1] := UInt<2>(2)
    T_175954[2] := UInt<2>(3)
    wire T_175955 : UInt<2>[2]
    T_175955[0] := UInt<2>(2)
    T_175955[1] := UInt<2>(3)
    wire T_175956 : UInt<2>[1]
    T_175956[0] := UInt<2>(3)
    wire T_175957 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_175957.state := UInt<2>(0)
    wire T_175958 : UInt<3>[3]
    T_175958[0] := UInt<3>(0)
    T_175958[1] := UInt<3>(1)
    T_175958[2] := UInt<3>(2)
    wire T_175959 : UInt<2>[2]
    T_175959[0] := UInt<2>(0)
    T_175959[1] := UInt<2>(1)
    wire T_175960 : UInt<2>[3]
    T_175960[0] := UInt<2>(1)
    T_175960[1] := UInt<2>(2)
    T_175960[2] := UInt<2>(3)
    wire T_175961 : UInt<2>[2]
    T_175961[0] := UInt<2>(2)
    T_175961[1] := UInt<2>(3)
    wire T_175962 : UInt<2>[1]
    T_175962[0] := UInt<2>(3)
    wire T_175963 : UInt<3>[3]
    T_175963[0] := UInt<3>(0)
    T_175963[1] := UInt<3>(1)
    T_175963[2] := UInt<3>(2)
    wire T_175964 : UInt<2>[2]
    T_175964[0] := UInt<2>(0)
    T_175964[1] := UInt<2>(1)
    wire T_175965 : UInt<2>[3]
    T_175965[0] := UInt<2>(1)
    T_175965[1] := UInt<2>(2)
    T_175965[2] := UInt<2>(3)
    wire T_175966 : UInt<2>[2]
    T_175966[0] := UInt<2>(2)
    T_175966[1] := UInt<2>(3)
    wire T_175967 : UInt<2>[1]
    T_175967[0] := UInt<2>(3)
    wire T_175968 : UInt<3>[3]
    T_175968[0] := UInt<3>(0)
    T_175968[1] := UInt<3>(1)
    T_175968[2] := UInt<3>(2)
    wire T_175969 : UInt<0>[1]
    T_175969[0] := UInt<0>(0)
    wire T_175970 : UInt<2>[2]
    T_175970[0] := UInt<2>(1)
    T_175970[1] := UInt<2>(2)
    wire T_175971 : UInt<2>[2]
    T_175971[0] := UInt<2>(1)
    T_175971[1] := UInt<2>(2)
    wire T_175972 : UInt<2>[1]
    T_175972[0] := UInt<2>(2)
    wire T_175973 : UInt<3>[3]
    T_175973[0] := UInt<3>(0)
    T_175973[1] := UInt<3>(1)
    T_175973[2] := UInt<3>(2)
    wire T_175974 : UInt<2>[2]
    T_175974[0] := UInt<2>(0)
    T_175974[1] := UInt<2>(1)
    wire T_175975 : UInt<2>[3]
    T_175975[0] := UInt<2>(1)
    T_175975[1] := UInt<2>(2)
    T_175975[2] := UInt<2>(3)
    wire T_175976 : UInt<2>[2]
    T_175976[0] := UInt<2>(2)
    T_175976[1] := UInt<2>(3)
    wire T_175977 : UInt<2>[1]
    T_175977[0] := UInt<2>(3)
    wire T_175978 : UInt<3>[3]
    T_175978[0] := UInt<3>(0)
    T_175978[1] := UInt<3>(1)
    T_175978[2] := UInt<3>(2)
    wire T_175979 : UInt<2>[2]
    T_175979[0] := UInt<2>(0)
    T_175979[1] := UInt<2>(1)
    wire T_175980 : UInt<2>[3]
    T_175980[0] := UInt<2>(1)
    T_175980[1] := UInt<2>(2)
    T_175980[2] := UInt<2>(3)
    wire T_175981 : UInt<2>[2]
    T_175981[0] := UInt<2>(2)
    T_175981[1] := UInt<2>(3)
    wire T_175982 : UInt<2>[1]
    T_175982[0] := UInt<2>(3)
    wire T_175983 : UInt<3>[3]
    T_175983[0] := UInt<3>(0)
    T_175983[1] := UInt<3>(1)
    T_175983[2] := UInt<3>(2)
    wire T_175984 : UInt<0>[1]
    T_175984[0] := UInt<0>(0)
    wire T_175985 : UInt<2>[2]
    T_175985[0] := UInt<2>(1)
    T_175985[1] := UInt<2>(2)
    wire T_175986 : UInt<2>[2]
    T_175986[0] := UInt<2>(1)
    T_175986[1] := UInt<2>(2)
    wire T_175987 : UInt<2>[1]
    T_175987[0] := UInt<2>(2)
    wire pending_coh_on_miss : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    pending_coh_on_miss.inner := T_175941
    pending_coh_on_miss.outer := T_175957
    
    
    node T_175988 = eq(state, UInt<4>(0))
    node T_175989 = and(T_175988, inner.acquire.valid)
    when T_175989 : 
      xact := inner.acquire.bits
      xact.data := UInt<1>(0)
      node T_175990 = eq(inner.acquire.bits.a_type, UInt<3>(3))
      node T_175991 = and(inner.acquire.bits.is_builtin_type, T_175990)
      node T_175992 = and(inner.acquire.ready, inner.acquire.valid)
      wire T_175993 : UInt<3>[3]
      T_175993[0] := UInt<3>(2)
      T_175993[1] := UInt<3>(3)
      T_175993[2] := UInt<3>(4)
      node T_175994 = eq(T_175993[0], inner.acquire.bits.a_type)
      node T_175995 = eq(T_175993[1], inner.acquire.bits.a_type)
      node T_175996 = eq(T_175993[2], inner.acquire.bits.a_type)
      node T_175997 = or(UInt<1>(0), T_175994)
      node T_175998 = or(T_175997, T_175995)
      node T_175999 = or(T_175998, T_175996)
      node T_176000 = and(inner.acquire.bits.is_builtin_type, T_175999)
      node T_176001 = and(T_175992, T_176000)
      node T_176002 = subw(UInt<4>(0), UInt<3>(4))
      node T_176003 = not(T_176002)
      node T_176004 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_176005 = not(T_176004)
      node T_176006 = or(T_176003, T_176005)
      wire T_176007 : UInt<1>
      T_176007 := UInt<1>(0)
      when T_175991 : T_176007 := T_176006
      pending_puts := T_176007
      node T_176008 = eq(inner.acquire.bits.a_type, UInt<3>(1))
      node T_176009 = and(inner.acquire.bits.is_builtin_type, T_176008)
      node T_176010 = eq(inner.acquire.bits.is_builtin_type, UInt<1>(0))
      node T_176011 = or(T_176009, T_176010)
      wire T_176012 : UInt<3>[3]
      T_176012[0] := UInt<3>(0)
      T_176012[1] := UInt<3>(1)
      T_176012[2] := UInt<3>(4)
      node T_176013 = eq(T_176012[0], inner.acquire.bits.a_type)
      node T_176014 = eq(T_176012[1], inner.acquire.bits.a_type)
      node T_176015 = eq(T_176012[2], inner.acquire.bits.a_type)
      node T_176016 = or(UInt<1>(0), T_176013)
      node T_176017 = or(T_176016, T_176014)
      node T_176018 = or(T_176017, T_176015)
      node T_176019 = and(inner.acquire.bits.is_builtin_type, T_176018)
      node T_176020 = and(inner.acquire.ready, inner.acquire.valid)
      node T_176021 = and(T_176020, T_176019)
      node T_176022 = subw(UInt<4>(0), UInt<3>(4))
      node T_176023 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_176024 = and(T_176022, T_176023)
      node T_176025 = eq(inner.acquire.bits.a_type, UInt<3>(4))
      node T_176026 = and(inner.acquire.bits.is_builtin_type, T_176025)
      node T_176027 = bits(inner.acquire.bits.union, 12, 9)
      node T_176028 = bits(T_176027, 3, 3)
      node T_176029 = dshl(UInt<1>(1), T_176028)
      node T_176030 = bit(T_176029, 0)
      node T_176031 = bit(T_176029, 1)
      node T_176032 = bit(T_176029, 2)
      wire T_176033 : UInt<1>[3]
      T_176033[0] := T_176030
      T_176033[1] := T_176031
      T_176033[2] := T_176032
      node T_176034 = subw(UInt<8>(0), UInt<4>(8))
      node T_176035 = subw(UInt<8>(0), UInt<4>(8))
      node T_176036 = subw(UInt<8>(0), UInt<4>(8))
      wire T_176037 : UInt<8>[3]
      T_176037[0] := T_176034
      T_176037[1] := T_176035
      T_176037[2] := T_176036
      node T_176038 = cat(T_176037[1], T_176037[0])
      node T_176039 = cat(T_176037[2], T_176038)
      node T_176040 = eq(inner.acquire.bits.a_type, UInt<3>(3))
      node T_176041 = and(inner.acquire.bits.is_builtin_type, T_176040)
      node T_176042 = eq(inner.acquire.bits.a_type, UInt<3>(2))
      node T_176043 = and(inner.acquire.bits.is_builtin_type, T_176042)
      node T_176044 = or(T_176041, T_176043)
      node T_176045 = bits(inner.acquire.bits.union, 16, 1)
      wire T_176046 : UInt<16>
      T_176046 := UInt<16>(0)
      when T_176044 : T_176046 := T_176045
      wire T_176047 : UInt<16>
      T_176047 := T_176046
      when T_176026 : T_176047 := T_176039
      wire T_176048 : UInt<3>[3]
      T_176048[0] := UInt<3>(0)
      T_176048[1] := UInt<3>(1)
      T_176048[2] := UInt<3>(2)
      wire T_176049 : UInt<2>[2]
      T_176049[0] := UInt<2>(0)
      T_176049[1] := UInt<2>(1)
      wire T_176050 : UInt<2>[3]
      T_176050[0] := UInt<2>(1)
      T_176050[1] := UInt<2>(2)
      T_176050[2] := UInt<2>(3)
      wire T_176051 : UInt<2>[2]
      T_176051[0] := UInt<2>(2)
      T_176051[1] := UInt<2>(3)
      wire T_176052 : UInt<2>[1]
      T_176052[0] := UInt<2>(3)
      node T_176053 = asUInt(SInt<16>(-1))
      node T_176054 = neq(T_176047, T_176053)
      node T_176055 = and(inner.acquire.ready, inner.acquire.valid)
      node T_176056 = and(T_176055, T_176054)
      node T_176057 = and(T_176056, UInt<1>(0))
      node T_176058 = subw(UInt<4>(0), UInt<3>(4))
      node T_176059 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_176060 = and(T_176058, T_176059)
      node T_176061 = or(T_176024, T_176060)
      node T_176062 = asSInt(T_176061)
      wire T_176063 : SInt<5>
      T_176063 := T_176062
      when T_176011 : T_176063 := SInt<1>(-1)
      node T_176064 = asUInt(T_176063)
      pending_reads := T_176064
      node T_176065 = and(inner.acquire.ready, inner.acquire.valid)
      wire T_176066 : UInt<3>[3]
      T_176066[0] := UInt<3>(2)
      T_176066[1] := UInt<3>(3)
      T_176066[2] := UInt<3>(4)
      node T_176067 = eq(T_176066[0], inner.acquire.bits.a_type)
      node T_176068 = eq(T_176066[1], inner.acquire.bits.a_type)
      node T_176069 = eq(T_176066[2], inner.acquire.bits.a_type)
      node T_176070 = or(UInt<1>(0), T_176067)
      node T_176071 = or(T_176070, T_176068)
      node T_176072 = or(T_176071, T_176069)
      node T_176073 = and(inner.acquire.bits.is_builtin_type, T_176072)
      node T_176074 = and(T_176065, T_176073)
      node T_176075 = bit(inner.acquire.bits.union, 0)
      node T_176076 = and(T_176074, T_176075)
      node T_176077 = subw(UInt<4>(0), UInt<3>(4))
      node T_176078 = dshl(UInt<1>(1), inner.acquire.bits.addr_beat)
      node T_176079 = and(T_176077, T_176078)
      pending_writes := T_176079
      pending_resps := UInt<1>(0)
      pending_ignt_data := UInt<1>(0)
      pending_meta_write := UInt<1>(0)
      state := UInt<4>(1)
    
    
    node T_176080 = eq(state, UInt<4>(1))
    node T_176081 = and(T_176080, meta.read.ready)
    when T_176081 : state := UInt<4>(2)
    
    
    node T_176082 = eq(state, UInt<4>(2))
    node T_176083 = and(T_176082, meta.resp.valid)
    when T_176083 : 
      xact_tag_match := meta.resp.bits.tag_match
      xact_old_meta := meta.resp.bits.meta
      xact_way_en := meta.resp.bits.way_en
      node T_176084 = eq(xact.a_type, UInt<3>(3))
      node T_176085 = and(xact.is_builtin_type, T_176084)
      node T_176086 = neq(meta.resp.bits.meta.coh.outer.state, UInt<2>(0))
      node T_176087 = and(meta.resp.bits.tag_match, T_176086)
      node T_176088 = or(T_176085, T_176087)
      node T_176089 = eq(meta.resp.bits.tag_match, UInt<1>(0))
      node T_176090 = bit(xact.union, 0)
      node T_176091 = and(T_176089, T_176090)
      node T_176092 = eq(T_174537[0], meta.resp.bits.meta.coh.outer.state)
      node T_176093 = or(UInt<1>(0), T_176092)
      node T_176094 = eq(meta.resp.bits.meta.coh.inner.sharers, UInt<1>(0))
      node T_176095 = eq(T_176094, UInt<1>(0))
      node T_176096 = or(T_176093, T_176095)
      node T_176097 = and(T_176091, T_176096)
      node T_176098 = eq(meta.resp.bits.meta.coh.inner.sharers, UInt<1>(0))
      node T_176099 = bit(meta.resp.bits.meta.coh.inner.sharers, 0)
      node T_176100 = eq(T_176099, UInt<1>(1))
      wire T_176101 : UInt<3>[3]
      T_176101[0] := UInt<3>(2)
      T_176101[1] := UInt<3>(3)
      T_176101[2] := UInt<3>(4)
      node T_176102 = eq(T_176101[0], xact.a_type)
      node T_176103 = eq(T_176101[1], xact.a_type)
      node T_176104 = eq(T_176101[2], xact.a_type)
      node T_176105 = or(UInt<1>(0), T_176102)
      node T_176106 = or(T_176105, T_176103)
      node T_176107 = or(T_176106, T_176104)
      node T_176108 = and(xact.is_builtin_type, T_176107)
      node T_176109 = neq(xact.a_type, UInt<1>(0))
      wire T_176110 : UInt<1>
      T_176110 := T_176109
      when xact.is_builtin_type : T_176110 := T_176108
      wire T_176111 : UInt<1>
      T_176111 := T_176110
      when T_176100 : T_176111 := UInt<1>(1)
      wire T_176112 : UInt<1>
      T_176112 := T_176111
      when T_176098 : T_176112 := UInt<1>(0)
      node T_176113 = and(meta.resp.bits.tag_match, T_176112)
      
      
      node T_176114 = eq(meta.resp.bits.tag_match, UInt<1>(0))
      node T_176115 = eq(pending_coh_on_hit.inner.sharers, meta.resp.bits.meta.coh.inner.sharers)
      node T_176116 = eq(pending_coh_on_hit.outer.state, meta.resp.bits.meta.coh.outer.state)
      node T_176117 = and(T_176115, T_176116)
      node T_176118 = eq(T_176117, UInt<1>(0))
      node T_176119 = and(T_176088, T_176118)
      node T_176120 = or(T_176114, T_176119)
      when T_176120 : pending_meta_write := UInt<1>(1)
      wire T_176121 : UInt<3>[3]
      T_176121[0] := UInt<3>(0)
      T_176121[1] := UInt<3>(1)
      T_176121[2] := UInt<3>(2)
      wire T_176122 : UInt<2>[2]
      T_176122[0] := UInt<2>(0)
      T_176122[1] := UInt<2>(1)
      wire T_176123 : UInt<2>[3]
      T_176123[0] := UInt<2>(1)
      T_176123[1] := UInt<2>(2)
      T_176123[2] := UInt<2>(3)
      wire T_176124 : UInt<2>[2]
      T_176124[0] := UInt<2>(2)
      T_176124[1] := UInt<2>(3)
      wire T_176125 : UInt<2>[1]
      T_176125[0] := UInt<2>(3)
      wire T_176126 : UInt<3>[3]
      T_176126[0] := UInt<3>(0)
      T_176126[1] := UInt<3>(1)
      T_176126[2] := UInt<3>(2)
      wire T_176127 : UInt<2>[2]
      T_176127[0] := UInt<2>(0)
      T_176127[1] := UInt<2>(1)
      wire T_176128 : UInt<2>[3]
      T_176128[0] := UInt<2>(1)
      T_176128[1] := UInt<2>(2)
      T_176128[2] := UInt<2>(3)
      wire T_176129 : UInt<2>[2]
      T_176129[0] := UInt<2>(2)
      T_176129[1] := UInt<2>(3)
      wire T_176130 : UInt<2>[1]
      T_176130[0] := UInt<2>(3)
      wire T_176131 : UInt<3>[3]
      T_176131[0] := UInt<3>(0)
      T_176131[1] := UInt<3>(1)
      T_176131[2] := UInt<3>(2)
      wire T_176132 : UInt<0>[1]
      T_176132[0] := UInt<0>(0)
      wire T_176133 : UInt<2>[2]
      T_176133[0] := UInt<2>(1)
      T_176133[1] := UInt<2>(2)
      wire T_176134 : UInt<2>[2]
      T_176134[0] := UInt<2>(1)
      T_176134[1] := UInt<2>(2)
      wire T_176135 : UInt<2>[1]
      T_176135[0] := UInt<2>(2)
      wire T_176136 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
      T_176136 := pending_coh_on_miss
      when meta.resp.bits.tag_match : T_176136 := meta.resp.bits.meta.coh
      wire T_176137 : UInt<3>[3]
      T_176137[0] := UInt<3>(0)
      T_176137[1] := UInt<3>(1)
      T_176137[2] := UInt<3>(2)
      wire T_176138 : UInt<2>[2]
      T_176138[0] := UInt<2>(0)
      T_176138[1] := UInt<2>(1)
      wire T_176139 : UInt<2>[3]
      T_176139[0] := UInt<2>(1)
      T_176139[1] := UInt<2>(2)
      T_176139[2] := UInt<2>(3)
      wire T_176140 : UInt<2>[2]
      T_176140[0] := UInt<2>(2)
      T_176140[1] := UInt<2>(3)
      wire T_176141 : UInt<2>[1]
      T_176141[0] := UInt<2>(3)
      wire T_176142 : UInt<3>[3]
      T_176142[0] := UInt<3>(0)
      T_176142[1] := UInt<3>(1)
      T_176142[2] := UInt<3>(2)
      wire T_176143 : UInt<2>[2]
      T_176143[0] := UInt<2>(0)
      T_176143[1] := UInt<2>(1)
      wire T_176144 : UInt<2>[3]
      T_176144[0] := UInt<2>(1)
      T_176144[1] := UInt<2>(2)
      T_176144[2] := UInt<2>(3)
      wire T_176145 : UInt<2>[2]
      T_176145[0] := UInt<2>(2)
      T_176145[1] := UInt<2>(3)
      wire T_176146 : UInt<2>[1]
      T_176146[0] := UInt<2>(3)
      wire T_176147 : UInt<3>[3]
      T_176147[0] := UInt<3>(0)
      T_176147[1] := UInt<3>(1)
      T_176147[2] := UInt<3>(2)
      wire T_176148 : UInt<0>[1]
      T_176148[0] := UInt<0>(0)
      wire T_176149 : UInt<2>[2]
      T_176149[0] := UInt<2>(1)
      T_176149[1] := UInt<2>(2)
      wire T_176150 : UInt<2>[2]
      T_176150[0] := UInt<2>(1)
      T_176150[1] := UInt<2>(2)
      wire T_176151 : UInt<2>[1]
      T_176151[0] := UInt<2>(2)
      wire T_176152 : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
      T_176152 := T_176136
      when T_176088 : T_176152 := pending_coh_on_hit
      pending_coh := T_176152
      when T_176113 : 
        node T_176153 = dshl(UInt<1>(1), xact.client_id)
        node T_176154 = or(meta.resp.bits.meta.coh.inner.sharers, T_176153)
        node T_176155 = dshl(UInt<1>(1), xact.client_id)
        node T_176156 = not(T_176155)
        node T_176157 = and(meta.resp.bits.meta.coh.inner.sharers, T_176156)
        wire T_176158 : UInt<5>
        T_176158 := T_176157
        when UInt<1>(0) : T_176158 := T_176154
        node T_176159 = not(incoherent[0])
        node T_176160 = and(T_176158, T_176159)
        pending_iprbs := T_176160
      node T_176161 = eq(T_176088, UInt<1>(0))
      wire T_176162 : UInt<4>
      T_176162 := UInt<4>(7)
      when T_176161 : T_176162 := UInt<4>(6)
      wire T_176163 : UInt<4>
      T_176163 := T_176162
      when T_176113 : T_176163 := UInt<4>(5)
      wire T_176164 : UInt<4>
      T_176164 := T_176163
      when T_176097 : T_176164 := UInt<4>(3)
      state := T_176164
    
    
    node T_176165 = eq(state, UInt<4>(3))
    node T_176166 = and(T_176165, wb.req.ready)
    when T_176166 : state := UInt<4>(4)
    
    
    node T_176167 = eq(state, UInt<4>(4))
    node T_176168 = and(T_176167, wb.resp.valid)
    when T_176168 : 
      node T_176169 = eq(xact.a_type, UInt<3>(3))
      node T_176170 = and(xact.is_builtin_type, T_176169)
      node T_176171 = and(UInt<1>(1), T_176170)
      node T_176172 = eq(T_176171, UInt<1>(0))
      wire T_176173 : UInt<4>
      T_176173 := UInt<4>(7)
      when T_176172 : T_176173 := UInt<4>(6)
      state := T_176173
    
    
    node T_176174 = eq(state, UInt<4>(5))
    node T_176175 = eq(pending_iprbs, UInt<1>(0))
    node T_176176 = eq(T_176175, UInt<1>(0))
    node T_176177 = or(T_176176, pending_irels)
    node T_176178 = eq(T_176177, UInt<1>(0))
    node T_176179 = and(T_176174, T_176178)
    when T_176179 : 
      node T_176180 = eq(xact.a_type, UInt<3>(3))
      node T_176181 = and(xact.is_builtin_type, T_176180)
      node T_176182 = neq(xact_old_meta.coh.outer.state, UInt<2>(0))
      node T_176183 = or(T_176181, T_176182)
      node T_176184 = eq(T_176183, UInt<1>(0))
      wire T_176185 : UInt<4>
      T_176185 := UInt<4>(7)
      when T_176184 : T_176185 := UInt<4>(6)
      state := T_176185
    
    
    node T_176186 = eq(state, UInt<4>(6))
    node T_176187 = and(T_176186, oacq_data_done)
    when T_176187 : state := UInt<4>(7)
    
    
    node T_176188 = eq(state, UInt<4>(7))
    node T_176189 = and(T_176188, all_pending_done)
    when T_176189 : state := UInt<4>(8)
    
    
    node T_176190 = eq(state, UInt<4>(8))
    node T_176191 = eq(pending_meta_write, UInt<1>(0))
    node T_176192 = or(meta.write.ready, T_176191)
    node T_176193 = and(T_176190, T_176192)
    when T_176193 : 
      wmask_buffer[0] := UInt<1>(0)
      wmask_buffer[1] := UInt<1>(0)
      wmask_buffer[2] := UInt<1>(0)
      wmask_buffer[3] := UInt<1>(0)
      state := UInt<4>(0)
    node T_176194 = bits(xact.addr_block, 11, 0)
    node T_176195 = bits(inner.acquire.bits.addr_block, 11, 0)
    node in_same_set = eq(T_176194, T_176195)
    node T_176196 = eq(xact.addr_block, inner.release.bits.addr_block)
    node T_176197 = eq(inner.release.bits.voluntary, UInt<1>(0))
    node T_176198 = and(T_176196, T_176197)
    node T_176199 = and(T_176198, inner.release.ready)
    has_release_match := T_176199
    node T_176200 = or(can_merge_iacq_put, can_merge_iacq_get)
    has_acquire_match := T_176200
    node T_176201 = neq(state, UInt<4>(0))
    node T_176202 = and(in_same_set, T_176201)
    node T_176203 = eq(has_acquire_match, UInt<1>(0))
    node T_176204 = and(T_176202, T_176203)
    has_acquire_conflict := T_176204
    node T_176205 = neq(state, UInt<4>(0))
    node T_176206 = and(inner.acquire.ready, inner.acquire.valid)
    node T_176207 = and(T_176205, T_176206)
    node T_176208 = neq(inner.acquire.bits.client_id, xact.client_id)
    node T_176209 = and(T_176207, T_176208)
    node T_176210 = eq(T_176209, UInt<1>(0))
  module L2WritebackUnit : 
    output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input incoherent : UInt<1>[1]
    output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output has_acquire_conflict : UInt<1>
    output has_acquire_match : UInt<1>
    output has_release_match : UInt<1>
    input wb : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>}}}
    output data : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}}
    
    wire T_176211 : UInt<3>[3]
    T_176211[0] := UInt<3>(0)
    T_176211[1] := UInt<3>(1)
    T_176211[2] := UInt<3>(2)
    wire T_176212 : UInt<2>[2]
    T_176212[0] := UInt<2>(0)
    T_176212[1] := UInt<2>(1)
    wire T_176213 : UInt<2>[3]
    T_176213[0] := UInt<2>(1)
    T_176213[1] := UInt<2>(2)
    T_176213[2] := UInt<2>(3)
    wire T_176214 : UInt<2>[2]
    T_176214[0] := UInt<2>(2)
    T_176214[1] := UInt<2>(3)
    wire T_176215 : UInt<2>[1]
    T_176215[0] := UInt<2>(3)
    wire T_176216 : UInt<3>[3]
    T_176216[0] := UInt<3>(0)
    T_176216[1] := UInt<3>(1)
    T_176216[2] := UInt<3>(2)
    wire T_176217 : UInt<2>[2]
    T_176217[0] := UInt<2>(0)
    T_176217[1] := UInt<2>(1)
    wire T_176218 : UInt<2>[3]
    T_176218[0] := UInt<2>(1)
    T_176218[1] := UInt<2>(2)
    T_176218[2] := UInt<2>(3)
    wire T_176219 : UInt<2>[2]
    T_176219[0] := UInt<2>(2)
    T_176219[1] := UInt<2>(3)
    wire T_176220 : UInt<2>[1]
    T_176220[0] := UInt<2>(3)
    wire T_176221 : UInt<3>[3]
    T_176221[0] := UInt<3>(0)
    T_176221[1] := UInt<3>(1)
    T_176221[2] := UInt<3>(2)
    wire T_176222 : UInt<2>[2]
    T_176222[0] := UInt<2>(0)
    T_176222[1] := UInt<2>(1)
    wire T_176223 : UInt<2>[3]
    T_176223[0] := UInt<2>(1)
    T_176223[1] := UInt<2>(2)
    T_176223[2] := UInt<2>(3)
    wire T_176224 : UInt<2>[2]
    T_176224[0] := UInt<2>(2)
    T_176224[1] := UInt<2>(3)
    wire T_176225 : UInt<2>[1]
    T_176225[0] := UInt<2>(3)
    wire T_176226 : UInt<3>[3]
    T_176226[0] := UInt<3>(0)
    T_176226[1] := UInt<3>(1)
    T_176226[2] := UInt<3>(2)
    wire T_176227 : UInt<2>[2]
    T_176227[0] := UInt<2>(0)
    T_176227[1] := UInt<2>(1)
    wire T_176228 : UInt<2>[3]
    T_176228[0] := UInt<2>(1)
    T_176228[1] := UInt<2>(2)
    T_176228[2] := UInt<2>(3)
    wire T_176229 : UInt<2>[2]
    T_176229[0] := UInt<2>(2)
    T_176229[1] := UInt<2>(3)
    wire T_176230 : UInt<2>[1]
    T_176230[0] := UInt<2>(3)
    wire T_176231 : UInt<3>[3]
    T_176231[0] := UInt<3>(0)
    T_176231[1] := UInt<3>(1)
    T_176231[2] := UInt<3>(2)
    wire T_176232 : UInt<2>[2]
    T_176232[0] := UInt<2>(0)
    T_176232[1] := UInt<2>(1)
    wire T_176233 : UInt<2>[3]
    T_176233[0] := UInt<2>(1)
    T_176233[1] := UInt<2>(2)
    T_176233[2] := UInt<2>(3)
    wire T_176234 : UInt<2>[2]
    T_176234[0] := UInt<2>(2)
    T_176234[1] := UInt<2>(3)
    wire T_176235 : UInt<2>[1]
    T_176235[0] := UInt<2>(3)
    wire T_176236 : UInt<3>[3]
    T_176236[0] := UInt<3>(0)
    T_176236[1] := UInt<3>(1)
    T_176236[2] := UInt<3>(2)
    wire T_176237 : UInt<2>[2]
    T_176237[0] := UInt<2>(0)
    T_176237[1] := UInt<2>(1)
    wire T_176238 : UInt<2>[3]
    T_176238[0] := UInt<2>(1)
    T_176238[1] := UInt<2>(2)
    T_176238[2] := UInt<2>(3)
    wire T_176239 : UInt<2>[2]
    T_176239[0] := UInt<2>(2)
    T_176239[1] := UInt<2>(3)
    wire T_176240 : UInt<2>[1]
    T_176240[0] := UInt<2>(3)
    wire T_176241 : UInt<3>[3]
    T_176241[0] := UInt<3>(0)
    T_176241[1] := UInt<3>(1)
    T_176241[2] := UInt<3>(2)
    wire T_176242 : UInt<2>[2]
    T_176242[0] := UInt<2>(0)
    T_176242[1] := UInt<2>(1)
    wire T_176243 : UInt<2>[3]
    T_176243[0] := UInt<2>(1)
    T_176243[1] := UInt<2>(2)
    T_176243[2] := UInt<2>(3)
    wire T_176244 : UInt<2>[2]
    T_176244[0] := UInt<2>(2)
    T_176244[1] := UInt<2>(3)
    wire T_176245 : UInt<2>[1]
    T_176245[0] := UInt<2>(3)
    wire T_176246 : UInt<3>[3]
    T_176246[0] := UInt<3>(0)
    T_176246[1] := UInt<3>(1)
    T_176246[2] := UInt<3>(2)
    wire T_176247 : UInt<2>[2]
    T_176247[0] := UInt<2>(0)
    T_176247[1] := UInt<2>(1)
    wire T_176248 : UInt<2>[3]
    T_176248[0] := UInt<2>(1)
    T_176248[1] := UInt<2>(2)
    T_176248[2] := UInt<2>(3)
    wire T_176249 : UInt<2>[2]
    T_176249[0] := UInt<2>(2)
    T_176249[1] := UInt<2>(3)
    wire T_176250 : UInt<2>[1]
    T_176250[0] := UInt<2>(3)
    wire T_176251 : UInt<3>[3]
    T_176251[0] := UInt<3>(0)
    T_176251[1] := UInt<3>(1)
    T_176251[2] := UInt<3>(2)
    wire T_176252 : UInt<2>[2]
    T_176252[0] := UInt<2>(0)
    T_176252[1] := UInt<2>(1)
    wire T_176253 : UInt<2>[3]
    T_176253[0] := UInt<2>(1)
    T_176253[1] := UInt<2>(2)
    T_176253[2] := UInt<2>(3)
    wire T_176254 : UInt<2>[2]
    T_176254[0] := UInt<2>(2)
    T_176254[1] := UInt<2>(3)
    wire T_176255 : UInt<2>[1]
    T_176255[0] := UInt<2>(3)
    wire T_176256 : UInt<3>[3]
    T_176256[0] := UInt<3>(0)
    T_176256[1] := UInt<3>(1)
    T_176256[2] := UInt<3>(2)
    wire T_176257 : UInt<2>[2]
    T_176257[0] := UInt<2>(0)
    T_176257[1] := UInt<2>(1)
    wire T_176258 : UInt<2>[3]
    T_176258[0] := UInt<2>(1)
    T_176258[1] := UInt<2>(2)
    T_176258[2] := UInt<2>(3)
    wire T_176259 : UInt<2>[2]
    T_176259[0] := UInt<2>(2)
    T_176259[1] := UInt<2>(3)
    wire T_176260 : UInt<2>[1]
    T_176260[0] := UInt<2>(3)
    wire T_176261 : UInt<3>[3]
    T_176261[0] := UInt<3>(0)
    T_176261[1] := UInt<3>(1)
    T_176261[2] := UInt<3>(2)
    wire T_176262 : UInt<2>[2]
    T_176262[0] := UInt<2>(0)
    T_176262[1] := UInt<2>(1)
    wire T_176263 : UInt<2>[3]
    T_176263[0] := UInt<2>(1)
    T_176263[1] := UInt<2>(2)
    T_176263[2] := UInt<2>(3)
    wire T_176264 : UInt<2>[2]
    T_176264[0] := UInt<2>(2)
    T_176264[1] := UInt<2>(3)
    wire T_176265 : UInt<2>[1]
    T_176265[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_176266
    wire T_176267 : UInt<3>[3]
    T_176267[0] := UInt<3>(0)
    T_176267[1] := UInt<3>(1)
    T_176267[2] := UInt<3>(2)
    wire T_176268 : UInt<0>[1]
    T_176268[0] := UInt<0>(0)
    wire T_176269 : UInt<2>[2]
    T_176269[0] := UInt<2>(1)
    T_176269[1] := UInt<2>(2)
    wire T_176270 : UInt<2>[2]
    T_176270[0] := UInt<2>(1)
    T_176270[1] := UInt<2>(2)
    wire T_176271 : UInt<2>[1]
    T_176271[0] := UInt<2>(2)
    wire T_176272 : UInt<3>[3]
    T_176272[0] := UInt<3>(0)
    T_176272[1] := UInt<3>(1)
    T_176272[2] := UInt<3>(2)
    wire T_176273 : UInt<0>[1]
    T_176273[0] := UInt<0>(0)
    wire T_176274 : UInt<2>[2]
    T_176274[0] := UInt<2>(1)
    T_176274[1] := UInt<2>(2)
    wire T_176275 : UInt<2>[2]
    T_176275[0] := UInt<2>(1)
    T_176275[1] := UInt<2>(2)
    wire T_176276 : UInt<2>[1]
    T_176276[0] := UInt<2>(2)
    wire T_176277 : UInt<3>[3]
    T_176277[0] := UInt<3>(0)
    T_176277[1] := UInt<3>(1)
    T_176277[2] := UInt<3>(2)
    wire T_176278 : UInt<0>[1]
    T_176278[0] := UInt<0>(0)
    wire T_176279 : UInt<2>[2]
    T_176279[0] := UInt<2>(1)
    T_176279[1] := UInt<2>(2)
    wire T_176280 : UInt<2>[2]
    T_176280[0] := UInt<2>(1)
    T_176280[1] := UInt<2>(2)
    wire T_176281 : UInt<2>[1]
    T_176281[0] := UInt<2>(2)
    wire T_176282 : UInt<3>[3]
    T_176282[0] := UInt<3>(0)
    T_176282[1] := UInt<3>(1)
    T_176282[2] := UInt<3>(2)
    wire T_176283 : UInt<0>[1]
    T_176283[0] := UInt<0>(0)
    wire T_176284 : UInt<2>[2]
    T_176284[0] := UInt<2>(1)
    T_176284[1] := UInt<2>(2)
    wire T_176285 : UInt<2>[2]
    T_176285[0] := UInt<2>(1)
    T_176285[1] := UInt<2>(2)
    wire T_176286 : UInt<2>[1]
    T_176286[0] := UInt<2>(2)
    wire T_176287 : UInt<3>[3]
    T_176287[0] := UInt<3>(0)
    T_176287[1] := UInt<3>(1)
    T_176287[2] := UInt<3>(2)
    wire T_176288 : UInt<0>[1]
    T_176288[0] := UInt<0>(0)
    wire T_176289 : UInt<2>[2]
    T_176289[0] := UInt<2>(1)
    T_176289[1] := UInt<2>(2)
    wire T_176290 : UInt<2>[2]
    T_176290[0] := UInt<2>(1)
    T_176290[1] := UInt<2>(2)
    wire T_176291 : UInt<2>[1]
    T_176291[0] := UInt<2>(2)
    wire T_176292 : UInt<3>[3]
    T_176292[0] := UInt<3>(0)
    T_176292[1] := UInt<3>(1)
    T_176292[2] := UInt<3>(2)
    wire T_176293 : UInt<0>[1]
    T_176293[0] := UInt<0>(0)
    wire T_176294 : UInt<2>[2]
    T_176294[0] := UInt<2>(1)
    T_176294[1] := UInt<2>(2)
    wire T_176295 : UInt<2>[2]
    T_176295[0] := UInt<2>(1)
    T_176295[1] := UInt<2>(2)
    wire T_176296 : UInt<2>[1]
    T_176296[0] := UInt<2>(2)
    wire T_176297 : UInt<3>[3]
    T_176297[0] := UInt<3>(0)
    T_176297[1] := UInt<3>(1)
    T_176297[2] := UInt<3>(2)
    wire T_176298 : UInt<0>[1]
    T_176298[0] := UInt<0>(0)
    wire T_176299 : UInt<2>[2]
    T_176299[0] := UInt<2>(1)
    T_176299[1] := UInt<2>(2)
    wire T_176300 : UInt<2>[2]
    T_176300[0] := UInt<2>(1)
    T_176300[1] := UInt<2>(2)
    wire T_176301 : UInt<2>[1]
    T_176301[0] := UInt<2>(2)
    wire T_176302 : UInt<3>[3]
    T_176302[0] := UInt<3>(0)
    T_176302[1] := UInt<3>(1)
    T_176302[2] := UInt<3>(2)
    wire T_176303 : UInt<0>[1]
    T_176303[0] := UInt<0>(0)
    wire T_176304 : UInt<2>[2]
    T_176304[0] := UInt<2>(1)
    T_176304[1] := UInt<2>(2)
    wire T_176305 : UInt<2>[2]
    T_176305[0] := UInt<2>(1)
    T_176305[1] := UInt<2>(2)
    wire T_176306 : UInt<2>[1]
    T_176306[0] := UInt<2>(2)
    wire T_176307 : UInt<3>[3]
    T_176307[0] := UInt<3>(0)
    T_176307[1] := UInt<3>(1)
    T_176307[2] := UInt<3>(2)
    wire T_176308 : UInt<0>[1]
    T_176308[0] := UInt<0>(0)
    wire T_176309 : UInt<2>[2]
    T_176309[0] := UInt<2>(1)
    T_176309[1] := UInt<2>(2)
    wire T_176310 : UInt<2>[2]
    T_176310[0] := UInt<2>(1)
    T_176310[1] := UInt<2>(2)
    wire T_176311 : UInt<2>[1]
    T_176311[0] := UInt<2>(2)
    wire T_176312 : UInt<3>[3]
    T_176312[0] := UInt<3>(0)
    T_176312[1] := UInt<3>(1)
    T_176312[2] := UInt<3>(2)
    wire T_176313 : UInt<2>[2]
    T_176313[0] := UInt<2>(0)
    T_176313[1] := UInt<2>(1)
    wire T_176314 : UInt<2>[3]
    T_176314[0] := UInt<2>(1)
    T_176314[1] := UInt<2>(2)
    T_176314[2] := UInt<2>(3)
    wire T_176315 : UInt<2>[2]
    T_176315[0] := UInt<2>(2)
    T_176315[1] := UInt<2>(3)
    wire T_176316 : UInt<2>[1]
    T_176316[0] := UInt<2>(3)
    wire T_176317 : UInt<3>[3]
    T_176317[0] := UInt<3>(0)
    T_176317[1] := UInt<3>(1)
    T_176317[2] := UInt<3>(2)
    wire T_176318 : UInt<2>[2]
    T_176318[0] := UInt<2>(0)
    T_176318[1] := UInt<2>(1)
    wire T_176319 : UInt<2>[3]
    T_176319[0] := UInt<2>(1)
    T_176319[1] := UInt<2>(2)
    T_176319[2] := UInt<2>(3)
    wire T_176320 : UInt<2>[2]
    T_176320[0] := UInt<2>(2)
    T_176320[1] := UInt<2>(3)
    wire T_176321 : UInt<2>[1]
    T_176321[0] := UInt<2>(3)
    wire T_176322 : UInt<3>[3]
    T_176322[0] := UInt<3>(0)
    T_176322[1] := UInt<3>(1)
    T_176322[2] := UInt<3>(2)
    wire T_176323 : UInt<0>[1]
    T_176323[0] := UInt<0>(0)
    wire T_176324 : UInt<2>[2]
    T_176324[0] := UInt<2>(1)
    T_176324[1] := UInt<2>(2)
    wire T_176325 : UInt<2>[2]
    T_176325[0] := UInt<2>(1)
    T_176325[1] := UInt<2>(2)
    wire T_176326 : UInt<2>[1]
    T_176326[0] := UInt<2>(2)
    wire T_176327 : UInt<3>[3]
    T_176327[0] := UInt<3>(0)
    T_176327[1] := UInt<3>(1)
    T_176327[2] := UInt<3>(2)
    wire T_176328 : UInt<2>[2]
    T_176328[0] := UInt<2>(0)
    T_176328[1] := UInt<2>(1)
    wire T_176329 : UInt<2>[3]
    T_176329[0] := UInt<2>(1)
    T_176329[1] := UInt<2>(2)
    T_176329[2] := UInt<2>(3)
    wire T_176330 : UInt<2>[2]
    T_176330[0] := UInt<2>(2)
    T_176330[1] := UInt<2>(3)
    wire T_176331 : UInt<2>[1]
    T_176331[0] := UInt<2>(3)
    wire T_176332 : UInt<3>[3]
    T_176332[0] := UInt<3>(0)
    T_176332[1] := UInt<3>(1)
    T_176332[2] := UInt<3>(2)
    wire T_176333 : UInt<2>[2]
    T_176333[0] := UInt<2>(0)
    T_176333[1] := UInt<2>(1)
    wire T_176334 : UInt<2>[3]
    T_176334[0] := UInt<2>(1)
    T_176334[1] := UInt<2>(2)
    T_176334[2] := UInt<2>(3)
    wire T_176335 : UInt<2>[2]
    T_176335[0] := UInt<2>(2)
    T_176335[1] := UInt<2>(3)
    wire T_176336 : UInt<2>[1]
    T_176336[0] := UInt<2>(3)
    wire T_176337 : UInt<3>[3]
    T_176337[0] := UInt<3>(0)
    T_176337[1] := UInt<3>(1)
    T_176337[2] := UInt<3>(2)
    wire T_176338 : UInt<0>[1]
    T_176338[0] := UInt<0>(0)
    wire T_176339 : UInt<2>[2]
    T_176339[0] := UInt<2>(1)
    T_176339[1] := UInt<2>(2)
    wire T_176340 : UInt<2>[2]
    T_176340[0] := UInt<2>(1)
    T_176340[1] := UInt<2>(2)
    wire T_176341 : UInt<2>[1]
    T_176341[0] := UInt<2>(2)
    data.write.valid := UInt<1>(0)
    data.resp.valid := UInt<1>(0)
    data.read.valid := UInt<1>(0)
    wb.resp.valid := UInt<1>(0)
    wb.req.valid := UInt<1>(0)
    outer.release.valid := UInt<1>(0)
    outer.probe.valid := UInt<1>(0)
    outer.grant.valid := UInt<1>(0)
    outer.acquire.valid := UInt<1>(0)
    inner.release.valid := UInt<1>(0)
    inner.probe.valid := UInt<1>(0)
    inner.finish.valid := UInt<1>(0)
    inner.grant.valid := UInt<1>(0)
    inner.acquire.valid := UInt<1>(0)
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    wire T_176342 : UInt<3>[3]
    T_176342[0] := UInt<3>(0)
    T_176342[1] := UInt<3>(1)
    T_176342[2] := UInt<3>(2)
    wire T_176343 : UInt<2>[2]
    T_176343[0] := UInt<2>(0)
    T_176343[1] := UInt<2>(1)
    wire T_176344 : UInt<2>[3]
    T_176344[0] := UInt<2>(1)
    T_176344[1] := UInt<2>(2)
    T_176344[2] := UInt<2>(3)
    wire T_176345 : UInt<2>[2]
    T_176345[0] := UInt<2>(2)
    T_176345[1] := UInt<2>(3)
    wire T_176346 : UInt<2>[1]
    T_176346[0] := UInt<2>(3)
    wire T_176347 : UInt<3>[3]
    T_176347[0] := UInt<3>(0)
    T_176347[1] := UInt<3>(1)
    T_176347[2] := UInt<3>(2)
    wire T_176348 : UInt<2>[2]
    T_176348[0] := UInt<2>(0)
    T_176348[1] := UInt<2>(1)
    wire T_176349 : UInt<2>[3]
    T_176349[0] := UInt<2>(1)
    T_176349[1] := UInt<2>(2)
    T_176349[2] := UInt<2>(3)
    wire T_176350 : UInt<2>[2]
    T_176350[0] := UInt<2>(2)
    T_176350[1] := UInt<2>(3)
    wire T_176351 : UInt<2>[1]
    T_176351[0] := UInt<2>(3)
    wire T_176352 : UInt<3>[3]
    T_176352[0] := UInt<3>(0)
    T_176352[1] := UInt<3>(1)
    T_176352[2] := UInt<3>(2)
    wire T_176353 : UInt<0>[1]
    T_176353[0] := UInt<0>(0)
    wire T_176354 : UInt<2>[2]
    T_176354[0] := UInt<2>(1)
    T_176354[1] := UInt<2>(2)
    wire T_176355 : UInt<2>[2]
    T_176355[0] := UInt<2>(1)
    T_176355[1] := UInt<2>(2)
    wire T_176356 : UInt<2>[1]
    T_176356[0] := UInt<2>(2)
    wire T_176357 : UInt<3>[3]
    T_176357[0] := UInt<3>(0)
    T_176357[1] := UInt<3>(1)
    T_176357[2] := UInt<3>(2)
    wire T_176358 : UInt<2>[2]
    T_176358[0] := UInt<2>(0)
    T_176358[1] := UInt<2>(1)
    wire T_176359 : UInt<2>[3]
    T_176359[0] := UInt<2>(1)
    T_176359[1] := UInt<2>(2)
    T_176359[2] := UInt<2>(3)
    wire T_176360 : UInt<2>[2]
    T_176360[0] := UInt<2>(2)
    T_176360[1] := UInt<2>(3)
    wire T_176361 : UInt<2>[1]
    T_176361[0] := UInt<2>(3)
    wire T_176362 : UInt<3>[3]
    T_176362[0] := UInt<3>(0)
    T_176362[1] := UInt<3>(1)
    T_176362[2] := UInt<3>(2)
    wire T_176363 : UInt<2>[2]
    T_176363[0] := UInt<2>(0)
    T_176363[1] := UInt<2>(1)
    wire T_176364 : UInt<2>[3]
    T_176364[0] := UInt<2>(1)
    T_176364[1] := UInt<2>(2)
    T_176364[2] := UInt<2>(3)
    wire T_176365 : UInt<2>[2]
    T_176365[0] := UInt<2>(2)
    T_176365[1] := UInt<2>(3)
    wire T_176366 : UInt<2>[1]
    T_176366[0] := UInt<2>(3)
    wire T_176367 : UInt<3>[3]
    T_176367[0] := UInt<3>(0)
    T_176367[1] := UInt<3>(1)
    T_176367[2] := UInt<3>(2)
    wire T_176368 : UInt<0>[1]
    T_176368[0] := UInt<0>(0)
    wire T_176369 : UInt<2>[2]
    T_176369[0] := UInt<2>(1)
    T_176369[1] := UInt<2>(2)
    wire T_176370 : UInt<2>[2]
    T_176370[0] := UInt<2>(1)
    T_176370[1] := UInt<2>(2)
    wire T_176371 : UInt<2>[1]
    T_176371[0] := UInt<2>(2)
    reg xact : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}
    wire T_176372 : UInt<128>[4]
    T_176372[0] := UInt<128>(0)
    T_176372[1] := UInt<128>(0)
    T_176372[2] := UInt<128>(0)
    T_176372[3] := UInt<128>(0)
    reg data_buffer : UInt<128>[4]
    onreset data_buffer := T_176372
    node xact_addr_block = cat(xact.tag, xact.idx)
    reg T_176373 : UInt<1>
    onreset T_176373 := UInt<1>(0)
    node T_176374 = and(inner.probe.ready, inner.probe.valid)
    node T_176375 = and(T_176374, UInt<1>(0))
    reg T_176376 : UInt<2>
    onreset T_176376 := UInt<2>(0)
    when T_176375 : 
      node T_176377 = eq(T_176376, UInt<2>(3))
      node T_176378 = and(UInt<1>(0), T_176377)
      node T_176379 = addw(T_176376, UInt<1>(1))
      wire T_176380 : UInt<2>
      T_176380 := T_176379
      when T_176378 : T_176380 := UInt<1>(0)
      T_176376 := T_176380
    node T_176381 = and(T_176375, T_176377)
    wire T_176382 : UInt<1>
    T_176382 := UInt<1>(0)
    when UInt<1>(0) : T_176382 := T_176376
    wire T_176383 : UInt<1>
    T_176383 := T_176374
    when UInt<1>(0) : T_176383 := T_176381
    node T_176384 = and(inner.release.ready, inner.release.valid)
    node T_176385 = eq(T_176261[0], inner.release.bits.r_type)
    node T_176386 = eq(T_176261[1], inner.release.bits.r_type)
    node T_176387 = eq(T_176261[2], inner.release.bits.r_type)
    node T_176388 = or(UInt<1>(0), T_176385)
    node T_176389 = or(T_176388, T_176386)
    node T_176390 = or(T_176389, T_176387)
    node T_176391 = and(UInt<1>(1), T_176390)
    node T_176392 = and(T_176384, T_176391)
    reg T_176393 : UInt<2>
    onreset T_176393 := UInt<2>(0)
    when T_176392 : 
      node T_176394 = eq(T_176393, UInt<2>(3))
      node T_176395 = and(UInt<1>(0), T_176394)
      node T_176396 = addw(T_176393, UInt<1>(1))
      wire T_176397 : UInt<2>
      T_176397 := T_176396
      when T_176395 : T_176397 := UInt<1>(0)
      T_176393 := T_176397
    node T_176398 = and(T_176392, T_176394)
    wire T_176399 : UInt<1>
    T_176399 := UInt<1>(0)
    when T_176391 : T_176399 := T_176393
    wire T_176400 : UInt<1>
    T_176400 := T_176384
    when T_176391 : T_176400 := T_176398
    node T_176401 = and(T_176383, UInt<1>(1))
    node T_176402 = subw(T_176373, UInt<1>(1))
    wire T_176403 : UInt<1>
    T_176403 := T_176402
    when T_176401 : T_176403 := T_176373
    node T_176404 = addw(T_176373, UInt<1>(1))
    wire T_176405 : UInt<1>
    T_176405 := T_176373
    when T_176401 : T_176405 := T_176404
    wire T_176406 : UInt<1>
    T_176406 := T_176405
    when T_176400 : T_176406 := T_176403
    T_176373 := T_176406
    node pending_irels = gt(T_176373, UInt<1>(0))
    reg T_176407 : UInt<1>
    onreset T_176407 := UInt<1>(0)
    node T_176408 = and(outer.release.ready, outer.release.valid)
    node T_176409 = eq(T_176307[0], outer.release.bits.r_type)
    node T_176410 = eq(T_176307[1], outer.release.bits.r_type)
    node T_176411 = eq(T_176307[2], outer.release.bits.r_type)
    node T_176412 = or(UInt<1>(0), T_176409)
    node T_176413 = or(T_176412, T_176410)
    node T_176414 = or(T_176413, T_176411)
    node T_176415 = and(UInt<1>(1), T_176414)
    node T_176416 = and(T_176408, T_176415)
    reg T_176417 : UInt<2>
    onreset T_176417 := UInt<2>(0)
    when T_176416 : 
      node T_176418 = eq(T_176417, UInt<2>(3))
      node T_176419 = and(UInt<1>(0), T_176418)
      node T_176420 = addw(T_176417, UInt<1>(1))
      wire T_176421 : UInt<2>
      T_176421 := T_176420
      when T_176419 : T_176421 := UInt<1>(0)
      T_176417 := T_176421
    node T_176422 = and(T_176416, T_176418)
    wire orel_data_idx : UInt<1>
    orel_data_idx := UInt<1>(0)
    when T_176415 : orel_data_idx := T_176417
    wire orel_data_done : UInt<1>
    orel_data_done := T_176408
    when T_176415 : orel_data_done := T_176422
    node T_176423 = and(outer.grant.ready, outer.grant.valid)
    wire T_176424 : UInt<3>[1]
    T_176424[0] := UInt<3>(5)
    node T_176425 = eq(T_176424[0], outer.grant.bits.g_type)
    node T_176426 = or(UInt<1>(0), T_176425)
    node T_176427 = eq(T_176288[0], outer.grant.bits.g_type)
    node T_176428 = or(UInt<1>(0), T_176427)
    wire T_176429 : UInt<1>
    T_176429 := T_176428
    when outer.grant.bits.is_builtin_type : T_176429 := T_176426
    node T_176430 = and(UInt<1>(1), T_176429)
    node T_176431 = and(T_176423, T_176430)
    reg T_176432 : UInt<2>
    onreset T_176432 := UInt<2>(0)
    when T_176431 : 
      node T_176433 = eq(T_176432, UInt<2>(3))
      node T_176434 = and(UInt<1>(0), T_176433)
      node T_176435 = addw(T_176432, UInt<1>(1))
      wire T_176436 : UInt<2>
      T_176436 := T_176435
      when T_176434 : T_176436 := UInt<1>(0)
      T_176432 := T_176436
    node T_176437 = and(T_176431, T_176433)
    wire ognt_data_idx : UInt<1>
    ognt_data_idx := UInt<1>(0)
    when T_176430 : ognt_data_idx := T_176432
    wire ognt_data_done : UInt<1>
    ognt_data_done := T_176423
    when T_176430 : ognt_data_done := T_176437
    node T_176438 = and(orel_data_done, UInt<1>(1))
    node T_176439 = subw(T_176407, UInt<1>(1))
    wire T_176440 : UInt<1>
    T_176440 := T_176439
    when T_176438 : T_176440 := T_176407
    node T_176441 = addw(T_176407, UInt<1>(1))
    wire T_176442 : UInt<1>
    T_176442 := T_176407
    when T_176438 : T_176442 := T_176441
    wire T_176443 : UInt<1>
    T_176443 := T_176442
    when ognt_data_done : T_176443 := T_176440
    T_176407 := T_176443
    node pending_ognt = gt(T_176407, UInt<1>(0))
    reg pending_iprbs : UInt<1>
    onreset pending_iprbs := UInt<1>(0)
    reg pending_reads : UInt<4>
    onreset pending_reads := UInt<4>(0)
    reg pending_resps : UInt<4>
    onreset pending_resps := UInt<4>(0)
    reg pending_orel_data : UInt<4>
    onreset pending_orel_data := UInt<4>(0)
    node T_176444 = eq(state, UInt<3>(0))
    wb.req.ready := T_176444
    node T_176445 = and(inner.probe.ready, inner.probe.valid)
    node T_176446 = not(T_176445)
    node T_176447 = dshl(UInt<1>(1), inner.probe.bits.client_id)
    node T_176448 = not(T_176447)
    node T_176449 = or(T_176446, T_176448)
    node T_176450 = and(pending_iprbs, T_176449)
    pending_iprbs := T_176450
    node T_176451 = bit(pending_iprbs, 0)
    wire T_176452 : UInt<1>[1]
    T_176452[0] := T_176451
    node T_176453 = eq(state, UInt<3>(1))
    node T_176454 = eq(pending_iprbs, UInt<1>(0))
    node T_176455 = eq(T_176454, UInt<1>(0))
    node T_176456 = and(T_176453, T_176455)
    inner.probe.valid := T_176456
    node T_176457 = eq(UInt<5>(17), UInt<5>(16))
    wire T_176458 : UInt<2>
    T_176458 := UInt<2>(2)
    when T_176457 : T_176458 := UInt<2>(1)
    node T_176459 = eq(UInt<5>(16), UInt<5>(16))
    wire T_176460 : UInt<2>
    T_176460 := T_176458
    when T_176459 : T_176460 := UInt<2>(0)
    wire T_176461 : UInt<3>[3]
    T_176461[0] := UInt<3>(0)
    T_176461[1] := UInt<3>(1)
    T_176461[2] := UInt<3>(2)
    wire T_176462 : UInt<2>[2]
    T_176462[0] := UInt<2>(0)
    T_176462[1] := UInt<2>(1)
    wire T_176463 : UInt<2>[3]
    T_176463[0] := UInt<2>(1)
    T_176463[1] := UInt<2>(2)
    T_176463[2] := UInt<2>(3)
    wire T_176464 : UInt<2>[2]
    T_176464[0] := UInt<2>(2)
    T_176464[1] := UInt<2>(3)
    wire T_176465 : UInt<2>[1]
    T_176465[0] := UInt<2>(3)
    wire T_176466 : UInt<3>[3]
    T_176466[0] := UInt<3>(0)
    T_176466[1] := UInt<3>(1)
    T_176466[2] := UInt<3>(2)
    wire T_176467 : UInt<2>[2]
    T_176467[0] := UInt<2>(0)
    T_176467[1] := UInt<2>(1)
    wire T_176468 : UInt<2>[3]
    T_176468[0] := UInt<2>(1)
    T_176468[1] := UInt<2>(2)
    T_176468[2] := UInt<2>(3)
    wire T_176469 : UInt<2>[2]
    T_176469[0] := UInt<2>(2)
    T_176469[1] := UInt<2>(3)
    wire T_176470 : UInt<2>[1]
    T_176470[0] := UInt<2>(3)
    wire T_176471 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}
    T_176471.client_id := UInt<1>(0)
    T_176471.p_type := T_176460
    T_176471.addr_block := xact_addr_block
    inner.probe.bits := T_176471
    node T_176472 = dshl(UInt<1>(1), inner.release.bits.client_id)
    node T_176473 = not(T_176472)
    node T_176474 = and(xact.coh.inner.sharers, T_176473)
    wire T_176475 : UInt<3>[3]
    T_176475[0] := UInt<3>(0)
    T_176475[1] := UInt<3>(1)
    T_176475[2] := UInt<3>(2)
    wire T_176476 : UInt<2>[2]
    T_176476[0] := UInt<2>(0)
    T_176476[1] := UInt<2>(1)
    wire T_176477 : UInt<2>[3]
    T_176477[0] := UInt<2>(1)
    T_176477[1] := UInt<2>(2)
    T_176477[2] := UInt<2>(3)
    wire T_176478 : UInt<2>[2]
    T_176478[0] := UInt<2>(2)
    T_176478[1] := UInt<2>(3)
    wire T_176479 : UInt<2>[1]
    T_176479[0] := UInt<2>(3)
    wire T_176480 : UInt<3>[3]
    T_176480[0] := UInt<3>(0)
    T_176480[1] := UInt<3>(1)
    T_176480[2] := UInt<3>(2)
    wire T_176481 : UInt<2>[2]
    T_176481[0] := UInt<2>(0)
    T_176481[1] := UInt<2>(1)
    wire T_176482 : UInt<2>[3]
    T_176482[0] := UInt<2>(1)
    T_176482[1] := UInt<2>(2)
    T_176482[2] := UInt<2>(3)
    wire T_176483 : UInt<2>[2]
    T_176483[0] := UInt<2>(2)
    T_176483[1] := UInt<2>(3)
    wire T_176484 : UInt<2>[1]
    T_176484[0] := UInt<2>(3)
    wire T_176485 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_176485.sharers := T_176474
    node T_176486 = eq(inner.release.bits.r_type, UInt<3>(0))
    node T_176487 = eq(inner.release.bits.r_type, UInt<3>(3))
    wire T_176488 : UInt<3>[3]
    T_176488[0] := UInt<3>(0)
    T_176488[1] := UInt<3>(1)
    T_176488[2] := UInt<3>(2)
    wire T_176489 : UInt<2>[2]
    T_176489[0] := UInt<2>(0)
    T_176489[1] := UInt<2>(1)
    wire T_176490 : UInt<2>[3]
    T_176490[0] := UInt<2>(1)
    T_176490[1] := UInt<2>(2)
    T_176490[2] := UInt<2>(3)
    wire T_176491 : UInt<2>[2]
    T_176491[0] := UInt<2>(2)
    T_176491[1] := UInt<2>(3)
    wire T_176492 : UInt<2>[1]
    T_176492[0] := UInt<2>(3)
    wire T_176493 : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    T_176493 := xact.coh.inner
    when T_176487 : T_176493 := T_176485
    wire T_176494 : UInt<3>[3]
    T_176494[0] := UInt<3>(0)
    T_176494[1] := UInt<3>(1)
    T_176494[2] := UInt<3>(2)
    wire T_176495 : UInt<2>[2]
    T_176495[0] := UInt<2>(0)
    T_176495[1] := UInt<2>(1)
    wire T_176496 : UInt<2>[3]
    T_176496[0] := UInt<2>(1)
    T_176496[1] := UInt<2>(2)
    T_176496[2] := UInt<2>(3)
    wire T_176497 : UInt<2>[2]
    T_176497[0] := UInt<2>(2)
    T_176497[1] := UInt<2>(3)
    wire T_176498 : UInt<2>[1]
    T_176498[0] := UInt<2>(3)
    wire inner_coh_on_irel : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}
    inner_coh_on_irel := T_176493
    when T_176486 : inner_coh_on_irel := T_176485
    node T_176499 = eq(UInt<5>(1), UInt<5>(1))
    node T_176500 = eq(UInt<5>(1), UInt<5>(7))
    node T_176501 = or(T_176499, T_176500)
    node T_176502 = eq(UInt<5>(1), UInt<5>(4))
    node T_176503 = or(UInt<1>(0), T_176502)
    node T_176504 = or(T_176501, T_176503)
    wire T_176505 : UInt<2>
    T_176505 := xact.coh.outer.state
    when T_176504 : T_176505 := UInt<2>(2)
    wire T_176506 : UInt<3>[3]
    T_176506[0] := UInt<3>(0)
    T_176506[1] := UInt<3>(1)
    T_176506[2] := UInt<3>(2)
    wire T_176507 : UInt<0>[1]
    T_176507[0] := UInt<0>(0)
    wire T_176508 : UInt<2>[2]
    T_176508[0] := UInt<2>(1)
    T_176508[1] := UInt<2>(2)
    wire T_176509 : UInt<2>[2]
    T_176509[0] := UInt<2>(1)
    T_176509[1] := UInt<2>(2)
    wire T_176510 : UInt<2>[1]
    T_176510[0] := UInt<2>(2)
    wire T_176511 : UInt<3>[3]
    T_176511[0] := UInt<3>(0)
    T_176511[1] := UInt<3>(1)
    T_176511[2] := UInt<3>(2)
    wire T_176512 : UInt<0>[1]
    T_176512[0] := UInt<0>(0)
    wire T_176513 : UInt<2>[2]
    T_176513[0] := UInt<2>(1)
    T_176513[1] := UInt<2>(2)
    wire T_176514 : UInt<2>[2]
    T_176514[0] := UInt<2>(1)
    T_176514[1] := UInt<2>(2)
    wire T_176515 : UInt<2>[1]
    T_176515[0] := UInt<2>(2)
    wire outer_coh_on_irel : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    outer_coh_on_irel.state := T_176505
    node T_176516 = eq(state, UInt<3>(1))
    node T_176517 = eq(state, UInt<3>(2))
    node T_176518 = or(T_176516, T_176517)
    inner.release.ready := T_176518
    
    node T_176519 = and(inner.release.ready, inner.release.valid)
    when T_176519 : 
      xact.coh.inner := inner_coh_on_irel
      accessor T_176520 = data_buffer[inner.release.bits.addr_beat]
      T_176520 := inner.release.bits.data
    
    
    node T_176521 = eq(inner.release.bits.addr_block, xact_addr_block)
    node T_176522 = and(inner.release.valid, T_176521)
    node T_176523 = eq(T_176261[0], inner.release.bits.r_type)
    node T_176524 = eq(T_176261[1], inner.release.bits.r_type)
    node T_176525 = eq(T_176261[2], inner.release.bits.r_type)
    node T_176526 = or(UInt<1>(0), T_176523)
    node T_176527 = or(T_176526, T_176524)
    node T_176528 = or(T_176527, T_176525)
    node T_176529 = and(T_176522, T_176528)
    when T_176529 : xact.coh.outer := outer_coh_on_irel
    node T_176530 = and(data.read.ready, data.read.valid)
    node T_176531 = subw(UInt<4>(0), UInt<3>(4))
    node T_176532 = not(T_176531)
    node T_176533 = dshl(UInt<1>(1), data.read.bits.addr_beat)
    node T_176534 = not(T_176533)
    node T_176535 = or(T_176532, T_176534)
    node T_176536 = and(pending_reads, T_176535)
    node T_176537 = and(inner.release.ready, inner.release.valid)
    node T_176538 = eq(T_176261[0], inner.release.bits.r_type)
    node T_176539 = eq(T_176261[1], inner.release.bits.r_type)
    node T_176540 = eq(T_176261[2], inner.release.bits.r_type)
    node T_176541 = or(UInt<1>(0), T_176538)
    node T_176542 = or(T_176541, T_176539)
    node T_176543 = or(T_176542, T_176540)
    node T_176544 = and(T_176537, T_176543)
    node T_176545 = subw(UInt<4>(0), UInt<3>(4))
    node T_176546 = not(T_176545)
    node T_176547 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_176548 = not(T_176547)
    node T_176549 = or(T_176546, T_176548)
    node T_176550 = and(T_176536, T_176549)
    pending_reads := T_176550
    node T_176551 = bit(pending_reads, 0)
    node T_176552 = bit(pending_reads, 1)
    node T_176553 = bit(pending_reads, 2)
    node T_176554 = bit(pending_reads, 3)
    wire T_176555 : UInt<1>[4]
    T_176555[0] := T_176551
    T_176555[1] := T_176552
    T_176555[2] := T_176553
    T_176555[3] := T_176554
    wire T_176556 : UInt<2>
    T_176556 := UInt<2>(3)
    when T_176555[2] : T_176556 := UInt<2>(2)
    wire T_176557 : UInt<2>
    T_176557 := T_176556
    when T_176555[1] : T_176557 := UInt<1>(1)
    wire curr_read_beat : UInt<2>
    curr_read_beat := T_176557
    when T_176555[0] : curr_read_beat := UInt<1>(0)
    node T_176558 = eq(state, UInt<3>(2))
    node T_176559 = eq(pending_reads, UInt<1>(0))
    node T_176560 = eq(T_176559, UInt<1>(0))
    node T_176561 = and(T_176558, T_176560)
    data.read.valid := T_176561
    data.read.bits.id := UInt<2>(3)
    data.read.bits.way_en := xact.way_en
    data.read.bits.addr_idx := xact.idx
    data.read.bits.addr_beat := curr_read_beat
    data.write.valid := UInt<1>(0)
    node T_176562 = subw(UInt<4>(0), UInt<3>(4))
    node T_176563 = not(T_176562)
    node T_176564 = dshl(UInt<1>(1), data.resp.bits.addr_beat)
    node T_176565 = not(T_176564)
    node T_176566 = or(T_176563, T_176565)
    node T_176567 = and(pending_resps, T_176566)
    node T_176568 = and(data.read.ready, data.read.valid)
    node T_176569 = subw(UInt<4>(0), UInt<3>(4))
    node T_176570 = dshl(UInt<1>(1), data.read.bits.addr_beat)
    node T_176571 = and(T_176569, T_176570)
    node T_176572 = or(T_176567, T_176571)
    pending_resps := T_176572
    when data.resp.valid : 
      accessor T_176573 = data_buffer[data.resp.bits.addr_beat]
      T_176573 := data.resp.bits.data
    node T_176574 = and(inner.release.ready, inner.release.valid)
    node T_176575 = eq(T_176261[0], inner.release.bits.r_type)
    node T_176576 = eq(T_176261[1], inner.release.bits.r_type)
    node T_176577 = eq(T_176261[2], inner.release.bits.r_type)
    node T_176578 = or(UInt<1>(0), T_176575)
    node T_176579 = or(T_176578, T_176576)
    node T_176580 = or(T_176579, T_176577)
    node T_176581 = and(T_176574, T_176580)
    node T_176582 = subw(UInt<4>(0), UInt<3>(4))
    node T_176583 = dshl(UInt<1>(1), inner.release.bits.addr_beat)
    node T_176584 = and(T_176582, T_176583)
    node T_176585 = or(pending_orel_data, T_176584)
    node T_176586 = subw(UInt<4>(0), UInt<3>(4))
    node T_176587 = dshl(UInt<1>(1), data.resp.bits.addr_beat)
    node T_176588 = and(T_176586, T_176587)
    node T_176589 = or(T_176585, T_176588)
    pending_orel_data := T_176589
    node T_176590 = eq(state, UInt<3>(2))
    node T_176591 = eq(T_176307[0], outer.release.bits.r_type)
    node T_176592 = eq(T_176307[1], outer.release.bits.r_type)
    node T_176593 = eq(T_176307[2], outer.release.bits.r_type)
    node T_176594 = or(UInt<1>(0), T_176591)
    node T_176595 = or(T_176594, T_176592)
    node T_176596 = or(T_176595, T_176593)
    node T_176597 = eq(T_176596, UInt<1>(0))
    node T_176598 = dshr(pending_orel_data, orel_data_idx)
    node T_176599 = bit(T_176598, 0)
    node T_176600 = or(T_176597, T_176599)
    node T_176601 = and(T_176590, T_176600)
    outer.release.valid := T_176601
    accessor T_176602 = data_buffer[orel_data_idx]
    node T_176603 = eq(T_176371[0], xact.coh.outer.state)
    node T_176604 = or(UInt<1>(0), T_176603)
    wire T_176605 : UInt<3>
    T_176605 := UInt<3>(3)
    when T_176604 : T_176605 := UInt<3>(0)
    wire T_176606 : UInt<3>
    T_176606 := UInt<3>(4)
    when T_176604 : T_176606 := UInt<3>(1)
    wire T_176607 : UInt<3>
    T_176607 := UInt<3>(5)
    when T_176604 : T_176607 := UInt<3>(2)
    node T_176608 = eq(UInt<5>(19), UInt<5>(16))
    wire T_176609 : UInt<3>
    T_176609 := UInt<3>(5)
    when T_176608 : T_176609 := T_176607
    node T_176610 = eq(UInt<5>(17), UInt<5>(16))
    wire T_176611 : UInt<3>
    T_176611 := T_176609
    when T_176610 : T_176611 := T_176606
    node T_176612 = eq(UInt<5>(16), UInt<5>(16))
    wire T_176613 : UInt<3>
    T_176613 := T_176611
    when T_176612 : T_176613 := T_176605
    wire T_176614 : UInt<3>[3]
    T_176614[0] := UInt<3>(0)
    T_176614[1] := UInt<3>(1)
    T_176614[2] := UInt<3>(2)
    wire T_176615 : UInt<0>[1]
    T_176615[0] := UInt<0>(0)
    wire T_176616 : UInt<2>[2]
    T_176616[0] := UInt<2>(1)
    T_176616[1] := UInt<2>(2)
    wire T_176617 : UInt<2>[2]
    T_176617[0] := UInt<2>(1)
    T_176617[1] := UInt<2>(2)
    wire T_176618 : UInt<2>[1]
    T_176618[0] := UInt<2>(2)
    wire T_176619 : UInt<3>[3]
    T_176619[0] := UInt<3>(0)
    T_176619[1] := UInt<3>(1)
    T_176619[2] := UInt<3>(2)
    wire T_176620 : UInt<0>[1]
    T_176620[0] := UInt<0>(0)
    wire T_176621 : UInt<2>[2]
    T_176621[0] := UInt<2>(1)
    T_176621[1] := UInt<2>(2)
    wire T_176622 : UInt<2>[2]
    T_176622[0] := UInt<2>(1)
    T_176622[1] := UInt<2>(2)
    wire T_176623 : UInt<2>[1]
    T_176623[0] := UInt<2>(2)
    wire T_176624 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}
    T_176624.r_type := T_176613
    T_176624.client_xact_id := UInt<2>(3)
    T_176624.addr_block := xact_addr_block
    T_176624.addr_beat := orel_data_idx
    T_176624.data := T_176602
    T_176624.voluntary := UInt<1>(1)
    outer.release.bits := T_176624
    node T_176625 = eq(state, UInt<3>(3))
    outer.grant.ready := T_176625
    node T_176626 = eq(state, UInt<3>(4))
    wb.resp.valid := T_176626
    wb.resp.bits.id := xact.id
    
    
    node T_176627 = eq(state, UInt<3>(0))
    node T_176628 = and(T_176627, wb.req.valid)
    when T_176628 : 
      xact := wb.req.bits
      node T_176629 = eq(wb.req.bits.coh.inner.sharers, UInt<1>(0))
      node T_176630 = eq(T_176629, UInt<1>(0))
      when T_176630 : 
        node T_176631 = not(incoherent[0])
        node T_176632 = and(wb.req.bits.coh.inner.sharers, T_176631)
        pending_iprbs := T_176632
      pending_reads := SInt<4>(-1)
      pending_resps := UInt<1>(0)
      pending_orel_data := UInt<1>(0)
      wire T_176633 : UInt<3>
      T_176633 := UInt<3>(2)
      when T_176630 : T_176633 := UInt<3>(1)
      state := T_176633
    
    
    node T_176634 = eq(state, UInt<3>(1))
    node T_176635 = eq(pending_iprbs, UInt<1>(0))
    node T_176636 = eq(T_176635, UInt<1>(0))
    node T_176637 = or(T_176636, pending_irels)
    node T_176638 = eq(T_176637, UInt<1>(0))
    node T_176639 = and(T_176634, T_176638)
    when T_176639 : 
      node T_176640 = eq(T_176371[0], xact.coh.outer.state)
      node T_176641 = or(UInt<1>(0), T_176640)
      wire T_176642 : UInt<3>
      T_176642 := UInt<3>(4)
      when T_176641 : T_176642 := UInt<3>(2)
      state := T_176642
    
    
    node T_176643 = eq(state, UInt<3>(2))
    node T_176644 = and(T_176643, orel_data_done)
    when T_176644 : 
      node T_176645 = eq(UInt<1>(0), UInt<1>(0))
      wire T_176646 : UInt<3>
      T_176646 := UInt<3>(4)
      when T_176645 : T_176646 := UInt<3>(3)
      state := T_176646
    
    
    node T_176647 = eq(state, UInt<3>(3))
    node T_176648 = and(T_176647, ognt_data_done)
    when T_176648 : state := UInt<3>(4)
    
    node T_176649 = eq(state, UInt<3>(4))
    when T_176649 : state := UInt<3>(0)
    node T_176650 = eq(inner.release.bits.addr_block, xact_addr_block)
    node T_176651 = eq(inner.release.bits.voluntary, UInt<1>(0))
    node T_176652 = and(T_176650, T_176651)
    node T_176653 = and(T_176652, inner.release.ready)
    has_release_match := T_176653
    has_acquire_match := UInt<1>(0)
    has_acquire_conflict := UInt<1>(0)
  module RRArbiter_97606 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, id : UInt<2>, idx : UInt<12>, way_en : UInt<8>}}
    output chosen : UInt<2>
    
    wire T_176654 : UInt<3>[3]
    T_176654[0] := UInt<3>(0)
    T_176654[1] := UInt<3>(1)
    T_176654[2] := UInt<3>(2)
    wire T_176655 : UInt<2>[2]
    T_176655[0] := UInt<2>(0)
    T_176655[1] := UInt<2>(1)
    wire T_176656 : UInt<2>[3]
    T_176656[0] := UInt<2>(1)
    T_176656[1] := UInt<2>(2)
    T_176656[2] := UInt<2>(3)
    wire T_176657 : UInt<2>[2]
    T_176657[0] := UInt<2>(2)
    T_176657[1] := UInt<2>(3)
    wire T_176658 : UInt<2>[1]
    T_176658[0] := UInt<2>(3)
    wire T_176659 : UInt<3>[3]
    T_176659[0] := UInt<3>(0)
    T_176659[1] := UInt<3>(1)
    T_176659[2] := UInt<3>(2)
    wire T_176660 : UInt<2>[2]
    T_176660[0] := UInt<2>(0)
    T_176660[1] := UInt<2>(1)
    wire T_176661 : UInt<2>[3]
    T_176661[0] := UInt<2>(1)
    T_176661[1] := UInt<2>(2)
    T_176661[2] := UInt<2>(3)
    wire T_176662 : UInt<2>[2]
    T_176662[0] := UInt<2>(2)
    T_176662[1] := UInt<2>(3)
    wire T_176663 : UInt<2>[1]
    T_176663[0] := UInt<2>(3)
    wire T_176664 : UInt<3>[3]
    T_176664[0] := UInt<3>(0)
    T_176664[1] := UInt<3>(1)
    T_176664[2] := UInt<3>(2)
    wire T_176665 : UInt<0>[1]
    T_176665[0] := UInt<0>(0)
    wire T_176666 : UInt<2>[2]
    T_176666[0] := UInt<2>(1)
    T_176666[1] := UInt<2>(2)
    wire T_176667 : UInt<2>[2]
    T_176667[0] := UInt<2>(1)
    T_176667[1] := UInt<2>(2)
    wire T_176668 : UInt<2>[1]
    T_176668[0] := UInt<2>(2)
    wire T_176669 : UInt<3>[3]
    T_176669[0] := UInt<3>(0)
    T_176669[1] := UInt<3>(1)
    T_176669[2] := UInt<3>(2)
    wire T_176670 : UInt<2>[2]
    T_176670[0] := UInt<2>(0)
    T_176670[1] := UInt<2>(1)
    wire T_176671 : UInt<2>[3]
    T_176671[0] := UInt<2>(1)
    T_176671[1] := UInt<2>(2)
    T_176671[2] := UInt<2>(3)
    wire T_176672 : UInt<2>[2]
    T_176672[0] := UInt<2>(2)
    T_176672[1] := UInt<2>(3)
    wire T_176673 : UInt<2>[1]
    T_176673[0] := UInt<2>(3)
    wire T_176674 : UInt<3>[3]
    T_176674[0] := UInt<3>(0)
    T_176674[1] := UInt<3>(1)
    T_176674[2] := UInt<3>(2)
    wire T_176675 : UInt<2>[2]
    T_176675[0] := UInt<2>(0)
    T_176675[1] := UInt<2>(1)
    wire T_176676 : UInt<2>[3]
    T_176676[0] := UInt<2>(1)
    T_176676[1] := UInt<2>(2)
    T_176676[2] := UInt<2>(3)
    wire T_176677 : UInt<2>[2]
    T_176677[0] := UInt<2>(2)
    T_176677[1] := UInt<2>(3)
    wire T_176678 : UInt<2>[1]
    T_176678[0] := UInt<2>(3)
    wire T_176679 : UInt<3>[3]
    T_176679[0] := UInt<3>(0)
    T_176679[1] := UInt<3>(1)
    T_176679[2] := UInt<3>(2)
    wire T_176680 : UInt<0>[1]
    T_176680[0] := UInt<0>(0)
    wire T_176681 : UInt<2>[2]
    T_176681[0] := UInt<2>(1)
    T_176681[1] := UInt<2>(2)
    wire T_176682 : UInt<2>[2]
    T_176682[0] := UInt<2>(1)
    T_176682[1] := UInt<2>(2)
    wire T_176683 : UInt<2>[1]
    T_176683[0] := UInt<2>(2)
    wire T_176684 : UInt<3>[3]
    T_176684[0] := UInt<3>(0)
    T_176684[1] := UInt<3>(1)
    T_176684[2] := UInt<3>(2)
    wire T_176685 : UInt<2>[2]
    T_176685[0] := UInt<2>(0)
    T_176685[1] := UInt<2>(1)
    wire T_176686 : UInt<2>[3]
    T_176686[0] := UInt<2>(1)
    T_176686[1] := UInt<2>(2)
    T_176686[2] := UInt<2>(3)
    wire T_176687 : UInt<2>[2]
    T_176687[0] := UInt<2>(2)
    T_176687[1] := UInt<2>(3)
    wire T_176688 : UInt<2>[1]
    T_176688[0] := UInt<2>(3)
    wire T_176689 : UInt<3>[3]
    T_176689[0] := UInt<3>(0)
    T_176689[1] := UInt<3>(1)
    T_176689[2] := UInt<3>(2)
    wire T_176690 : UInt<2>[2]
    T_176690[0] := UInt<2>(0)
    T_176690[1] := UInt<2>(1)
    wire T_176691 : UInt<2>[3]
    T_176691[0] := UInt<2>(1)
    T_176691[1] := UInt<2>(2)
    T_176691[2] := UInt<2>(3)
    wire T_176692 : UInt<2>[2]
    T_176692[0] := UInt<2>(2)
    T_176692[1] := UInt<2>(3)
    wire T_176693 : UInt<2>[1]
    T_176693[0] := UInt<2>(3)
    wire T_176694 : UInt<3>[3]
    T_176694[0] := UInt<3>(0)
    T_176694[1] := UInt<3>(1)
    T_176694[2] := UInt<3>(2)
    wire T_176695 : UInt<0>[1]
    T_176695[0] := UInt<0>(0)
    wire T_176696 : UInt<2>[2]
    T_176696[0] := UInt<2>(1)
    T_176696[1] := UInt<2>(2)
    wire T_176697 : UInt<2>[2]
    T_176697[0] := UInt<2>(1)
    T_176697[1] := UInt<2>(2)
    wire T_176698 : UInt<2>[1]
    T_176698[0] := UInt<2>(2)
    wire T_176699 : UInt<3>[3]
    T_176699[0] := UInt<3>(0)
    T_176699[1] := UInt<3>(1)
    T_176699[2] := UInt<3>(2)
    wire T_176700 : UInt<2>[2]
    T_176700[0] := UInt<2>(0)
    T_176700[1] := UInt<2>(1)
    wire T_176701 : UInt<2>[3]
    T_176701[0] := UInt<2>(1)
    T_176701[1] := UInt<2>(2)
    T_176701[2] := UInt<2>(3)
    wire T_176702 : UInt<2>[2]
    T_176702[0] := UInt<2>(2)
    T_176702[1] := UInt<2>(3)
    wire T_176703 : UInt<2>[1]
    T_176703[0] := UInt<2>(3)
    wire T_176704 : UInt<3>[3]
    T_176704[0] := UInt<3>(0)
    T_176704[1] := UInt<3>(1)
    T_176704[2] := UInt<3>(2)
    wire T_176705 : UInt<2>[2]
    T_176705[0] := UInt<2>(0)
    T_176705[1] := UInt<2>(1)
    wire T_176706 : UInt<2>[3]
    T_176706[0] := UInt<2>(1)
    T_176706[1] := UInt<2>(2)
    T_176706[2] := UInt<2>(3)
    wire T_176707 : UInt<2>[2]
    T_176707[0] := UInt<2>(2)
    T_176707[1] := UInt<2>(3)
    wire T_176708 : UInt<2>[1]
    T_176708[0] := UInt<2>(3)
    wire T_176709 : UInt<3>[3]
    T_176709[0] := UInt<3>(0)
    T_176709[1] := UInt<3>(1)
    T_176709[2] := UInt<3>(2)
    wire T_176710 : UInt<0>[1]
    T_176710[0] := UInt<0>(0)
    wire T_176711 : UInt<2>[2]
    T_176711[0] := UInt<2>(1)
    T_176711[1] := UInt<2>(2)
    wire T_176712 : UInt<2>[2]
    T_176712[0] := UInt<2>(1)
    T_176712[1] := UInt<2>(2)
    wire T_176713 : UInt<2>[1]
    T_176713[0] := UInt<2>(2)
    wire T_176714 : UInt<3>[3]
    T_176714[0] := UInt<3>(0)
    T_176714[1] := UInt<3>(1)
    T_176714[2] := UInt<3>(2)
    wire T_176715 : UInt<2>[2]
    T_176715[0] := UInt<2>(0)
    T_176715[1] := UInt<2>(1)
    wire T_176716 : UInt<2>[3]
    T_176716[0] := UInt<2>(1)
    T_176716[1] := UInt<2>(2)
    T_176716[2] := UInt<2>(3)
    wire T_176717 : UInt<2>[2]
    T_176717[0] := UInt<2>(2)
    T_176717[1] := UInt<2>(3)
    wire T_176718 : UInt<2>[1]
    T_176718[0] := UInt<2>(3)
    wire T_176719 : UInt<3>[3]
    T_176719[0] := UInt<3>(0)
    T_176719[1] := UInt<3>(1)
    T_176719[2] := UInt<3>(2)
    wire T_176720 : UInt<2>[2]
    T_176720[0] := UInt<2>(0)
    T_176720[1] := UInt<2>(1)
    wire T_176721 : UInt<2>[3]
    T_176721[0] := UInt<2>(1)
    T_176721[1] := UInt<2>(2)
    T_176721[2] := UInt<2>(3)
    wire T_176722 : UInt<2>[2]
    T_176722[0] := UInt<2>(2)
    T_176722[1] := UInt<2>(3)
    wire T_176723 : UInt<2>[1]
    T_176723[0] := UInt<2>(3)
    wire T_176724 : UInt<3>[3]
    T_176724[0] := UInt<3>(0)
    T_176724[1] := UInt<3>(1)
    T_176724[2] := UInt<3>(2)
    wire T_176725 : UInt<0>[1]
    T_176725[0] := UInt<0>(0)
    wire T_176726 : UInt<2>[2]
    T_176726[0] := UInt<2>(1)
    T_176726[1] := UInt<2>(2)
    wire T_176727 : UInt<2>[2]
    T_176727[0] := UInt<2>(1)
    T_176727[1] := UInt<2>(2)
    wire T_176728 : UInt<2>[1]
    T_176728[0] := UInt<2>(2)
    wire T_176729 : UInt<2>
    reg T_176730 : UInt<2>
    onreset T_176730 := UInt<2>(0)
    node T_176731 = gt(UInt<1>(0), T_176730)
    node T_176732 = and(in[0].valid, T_176731)
    node T_176733 = gt(UInt<1>(1), T_176730)
    node T_176734 = and(in[1].valid, T_176733)
    node T_176735 = gt(UInt<2>(2), T_176730)
    node T_176736 = and(in[2].valid, T_176735)
    node T_176737 = or(UInt<1>(0), T_176732)
    node T_176738 = eq(T_176737, UInt<1>(0))
    node T_176739 = or(UInt<1>(0), T_176732)
    node T_176740 = or(T_176739, T_176734)
    node T_176741 = eq(T_176740, UInt<1>(0))
    node T_176742 = or(UInt<1>(0), T_176732)
    node T_176743 = or(T_176742, T_176734)
    node T_176744 = or(T_176743, T_176736)
    node T_176745 = eq(T_176744, UInt<1>(0))
    node T_176746 = or(UInt<1>(0), T_176732)
    node T_176747 = or(T_176746, T_176734)
    node T_176748 = or(T_176747, T_176736)
    node T_176749 = or(T_176748, in[0].valid)
    node T_176750 = eq(T_176749, UInt<1>(0))
    node T_176751 = or(UInt<1>(0), T_176732)
    node T_176752 = or(T_176751, T_176734)
    node T_176753 = or(T_176752, T_176736)
    node T_176754 = or(T_176753, in[0].valid)
    node T_176755 = or(T_176754, in[1].valid)
    node T_176756 = eq(T_176755, UInt<1>(0))
    node T_176757 = gt(UInt<1>(0), T_176730)
    node T_176758 = and(UInt<1>(1), T_176757)
    node T_176759 = or(T_176758, T_176745)
    node T_176760 = gt(UInt<1>(1), T_176730)
    node T_176761 = and(T_176738, T_176760)
    node T_176762 = or(T_176761, T_176750)
    node T_176763 = gt(UInt<2>(2), T_176730)
    node T_176764 = and(T_176741, T_176763)
    node T_176765 = or(T_176764, T_176756)
    node T_176766 = eq(UInt<2>(2), UInt<1>(0))
    wire T_176767 : UInt<1>
    T_176767 := T_176759
    when UInt<1>(0) : T_176767 := T_176766
    node T_176768 = and(T_176767, out.ready)
    in[0].ready := T_176768
    node T_176769 = eq(UInt<2>(2), UInt<1>(1))
    wire T_176770 : UInt<1>
    T_176770 := T_176762
    when UInt<1>(0) : T_176770 := T_176769
    node T_176771 = and(T_176770, out.ready)
    in[1].ready := T_176771
    node T_176772 = eq(UInt<2>(2), UInt<2>(2))
    wire T_176773 : UInt<1>
    T_176773 := T_176765
    when UInt<1>(0) : T_176773 := T_176772
    node T_176774 = and(T_176773, out.ready)
    in[2].ready := T_176774
    wire T_176775 : UInt<3>[3]
    T_176775[0] := UInt<3>(0)
    T_176775[1] := UInt<3>(1)
    T_176775[2] := UInt<3>(2)
    wire T_176776 : UInt<2>[2]
    T_176776[0] := UInt<2>(0)
    T_176776[1] := UInt<2>(1)
    wire T_176777 : UInt<2>[3]
    T_176777[0] := UInt<2>(1)
    T_176777[1] := UInt<2>(2)
    T_176777[2] := UInt<2>(3)
    wire T_176778 : UInt<2>[2]
    T_176778[0] := UInt<2>(2)
    T_176778[1] := UInt<2>(3)
    wire T_176779 : UInt<2>[1]
    T_176779[0] := UInt<2>(3)
    wire T_176780 : UInt<3>[3]
    T_176780[0] := UInt<3>(0)
    T_176780[1] := UInt<3>(1)
    T_176780[2] := UInt<3>(2)
    wire T_176781 : UInt<2>[2]
    T_176781[0] := UInt<2>(0)
    T_176781[1] := UInt<2>(1)
    wire T_176782 : UInt<2>[3]
    T_176782[0] := UInt<2>(1)
    T_176782[1] := UInt<2>(2)
    T_176782[2] := UInt<2>(3)
    wire T_176783 : UInt<2>[2]
    T_176783[0] := UInt<2>(2)
    T_176783[1] := UInt<2>(3)
    wire T_176784 : UInt<2>[1]
    T_176784[0] := UInt<2>(3)
    wire T_176785 : UInt<3>[3]
    T_176785[0] := UInt<3>(0)
    T_176785[1] := UInt<3>(1)
    T_176785[2] := UInt<3>(2)
    wire T_176786 : UInt<0>[1]
    T_176786[0] := UInt<0>(0)
    wire T_176787 : UInt<2>[2]
    T_176787[0] := UInt<2>(1)
    T_176787[1] := UInt<2>(2)
    wire T_176788 : UInt<2>[2]
    T_176788[0] := UInt<2>(1)
    T_176788[1] := UInt<2>(2)
    wire T_176789 : UInt<2>[1]
    T_176789[0] := UInt<2>(2)
    accessor T_176790 = in[T_176729]
    out.valid := T_176790.valid
    wire T_176791 : UInt<3>[3]
    T_176791[0] := UInt<3>(0)
    T_176791[1] := UInt<3>(1)
    T_176791[2] := UInt<3>(2)
    wire T_176792 : UInt<2>[2]
    T_176792[0] := UInt<2>(0)
    T_176792[1] := UInt<2>(1)
    wire T_176793 : UInt<2>[3]
    T_176793[0] := UInt<2>(1)
    T_176793[1] := UInt<2>(2)
    T_176793[2] := UInt<2>(3)
    wire T_176794 : UInt<2>[2]
    T_176794[0] := UInt<2>(2)
    T_176794[1] := UInt<2>(3)
    wire T_176795 : UInt<2>[1]
    T_176795[0] := UInt<2>(3)
    wire T_176796 : UInt<3>[3]
    T_176796[0] := UInt<3>(0)
    T_176796[1] := UInt<3>(1)
    T_176796[2] := UInt<3>(2)
    wire T_176797 : UInt<2>[2]
    T_176797[0] := UInt<2>(0)
    T_176797[1] := UInt<2>(1)
    wire T_176798 : UInt<2>[3]
    T_176798[0] := UInt<2>(1)
    T_176798[1] := UInt<2>(2)
    T_176798[2] := UInt<2>(3)
    wire T_176799 : UInt<2>[2]
    T_176799[0] := UInt<2>(2)
    T_176799[1] := UInt<2>(3)
    wire T_176800 : UInt<2>[1]
    T_176800[0] := UInt<2>(3)
    wire T_176801 : UInt<3>[3]
    T_176801[0] := UInt<3>(0)
    T_176801[1] := UInt<3>(1)
    T_176801[2] := UInt<3>(2)
    wire T_176802 : UInt<0>[1]
    T_176802[0] := UInt<0>(0)
    wire T_176803 : UInt<2>[2]
    T_176803[0] := UInt<2>(1)
    T_176803[1] := UInt<2>(2)
    wire T_176804 : UInt<2>[2]
    T_176804[0] := UInt<2>(1)
    T_176804[1] := UInt<2>(2)
    wire T_176805 : UInt<2>[1]
    T_176805[0] := UInt<2>(2)
    accessor T_176806 = in[T_176729]
    out.bits := T_176806.bits
    chosen := T_176729
    wire T_176807 : UInt<2>
    T_176807 := UInt<2>(2)
    when in[1].valid : T_176807 := UInt<1>(1)
    wire T_176808 : UInt<2>
    T_176808 := T_176807
    when in[0].valid : T_176808 := UInt<1>(0)
    node T_176809 = gt(UInt<2>(2), T_176730)
    node T_176810 = and(in[2].valid, T_176809)
    wire T_176811 : UInt<2>
    T_176811 := T_176808
    when T_176810 : T_176811 := UInt<2>(2)
    node T_176812 = gt(UInt<1>(1), T_176730)
    node T_176813 = and(in[1].valid, T_176812)
    wire T_176814 : UInt<2>
    T_176814 := T_176811
    when T_176813 : T_176814 := UInt<1>(1)
    wire T_176815 : UInt<2>
    T_176815 := T_176814
    when UInt<1>(0) : T_176815 := UInt<2>(2)
    T_176729 := T_176815
    
    node T_176816 = and(out.ready, out.valid)
    when T_176816 : T_176730 := T_176729
  module LockingRRArbiter_98418 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[4]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}
    output chosen : UInt<2>
    
    wire T_176817 : UInt<3>[3]
    T_176817[0] := UInt<3>(0)
    T_176817[1] := UInt<3>(1)
    T_176817[2] := UInt<3>(2)
    wire T_176818 : UInt<2>[2]
    T_176818[0] := UInt<2>(0)
    T_176818[1] := UInt<2>(1)
    wire T_176819 : UInt<2>[3]
    T_176819[0] := UInt<2>(1)
    T_176819[1] := UInt<2>(2)
    T_176819[2] := UInt<2>(3)
    wire T_176820 : UInt<2>[2]
    T_176820[0] := UInt<2>(2)
    T_176820[1] := UInt<2>(3)
    wire T_176821 : UInt<2>[1]
    T_176821[0] := UInt<2>(3)
    wire T_176822 : UInt<3>[3]
    T_176822[0] := UInt<3>(0)
    T_176822[1] := UInt<3>(1)
    T_176822[2] := UInt<3>(2)
    wire T_176823 : UInt<2>[2]
    T_176823[0] := UInt<2>(0)
    T_176823[1] := UInt<2>(1)
    wire T_176824 : UInt<2>[3]
    T_176824[0] := UInt<2>(1)
    T_176824[1] := UInt<2>(2)
    T_176824[2] := UInt<2>(3)
    wire T_176825 : UInt<2>[2]
    T_176825[0] := UInt<2>(2)
    T_176825[1] := UInt<2>(3)
    wire T_176826 : UInt<2>[1]
    T_176826[0] := UInt<2>(3)
    wire T_176827 : UInt<3>[3]
    T_176827[0] := UInt<3>(0)
    T_176827[1] := UInt<3>(1)
    T_176827[2] := UInt<3>(2)
    wire T_176828 : UInt<2>[2]
    T_176828[0] := UInt<2>(0)
    T_176828[1] := UInt<2>(1)
    wire T_176829 : UInt<2>[3]
    T_176829[0] := UInt<2>(1)
    T_176829[1] := UInt<2>(2)
    T_176829[2] := UInt<2>(3)
    wire T_176830 : UInt<2>[2]
    T_176830[0] := UInt<2>(2)
    T_176830[1] := UInt<2>(3)
    wire T_176831 : UInt<2>[1]
    T_176831[0] := UInt<2>(3)
    wire T_176832 : UInt<3>[3]
    T_176832[0] := UInt<3>(0)
    T_176832[1] := UInt<3>(1)
    T_176832[2] := UInt<3>(2)
    wire T_176833 : UInt<2>[2]
    T_176833[0] := UInt<2>(0)
    T_176833[1] := UInt<2>(1)
    wire T_176834 : UInt<2>[3]
    T_176834[0] := UInt<2>(1)
    T_176834[1] := UInt<2>(2)
    T_176834[2] := UInt<2>(3)
    wire T_176835 : UInt<2>[2]
    T_176835[0] := UInt<2>(2)
    T_176835[1] := UInt<2>(3)
    wire T_176836 : UInt<2>[1]
    T_176836[0] := UInt<2>(3)
    wire T_176837 : UInt<3>[3]
    T_176837[0] := UInt<3>(0)
    T_176837[1] := UInt<3>(1)
    T_176837[2] := UInt<3>(2)
    wire T_176838 : UInt<2>[2]
    T_176838[0] := UInt<2>(0)
    T_176838[1] := UInt<2>(1)
    wire T_176839 : UInt<2>[3]
    T_176839[0] := UInt<2>(1)
    T_176839[1] := UInt<2>(2)
    T_176839[2] := UInt<2>(3)
    wire T_176840 : UInt<2>[2]
    T_176840[0] := UInt<2>(2)
    T_176840[1] := UInt<2>(3)
    wire T_176841 : UInt<2>[1]
    T_176841[0] := UInt<2>(3)
    wire T_176842 : UInt<3>[3]
    T_176842[0] := UInt<3>(0)
    T_176842[1] := UInt<3>(1)
    T_176842[2] := UInt<3>(2)
    wire T_176843 : UInt<2>[2]
    T_176843[0] := UInt<2>(0)
    T_176843[1] := UInt<2>(1)
    wire T_176844 : UInt<2>[3]
    T_176844[0] := UInt<2>(1)
    T_176844[1] := UInt<2>(2)
    T_176844[2] := UInt<2>(3)
    wire T_176845 : UInt<2>[2]
    T_176845[0] := UInt<2>(2)
    T_176845[1] := UInt<2>(3)
    wire T_176846 : UInt<2>[1]
    T_176846[0] := UInt<2>(3)
    reg T_176847 : UInt<1>
    onreset T_176847 := UInt<1>(0)
    reg T_176848 : UInt<2>
    onreset T_176848 := UInt<2>(3)
    wire T_176849 : UInt<2>
    reg last_grant : UInt<2>
    onreset last_grant := UInt<2>(0)
    node T_176850 = gt(UInt<1>(0), last_grant)
    node T_176851 = and(in[0].valid, T_176850)
    node T_176852 = gt(UInt<1>(1), last_grant)
    node T_176853 = and(in[1].valid, T_176852)
    node T_176854 = gt(UInt<2>(2), last_grant)
    node T_176855 = and(in[2].valid, T_176854)
    node T_176856 = gt(UInt<2>(3), last_grant)
    node T_176857 = and(in[3].valid, T_176856)
    node T_176858 = or(UInt<1>(0), T_176851)
    node T_176859 = eq(T_176858, UInt<1>(0))
    node T_176860 = or(UInt<1>(0), T_176851)
    node T_176861 = or(T_176860, T_176853)
    node T_176862 = eq(T_176861, UInt<1>(0))
    node T_176863 = or(UInt<1>(0), T_176851)
    node T_176864 = or(T_176863, T_176853)
    node T_176865 = or(T_176864, T_176855)
    node T_176866 = eq(T_176865, UInt<1>(0))
    node T_176867 = or(UInt<1>(0), T_176851)
    node T_176868 = or(T_176867, T_176853)
    node T_176869 = or(T_176868, T_176855)
    node T_176870 = or(T_176869, T_176857)
    node T_176871 = eq(T_176870, UInt<1>(0))
    node T_176872 = or(UInt<1>(0), T_176851)
    node T_176873 = or(T_176872, T_176853)
    node T_176874 = or(T_176873, T_176855)
    node T_176875 = or(T_176874, T_176857)
    node T_176876 = or(T_176875, in[0].valid)
    node T_176877 = eq(T_176876, UInt<1>(0))
    node T_176878 = or(UInt<1>(0), T_176851)
    node T_176879 = or(T_176878, T_176853)
    node T_176880 = or(T_176879, T_176855)
    node T_176881 = or(T_176880, T_176857)
    node T_176882 = or(T_176881, in[0].valid)
    node T_176883 = or(T_176882, in[1].valid)
    node T_176884 = eq(T_176883, UInt<1>(0))
    node T_176885 = or(UInt<1>(0), T_176851)
    node T_176886 = or(T_176885, T_176853)
    node T_176887 = or(T_176886, T_176855)
    node T_176888 = or(T_176887, T_176857)
    node T_176889 = or(T_176888, in[0].valid)
    node T_176890 = or(T_176889, in[1].valid)
    node T_176891 = or(T_176890, in[2].valid)
    node T_176892 = eq(T_176891, UInt<1>(0))
    node T_176893 = gt(UInt<1>(0), last_grant)
    node T_176894 = and(UInt<1>(1), T_176893)
    node T_176895 = or(T_176894, T_176871)
    node T_176896 = gt(UInt<1>(1), last_grant)
    node T_176897 = and(T_176859, T_176896)
    node T_176898 = or(T_176897, T_176877)
    node T_176899 = gt(UInt<2>(2), last_grant)
    node T_176900 = and(T_176862, T_176899)
    node T_176901 = or(T_176900, T_176884)
    node T_176902 = gt(UInt<2>(3), last_grant)
    node T_176903 = and(T_176866, T_176902)
    node T_176904 = or(T_176903, T_176892)
    node T_176905 = eq(T_176848, UInt<1>(0))
    wire T_176906 : UInt<1>
    T_176906 := T_176895
    when T_176847 : T_176906 := T_176905
    node T_176907 = and(T_176906, out.ready)
    in[0].ready := T_176907
    node T_176908 = eq(T_176848, UInt<1>(1))
    wire T_176909 : UInt<1>
    T_176909 := T_176898
    when T_176847 : T_176909 := T_176908
    node T_176910 = and(T_176909, out.ready)
    in[1].ready := T_176910
    node T_176911 = eq(T_176848, UInt<2>(2))
    wire T_176912 : UInt<1>
    T_176912 := T_176901
    when T_176847 : T_176912 := T_176911
    node T_176913 = and(T_176912, out.ready)
    in[2].ready := T_176913
    node T_176914 = eq(T_176848, UInt<2>(3))
    wire T_176915 : UInt<1>
    T_176915 := T_176904
    when T_176847 : T_176915 := T_176914
    node T_176916 = and(T_176915, out.ready)
    in[3].ready := T_176916
    wire T_176917 : UInt<3>[3]
    T_176917[0] := UInt<3>(0)
    T_176917[1] := UInt<3>(1)
    T_176917[2] := UInt<3>(2)
    wire T_176918 : UInt<2>[2]
    T_176918[0] := UInt<2>(0)
    T_176918[1] := UInt<2>(1)
    wire T_176919 : UInt<2>[3]
    T_176919[0] := UInt<2>(1)
    T_176919[1] := UInt<2>(2)
    T_176919[2] := UInt<2>(3)
    wire T_176920 : UInt<2>[2]
    T_176920[0] := UInt<2>(2)
    T_176920[1] := UInt<2>(3)
    wire T_176921 : UInt<2>[1]
    T_176921[0] := UInt<2>(3)
    accessor T_176922 = in[T_176849]
    out.valid := T_176922.valid
    wire T_176923 : UInt<3>[3]
    T_176923[0] := UInt<3>(0)
    T_176923[1] := UInt<3>(1)
    T_176923[2] := UInt<3>(2)
    wire T_176924 : UInt<2>[2]
    T_176924[0] := UInt<2>(0)
    T_176924[1] := UInt<2>(1)
    wire T_176925 : UInt<2>[3]
    T_176925[0] := UInt<2>(1)
    T_176925[1] := UInt<2>(2)
    T_176925[2] := UInt<2>(3)
    wire T_176926 : UInt<2>[2]
    T_176926[0] := UInt<2>(2)
    T_176926[1] := UInt<2>(3)
    wire T_176927 : UInt<2>[1]
    T_176927[0] := UInt<2>(3)
    accessor T_176928 = in[T_176849]
    out.bits := T_176928.bits
    chosen := T_176849
    reg T_176929 : UInt<2>
    onreset T_176929 := UInt<2>(0)
    node T_176930 = addw(T_176929, UInt<1>(1))
    
    node T_176931 = and(out.ready, out.valid)
    when T_176931 : 
      when UInt<1>(0) : 
        T_176929 := T_176930
        
        node T_176932 = eq(T_176847, UInt<1>(0))
        when T_176932 : 
          T_176847 := UInt<1>(1)
          node T_176933 = and(in[0].ready, in[0].valid)
          node T_176934 = and(in[1].ready, in[1].valid)
          node T_176935 = and(in[2].ready, in[2].valid)
          node T_176936 = and(in[3].ready, in[3].valid)
          wire T_176937 : UInt<1>[4]
          T_176937[0] := T_176933
          T_176937[1] := T_176934
          T_176937[2] := T_176935
          T_176937[3] := T_176936
          wire T_176938 : UInt<2>
          T_176938 := UInt<2>(3)
          when T_176937[2] : T_176938 := UInt<2>(2)
          wire T_176939 : UInt<2>
          T_176939 := T_176938
          when T_176937[1] : T_176939 := UInt<1>(1)
          wire T_176940 : UInt<2>
          T_176940 := T_176939
          when T_176937[0] : T_176940 := UInt<1>(0)
          T_176848 := T_176940
      
      node T_176941 = eq(T_176930, UInt<1>(0))
      when T_176941 : T_176847 := UInt<1>(0)
    wire T_176942 : UInt<2>
    T_176942 := UInt<2>(3)
    when in[2].valid : T_176942 := UInt<2>(2)
    wire T_176943 : UInt<2>
    T_176943 := T_176942
    when in[1].valid : T_176943 := UInt<1>(1)
    wire T_176944 : UInt<2>
    T_176944 := T_176943
    when in[0].valid : T_176944 := UInt<1>(0)
    node T_176945 = gt(UInt<2>(3), last_grant)
    node T_176946 = and(in[3].valid, T_176945)
    wire T_176947 : UInt<2>
    T_176947 := T_176944
    when T_176946 : T_176947 := UInt<2>(3)
    node T_176948 = gt(UInt<2>(2), last_grant)
    node T_176949 = and(in[2].valid, T_176948)
    wire T_176950 : UInt<2>
    T_176950 := T_176947
    when T_176949 : T_176950 := UInt<2>(2)
    node T_176951 = gt(UInt<1>(1), last_grant)
    node T_176952 = and(in[1].valid, T_176951)
    wire choose : UInt<2>
    choose := T_176950
    when T_176952 : choose := UInt<1>(1)
    wire T_176953 : UInt<2>
    T_176953 := choose
    when T_176847 : T_176953 := T_176848
    T_176849 := T_176953
    
    node T_176954 = and(out.ready, out.valid)
    when T_176954 : last_grant := T_176849
  module LockingRRArbiter_99026 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}
    output chosen : UInt<2>
    
    wire T_176955 : UInt<3>[3]
    T_176955[0] := UInt<3>(0)
    T_176955[1] := UInt<3>(1)
    T_176955[2] := UInt<3>(2)
    wire T_176956 : UInt<2>[2]
    T_176956[0] := UInt<2>(0)
    T_176956[1] := UInt<2>(1)
    wire T_176957 : UInt<2>[3]
    T_176957[0] := UInt<2>(1)
    T_176957[1] := UInt<2>(2)
    T_176957[2] := UInt<2>(3)
    wire T_176958 : UInt<2>[2]
    T_176958[0] := UInt<2>(2)
    T_176958[1] := UInt<2>(3)
    wire T_176959 : UInt<2>[1]
    T_176959[0] := UInt<2>(3)
    wire T_176960 : UInt<3>[3]
    T_176960[0] := UInt<3>(0)
    T_176960[1] := UInt<3>(1)
    T_176960[2] := UInt<3>(2)
    wire T_176961 : UInt<2>[2]
    T_176961[0] := UInt<2>(0)
    T_176961[1] := UInt<2>(1)
    wire T_176962 : UInt<2>[3]
    T_176962[0] := UInt<2>(1)
    T_176962[1] := UInt<2>(2)
    T_176962[2] := UInt<2>(3)
    wire T_176963 : UInt<2>[2]
    T_176963[0] := UInt<2>(2)
    T_176963[1] := UInt<2>(3)
    wire T_176964 : UInt<2>[1]
    T_176964[0] := UInt<2>(3)
    wire T_176965 : UInt<3>[3]
    T_176965[0] := UInt<3>(0)
    T_176965[1] := UInt<3>(1)
    T_176965[2] := UInt<3>(2)
    wire T_176966 : UInt<2>[2]
    T_176966[0] := UInt<2>(0)
    T_176966[1] := UInt<2>(1)
    wire T_176967 : UInt<2>[3]
    T_176967[0] := UInt<2>(1)
    T_176967[1] := UInt<2>(2)
    T_176967[2] := UInt<2>(3)
    wire T_176968 : UInt<2>[2]
    T_176968[0] := UInt<2>(2)
    T_176968[1] := UInt<2>(3)
    wire T_176969 : UInt<2>[1]
    T_176969[0] := UInt<2>(3)
    wire T_176970 : UInt<3>[3]
    T_176970[0] := UInt<3>(0)
    T_176970[1] := UInt<3>(1)
    T_176970[2] := UInt<3>(2)
    wire T_176971 : UInt<2>[2]
    T_176971[0] := UInt<2>(0)
    T_176971[1] := UInt<2>(1)
    wire T_176972 : UInt<2>[3]
    T_176972[0] := UInt<2>(1)
    T_176972[1] := UInt<2>(2)
    T_176972[2] := UInt<2>(3)
    wire T_176973 : UInt<2>[2]
    T_176973[0] := UInt<2>(2)
    T_176973[1] := UInt<2>(3)
    wire T_176974 : UInt<2>[1]
    T_176974[0] := UInt<2>(3)
    wire T_176975 : UInt<3>[3]
    T_176975[0] := UInt<3>(0)
    T_176975[1] := UInt<3>(1)
    T_176975[2] := UInt<3>(2)
    wire T_176976 : UInt<2>[2]
    T_176976[0] := UInt<2>(0)
    T_176976[1] := UInt<2>(1)
    wire T_176977 : UInt<2>[3]
    T_176977[0] := UInt<2>(1)
    T_176977[1] := UInt<2>(2)
    T_176977[2] := UInt<2>(3)
    wire T_176978 : UInt<2>[2]
    T_176978[0] := UInt<2>(2)
    T_176978[1] := UInt<2>(3)
    wire T_176979 : UInt<2>[1]
    T_176979[0] := UInt<2>(3)
    reg T_176980 : UInt<1>
    onreset T_176980 := UInt<1>(0)
    reg T_176981 : UInt<2>
    onreset T_176981 := UInt<2>(2)
    wire T_176982 : UInt<2>
    reg last_grant : UInt<2>
    onreset last_grant := UInt<2>(0)
    node T_176983 = gt(UInt<1>(0), last_grant)
    node T_176984 = and(in[0].valid, T_176983)
    node T_176985 = gt(UInt<1>(1), last_grant)
    node T_176986 = and(in[1].valid, T_176985)
    node T_176987 = gt(UInt<2>(2), last_grant)
    node T_176988 = and(in[2].valid, T_176987)
    node T_176989 = or(UInt<1>(0), T_176984)
    node T_176990 = eq(T_176989, UInt<1>(0))
    node T_176991 = or(UInt<1>(0), T_176984)
    node T_176992 = or(T_176991, T_176986)
    node T_176993 = eq(T_176992, UInt<1>(0))
    node T_176994 = or(UInt<1>(0), T_176984)
    node T_176995 = or(T_176994, T_176986)
    node T_176996 = or(T_176995, T_176988)
    node T_176997 = eq(T_176996, UInt<1>(0))
    node T_176998 = or(UInt<1>(0), T_176984)
    node T_176999 = or(T_176998, T_176986)
    node T_177000 = or(T_176999, T_176988)
    node T_177001 = or(T_177000, in[0].valid)
    node T_177002 = eq(T_177001, UInt<1>(0))
    node T_177003 = or(UInt<1>(0), T_176984)
    node T_177004 = or(T_177003, T_176986)
    node T_177005 = or(T_177004, T_176988)
    node T_177006 = or(T_177005, in[0].valid)
    node T_177007 = or(T_177006, in[1].valid)
    node T_177008 = eq(T_177007, UInt<1>(0))
    node T_177009 = gt(UInt<1>(0), last_grant)
    node T_177010 = and(UInt<1>(1), T_177009)
    node T_177011 = or(T_177010, T_176997)
    node T_177012 = gt(UInt<1>(1), last_grant)
    node T_177013 = and(T_176990, T_177012)
    node T_177014 = or(T_177013, T_177002)
    node T_177015 = gt(UInt<2>(2), last_grant)
    node T_177016 = and(T_176993, T_177015)
    node T_177017 = or(T_177016, T_177008)
    node T_177018 = eq(T_176981, UInt<1>(0))
    wire T_177019 : UInt<1>
    T_177019 := T_177011
    when T_176980 : T_177019 := T_177018
    node T_177020 = and(T_177019, out.ready)
    in[0].ready := T_177020
    node T_177021 = eq(T_176981, UInt<1>(1))
    wire T_177022 : UInt<1>
    T_177022 := T_177014
    when T_176980 : T_177022 := T_177021
    node T_177023 = and(T_177022, out.ready)
    in[1].ready := T_177023
    node T_177024 = eq(T_176981, UInt<2>(2))
    wire T_177025 : UInt<1>
    T_177025 := T_177017
    when T_176980 : T_177025 := T_177024
    node T_177026 = and(T_177025, out.ready)
    in[2].ready := T_177026
    wire T_177027 : UInt<3>[3]
    T_177027[0] := UInt<3>(0)
    T_177027[1] := UInt<3>(1)
    T_177027[2] := UInt<3>(2)
    wire T_177028 : UInt<2>[2]
    T_177028[0] := UInt<2>(0)
    T_177028[1] := UInt<2>(1)
    wire T_177029 : UInt<2>[3]
    T_177029[0] := UInt<2>(1)
    T_177029[1] := UInt<2>(2)
    T_177029[2] := UInt<2>(3)
    wire T_177030 : UInt<2>[2]
    T_177030[0] := UInt<2>(2)
    T_177030[1] := UInt<2>(3)
    wire T_177031 : UInt<2>[1]
    T_177031[0] := UInt<2>(3)
    accessor T_177032 = in[T_176982]
    out.valid := T_177032.valid
    wire T_177033 : UInt<3>[3]
    T_177033[0] := UInt<3>(0)
    T_177033[1] := UInt<3>(1)
    T_177033[2] := UInt<3>(2)
    wire T_177034 : UInt<2>[2]
    T_177034[0] := UInt<2>(0)
    T_177034[1] := UInt<2>(1)
    wire T_177035 : UInt<2>[3]
    T_177035[0] := UInt<2>(1)
    T_177035[1] := UInt<2>(2)
    T_177035[2] := UInt<2>(3)
    wire T_177036 : UInt<2>[2]
    T_177036[0] := UInt<2>(2)
    T_177036[1] := UInt<2>(3)
    wire T_177037 : UInt<2>[1]
    T_177037[0] := UInt<2>(3)
    accessor T_177038 = in[T_176982]
    out.bits := T_177038.bits
    chosen := T_176982
    reg T_177039 : UInt<2>
    onreset T_177039 := UInt<2>(0)
    node T_177040 = addw(T_177039, UInt<1>(1))
    
    node T_177041 = and(out.ready, out.valid)
    when T_177041 : 
      
      
      wire T_177042 : UInt<3>[1]
      T_177042[0] := UInt<3>(5)
      node T_177043 = eq(T_177042[0], out.bits.g_type)
      node T_177044 = or(UInt<1>(0), T_177043)
      node T_177045 = eq(T_176976[0], out.bits.g_type)
      node T_177046 = eq(T_176976[1], out.bits.g_type)
      node T_177047 = or(UInt<1>(0), T_177045)
      node T_177048 = or(T_177047, T_177046)
      wire T_177049 : UInt<1>
      T_177049 := T_177048
      when out.bits.is_builtin_type : T_177049 := T_177044
      node T_177050 = and(UInt<1>(1), T_177049)
      when T_177050 : 
        T_177039 := T_177040
        
        node T_177051 = eq(T_176980, UInt<1>(0))
        when T_177051 : 
          T_176980 := UInt<1>(1)
          node T_177052 = and(in[0].ready, in[0].valid)
          node T_177053 = and(in[1].ready, in[1].valid)
          node T_177054 = and(in[2].ready, in[2].valid)
          wire T_177055 : UInt<1>[3]
          T_177055[0] := T_177052
          T_177055[1] := T_177053
          T_177055[2] := T_177054
          wire T_177056 : UInt<2>
          T_177056 := UInt<2>(2)
          when T_177055[1] : T_177056 := UInt<1>(1)
          wire T_177057 : UInt<2>
          T_177057 := T_177056
          when T_177055[0] : T_177057 := UInt<1>(0)
          T_176981 := T_177057
      
      node T_177058 = eq(T_177040, UInt<1>(0))
      when T_177058 : T_176980 := UInt<1>(0)
    wire T_177059 : UInt<2>
    T_177059 := UInt<2>(2)
    when in[1].valid : T_177059 := UInt<1>(1)
    wire T_177060 : UInt<2>
    T_177060 := T_177059
    when in[0].valid : T_177060 := UInt<1>(0)
    node T_177061 = gt(UInt<2>(2), last_grant)
    node T_177062 = and(in[2].valid, T_177061)
    wire T_177063 : UInt<2>
    T_177063 := T_177060
    when T_177062 : T_177063 := UInt<2>(2)
    node T_177064 = gt(UInt<1>(1), last_grant)
    node T_177065 = and(in[1].valid, T_177064)
    wire choose : UInt<2>
    choose := T_177063
    when T_177065 : choose := UInt<1>(1)
    wire T_177066 : UInt<2>
    T_177066 := choose
    when T_176980 : T_177066 := T_176981
    T_176982 := T_177066
    
    node T_177067 = and(out.ready, out.valid)
    when T_177067 : last_grant := T_176982
  module LockingRRArbiter_104277 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[4]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    output chosen : UInt<2>
    
    wire T_177068 : UInt<3>[3]
    T_177068[0] := UInt<3>(0)
    T_177068[1] := UInt<3>(1)
    T_177068[2] := UInt<3>(2)
    wire T_177069 : UInt<0>[1]
    T_177069[0] := UInt<0>(0)
    wire T_177070 : UInt<2>[2]
    T_177070[0] := UInt<2>(1)
    T_177070[1] := UInt<2>(2)
    wire T_177071 : UInt<2>[2]
    T_177071[0] := UInt<2>(1)
    T_177071[1] := UInt<2>(2)
    wire T_177072 : UInt<2>[1]
    T_177072[0] := UInt<2>(2)
    wire T_177073 : UInt<3>[3]
    T_177073[0] := UInt<3>(0)
    T_177073[1] := UInt<3>(1)
    T_177073[2] := UInt<3>(2)
    wire T_177074 : UInt<0>[1]
    T_177074[0] := UInt<0>(0)
    wire T_177075 : UInt<2>[2]
    T_177075[0] := UInt<2>(1)
    T_177075[1] := UInt<2>(2)
    wire T_177076 : UInt<2>[2]
    T_177076[0] := UInt<2>(1)
    T_177076[1] := UInt<2>(2)
    wire T_177077 : UInt<2>[1]
    T_177077[0] := UInt<2>(2)
    wire T_177078 : UInt<3>[3]
    T_177078[0] := UInt<3>(0)
    T_177078[1] := UInt<3>(1)
    T_177078[2] := UInt<3>(2)
    wire T_177079 : UInt<0>[1]
    T_177079[0] := UInt<0>(0)
    wire T_177080 : UInt<2>[2]
    T_177080[0] := UInt<2>(1)
    T_177080[1] := UInt<2>(2)
    wire T_177081 : UInt<2>[2]
    T_177081[0] := UInt<2>(1)
    T_177081[1] := UInt<2>(2)
    wire T_177082 : UInt<2>[1]
    T_177082[0] := UInt<2>(2)
    wire T_177083 : UInt<3>[3]
    T_177083[0] := UInt<3>(0)
    T_177083[1] := UInt<3>(1)
    T_177083[2] := UInt<3>(2)
    wire T_177084 : UInt<0>[1]
    T_177084[0] := UInt<0>(0)
    wire T_177085 : UInt<2>[2]
    T_177085[0] := UInt<2>(1)
    T_177085[1] := UInt<2>(2)
    wire T_177086 : UInt<2>[2]
    T_177086[0] := UInt<2>(1)
    T_177086[1] := UInt<2>(2)
    wire T_177087 : UInt<2>[1]
    T_177087[0] := UInt<2>(2)
    wire T_177088 : UInt<3>[3]
    T_177088[0] := UInt<3>(0)
    T_177088[1] := UInt<3>(1)
    T_177088[2] := UInt<3>(2)
    wire T_177089 : UInt<0>[1]
    T_177089[0] := UInt<0>(0)
    wire T_177090 : UInt<2>[2]
    T_177090[0] := UInt<2>(1)
    T_177090[1] := UInt<2>(2)
    wire T_177091 : UInt<2>[2]
    T_177091[0] := UInt<2>(1)
    T_177091[1] := UInt<2>(2)
    wire T_177092 : UInt<2>[1]
    T_177092[0] := UInt<2>(2)
    wire T_177093 : UInt<3>[3]
    T_177093[0] := UInt<3>(0)
    T_177093[1] := UInt<3>(1)
    T_177093[2] := UInt<3>(2)
    wire T_177094 : UInt<0>[1]
    T_177094[0] := UInt<0>(0)
    wire T_177095 : UInt<2>[2]
    T_177095[0] := UInt<2>(1)
    T_177095[1] := UInt<2>(2)
    wire T_177096 : UInt<2>[2]
    T_177096[0] := UInt<2>(1)
    T_177096[1] := UInt<2>(2)
    wire T_177097 : UInt<2>[1]
    T_177097[0] := UInt<2>(2)
    reg T_177098 : UInt<1>
    onreset T_177098 := UInt<1>(0)
    reg T_177099 : UInt<2>
    onreset T_177099 := UInt<2>(3)
    wire T_177100 : UInt<2>
    reg last_grant : UInt<2>
    onreset last_grant := UInt<2>(0)
    node T_177101 = gt(UInt<1>(0), last_grant)
    node T_177102 = and(in[0].valid, T_177101)
    node T_177103 = gt(UInt<1>(1), last_grant)
    node T_177104 = and(in[1].valid, T_177103)
    node T_177105 = gt(UInt<2>(2), last_grant)
    node T_177106 = and(in[2].valid, T_177105)
    node T_177107 = gt(UInt<2>(3), last_grant)
    node T_177108 = and(in[3].valid, T_177107)
    node T_177109 = or(UInt<1>(0), T_177102)
    node T_177110 = eq(T_177109, UInt<1>(0))
    node T_177111 = or(UInt<1>(0), T_177102)
    node T_177112 = or(T_177111, T_177104)
    node T_177113 = eq(T_177112, UInt<1>(0))
    node T_177114 = or(UInt<1>(0), T_177102)
    node T_177115 = or(T_177114, T_177104)
    node T_177116 = or(T_177115, T_177106)
    node T_177117 = eq(T_177116, UInt<1>(0))
    node T_177118 = or(UInt<1>(0), T_177102)
    node T_177119 = or(T_177118, T_177104)
    node T_177120 = or(T_177119, T_177106)
    node T_177121 = or(T_177120, T_177108)
    node T_177122 = eq(T_177121, UInt<1>(0))
    node T_177123 = or(UInt<1>(0), T_177102)
    node T_177124 = or(T_177123, T_177104)
    node T_177125 = or(T_177124, T_177106)
    node T_177126 = or(T_177125, T_177108)
    node T_177127 = or(T_177126, in[0].valid)
    node T_177128 = eq(T_177127, UInt<1>(0))
    node T_177129 = or(UInt<1>(0), T_177102)
    node T_177130 = or(T_177129, T_177104)
    node T_177131 = or(T_177130, T_177106)
    node T_177132 = or(T_177131, T_177108)
    node T_177133 = or(T_177132, in[0].valid)
    node T_177134 = or(T_177133, in[1].valid)
    node T_177135 = eq(T_177134, UInt<1>(0))
    node T_177136 = or(UInt<1>(0), T_177102)
    node T_177137 = or(T_177136, T_177104)
    node T_177138 = or(T_177137, T_177106)
    node T_177139 = or(T_177138, T_177108)
    node T_177140 = or(T_177139, in[0].valid)
    node T_177141 = or(T_177140, in[1].valid)
    node T_177142 = or(T_177141, in[2].valid)
    node T_177143 = eq(T_177142, UInt<1>(0))
    node T_177144 = gt(UInt<1>(0), last_grant)
    node T_177145 = and(UInt<1>(1), T_177144)
    node T_177146 = or(T_177145, T_177122)
    node T_177147 = gt(UInt<1>(1), last_grant)
    node T_177148 = and(T_177110, T_177147)
    node T_177149 = or(T_177148, T_177128)
    node T_177150 = gt(UInt<2>(2), last_grant)
    node T_177151 = and(T_177113, T_177150)
    node T_177152 = or(T_177151, T_177135)
    node T_177153 = gt(UInt<2>(3), last_grant)
    node T_177154 = and(T_177117, T_177153)
    node T_177155 = or(T_177154, T_177143)
    node T_177156 = eq(T_177099, UInt<1>(0))
    wire T_177157 : UInt<1>
    T_177157 := T_177146
    when T_177098 : T_177157 := T_177156
    node T_177158 = and(T_177157, out.ready)
    in[0].ready := T_177158
    node T_177159 = eq(T_177099, UInt<1>(1))
    wire T_177160 : UInt<1>
    T_177160 := T_177149
    when T_177098 : T_177160 := T_177159
    node T_177161 = and(T_177160, out.ready)
    in[1].ready := T_177161
    node T_177162 = eq(T_177099, UInt<2>(2))
    wire T_177163 : UInt<1>
    T_177163 := T_177152
    when T_177098 : T_177163 := T_177162
    node T_177164 = and(T_177163, out.ready)
    in[2].ready := T_177164
    node T_177165 = eq(T_177099, UInt<2>(3))
    wire T_177166 : UInt<1>
    T_177166 := T_177155
    when T_177098 : T_177166 := T_177165
    node T_177167 = and(T_177166, out.ready)
    in[3].ready := T_177167
    wire T_177168 : UInt<3>[3]
    T_177168[0] := UInt<3>(0)
    T_177168[1] := UInt<3>(1)
    T_177168[2] := UInt<3>(2)
    wire T_177169 : UInt<0>[1]
    T_177169[0] := UInt<0>(0)
    wire T_177170 : UInt<2>[2]
    T_177170[0] := UInt<2>(1)
    T_177170[1] := UInt<2>(2)
    wire T_177171 : UInt<2>[2]
    T_177171[0] := UInt<2>(1)
    T_177171[1] := UInt<2>(2)
    wire T_177172 : UInt<2>[1]
    T_177172[0] := UInt<2>(2)
    accessor T_177173 = in[T_177100]
    out.valid := T_177173.valid
    wire T_177174 : UInt<3>[3]
    T_177174[0] := UInt<3>(0)
    T_177174[1] := UInt<3>(1)
    T_177174[2] := UInt<3>(2)
    wire T_177175 : UInt<0>[1]
    T_177175[0] := UInt<0>(0)
    wire T_177176 : UInt<2>[2]
    T_177176[0] := UInt<2>(1)
    T_177176[1] := UInt<2>(2)
    wire T_177177 : UInt<2>[2]
    T_177177[0] := UInt<2>(1)
    T_177177[1] := UInt<2>(2)
    wire T_177178 : UInt<2>[1]
    T_177178[0] := UInt<2>(2)
    accessor T_177179 = in[T_177100]
    out.bits := T_177179.bits
    chosen := T_177100
    reg T_177180 : UInt<2>
    onreset T_177180 := UInt<2>(0)
    node T_177181 = addw(T_177180, UInt<1>(1))
    
    node T_177182 = and(out.ready, out.valid)
    when T_177182 : 
      
      
      node T_177183 = and(UInt<1>(1), out.bits.is_builtin_type)
      wire T_177184 : UInt<3>[1]
      T_177184[0] := UInt<3>(3)
      node T_177185 = eq(T_177184[0], out.bits.a_type)
      node T_177186 = or(UInt<1>(0), T_177185)
      node T_177187 = and(T_177183, T_177186)
      when T_177187 : 
        T_177180 := T_177181
        
        node T_177188 = eq(T_177098, UInt<1>(0))
        when T_177188 : 
          T_177098 := UInt<1>(1)
          node T_177189 = and(in[0].ready, in[0].valid)
          node T_177190 = and(in[1].ready, in[1].valid)
          node T_177191 = and(in[2].ready, in[2].valid)
          node T_177192 = and(in[3].ready, in[3].valid)
          wire T_177193 : UInt<1>[4]
          T_177193[0] := T_177189
          T_177193[1] := T_177190
          T_177193[2] := T_177191
          T_177193[3] := T_177192
          wire T_177194 : UInt<2>
          T_177194 := UInt<2>(3)
          when T_177193[2] : T_177194 := UInt<2>(2)
          wire T_177195 : UInt<2>
          T_177195 := T_177194
          when T_177193[1] : T_177195 := UInt<1>(1)
          wire T_177196 : UInt<2>
          T_177196 := T_177195
          when T_177193[0] : T_177196 := UInt<1>(0)
          T_177099 := T_177196
      
      node T_177197 = eq(T_177181, UInt<1>(0))
      when T_177197 : T_177098 := UInt<1>(0)
    wire T_177198 : UInt<2>
    T_177198 := UInt<2>(3)
    when in[2].valid : T_177198 := UInt<2>(2)
    wire T_177199 : UInt<2>
    T_177199 := T_177198
    when in[1].valid : T_177199 := UInt<1>(1)
    wire T_177200 : UInt<2>
    T_177200 := T_177199
    when in[0].valid : T_177200 := UInt<1>(0)
    node T_177201 = gt(UInt<2>(3), last_grant)
    node T_177202 = and(in[3].valid, T_177201)
    wire T_177203 : UInt<2>
    T_177203 := T_177200
    when T_177202 : T_177203 := UInt<2>(3)
    node T_177204 = gt(UInt<2>(2), last_grant)
    node T_177205 = and(in[2].valid, T_177204)
    wire T_177206 : UInt<2>
    T_177206 := T_177203
    when T_177205 : T_177206 := UInt<2>(2)
    node T_177207 = gt(UInt<1>(1), last_grant)
    node T_177208 = and(in[1].valid, T_177207)
    wire choose : UInt<2>
    choose := T_177206
    when T_177208 : choose := UInt<1>(1)
    wire T_177209 : UInt<2>
    T_177209 := choose
    when T_177098 : T_177209 := T_177099
    T_177100 := T_177209
    
    node T_177210 = and(out.ready, out.valid)
    when T_177210 : last_grant := T_177100
  module LockingRRArbiter_104925 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[4]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    output chosen : UInt<2>
    
    wire T_177211 : UInt<3>[3]
    T_177211[0] := UInt<3>(0)
    T_177211[1] := UInt<3>(1)
    T_177211[2] := UInt<3>(2)
    wire T_177212 : UInt<0>[1]
    T_177212[0] := UInt<0>(0)
    wire T_177213 : UInt<2>[2]
    T_177213[0] := UInt<2>(1)
    T_177213[1] := UInt<2>(2)
    wire T_177214 : UInt<2>[2]
    T_177214[0] := UInt<2>(1)
    T_177214[1] := UInt<2>(2)
    wire T_177215 : UInt<2>[1]
    T_177215[0] := UInt<2>(2)
    wire T_177216 : UInt<3>[3]
    T_177216[0] := UInt<3>(0)
    T_177216[1] := UInt<3>(1)
    T_177216[2] := UInt<3>(2)
    wire T_177217 : UInt<0>[1]
    T_177217[0] := UInt<0>(0)
    wire T_177218 : UInt<2>[2]
    T_177218[0] := UInt<2>(1)
    T_177218[1] := UInt<2>(2)
    wire T_177219 : UInt<2>[2]
    T_177219[0] := UInt<2>(1)
    T_177219[1] := UInt<2>(2)
    wire T_177220 : UInt<2>[1]
    T_177220[0] := UInt<2>(2)
    wire T_177221 : UInt<3>[3]
    T_177221[0] := UInt<3>(0)
    T_177221[1] := UInt<3>(1)
    T_177221[2] := UInt<3>(2)
    wire T_177222 : UInt<0>[1]
    T_177222[0] := UInt<0>(0)
    wire T_177223 : UInt<2>[2]
    T_177223[0] := UInt<2>(1)
    T_177223[1] := UInt<2>(2)
    wire T_177224 : UInt<2>[2]
    T_177224[0] := UInt<2>(1)
    T_177224[1] := UInt<2>(2)
    wire T_177225 : UInt<2>[1]
    T_177225[0] := UInt<2>(2)
    wire T_177226 : UInt<3>[3]
    T_177226[0] := UInt<3>(0)
    T_177226[1] := UInt<3>(1)
    T_177226[2] := UInt<3>(2)
    wire T_177227 : UInt<0>[1]
    T_177227[0] := UInt<0>(0)
    wire T_177228 : UInt<2>[2]
    T_177228[0] := UInt<2>(1)
    T_177228[1] := UInt<2>(2)
    wire T_177229 : UInt<2>[2]
    T_177229[0] := UInt<2>(1)
    T_177229[1] := UInt<2>(2)
    wire T_177230 : UInt<2>[1]
    T_177230[0] := UInt<2>(2)
    wire T_177231 : UInt<3>[3]
    T_177231[0] := UInt<3>(0)
    T_177231[1] := UInt<3>(1)
    T_177231[2] := UInt<3>(2)
    wire T_177232 : UInt<0>[1]
    T_177232[0] := UInt<0>(0)
    wire T_177233 : UInt<2>[2]
    T_177233[0] := UInt<2>(1)
    T_177233[1] := UInt<2>(2)
    wire T_177234 : UInt<2>[2]
    T_177234[0] := UInt<2>(1)
    T_177234[1] := UInt<2>(2)
    wire T_177235 : UInt<2>[1]
    T_177235[0] := UInt<2>(2)
    wire T_177236 : UInt<3>[3]
    T_177236[0] := UInt<3>(0)
    T_177236[1] := UInt<3>(1)
    T_177236[2] := UInt<3>(2)
    wire T_177237 : UInt<0>[1]
    T_177237[0] := UInt<0>(0)
    wire T_177238 : UInt<2>[2]
    T_177238[0] := UInt<2>(1)
    T_177238[1] := UInt<2>(2)
    wire T_177239 : UInt<2>[2]
    T_177239[0] := UInt<2>(1)
    T_177239[1] := UInt<2>(2)
    wire T_177240 : UInt<2>[1]
    T_177240[0] := UInt<2>(2)
    reg T_177241 : UInt<1>
    onreset T_177241 := UInt<1>(0)
    reg T_177242 : UInt<2>
    onreset T_177242 := UInt<2>(3)
    wire T_177243 : UInt<2>
    reg last_grant : UInt<2>
    onreset last_grant := UInt<2>(0)
    node T_177244 = gt(UInt<1>(0), last_grant)
    node T_177245 = and(in[0].valid, T_177244)
    node T_177246 = gt(UInt<1>(1), last_grant)
    node T_177247 = and(in[1].valid, T_177246)
    node T_177248 = gt(UInt<2>(2), last_grant)
    node T_177249 = and(in[2].valid, T_177248)
    node T_177250 = gt(UInt<2>(3), last_grant)
    node T_177251 = and(in[3].valid, T_177250)
    node T_177252 = or(UInt<1>(0), T_177245)
    node T_177253 = eq(T_177252, UInt<1>(0))
    node T_177254 = or(UInt<1>(0), T_177245)
    node T_177255 = or(T_177254, T_177247)
    node T_177256 = eq(T_177255, UInt<1>(0))
    node T_177257 = or(UInt<1>(0), T_177245)
    node T_177258 = or(T_177257, T_177247)
    node T_177259 = or(T_177258, T_177249)
    node T_177260 = eq(T_177259, UInt<1>(0))
    node T_177261 = or(UInt<1>(0), T_177245)
    node T_177262 = or(T_177261, T_177247)
    node T_177263 = or(T_177262, T_177249)
    node T_177264 = or(T_177263, T_177251)
    node T_177265 = eq(T_177264, UInt<1>(0))
    node T_177266 = or(UInt<1>(0), T_177245)
    node T_177267 = or(T_177266, T_177247)
    node T_177268 = or(T_177267, T_177249)
    node T_177269 = or(T_177268, T_177251)
    node T_177270 = or(T_177269, in[0].valid)
    node T_177271 = eq(T_177270, UInt<1>(0))
    node T_177272 = or(UInt<1>(0), T_177245)
    node T_177273 = or(T_177272, T_177247)
    node T_177274 = or(T_177273, T_177249)
    node T_177275 = or(T_177274, T_177251)
    node T_177276 = or(T_177275, in[0].valid)
    node T_177277 = or(T_177276, in[1].valid)
    node T_177278 = eq(T_177277, UInt<1>(0))
    node T_177279 = or(UInt<1>(0), T_177245)
    node T_177280 = or(T_177279, T_177247)
    node T_177281 = or(T_177280, T_177249)
    node T_177282 = or(T_177281, T_177251)
    node T_177283 = or(T_177282, in[0].valid)
    node T_177284 = or(T_177283, in[1].valid)
    node T_177285 = or(T_177284, in[2].valid)
    node T_177286 = eq(T_177285, UInt<1>(0))
    node T_177287 = gt(UInt<1>(0), last_grant)
    node T_177288 = and(UInt<1>(1), T_177287)
    node T_177289 = or(T_177288, T_177265)
    node T_177290 = gt(UInt<1>(1), last_grant)
    node T_177291 = and(T_177253, T_177290)
    node T_177292 = or(T_177291, T_177271)
    node T_177293 = gt(UInt<2>(2), last_grant)
    node T_177294 = and(T_177256, T_177293)
    node T_177295 = or(T_177294, T_177278)
    node T_177296 = gt(UInt<2>(3), last_grant)
    node T_177297 = and(T_177260, T_177296)
    node T_177298 = or(T_177297, T_177286)
    node T_177299 = eq(T_177242, UInt<1>(0))
    wire T_177300 : UInt<1>
    T_177300 := T_177289
    when T_177241 : T_177300 := T_177299
    node T_177301 = and(T_177300, out.ready)
    in[0].ready := T_177301
    node T_177302 = eq(T_177242, UInt<1>(1))
    wire T_177303 : UInt<1>
    T_177303 := T_177292
    when T_177241 : T_177303 := T_177302
    node T_177304 = and(T_177303, out.ready)
    in[1].ready := T_177304
    node T_177305 = eq(T_177242, UInt<2>(2))
    wire T_177306 : UInt<1>
    T_177306 := T_177295
    when T_177241 : T_177306 := T_177305
    node T_177307 = and(T_177306, out.ready)
    in[2].ready := T_177307
    node T_177308 = eq(T_177242, UInt<2>(3))
    wire T_177309 : UInt<1>
    T_177309 := T_177298
    when T_177241 : T_177309 := T_177308
    node T_177310 = and(T_177309, out.ready)
    in[3].ready := T_177310
    wire T_177311 : UInt<3>[3]
    T_177311[0] := UInt<3>(0)
    T_177311[1] := UInt<3>(1)
    T_177311[2] := UInt<3>(2)
    wire T_177312 : UInt<0>[1]
    T_177312[0] := UInt<0>(0)
    wire T_177313 : UInt<2>[2]
    T_177313[0] := UInt<2>(1)
    T_177313[1] := UInt<2>(2)
    wire T_177314 : UInt<2>[2]
    T_177314[0] := UInt<2>(1)
    T_177314[1] := UInt<2>(2)
    wire T_177315 : UInt<2>[1]
    T_177315[0] := UInt<2>(2)
    accessor T_177316 = in[T_177243]
    out.valid := T_177316.valid
    wire T_177317 : UInt<3>[3]
    T_177317[0] := UInt<3>(0)
    T_177317[1] := UInt<3>(1)
    T_177317[2] := UInt<3>(2)
    wire T_177318 : UInt<0>[1]
    T_177318[0] := UInt<0>(0)
    wire T_177319 : UInt<2>[2]
    T_177319[0] := UInt<2>(1)
    T_177319[1] := UInt<2>(2)
    wire T_177320 : UInt<2>[2]
    T_177320[0] := UInt<2>(1)
    T_177320[1] := UInt<2>(2)
    wire T_177321 : UInt<2>[1]
    T_177321[0] := UInt<2>(2)
    accessor T_177322 = in[T_177243]
    out.bits := T_177322.bits
    chosen := T_177243
    reg T_177323 : UInt<2>
    onreset T_177323 := UInt<2>(0)
    node T_177324 = addw(T_177323, UInt<1>(1))
    
    node T_177325 = and(out.ready, out.valid)
    when T_177325 : 
      
      
      node T_177326 = eq(T_177236[0], out.bits.r_type)
      node T_177327 = eq(T_177236[1], out.bits.r_type)
      node T_177328 = eq(T_177236[2], out.bits.r_type)
      node T_177329 = or(UInt<1>(0), T_177326)
      node T_177330 = or(T_177329, T_177327)
      node T_177331 = or(T_177330, T_177328)
      node T_177332 = and(UInt<1>(1), T_177331)
      when T_177332 : 
        T_177323 := T_177324
        
        node T_177333 = eq(T_177241, UInt<1>(0))
        when T_177333 : 
          T_177241 := UInt<1>(1)
          node T_177334 = and(in[0].ready, in[0].valid)
          node T_177335 = and(in[1].ready, in[1].valid)
          node T_177336 = and(in[2].ready, in[2].valid)
          node T_177337 = and(in[3].ready, in[3].valid)
          wire T_177338 : UInt<1>[4]
          T_177338[0] := T_177334
          T_177338[1] := T_177335
          T_177338[2] := T_177336
          T_177338[3] := T_177337
          wire T_177339 : UInt<2>
          T_177339 := UInt<2>(3)
          when T_177338[2] : T_177339 := UInt<2>(2)
          wire T_177340 : UInt<2>
          T_177340 := T_177339
          when T_177338[1] : T_177340 := UInt<1>(1)
          wire T_177341 : UInt<2>
          T_177341 := T_177340
          when T_177338[0] : T_177341 := UInt<1>(0)
          T_177242 := T_177341
      
      node T_177342 = eq(T_177324, UInt<1>(0))
      when T_177342 : T_177241 := UInt<1>(0)
    wire T_177343 : UInt<2>
    T_177343 := UInt<2>(3)
    when in[2].valid : T_177343 := UInt<2>(2)
    wire T_177344 : UInt<2>
    T_177344 := T_177343
    when in[1].valid : T_177344 := UInt<1>(1)
    wire T_177345 : UInt<2>
    T_177345 := T_177344
    when in[0].valid : T_177345 := UInt<1>(0)
    node T_177346 = gt(UInt<2>(3), last_grant)
    node T_177347 = and(in[3].valid, T_177346)
    wire T_177348 : UInt<2>
    T_177348 := T_177345
    when T_177347 : T_177348 := UInt<2>(3)
    node T_177349 = gt(UInt<2>(2), last_grant)
    node T_177350 = and(in[2].valid, T_177349)
    wire T_177351 : UInt<2>
    T_177351 := T_177348
    when T_177350 : T_177351 := UInt<2>(2)
    node T_177352 = gt(UInt<1>(1), last_grant)
    node T_177353 = and(in[1].valid, T_177352)
    wire choose : UInt<2>
    choose := T_177351
    when T_177353 : choose := UInt<1>(1)
    wire T_177354 : UInt<2>
    T_177354 := choose
    when T_177241 : T_177354 := T_177242
    T_177243 := T_177354
    
    node T_177355 = and(out.ready, out.valid)
    when T_177355 : last_grant := T_177243
  module ClientTileLinkIOArbiter : 
    input in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[4]
    output out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    
    wire T_177356 : UInt<3>[3]
    T_177356[0] := UInt<3>(0)
    T_177356[1] := UInt<3>(1)
    T_177356[2] := UInt<3>(2)
    wire T_177357 : UInt<0>[1]
    T_177357[0] := UInt<0>(0)
    wire T_177358 : UInt<2>[2]
    T_177358[0] := UInt<2>(1)
    T_177358[1] := UInt<2>(2)
    wire T_177359 : UInt<2>[2]
    T_177359[0] := UInt<2>(1)
    T_177359[1] := UInt<2>(2)
    wire T_177360 : UInt<2>[1]
    T_177360[0] := UInt<2>(2)
    wire T_177361 : UInt<3>[3]
    T_177361[0] := UInt<3>(0)
    T_177361[1] := UInt<3>(1)
    T_177361[2] := UInt<3>(2)
    wire T_177362 : UInt<0>[1]
    T_177362[0] := UInt<0>(0)
    wire T_177363 : UInt<2>[2]
    T_177363[0] := UInt<2>(1)
    T_177363[1] := UInt<2>(2)
    wire T_177364 : UInt<2>[2]
    T_177364[0] := UInt<2>(1)
    T_177364[1] := UInt<2>(2)
    wire T_177365 : UInt<2>[1]
    T_177365[0] := UInt<2>(2)
    wire T_177366 : UInt<3>[3]
    T_177366[0] := UInt<3>(0)
    T_177366[1] := UInt<3>(1)
    T_177366[2] := UInt<3>(2)
    wire T_177367 : UInt<0>[1]
    T_177367[0] := UInt<0>(0)
    wire T_177368 : UInt<2>[2]
    T_177368[0] := UInt<2>(1)
    T_177368[1] := UInt<2>(2)
    wire T_177369 : UInt<2>[2]
    T_177369[0] := UInt<2>(1)
    T_177369[1] := UInt<2>(2)
    wire T_177370 : UInt<2>[1]
    T_177370[0] := UInt<2>(2)
    wire T_177371 : UInt<3>[3]
    T_177371[0] := UInt<3>(0)
    T_177371[1] := UInt<3>(1)
    T_177371[2] := UInt<3>(2)
    wire T_177372 : UInt<0>[1]
    T_177372[0] := UInt<0>(0)
    wire T_177373 : UInt<2>[2]
    T_177373[0] := UInt<2>(1)
    T_177373[1] := UInt<2>(2)
    wire T_177374 : UInt<2>[2]
    T_177374[0] := UInt<2>(1)
    T_177374[1] := UInt<2>(2)
    wire T_177375 : UInt<2>[1]
    T_177375[0] := UInt<2>(2)
    wire T_177376 : UInt<3>[3]
    T_177376[0] := UInt<3>(0)
    T_177376[1] := UInt<3>(1)
    T_177376[2] := UInt<3>(2)
    wire T_177377 : UInt<0>[1]
    T_177377[0] := UInt<0>(0)
    wire T_177378 : UInt<2>[2]
    T_177378[0] := UInt<2>(1)
    T_177378[1] := UInt<2>(2)
    wire T_177379 : UInt<2>[2]
    T_177379[0] := UInt<2>(1)
    T_177379[1] := UInt<2>(2)
    wire T_177380 : UInt<2>[1]
    T_177380[0] := UInt<2>(2)
    wire T_177381 : UInt<3>[3]
    T_177381[0] := UInt<3>(0)
    T_177381[1] := UInt<3>(1)
    T_177381[2] := UInt<3>(2)
    wire T_177382 : UInt<0>[1]
    T_177382[0] := UInt<0>(0)
    wire T_177383 : UInt<2>[2]
    T_177383[0] := UInt<2>(1)
    T_177383[1] := UInt<2>(2)
    wire T_177384 : UInt<2>[2]
    T_177384[0] := UInt<2>(1)
    T_177384[1] := UInt<2>(2)
    wire T_177385 : UInt<2>[1]
    T_177385[0] := UInt<2>(2)
    wire T_177386 : UInt<3>[3]
    T_177386[0] := UInt<3>(0)
    T_177386[1] := UInt<3>(1)
    T_177386[2] := UInt<3>(2)
    wire T_177387 : UInt<0>[1]
    T_177387[0] := UInt<0>(0)
    wire T_177388 : UInt<2>[2]
    T_177388[0] := UInt<2>(1)
    T_177388[1] := UInt<2>(2)
    wire T_177389 : UInt<2>[2]
    T_177389[0] := UInt<2>(1)
    T_177389[1] := UInt<2>(2)
    wire T_177390 : UInt<2>[1]
    T_177390[0] := UInt<2>(2)
    wire T_177391 : UInt<3>[3]
    T_177391[0] := UInt<3>(0)
    T_177391[1] := UInt<3>(1)
    T_177391[2] := UInt<3>(2)
    wire T_177392 : UInt<0>[1]
    T_177392[0] := UInt<0>(0)
    wire T_177393 : UInt<2>[2]
    T_177393[0] := UInt<2>(1)
    T_177393[1] := UInt<2>(2)
    wire T_177394 : UInt<2>[2]
    T_177394[0] := UInt<2>(1)
    T_177394[1] := UInt<2>(2)
    wire T_177395 : UInt<2>[1]
    T_177395[0] := UInt<2>(2)
    wire T_177396 : UInt<3>[3]
    T_177396[0] := UInt<3>(0)
    T_177396[1] := UInt<3>(1)
    T_177396[2] := UInt<3>(2)
    wire T_177397 : UInt<0>[1]
    T_177397[0] := UInt<0>(0)
    wire T_177398 : UInt<2>[2]
    T_177398[0] := UInt<2>(1)
    T_177398[1] := UInt<2>(2)
    wire T_177399 : UInt<2>[2]
    T_177399[0] := UInt<2>(1)
    T_177399[1] := UInt<2>(2)
    wire T_177400 : UInt<2>[1]
    T_177400[0] := UInt<2>(2)
    wire T_177401 : UInt<3>[3]
    T_177401[0] := UInt<3>(0)
    T_177401[1] := UInt<3>(1)
    T_177401[2] := UInt<3>(2)
    wire T_177402 : UInt<0>[1]
    T_177402[0] := UInt<0>(0)
    wire T_177403 : UInt<2>[2]
    T_177403[0] := UInt<2>(1)
    T_177403[1] := UInt<2>(2)
    wire T_177404 : UInt<2>[2]
    T_177404[0] := UInt<2>(1)
    T_177404[1] := UInt<2>(2)
    wire T_177405 : UInt<2>[1]
    T_177405[0] := UInt<2>(2)
    wire T_177406 : UInt<3>[3]
    T_177406[0] := UInt<3>(0)
    T_177406[1] := UInt<3>(1)
    T_177406[2] := UInt<3>(2)
    wire T_177407 : UInt<0>[1]
    T_177407[0] := UInt<0>(0)
    wire T_177408 : UInt<2>[2]
    T_177408[0] := UInt<2>(1)
    T_177408[1] := UInt<2>(2)
    wire T_177409 : UInt<2>[2]
    T_177409[0] := UInt<2>(1)
    T_177409[1] := UInt<2>(2)
    wire T_177410 : UInt<2>[1]
    T_177410[0] := UInt<2>(2)
    wire T_177411 : UInt<3>[3]
    T_177411[0] := UInt<3>(0)
    T_177411[1] := UInt<3>(1)
    T_177411[2] := UInt<3>(2)
    wire T_177412 : UInt<0>[1]
    T_177412[0] := UInt<0>(0)
    wire T_177413 : UInt<2>[2]
    T_177413[0] := UInt<2>(1)
    T_177413[1] := UInt<2>(2)
    wire T_177414 : UInt<2>[2]
    T_177414[0] := UInt<2>(1)
    T_177414[1] := UInt<2>(2)
    wire T_177415 : UInt<2>[1]
    T_177415[0] := UInt<2>(2)
    wire T_177416 : UInt<3>[3]
    T_177416[0] := UInt<3>(0)
    T_177416[1] := UInt<3>(1)
    T_177416[2] := UInt<3>(2)
    wire T_177417 : UInt<0>[1]
    T_177417[0] := UInt<0>(0)
    wire T_177418 : UInt<2>[2]
    T_177418[0] := UInt<2>(1)
    T_177418[1] := UInt<2>(2)
    wire T_177419 : UInt<2>[2]
    T_177419[0] := UInt<2>(1)
    T_177419[1] := UInt<2>(2)
    wire T_177420 : UInt<2>[1]
    T_177420[0] := UInt<2>(2)
    wire T_177421 : UInt<3>[3]
    T_177421[0] := UInt<3>(0)
    T_177421[1] := UInt<3>(1)
    T_177421[2] := UInt<3>(2)
    wire T_177422 : UInt<0>[1]
    T_177422[0] := UInt<0>(0)
    wire T_177423 : UInt<2>[2]
    T_177423[0] := UInt<2>(1)
    T_177423[1] := UInt<2>(2)
    wire T_177424 : UInt<2>[2]
    T_177424[0] := UInt<2>(1)
    T_177424[1] := UInt<2>(2)
    wire T_177425 : UInt<2>[1]
    T_177425[0] := UInt<2>(2)
    wire T_177426 : UInt<3>[3]
    T_177426[0] := UInt<3>(0)
    T_177426[1] := UInt<3>(1)
    T_177426[2] := UInt<3>(2)
    wire T_177427 : UInt<0>[1]
    T_177427[0] := UInt<0>(0)
    wire T_177428 : UInt<2>[2]
    T_177428[0] := UInt<2>(1)
    T_177428[1] := UInt<2>(2)
    wire T_177429 : UInt<2>[2]
    T_177429[0] := UInt<2>(1)
    T_177429[1] := UInt<2>(2)
    wire T_177430 : UInt<2>[1]
    T_177430[0] := UInt<2>(2)
    wire T_177431 : UInt<3>[3]
    T_177431[0] := UInt<3>(0)
    T_177431[1] := UInt<3>(1)
    T_177431[2] := UInt<3>(2)
    wire T_177432 : UInt<0>[1]
    T_177432[0] := UInt<0>(0)
    wire T_177433 : UInt<2>[2]
    T_177433[0] := UInt<2>(1)
    T_177433[1] := UInt<2>(2)
    wire T_177434 : UInt<2>[2]
    T_177434[0] := UInt<2>(1)
    T_177434[1] := UInt<2>(2)
    wire T_177435 : UInt<2>[1]
    T_177435[0] := UInt<2>(2)
    wire T_177436 : UInt<3>[3]
    T_177436[0] := UInt<3>(0)
    T_177436[1] := UInt<3>(1)
    T_177436[2] := UInt<3>(2)
    wire T_177437 : UInt<0>[1]
    T_177437[0] := UInt<0>(0)
    wire T_177438 : UInt<2>[2]
    T_177438[0] := UInt<2>(1)
    T_177438[1] := UInt<2>(2)
    wire T_177439 : UInt<2>[2]
    T_177439[0] := UInt<2>(1)
    T_177439[1] := UInt<2>(2)
    wire T_177440 : UInt<2>[1]
    T_177440[0] := UInt<2>(2)
    wire T_177441 : UInt<3>[3]
    T_177441[0] := UInt<3>(0)
    T_177441[1] := UInt<3>(1)
    T_177441[2] := UInt<3>(2)
    wire T_177442 : UInt<0>[1]
    T_177442[0] := UInt<0>(0)
    wire T_177443 : UInt<2>[2]
    T_177443[0] := UInt<2>(1)
    T_177443[1] := UInt<2>(2)
    wire T_177444 : UInt<2>[2]
    T_177444[0] := UInt<2>(1)
    T_177444[1] := UInt<2>(2)
    wire T_177445 : UInt<2>[1]
    T_177445[0] := UInt<2>(2)
    wire T_177446 : UInt<3>[3]
    T_177446[0] := UInt<3>(0)
    T_177446[1] := UInt<3>(1)
    T_177446[2] := UInt<3>(2)
    wire T_177447 : UInt<0>[1]
    T_177447[0] := UInt<0>(0)
    wire T_177448 : UInt<2>[2]
    T_177448[0] := UInt<2>(1)
    T_177448[1] := UInt<2>(2)
    wire T_177449 : UInt<2>[2]
    T_177449[0] := UInt<2>(1)
    T_177449[1] := UInt<2>(2)
    wire T_177450 : UInt<2>[1]
    T_177450[0] := UInt<2>(2)
    wire T_177451 : UInt<3>[3]
    T_177451[0] := UInt<3>(0)
    T_177451[1] := UInt<3>(1)
    T_177451[2] := UInt<3>(2)
    wire T_177452 : UInt<0>[1]
    T_177452[0] := UInt<0>(0)
    wire T_177453 : UInt<2>[2]
    T_177453[0] := UInt<2>(1)
    T_177453[1] := UInt<2>(2)
    wire T_177454 : UInt<2>[2]
    T_177454[0] := UInt<2>(1)
    T_177454[1] := UInt<2>(2)
    wire T_177455 : UInt<2>[1]
    T_177455[0] := UInt<2>(2)
    wire T_177456 : UInt<3>[3]
    T_177456[0] := UInt<3>(0)
    T_177456[1] := UInt<3>(1)
    T_177456[2] := UInt<3>(2)
    wire T_177457 : UInt<0>[1]
    T_177457[0] := UInt<0>(0)
    wire T_177458 : UInt<2>[2]
    T_177458[0] := UInt<2>(1)
    T_177458[1] := UInt<2>(2)
    wire T_177459 : UInt<2>[2]
    T_177459[0] := UInt<2>(1)
    T_177459[1] := UInt<2>(2)
    wire T_177460 : UInt<2>[1]
    T_177460[0] := UInt<2>(2)
    wire T_177461 : UInt<3>[3]
    T_177461[0] := UInt<3>(0)
    T_177461[1] := UInt<3>(1)
    T_177461[2] := UInt<3>(2)
    wire T_177462 : UInt<0>[1]
    T_177462[0] := UInt<0>(0)
    wire T_177463 : UInt<2>[2]
    T_177463[0] := UInt<2>(1)
    T_177463[1] := UInt<2>(2)
    wire T_177464 : UInt<2>[2]
    T_177464[0] := UInt<2>(1)
    T_177464[1] := UInt<2>(2)
    wire T_177465 : UInt<2>[1]
    T_177465[0] := UInt<2>(2)
    wire T_177466 : UInt<3>[3]
    T_177466[0] := UInt<3>(0)
    T_177466[1] := UInt<3>(1)
    T_177466[2] := UInt<3>(2)
    wire T_177467 : UInt<0>[1]
    T_177467[0] := UInt<0>(0)
    wire T_177468 : UInt<2>[2]
    T_177468[0] := UInt<2>(1)
    T_177468[1] := UInt<2>(2)
    wire T_177469 : UInt<2>[2]
    T_177469[0] := UInt<2>(1)
    T_177469[1] := UInt<2>(2)
    wire T_177470 : UInt<2>[1]
    T_177470[0] := UInt<2>(2)
    wire T_177471 : UInt<3>[3]
    T_177471[0] := UInt<3>(0)
    T_177471[1] := UInt<3>(1)
    T_177471[2] := UInt<3>(2)
    wire T_177472 : UInt<0>[1]
    T_177472[0] := UInt<0>(0)
    wire T_177473 : UInt<2>[2]
    T_177473[0] := UInt<2>(1)
    T_177473[1] := UInt<2>(2)
    wire T_177474 : UInt<2>[2]
    T_177474[0] := UInt<2>(1)
    T_177474[1] := UInt<2>(2)
    wire T_177475 : UInt<2>[1]
    T_177475[0] := UInt<2>(2)
    wire T_177476 : UInt<3>[3]
    T_177476[0] := UInt<3>(0)
    T_177476[1] := UInt<3>(1)
    T_177476[2] := UInt<3>(2)
    wire T_177477 : UInt<0>[1]
    T_177477[0] := UInt<0>(0)
    wire T_177478 : UInt<2>[2]
    T_177478[0] := UInt<2>(1)
    T_177478[1] := UInt<2>(2)
    wire T_177479 : UInt<2>[2]
    T_177479[0] := UInt<2>(1)
    T_177479[1] := UInt<2>(2)
    wire T_177480 : UInt<2>[1]
    T_177480[0] := UInt<2>(2)
    wire T_177481 : UInt<3>[3]
    T_177481[0] := UInt<3>(0)
    T_177481[1] := UInt<3>(1)
    T_177481[2] := UInt<3>(2)
    wire T_177482 : UInt<0>[1]
    T_177482[0] := UInt<0>(0)
    wire T_177483 : UInt<2>[2]
    T_177483[0] := UInt<2>(1)
    T_177483[1] := UInt<2>(2)
    wire T_177484 : UInt<2>[2]
    T_177484[0] := UInt<2>(1)
    T_177484[1] := UInt<2>(2)
    wire T_177485 : UInt<2>[1]
    T_177485[0] := UInt<2>(2)
    wire T_177486 : UInt<3>[3]
    T_177486[0] := UInt<3>(0)
    T_177486[1] := UInt<3>(1)
    T_177486[2] := UInt<3>(2)
    wire T_177487 : UInt<0>[1]
    T_177487[0] := UInt<0>(0)
    wire T_177488 : UInt<2>[2]
    T_177488[0] := UInt<2>(1)
    T_177488[1] := UInt<2>(2)
    wire T_177489 : UInt<2>[2]
    T_177489[0] := UInt<2>(1)
    T_177489[1] := UInt<2>(2)
    wire T_177490 : UInt<2>[1]
    T_177490[0] := UInt<2>(2)
    wire T_177491 : UInt<3>[3]
    T_177491[0] := UInt<3>(0)
    T_177491[1] := UInt<3>(1)
    T_177491[2] := UInt<3>(2)
    wire T_177492 : UInt<0>[1]
    T_177492[0] := UInt<0>(0)
    wire T_177493 : UInt<2>[2]
    T_177493[0] := UInt<2>(1)
    T_177493[1] := UInt<2>(2)
    wire T_177494 : UInt<2>[2]
    T_177494[0] := UInt<2>(1)
    T_177494[1] := UInt<2>(2)
    wire T_177495 : UInt<2>[1]
    T_177495[0] := UInt<2>(2)
    wire T_177496 : UInt<3>[3]
    T_177496[0] := UInt<3>(0)
    T_177496[1] := UInt<3>(1)
    T_177496[2] := UInt<3>(2)
    wire T_177497 : UInt<0>[1]
    T_177497[0] := UInt<0>(0)
    wire T_177498 : UInt<2>[2]
    T_177498[0] := UInt<2>(1)
    T_177498[1] := UInt<2>(2)
    wire T_177499 : UInt<2>[2]
    T_177499[0] := UInt<2>(1)
    T_177499[1] := UInt<2>(2)
    wire T_177500 : UInt<2>[1]
    T_177500[0] := UInt<2>(2)
    wire T_177501 : UInt<3>[3]
    T_177501[0] := UInt<3>(0)
    T_177501[1] := UInt<3>(1)
    T_177501[2] := UInt<3>(2)
    wire T_177502 : UInt<0>[1]
    T_177502[0] := UInt<0>(0)
    wire T_177503 : UInt<2>[2]
    T_177503[0] := UInt<2>(1)
    T_177503[1] := UInt<2>(2)
    wire T_177504 : UInt<2>[2]
    T_177504[0] := UInt<2>(1)
    T_177504[1] := UInt<2>(2)
    wire T_177505 : UInt<2>[1]
    T_177505[0] := UInt<2>(2)
    wire T_177506 : UInt<3>[3]
    T_177506[0] := UInt<3>(0)
    T_177506[1] := UInt<3>(1)
    T_177506[2] := UInt<3>(2)
    wire T_177507 : UInt<0>[1]
    T_177507[0] := UInt<0>(0)
    wire T_177508 : UInt<2>[2]
    T_177508[0] := UInt<2>(1)
    T_177508[1] := UInt<2>(2)
    wire T_177509 : UInt<2>[2]
    T_177509[0] := UInt<2>(1)
    T_177509[1] := UInt<2>(2)
    wire T_177510 : UInt<2>[1]
    T_177510[0] := UInt<2>(2)
    wire T_177511 : UInt<3>[3]
    T_177511[0] := UInt<3>(0)
    T_177511[1] := UInt<3>(1)
    T_177511[2] := UInt<3>(2)
    wire T_177512 : UInt<0>[1]
    T_177512[0] := UInt<0>(0)
    wire T_177513 : UInt<2>[2]
    T_177513[0] := UInt<2>(1)
    T_177513[1] := UInt<2>(2)
    wire T_177514 : UInt<2>[2]
    T_177514[0] := UInt<2>(1)
    T_177514[1] := UInt<2>(2)
    wire T_177515 : UInt<2>[1]
    T_177515[0] := UInt<2>(2)
    wire T_177516 : UInt<3>[3]
    T_177516[0] := UInt<3>(0)
    T_177516[1] := UInt<3>(1)
    T_177516[2] := UInt<3>(2)
    wire T_177517 : UInt<0>[1]
    T_177517[0] := UInt<0>(0)
    wire T_177518 : UInt<2>[2]
    T_177518[0] := UInt<2>(1)
    T_177518[1] := UInt<2>(2)
    wire T_177519 : UInt<2>[2]
    T_177519[0] := UInt<2>(1)
    T_177519[1] := UInt<2>(2)
    wire T_177520 : UInt<2>[1]
    T_177520[0] := UInt<2>(2)
    wire T_177521 : UInt<3>[3]
    T_177521[0] := UInt<3>(0)
    T_177521[1] := UInt<3>(1)
    T_177521[2] := UInt<3>(2)
    wire T_177522 : UInt<0>[1]
    T_177522[0] := UInt<0>(0)
    wire T_177523 : UInt<2>[2]
    T_177523[0] := UInt<2>(1)
    T_177523[1] := UInt<2>(2)
    wire T_177524 : UInt<2>[2]
    T_177524[0] := UInt<2>(1)
    T_177524[1] := UInt<2>(2)
    wire T_177525 : UInt<2>[1]
    T_177525[0] := UInt<2>(2)
    wire T_177526 : UInt<3>[3]
    T_177526[0] := UInt<3>(0)
    T_177526[1] := UInt<3>(1)
    T_177526[2] := UInt<3>(2)
    wire T_177527 : UInt<0>[1]
    T_177527[0] := UInt<0>(0)
    wire T_177528 : UInt<2>[2]
    T_177528[0] := UInt<2>(1)
    T_177528[1] := UInt<2>(2)
    wire T_177529 : UInt<2>[2]
    T_177529[0] := UInt<2>(1)
    T_177529[1] := UInt<2>(2)
    wire T_177530 : UInt<2>[1]
    T_177530[0] := UInt<2>(2)
    wire T_177531 : UInt<3>[3]
    T_177531[0] := UInt<3>(0)
    T_177531[1] := UInt<3>(1)
    T_177531[2] := UInt<3>(2)
    wire T_177532 : UInt<0>[1]
    T_177532[0] := UInt<0>(0)
    wire T_177533 : UInt<2>[2]
    T_177533[0] := UInt<2>(1)
    T_177533[1] := UInt<2>(2)
    wire T_177534 : UInt<2>[2]
    T_177534[0] := UInt<2>(1)
    T_177534[1] := UInt<2>(2)
    wire T_177535 : UInt<2>[1]
    T_177535[0] := UInt<2>(2)
    wire T_177536 : UInt<3>[3]
    T_177536[0] := UInt<3>(0)
    T_177536[1] := UInt<3>(1)
    T_177536[2] := UInt<3>(2)
    wire T_177537 : UInt<0>[1]
    T_177537[0] := UInt<0>(0)
    wire T_177538 : UInt<2>[2]
    T_177538[0] := UInt<2>(1)
    T_177538[1] := UInt<2>(2)
    wire T_177539 : UInt<2>[2]
    T_177539[0] := UInt<2>(1)
    T_177539[1] := UInt<2>(2)
    wire T_177540 : UInt<2>[1]
    T_177540[0] := UInt<2>(2)
    wire T_177541 : UInt<3>[3]
    T_177541[0] := UInt<3>(0)
    T_177541[1] := UInt<3>(1)
    T_177541[2] := UInt<3>(2)
    wire T_177542 : UInt<0>[1]
    T_177542[0] := UInt<0>(0)
    wire T_177543 : UInt<2>[2]
    T_177543[0] := UInt<2>(1)
    T_177543[1] := UInt<2>(2)
    wire T_177544 : UInt<2>[2]
    T_177544[0] := UInt<2>(1)
    T_177544[1] := UInt<2>(2)
    wire T_177545 : UInt<2>[1]
    T_177545[0] := UInt<2>(2)
    wire T_177546 : UInt<3>[3]
    T_177546[0] := UInt<3>(0)
    T_177546[1] := UInt<3>(1)
    T_177546[2] := UInt<3>(2)
    wire T_177547 : UInt<0>[1]
    T_177547[0] := UInt<0>(0)
    wire T_177548 : UInt<2>[2]
    T_177548[0] := UInt<2>(1)
    T_177548[1] := UInt<2>(2)
    wire T_177549 : UInt<2>[2]
    T_177549[0] := UInt<2>(1)
    T_177549[1] := UInt<2>(2)
    wire T_177550 : UInt<2>[1]
    T_177550[0] := UInt<2>(2)
    wire T_177551 : UInt<3>[3]
    T_177551[0] := UInt<3>(0)
    T_177551[1] := UInt<3>(1)
    T_177551[2] := UInt<3>(2)
    wire T_177552 : UInt<0>[1]
    T_177552[0] := UInt<0>(0)
    wire T_177553 : UInt<2>[2]
    T_177553[0] := UInt<2>(1)
    T_177553[1] := UInt<2>(2)
    wire T_177554 : UInt<2>[2]
    T_177554[0] := UInt<2>(1)
    T_177554[1] := UInt<2>(2)
    wire T_177555 : UInt<2>[1]
    T_177555[0] := UInt<2>(2)
    wire T_177556 : UInt<3>[3]
    T_177556[0] := UInt<3>(0)
    T_177556[1] := UInt<3>(1)
    T_177556[2] := UInt<3>(2)
    wire T_177557 : UInt<0>[1]
    T_177557[0] := UInt<0>(0)
    wire T_177558 : UInt<2>[2]
    T_177558[0] := UInt<2>(1)
    T_177558[1] := UInt<2>(2)
    wire T_177559 : UInt<2>[2]
    T_177559[0] := UInt<2>(1)
    T_177559[1] := UInt<2>(2)
    wire T_177560 : UInt<2>[1]
    T_177560[0] := UInt<2>(2)
    wire T_177561 : UInt<3>[3]
    T_177561[0] := UInt<3>(0)
    T_177561[1] := UInt<3>(1)
    T_177561[2] := UInt<3>(2)
    wire T_177562 : UInt<0>[1]
    T_177562[0] := UInt<0>(0)
    wire T_177563 : UInt<2>[2]
    T_177563[0] := UInt<2>(1)
    T_177563[1] := UInt<2>(2)
    wire T_177564 : UInt<2>[2]
    T_177564[0] := UInt<2>(1)
    T_177564[1] := UInt<2>(2)
    wire T_177565 : UInt<2>[1]
    T_177565[0] := UInt<2>(2)
    wire T_177566 : UInt<3>[3]
    T_177566[0] := UInt<3>(0)
    T_177566[1] := UInt<3>(1)
    T_177566[2] := UInt<3>(2)
    wire T_177567 : UInt<0>[1]
    T_177567[0] := UInt<0>(0)
    wire T_177568 : UInt<2>[2]
    T_177568[0] := UInt<2>(1)
    T_177568[1] := UInt<2>(2)
    wire T_177569 : UInt<2>[2]
    T_177569[0] := UInt<2>(1)
    T_177569[1] := UInt<2>(2)
    wire T_177570 : UInt<2>[1]
    T_177570[0] := UInt<2>(2)
    wire T_177571 : UInt<3>[3]
    T_177571[0] := UInt<3>(0)
    T_177571[1] := UInt<3>(1)
    T_177571[2] := UInt<3>(2)
    wire T_177572 : UInt<0>[1]
    T_177572[0] := UInt<0>(0)
    wire T_177573 : UInt<2>[2]
    T_177573[0] := UInt<2>(1)
    T_177573[1] := UInt<2>(2)
    wire T_177574 : UInt<2>[2]
    T_177574[0] := UInt<2>(1)
    T_177574[1] := UInt<2>(2)
    wire T_177575 : UInt<2>[1]
    T_177575[0] := UInt<2>(2)
    wire T_177576 : UInt<3>[3]
    T_177576[0] := UInt<3>(0)
    T_177576[1] := UInt<3>(1)
    T_177576[2] := UInt<3>(2)
    wire T_177577 : UInt<0>[1]
    T_177577[0] := UInt<0>(0)
    wire T_177578 : UInt<2>[2]
    T_177578[0] := UInt<2>(1)
    T_177578[1] := UInt<2>(2)
    wire T_177579 : UInt<2>[2]
    T_177579[0] := UInt<2>(1)
    T_177579[1] := UInt<2>(2)
    wire T_177580 : UInt<2>[1]
    T_177580[0] := UInt<2>(2)
    wire T_177581 : UInt<3>[3]
    T_177581[0] := UInt<3>(0)
    T_177581[1] := UInt<3>(1)
    T_177581[2] := UInt<3>(2)
    wire T_177582 : UInt<0>[1]
    T_177582[0] := UInt<0>(0)
    wire T_177583 : UInt<2>[2]
    T_177583[0] := UInt<2>(1)
    T_177583[1] := UInt<2>(2)
    wire T_177584 : UInt<2>[2]
    T_177584[0] := UInt<2>(1)
    T_177584[1] := UInt<2>(2)
    wire T_177585 : UInt<2>[1]
    T_177585[0] := UInt<2>(2)
    wire T_177586 : UInt<3>[3]
    T_177586[0] := UInt<3>(0)
    T_177586[1] := UInt<3>(1)
    T_177586[2] := UInt<3>(2)
    wire T_177587 : UInt<0>[1]
    T_177587[0] := UInt<0>(0)
    wire T_177588 : UInt<2>[2]
    T_177588[0] := UInt<2>(1)
    T_177588[1] := UInt<2>(2)
    wire T_177589 : UInt<2>[2]
    T_177589[0] := UInt<2>(1)
    T_177589[1] := UInt<2>(2)
    wire T_177590 : UInt<2>[1]
    T_177590[0] := UInt<2>(2)
    wire T_177591 : UInt<3>[3]
    T_177591[0] := UInt<3>(0)
    T_177591[1] := UInt<3>(1)
    T_177591[2] := UInt<3>(2)
    wire T_177592 : UInt<0>[1]
    T_177592[0] := UInt<0>(0)
    wire T_177593 : UInt<2>[2]
    T_177593[0] := UInt<2>(1)
    T_177593[1] := UInt<2>(2)
    wire T_177594 : UInt<2>[2]
    T_177594[0] := UInt<2>(1)
    T_177594[1] := UInt<2>(2)
    wire T_177595 : UInt<2>[1]
    T_177595[0] := UInt<2>(2)
    wire T_177596 : UInt<3>[3]
    T_177596[0] := UInt<3>(0)
    T_177596[1] := UInt<3>(1)
    T_177596[2] := UInt<3>(2)
    wire T_177597 : UInt<0>[1]
    T_177597[0] := UInt<0>(0)
    wire T_177598 : UInt<2>[2]
    T_177598[0] := UInt<2>(1)
    T_177598[1] := UInt<2>(2)
    wire T_177599 : UInt<2>[2]
    T_177599[0] := UInt<2>(1)
    T_177599[1] := UInt<2>(2)
    wire T_177600 : UInt<2>[1]
    T_177600[0] := UInt<2>(2)
    wire T_177601 : UInt<3>[3]
    T_177601[0] := UInt<3>(0)
    T_177601[1] := UInt<3>(1)
    T_177601[2] := UInt<3>(2)
    wire T_177602 : UInt<0>[1]
    T_177602[0] := UInt<0>(0)
    wire T_177603 : UInt<2>[2]
    T_177603[0] := UInt<2>(1)
    T_177603[1] := UInt<2>(2)
    wire T_177604 : UInt<2>[2]
    T_177604[0] := UInt<2>(1)
    T_177604[1] := UInt<2>(2)
    wire T_177605 : UInt<2>[1]
    T_177605[0] := UInt<2>(2)
    wire T_177606 : UInt<3>[3]
    T_177606[0] := UInt<3>(0)
    T_177606[1] := UInt<3>(1)
    T_177606[2] := UInt<3>(2)
    wire T_177607 : UInt<0>[1]
    T_177607[0] := UInt<0>(0)
    wire T_177608 : UInt<2>[2]
    T_177608[0] := UInt<2>(1)
    T_177608[1] := UInt<2>(2)
    wire T_177609 : UInt<2>[2]
    T_177609[0] := UInt<2>(1)
    T_177609[1] := UInt<2>(2)
    wire T_177610 : UInt<2>[1]
    T_177610[0] := UInt<2>(2)
    wire T_177611 : UInt<3>[3]
    T_177611[0] := UInt<3>(0)
    T_177611[1] := UInt<3>(1)
    T_177611[2] := UInt<3>(2)
    wire T_177612 : UInt<0>[1]
    T_177612[0] := UInt<0>(0)
    wire T_177613 : UInt<2>[2]
    T_177613[0] := UInt<2>(1)
    T_177613[1] := UInt<2>(2)
    wire T_177614 : UInt<2>[2]
    T_177614[0] := UInt<2>(1)
    T_177614[1] := UInt<2>(2)
    wire T_177615 : UInt<2>[1]
    T_177615[0] := UInt<2>(2)
    wire T_177616 : UInt<3>[3]
    T_177616[0] := UInt<3>(0)
    T_177616[1] := UInt<3>(1)
    T_177616[2] := UInt<3>(2)
    wire T_177617 : UInt<0>[1]
    T_177617[0] := UInt<0>(0)
    wire T_177618 : UInt<2>[2]
    T_177618[0] := UInt<2>(1)
    T_177618[1] := UInt<2>(2)
    wire T_177619 : UInt<2>[2]
    T_177619[0] := UInt<2>(1)
    T_177619[1] := UInt<2>(2)
    wire T_177620 : UInt<2>[1]
    T_177620[0] := UInt<2>(2)
    wire T_177621 : UInt<3>[3]
    T_177621[0] := UInt<3>(0)
    T_177621[1] := UInt<3>(1)
    T_177621[2] := UInt<3>(2)
    wire T_177622 : UInt<0>[1]
    T_177622[0] := UInt<0>(0)
    wire T_177623 : UInt<2>[2]
    T_177623[0] := UInt<2>(1)
    T_177623[1] := UInt<2>(2)
    wire T_177624 : UInt<2>[2]
    T_177624[0] := UInt<2>(1)
    T_177624[1] := UInt<2>(2)
    wire T_177625 : UInt<2>[1]
    T_177625[0] := UInt<2>(2)
    wire T_177626 : UInt<3>[3]
    T_177626[0] := UInt<3>(0)
    T_177626[1] := UInt<3>(1)
    T_177626[2] := UInt<3>(2)
    wire T_177627 : UInt<0>[1]
    T_177627[0] := UInt<0>(0)
    wire T_177628 : UInt<2>[2]
    T_177628[0] := UInt<2>(1)
    T_177628[1] := UInt<2>(2)
    wire T_177629 : UInt<2>[2]
    T_177629[0] := UInt<2>(1)
    T_177629[1] := UInt<2>(2)
    wire T_177630 : UInt<2>[1]
    T_177630[0] := UInt<2>(2)
    wire T_177631 : UInt<3>[3]
    T_177631[0] := UInt<3>(0)
    T_177631[1] := UInt<3>(1)
    T_177631[2] := UInt<3>(2)
    wire T_177632 : UInt<0>[1]
    T_177632[0] := UInt<0>(0)
    wire T_177633 : UInt<2>[2]
    T_177633[0] := UInt<2>(1)
    T_177633[1] := UInt<2>(2)
    wire T_177634 : UInt<2>[2]
    T_177634[0] := UInt<2>(1)
    T_177634[1] := UInt<2>(2)
    wire T_177635 : UInt<2>[1]
    T_177635[0] := UInt<2>(2)
    wire T_177636 : UInt<3>[3]
    T_177636[0] := UInt<3>(0)
    T_177636[1] := UInt<3>(1)
    T_177636[2] := UInt<3>(2)
    wire T_177637 : UInt<0>[1]
    T_177637[0] := UInt<0>(0)
    wire T_177638 : UInt<2>[2]
    T_177638[0] := UInt<2>(1)
    T_177638[1] := UInt<2>(2)
    wire T_177639 : UInt<2>[2]
    T_177639[0] := UInt<2>(1)
    T_177639[1] := UInt<2>(2)
    wire T_177640 : UInt<2>[1]
    T_177640[0] := UInt<2>(2)
    wire T_177641 : UInt<3>[3]
    T_177641[0] := UInt<3>(0)
    T_177641[1] := UInt<3>(1)
    T_177641[2] := UInt<3>(2)
    wire T_177642 : UInt<0>[1]
    T_177642[0] := UInt<0>(0)
    wire T_177643 : UInt<2>[2]
    T_177643[0] := UInt<2>(1)
    T_177643[1] := UInt<2>(2)
    wire T_177644 : UInt<2>[2]
    T_177644[0] := UInt<2>(1)
    T_177644[1] := UInt<2>(2)
    wire T_177645 : UInt<2>[1]
    T_177645[0] := UInt<2>(2)
    wire T_177646 : UInt<3>[3]
    T_177646[0] := UInt<3>(0)
    T_177646[1] := UInt<3>(1)
    T_177646[2] := UInt<3>(2)
    wire T_177647 : UInt<0>[1]
    T_177647[0] := UInt<0>(0)
    wire T_177648 : UInt<2>[2]
    T_177648[0] := UInt<2>(1)
    T_177648[1] := UInt<2>(2)
    wire T_177649 : UInt<2>[2]
    T_177649[0] := UInt<2>(1)
    T_177649[1] := UInt<2>(2)
    wire T_177650 : UInt<2>[1]
    T_177650[0] := UInt<2>(2)
    wire T_177651 : UInt<3>[3]
    T_177651[0] := UInt<3>(0)
    T_177651[1] := UInt<3>(1)
    T_177651[2] := UInt<3>(2)
    wire T_177652 : UInt<0>[1]
    T_177652[0] := UInt<0>(0)
    wire T_177653 : UInt<2>[2]
    T_177653[0] := UInt<2>(1)
    T_177653[1] := UInt<2>(2)
    wire T_177654 : UInt<2>[2]
    T_177654[0] := UInt<2>(1)
    T_177654[1] := UInt<2>(2)
    wire T_177655 : UInt<2>[1]
    T_177655[0] := UInt<2>(2)
    wire T_177656 : UInt<3>[3]
    T_177656[0] := UInt<3>(0)
    T_177656[1] := UInt<3>(1)
    T_177656[2] := UInt<3>(2)
    wire T_177657 : UInt<0>[1]
    T_177657[0] := UInt<0>(0)
    wire T_177658 : UInt<2>[2]
    T_177658[0] := UInt<2>(1)
    T_177658[1] := UInt<2>(2)
    wire T_177659 : UInt<2>[2]
    T_177659[0] := UInt<2>(1)
    T_177659[1] := UInt<2>(2)
    wire T_177660 : UInt<2>[1]
    T_177660[0] := UInt<2>(2)
    wire T_177661 : UInt<3>[3]
    T_177661[0] := UInt<3>(0)
    T_177661[1] := UInt<3>(1)
    T_177661[2] := UInt<3>(2)
    wire T_177662 : UInt<0>[1]
    T_177662[0] := UInt<0>(0)
    wire T_177663 : UInt<2>[2]
    T_177663[0] := UInt<2>(1)
    T_177663[1] := UInt<2>(2)
    wire T_177664 : UInt<2>[2]
    T_177664[0] := UInt<2>(1)
    T_177664[1] := UInt<2>(2)
    wire T_177665 : UInt<2>[1]
    T_177665[0] := UInt<2>(2)
    wire T_177666 : UInt<3>[3]
    T_177666[0] := UInt<3>(0)
    T_177666[1] := UInt<3>(1)
    T_177666[2] := UInt<3>(2)
    wire T_177667 : UInt<0>[1]
    T_177667[0] := UInt<0>(0)
    wire T_177668 : UInt<2>[2]
    T_177668[0] := UInt<2>(1)
    T_177668[1] := UInt<2>(2)
    wire T_177669 : UInt<2>[2]
    T_177669[0] := UInt<2>(1)
    T_177669[1] := UInt<2>(2)
    wire T_177670 : UInt<2>[1]
    T_177670[0] := UInt<2>(2)
    wire T_177671 : UInt<3>[3]
    T_177671[0] := UInt<3>(0)
    T_177671[1] := UInt<3>(1)
    T_177671[2] := UInt<3>(2)
    wire T_177672 : UInt<0>[1]
    T_177672[0] := UInt<0>(0)
    wire T_177673 : UInt<2>[2]
    T_177673[0] := UInt<2>(1)
    T_177673[1] := UInt<2>(2)
    wire T_177674 : UInt<2>[2]
    T_177674[0] := UInt<2>(1)
    T_177674[1] := UInt<2>(2)
    wire T_177675 : UInt<2>[1]
    T_177675[0] := UInt<2>(2)
    wire T_177676 : UInt<3>[3]
    T_177676[0] := UInt<3>(0)
    T_177676[1] := UInt<3>(1)
    T_177676[2] := UInt<3>(2)
    wire T_177677 : UInt<0>[1]
    T_177677[0] := UInt<0>(0)
    wire T_177678 : UInt<2>[2]
    T_177678[0] := UInt<2>(1)
    T_177678[1] := UInt<2>(2)
    wire T_177679 : UInt<2>[2]
    T_177679[0] := UInt<2>(1)
    T_177679[1] := UInt<2>(2)
    wire T_177680 : UInt<2>[1]
    T_177680[0] := UInt<2>(2)
    wire T_177681 : UInt<3>[3]
    T_177681[0] := UInt<3>(0)
    T_177681[1] := UInt<3>(1)
    T_177681[2] := UInt<3>(2)
    wire T_177682 : UInt<0>[1]
    T_177682[0] := UInt<0>(0)
    wire T_177683 : UInt<2>[2]
    T_177683[0] := UInt<2>(1)
    T_177683[1] := UInt<2>(2)
    wire T_177684 : UInt<2>[2]
    T_177684[0] := UInt<2>(1)
    T_177684[1] := UInt<2>(2)
    wire T_177685 : UInt<2>[1]
    T_177685[0] := UInt<2>(2)
    wire T_177686 : UInt<3>[3]
    T_177686[0] := UInt<3>(0)
    T_177686[1] := UInt<3>(1)
    T_177686[2] := UInt<3>(2)
    wire T_177687 : UInt<0>[1]
    T_177687[0] := UInt<0>(0)
    wire T_177688 : UInt<2>[2]
    T_177688[0] := UInt<2>(1)
    T_177688[1] := UInt<2>(2)
    wire T_177689 : UInt<2>[2]
    T_177689[0] := UInt<2>(1)
    T_177689[1] := UInt<2>(2)
    wire T_177690 : UInt<2>[1]
    T_177690[0] := UInt<2>(2)
    wire T_177691 : UInt<3>[3]
    T_177691[0] := UInt<3>(0)
    T_177691[1] := UInt<3>(1)
    T_177691[2] := UInt<3>(2)
    wire T_177692 : UInt<0>[1]
    T_177692[0] := UInt<0>(0)
    wire T_177693 : UInt<2>[2]
    T_177693[0] := UInt<2>(1)
    T_177693[1] := UInt<2>(2)
    wire T_177694 : UInt<2>[2]
    T_177694[0] := UInt<2>(1)
    T_177694[1] := UInt<2>(2)
    wire T_177695 : UInt<2>[1]
    T_177695[0] := UInt<2>(2)
    wire T_177696 : UInt<3>[3]
    T_177696[0] := UInt<3>(0)
    T_177696[1] := UInt<3>(1)
    T_177696[2] := UInt<3>(2)
    wire T_177697 : UInt<0>[1]
    T_177697[0] := UInt<0>(0)
    wire T_177698 : UInt<2>[2]
    T_177698[0] := UInt<2>(1)
    T_177698[1] := UInt<2>(2)
    wire T_177699 : UInt<2>[2]
    T_177699[0] := UInt<2>(1)
    T_177699[1] := UInt<2>(2)
    wire T_177700 : UInt<2>[1]
    T_177700[0] := UInt<2>(2)
    wire T_177701 : UInt<3>[3]
    T_177701[0] := UInt<3>(0)
    T_177701[1] := UInt<3>(1)
    T_177701[2] := UInt<3>(2)
    wire T_177702 : UInt<0>[1]
    T_177702[0] := UInt<0>(0)
    wire T_177703 : UInt<2>[2]
    T_177703[0] := UInt<2>(1)
    T_177703[1] := UInt<2>(2)
    wire T_177704 : UInt<2>[2]
    T_177704[0] := UInt<2>(1)
    T_177704[1] := UInt<2>(2)
    wire T_177705 : UInt<2>[1]
    T_177705[0] := UInt<2>(2)
    wire T_177706 : UInt<3>[3]
    T_177706[0] := UInt<3>(0)
    T_177706[1] := UInt<3>(1)
    T_177706[2] := UInt<3>(2)
    wire T_177707 : UInt<0>[1]
    T_177707[0] := UInt<0>(0)
    wire T_177708 : UInt<2>[2]
    T_177708[0] := UInt<2>(1)
    T_177708[1] := UInt<2>(2)
    wire T_177709 : UInt<2>[2]
    T_177709[0] := UInt<2>(1)
    T_177709[1] := UInt<2>(2)
    wire T_177710 : UInt<2>[1]
    T_177710[0] := UInt<2>(2)
    wire T_177711 : UInt<3>[3]
    T_177711[0] := UInt<3>(0)
    T_177711[1] := UInt<3>(1)
    T_177711[2] := UInt<3>(2)
    wire T_177712 : UInt<0>[1]
    T_177712[0] := UInt<0>(0)
    wire T_177713 : UInt<2>[2]
    T_177713[0] := UInt<2>(1)
    T_177713[1] := UInt<2>(2)
    wire T_177714 : UInt<2>[2]
    T_177714[0] := UInt<2>(1)
    T_177714[1] := UInt<2>(2)
    wire T_177715 : UInt<2>[1]
    T_177715[0] := UInt<2>(2)
    wire T_177716 : UInt<3>[3]
    T_177716[0] := UInt<3>(0)
    T_177716[1] := UInt<3>(1)
    T_177716[2] := UInt<3>(2)
    wire T_177717 : UInt<0>[1]
    T_177717[0] := UInt<0>(0)
    wire T_177718 : UInt<2>[2]
    T_177718[0] := UInt<2>(1)
    T_177718[1] := UInt<2>(2)
    wire T_177719 : UInt<2>[2]
    T_177719[0] := UInt<2>(1)
    T_177719[1] := UInt<2>(2)
    wire T_177720 : UInt<2>[1]
    T_177720[0] := UInt<2>(2)
    wire in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[4]
    in[0] := T_177721
    in[1] := T_177722
    in[2] := T_177723
    in[3] := T_177724
    wire T_177725 : UInt<3>[3]
    T_177725[0] := UInt<3>(0)
    T_177725[1] := UInt<3>(1)
    T_177725[2] := UInt<3>(2)
    wire T_177726 : UInt<0>[1]
    T_177726[0] := UInt<0>(0)
    wire T_177727 : UInt<2>[2]
    T_177727[0] := UInt<2>(1)
    T_177727[1] := UInt<2>(2)
    wire T_177728 : UInt<2>[2]
    T_177728[0] := UInt<2>(1)
    T_177728[1] := UInt<2>(2)
    wire T_177729 : UInt<2>[1]
    T_177729[0] := UInt<2>(2)
    wire T_177730 : UInt<3>[3]
    T_177730[0] := UInt<3>(0)
    T_177730[1] := UInt<3>(1)
    T_177730[2] := UInt<3>(2)
    wire T_177731 : UInt<0>[1]
    T_177731[0] := UInt<0>(0)
    wire T_177732 : UInt<2>[2]
    T_177732[0] := UInt<2>(1)
    T_177732[1] := UInt<2>(2)
    wire T_177733 : UInt<2>[2]
    T_177733[0] := UInt<2>(1)
    T_177733[1] := UInt<2>(2)
    wire T_177734 : UInt<2>[1]
    T_177734[0] := UInt<2>(2)
    wire T_177735 : UInt<3>[3]
    T_177735[0] := UInt<3>(0)
    T_177735[1] := UInt<3>(1)
    T_177735[2] := UInt<3>(2)
    wire T_177736 : UInt<0>[1]
    T_177736[0] := UInt<0>(0)
    wire T_177737 : UInt<2>[2]
    T_177737[0] := UInt<2>(1)
    T_177737[1] := UInt<2>(2)
    wire T_177738 : UInt<2>[2]
    T_177738[0] := UInt<2>(1)
    T_177738[1] := UInt<2>(2)
    wire T_177739 : UInt<2>[1]
    T_177739[0] := UInt<2>(2)
    wire T_177740 : UInt<3>[3]
    T_177740[0] := UInt<3>(0)
    T_177740[1] := UInt<3>(1)
    T_177740[2] := UInt<3>(2)
    wire T_177741 : UInt<0>[1]
    T_177741[0] := UInt<0>(0)
    wire T_177742 : UInt<2>[2]
    T_177742[0] := UInt<2>(1)
    T_177742[1] := UInt<2>(2)
    wire T_177743 : UInt<2>[2]
    T_177743[0] := UInt<2>(1)
    T_177743[1] := UInt<2>(2)
    wire T_177744 : UInt<2>[1]
    T_177744[0] := UInt<2>(2)
    wire T_177745 : UInt<3>[3]
    T_177745[0] := UInt<3>(0)
    T_177745[1] := UInt<3>(1)
    T_177745[2] := UInt<3>(2)
    wire T_177746 : UInt<0>[1]
    T_177746[0] := UInt<0>(0)
    wire T_177747 : UInt<2>[2]
    T_177747[0] := UInt<2>(1)
    T_177747[1] := UInt<2>(2)
    wire T_177748 : UInt<2>[2]
    T_177748[0] := UInt<2>(1)
    T_177748[1] := UInt<2>(2)
    wire T_177749 : UInt<2>[1]
    T_177749[0] := UInt<2>(2)
    wire T_177750 : UInt<3>[3]
    T_177750[0] := UInt<3>(0)
    T_177750[1] := UInt<3>(1)
    T_177750[2] := UInt<3>(2)
    wire T_177751 : UInt<0>[1]
    T_177751[0] := UInt<0>(0)
    wire T_177752 : UInt<2>[2]
    T_177752[0] := UInt<2>(1)
    T_177752[1] := UInt<2>(2)
    wire T_177753 : UInt<2>[2]
    T_177753[0] := UInt<2>(1)
    T_177753[1] := UInt<2>(2)
    wire T_177754 : UInt<2>[1]
    T_177754[0] := UInt<2>(2)
    wire T_177755 : UInt<3>[3]
    T_177755[0] := UInt<3>(0)
    T_177755[1] := UInt<3>(1)
    T_177755[2] := UInt<3>(2)
    wire T_177756 : UInt<0>[1]
    T_177756[0] := UInt<0>(0)
    wire T_177757 : UInt<2>[2]
    T_177757[0] := UInt<2>(1)
    T_177757[1] := UInt<2>(2)
    wire T_177758 : UInt<2>[2]
    T_177758[0] := UInt<2>(1)
    T_177758[1] := UInt<2>(2)
    wire T_177759 : UInt<2>[1]
    T_177759[0] := UInt<2>(2)
    wire T_177760 : UInt<3>[3]
    T_177760[0] := UInt<3>(0)
    T_177760[1] := UInt<3>(1)
    T_177760[2] := UInt<3>(2)
    wire T_177761 : UInt<0>[1]
    T_177761[0] := UInt<0>(0)
    wire T_177762 : UInt<2>[2]
    T_177762[0] := UInt<2>(1)
    T_177762[1] := UInt<2>(2)
    wire T_177763 : UInt<2>[2]
    T_177763[0] := UInt<2>(1)
    T_177763[1] := UInt<2>(2)
    wire T_177764 : UInt<2>[1]
    T_177764[0] := UInt<2>(2)
    wire T_177765 : UInt<3>[3]
    T_177765[0] := UInt<3>(0)
    T_177765[1] := UInt<3>(1)
    T_177765[2] := UInt<3>(2)
    wire T_177766 : UInt<0>[1]
    T_177766[0] := UInt<0>(0)
    wire T_177767 : UInt<2>[2]
    T_177767[0] := UInt<2>(1)
    T_177767[1] := UInt<2>(2)
    wire T_177768 : UInt<2>[2]
    T_177768[0] := UInt<2>(1)
    T_177768[1] := UInt<2>(2)
    wire T_177769 : UInt<2>[1]
    T_177769[0] := UInt<2>(2)
    inst T_177770 of LockingRRArbiter_104277
    T_177770.in[0].valid := in[0].acquire.valid
    T_177770.in[0].bits := in[0].acquire.bits
    node T_177771 = cat(in[0].acquire.bits.client_xact_id, UInt<2>(0))
    T_177770.in[0].bits.client_xact_id := T_177771
    in[0].acquire.ready := T_177770.in[0].ready
    T_177770.in[1].valid := in[1].acquire.valid
    T_177770.in[1].bits := in[1].acquire.bits
    node T_177772 = cat(in[1].acquire.bits.client_xact_id, UInt<2>(1))
    T_177770.in[1].bits.client_xact_id := T_177772
    in[1].acquire.ready := T_177770.in[1].ready
    T_177770.in[2].valid := in[2].acquire.valid
    T_177770.in[2].bits := in[2].acquire.bits
    node T_177773 = cat(in[2].acquire.bits.client_xact_id, UInt<2>(2))
    T_177770.in[2].bits.client_xact_id := T_177773
    in[2].acquire.ready := T_177770.in[2].ready
    T_177770.in[3].valid := in[3].acquire.valid
    T_177770.in[3].bits := in[3].acquire.bits
    node T_177774 = cat(in[3].acquire.bits.client_xact_id, UInt<2>(3))
    T_177770.in[3].bits.client_xact_id := T_177774
    in[3].acquire.ready := T_177770.in[3].ready
    T_177770.out <> out.acquire
    inst T_177775 of LockingRRArbiter_104925
    T_177775.in[0].valid := in[0].release.valid
    T_177775.in[0].bits := in[0].release.bits
    node T_177776 = cat(in[0].release.bits.client_xact_id, UInt<2>(0))
    T_177775.in[0].bits.client_xact_id := T_177776
    in[0].release.ready := T_177775.in[0].ready
    T_177775.in[1].valid := in[1].release.valid
    T_177775.in[1].bits := in[1].release.bits
    node T_177777 = cat(in[1].release.bits.client_xact_id, UInt<2>(1))
    T_177775.in[1].bits.client_xact_id := T_177777
    in[1].release.ready := T_177775.in[1].ready
    T_177775.in[2].valid := in[2].release.valid
    T_177775.in[2].bits := in[2].release.bits
    node T_177778 = cat(in[2].release.bits.client_xact_id, UInt<2>(2))
    T_177775.in[2].bits.client_xact_id := T_177778
    in[2].release.ready := T_177775.in[2].ready
    T_177775.in[3].valid := in[3].release.valid
    T_177775.in[3].bits := in[3].release.bits
    node T_177779 = cat(in[3].release.bits.client_xact_id, UInt<2>(3))
    T_177775.in[3].bits.client_xact_id := T_177779
    in[3].release.ready := T_177775.in[3].ready
    T_177775.out <> out.release
    in[0].probe.valid := out.probe.valid
    in[1].probe.valid := out.probe.valid
    in[2].probe.valid := out.probe.valid
    in[3].probe.valid := out.probe.valid
    in[0].probe.bits := out.probe.bits
    in[1].probe.bits := out.probe.bits
    in[2].probe.bits := out.probe.bits
    in[3].probe.bits := out.probe.bits
    node T_177780 = and(in[0].probe.ready, in[1].probe.ready)
    node T_177781 = and(T_177780, in[2].probe.ready)
    node T_177782 = and(T_177781, in[3].probe.ready)
    out.probe.ready := T_177782
    out.grant.ready := UInt<1>(0)
    in[0].grant.valid := UInt<1>(0)
    
    
    node T_177783 = bits(out.grant.bits.client_xact_id, 1, 0)
    node T_177784 = eq(T_177783, UInt<1>(0))
    when T_177784 : 
      in[0].grant.valid := out.grant.valid
      out.grant.ready := in[0].grant.ready
    in[0].grant.bits := out.grant.bits
    node T_177785 = dshr(out.grant.bits.client_xact_id, UInt<2>(2))
    in[0].grant.bits.client_xact_id := T_177785
    in[1].grant.valid := UInt<1>(0)
    
    
    node T_177786 = bits(out.grant.bits.client_xact_id, 1, 0)
    node T_177787 = eq(T_177786, UInt<1>(1))
    when T_177787 : 
      in[1].grant.valid := out.grant.valid
      out.grant.ready := in[1].grant.ready
    in[1].grant.bits := out.grant.bits
    node T_177788 = dshr(out.grant.bits.client_xact_id, UInt<2>(2))
    in[1].grant.bits.client_xact_id := T_177788
    in[2].grant.valid := UInt<1>(0)
    
    
    node T_177789 = bits(out.grant.bits.client_xact_id, 1, 0)
    node T_177790 = eq(T_177789, UInt<2>(2))
    when T_177790 : 
      in[2].grant.valid := out.grant.valid
      out.grant.ready := in[2].grant.ready
    in[2].grant.bits := out.grant.bits
    node T_177791 = dshr(out.grant.bits.client_xact_id, UInt<2>(2))
    in[2].grant.bits.client_xact_id := T_177791
    in[3].grant.valid := UInt<1>(0)
    
    
    node T_177792 = bits(out.grant.bits.client_xact_id, 1, 0)
    node T_177793 = eq(T_177792, UInt<2>(3))
    when T_177793 : 
      in[3].grant.valid := out.grant.valid
      out.grant.ready := in[3].grant.ready
    in[3].grant.bits := out.grant.bits
    node T_177794 = dshr(out.grant.bits.client_xact_id, UInt<2>(2))
    in[3].grant.bits.client_xact_id := T_177794
  module RRArbiter_105103 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}
    output chosen : UInt<2>
    
    wire T_177795 : UInt<2>
    reg T_177796 : UInt<2>
    onreset T_177796 := UInt<2>(0)
    node T_177797 = gt(UInt<1>(0), T_177796)
    node T_177798 = and(in[0].valid, T_177797)
    node T_177799 = gt(UInt<1>(1), T_177796)
    node T_177800 = and(in[1].valid, T_177799)
    node T_177801 = gt(UInt<2>(2), T_177796)
    node T_177802 = and(in[2].valid, T_177801)
    node T_177803 = or(UInt<1>(0), T_177798)
    node T_177804 = eq(T_177803, UInt<1>(0))
    node T_177805 = or(UInt<1>(0), T_177798)
    node T_177806 = or(T_177805, T_177800)
    node T_177807 = eq(T_177806, UInt<1>(0))
    node T_177808 = or(UInt<1>(0), T_177798)
    node T_177809 = or(T_177808, T_177800)
    node T_177810 = or(T_177809, T_177802)
    node T_177811 = eq(T_177810, UInt<1>(0))
    node T_177812 = or(UInt<1>(0), T_177798)
    node T_177813 = or(T_177812, T_177800)
    node T_177814 = or(T_177813, T_177802)
    node T_177815 = or(T_177814, in[0].valid)
    node T_177816 = eq(T_177815, UInt<1>(0))
    node T_177817 = or(UInt<1>(0), T_177798)
    node T_177818 = or(T_177817, T_177800)
    node T_177819 = or(T_177818, T_177802)
    node T_177820 = or(T_177819, in[0].valid)
    node T_177821 = or(T_177820, in[1].valid)
    node T_177822 = eq(T_177821, UInt<1>(0))
    node T_177823 = gt(UInt<1>(0), T_177796)
    node T_177824 = and(UInt<1>(1), T_177823)
    node T_177825 = or(T_177824, T_177811)
    node T_177826 = gt(UInt<1>(1), T_177796)
    node T_177827 = and(T_177804, T_177826)
    node T_177828 = or(T_177827, T_177816)
    node T_177829 = gt(UInt<2>(2), T_177796)
    node T_177830 = and(T_177807, T_177829)
    node T_177831 = or(T_177830, T_177822)
    node T_177832 = eq(UInt<2>(2), UInt<1>(0))
    wire T_177833 : UInt<1>
    T_177833 := T_177825
    when UInt<1>(0) : T_177833 := T_177832
    node T_177834 = and(T_177833, out.ready)
    in[0].ready := T_177834
    node T_177835 = eq(UInt<2>(2), UInt<1>(1))
    wire T_177836 : UInt<1>
    T_177836 := T_177828
    when UInt<1>(0) : T_177836 := T_177835
    node T_177837 = and(T_177836, out.ready)
    in[1].ready := T_177837
    node T_177838 = eq(UInt<2>(2), UInt<2>(2))
    wire T_177839 : UInt<1>
    T_177839 := T_177831
    when UInt<1>(0) : T_177839 := T_177838
    node T_177840 = and(T_177839, out.ready)
    in[2].ready := T_177840
    accessor T_177841 = in[T_177795]
    out.valid := T_177841.valid
    accessor T_177842 = in[T_177795]
    out.bits := T_177842.bits
    chosen := T_177795
    wire T_177843 : UInt<2>
    T_177843 := UInt<2>(2)
    when in[1].valid : T_177843 := UInt<1>(1)
    wire T_177844 : UInt<2>
    T_177844 := T_177843
    when in[0].valid : T_177844 := UInt<1>(0)
    node T_177845 = gt(UInt<2>(2), T_177796)
    node T_177846 = and(in[2].valid, T_177845)
    wire T_177847 : UInt<2>
    T_177847 := T_177844
    when T_177846 : T_177847 := UInt<2>(2)
    node T_177848 = gt(UInt<1>(1), T_177796)
    node T_177849 = and(in[1].valid, T_177848)
    wire T_177850 : UInt<2>
    T_177850 := T_177847
    when T_177849 : T_177850 := UInt<1>(1)
    wire T_177851 : UInt<2>
    T_177851 := T_177850
    when UInt<1>(0) : T_177851 := UInt<2>(2)
    T_177795 := T_177851
    
    node T_177852 = and(out.ready, out.valid)
    when T_177852 : T_177796 := T_177795
  module RRArbiter_107737 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}
    output chosen : UInt<2>
    
    wire T_177853 : UInt<3>[3]
    T_177853[0] := UInt<3>(0)
    T_177853[1] := UInt<3>(1)
    T_177853[2] := UInt<3>(2)
    wire T_177854 : UInt<2>[2]
    T_177854[0] := UInt<2>(0)
    T_177854[1] := UInt<2>(1)
    wire T_177855 : UInt<2>[3]
    T_177855[0] := UInt<2>(1)
    T_177855[1] := UInt<2>(2)
    T_177855[2] := UInt<2>(3)
    wire T_177856 : UInt<2>[2]
    T_177856[0] := UInt<2>(2)
    T_177856[1] := UInt<2>(3)
    wire T_177857 : UInt<2>[1]
    T_177857[0] := UInt<2>(3)
    wire T_177858 : UInt<3>[3]
    T_177858[0] := UInt<3>(0)
    T_177858[1] := UInt<3>(1)
    T_177858[2] := UInt<3>(2)
    wire T_177859 : UInt<2>[2]
    T_177859[0] := UInt<2>(0)
    T_177859[1] := UInt<2>(1)
    wire T_177860 : UInt<2>[3]
    T_177860[0] := UInt<2>(1)
    T_177860[1] := UInt<2>(2)
    T_177860[2] := UInt<2>(3)
    wire T_177861 : UInt<2>[2]
    T_177861[0] := UInt<2>(2)
    T_177861[1] := UInt<2>(3)
    wire T_177862 : UInt<2>[1]
    T_177862[0] := UInt<2>(3)
    wire T_177863 : UInt<3>[3]
    T_177863[0] := UInt<3>(0)
    T_177863[1] := UInt<3>(1)
    T_177863[2] := UInt<3>(2)
    wire T_177864 : UInt<0>[1]
    T_177864[0] := UInt<0>(0)
    wire T_177865 : UInt<2>[2]
    T_177865[0] := UInt<2>(1)
    T_177865[1] := UInt<2>(2)
    wire T_177866 : UInt<2>[2]
    T_177866[0] := UInt<2>(1)
    T_177866[1] := UInt<2>(2)
    wire T_177867 : UInt<2>[1]
    T_177867[0] := UInt<2>(2)
    wire T_177868 : UInt<3>[3]
    T_177868[0] := UInt<3>(0)
    T_177868[1] := UInt<3>(1)
    T_177868[2] := UInt<3>(2)
    wire T_177869 : UInt<2>[2]
    T_177869[0] := UInt<2>(0)
    T_177869[1] := UInt<2>(1)
    wire T_177870 : UInt<2>[3]
    T_177870[0] := UInt<2>(1)
    T_177870[1] := UInt<2>(2)
    T_177870[2] := UInt<2>(3)
    wire T_177871 : UInt<2>[2]
    T_177871[0] := UInt<2>(2)
    T_177871[1] := UInt<2>(3)
    wire T_177872 : UInt<2>[1]
    T_177872[0] := UInt<2>(3)
    wire T_177873 : UInt<3>[3]
    T_177873[0] := UInt<3>(0)
    T_177873[1] := UInt<3>(1)
    T_177873[2] := UInt<3>(2)
    wire T_177874 : UInt<2>[2]
    T_177874[0] := UInt<2>(0)
    T_177874[1] := UInt<2>(1)
    wire T_177875 : UInt<2>[3]
    T_177875[0] := UInt<2>(1)
    T_177875[1] := UInt<2>(2)
    T_177875[2] := UInt<2>(3)
    wire T_177876 : UInt<2>[2]
    T_177876[0] := UInt<2>(2)
    T_177876[1] := UInt<2>(3)
    wire T_177877 : UInt<2>[1]
    T_177877[0] := UInt<2>(3)
    wire T_177878 : UInt<3>[3]
    T_177878[0] := UInt<3>(0)
    T_177878[1] := UInt<3>(1)
    T_177878[2] := UInt<3>(2)
    wire T_177879 : UInt<0>[1]
    T_177879[0] := UInt<0>(0)
    wire T_177880 : UInt<2>[2]
    T_177880[0] := UInt<2>(1)
    T_177880[1] := UInt<2>(2)
    wire T_177881 : UInt<2>[2]
    T_177881[0] := UInt<2>(1)
    T_177881[1] := UInt<2>(2)
    wire T_177882 : UInt<2>[1]
    T_177882[0] := UInt<2>(2)
    wire T_177883 : UInt<3>[3]
    T_177883[0] := UInt<3>(0)
    T_177883[1] := UInt<3>(1)
    T_177883[2] := UInt<3>(2)
    wire T_177884 : UInt<2>[2]
    T_177884[0] := UInt<2>(0)
    T_177884[1] := UInt<2>(1)
    wire T_177885 : UInt<2>[3]
    T_177885[0] := UInt<2>(1)
    T_177885[1] := UInt<2>(2)
    T_177885[2] := UInt<2>(3)
    wire T_177886 : UInt<2>[2]
    T_177886[0] := UInt<2>(2)
    T_177886[1] := UInt<2>(3)
    wire T_177887 : UInt<2>[1]
    T_177887[0] := UInt<2>(3)
    wire T_177888 : UInt<3>[3]
    T_177888[0] := UInt<3>(0)
    T_177888[1] := UInt<3>(1)
    T_177888[2] := UInt<3>(2)
    wire T_177889 : UInt<2>[2]
    T_177889[0] := UInt<2>(0)
    T_177889[1] := UInt<2>(1)
    wire T_177890 : UInt<2>[3]
    T_177890[0] := UInt<2>(1)
    T_177890[1] := UInt<2>(2)
    T_177890[2] := UInt<2>(3)
    wire T_177891 : UInt<2>[2]
    T_177891[0] := UInt<2>(2)
    T_177891[1] := UInt<2>(3)
    wire T_177892 : UInt<2>[1]
    T_177892[0] := UInt<2>(3)
    wire T_177893 : UInt<3>[3]
    T_177893[0] := UInt<3>(0)
    T_177893[1] := UInt<3>(1)
    T_177893[2] := UInt<3>(2)
    wire T_177894 : UInt<0>[1]
    T_177894[0] := UInt<0>(0)
    wire T_177895 : UInt<2>[2]
    T_177895[0] := UInt<2>(1)
    T_177895[1] := UInt<2>(2)
    wire T_177896 : UInt<2>[2]
    T_177896[0] := UInt<2>(1)
    T_177896[1] := UInt<2>(2)
    wire T_177897 : UInt<2>[1]
    T_177897[0] := UInt<2>(2)
    wire T_177898 : UInt<3>[3]
    T_177898[0] := UInt<3>(0)
    T_177898[1] := UInt<3>(1)
    T_177898[2] := UInt<3>(2)
    wire T_177899 : UInt<2>[2]
    T_177899[0] := UInt<2>(0)
    T_177899[1] := UInt<2>(1)
    wire T_177900 : UInt<2>[3]
    T_177900[0] := UInt<2>(1)
    T_177900[1] := UInt<2>(2)
    T_177900[2] := UInt<2>(3)
    wire T_177901 : UInt<2>[2]
    T_177901[0] := UInt<2>(2)
    T_177901[1] := UInt<2>(3)
    wire T_177902 : UInt<2>[1]
    T_177902[0] := UInt<2>(3)
    wire T_177903 : UInt<3>[3]
    T_177903[0] := UInt<3>(0)
    T_177903[1] := UInt<3>(1)
    T_177903[2] := UInt<3>(2)
    wire T_177904 : UInt<2>[2]
    T_177904[0] := UInt<2>(0)
    T_177904[1] := UInt<2>(1)
    wire T_177905 : UInt<2>[3]
    T_177905[0] := UInt<2>(1)
    T_177905[1] := UInt<2>(2)
    T_177905[2] := UInt<2>(3)
    wire T_177906 : UInt<2>[2]
    T_177906[0] := UInt<2>(2)
    T_177906[1] := UInt<2>(3)
    wire T_177907 : UInt<2>[1]
    T_177907[0] := UInt<2>(3)
    wire T_177908 : UInt<3>[3]
    T_177908[0] := UInt<3>(0)
    T_177908[1] := UInt<3>(1)
    T_177908[2] := UInt<3>(2)
    wire T_177909 : UInt<0>[1]
    T_177909[0] := UInt<0>(0)
    wire T_177910 : UInt<2>[2]
    T_177910[0] := UInt<2>(1)
    T_177910[1] := UInt<2>(2)
    wire T_177911 : UInt<2>[2]
    T_177911[0] := UInt<2>(1)
    T_177911[1] := UInt<2>(2)
    wire T_177912 : UInt<2>[1]
    T_177912[0] := UInt<2>(2)
    wire T_177913 : UInt<3>[3]
    T_177913[0] := UInt<3>(0)
    T_177913[1] := UInt<3>(1)
    T_177913[2] := UInt<3>(2)
    wire T_177914 : UInt<2>[2]
    T_177914[0] := UInt<2>(0)
    T_177914[1] := UInt<2>(1)
    wire T_177915 : UInt<2>[3]
    T_177915[0] := UInt<2>(1)
    T_177915[1] := UInt<2>(2)
    T_177915[2] := UInt<2>(3)
    wire T_177916 : UInt<2>[2]
    T_177916[0] := UInt<2>(2)
    T_177916[1] := UInt<2>(3)
    wire T_177917 : UInt<2>[1]
    T_177917[0] := UInt<2>(3)
    wire T_177918 : UInt<3>[3]
    T_177918[0] := UInt<3>(0)
    T_177918[1] := UInt<3>(1)
    T_177918[2] := UInt<3>(2)
    wire T_177919 : UInt<2>[2]
    T_177919[0] := UInt<2>(0)
    T_177919[1] := UInt<2>(1)
    wire T_177920 : UInt<2>[3]
    T_177920[0] := UInt<2>(1)
    T_177920[1] := UInt<2>(2)
    T_177920[2] := UInt<2>(3)
    wire T_177921 : UInt<2>[2]
    T_177921[0] := UInt<2>(2)
    T_177921[1] := UInt<2>(3)
    wire T_177922 : UInt<2>[1]
    T_177922[0] := UInt<2>(3)
    wire T_177923 : UInt<3>[3]
    T_177923[0] := UInt<3>(0)
    T_177923[1] := UInt<3>(1)
    T_177923[2] := UInt<3>(2)
    wire T_177924 : UInt<0>[1]
    T_177924[0] := UInt<0>(0)
    wire T_177925 : UInt<2>[2]
    T_177925[0] := UInt<2>(1)
    T_177925[1] := UInt<2>(2)
    wire T_177926 : UInt<2>[2]
    T_177926[0] := UInt<2>(1)
    T_177926[1] := UInt<2>(2)
    wire T_177927 : UInt<2>[1]
    T_177927[0] := UInt<2>(2)
    wire T_177928 : UInt<3>[3]
    T_177928[0] := UInt<3>(0)
    T_177928[1] := UInt<3>(1)
    T_177928[2] := UInt<3>(2)
    wire T_177929 : UInt<2>[2]
    T_177929[0] := UInt<2>(0)
    T_177929[1] := UInt<2>(1)
    wire T_177930 : UInt<2>[3]
    T_177930[0] := UInt<2>(1)
    T_177930[1] := UInt<2>(2)
    T_177930[2] := UInt<2>(3)
    wire T_177931 : UInt<2>[2]
    T_177931[0] := UInt<2>(2)
    T_177931[1] := UInt<2>(3)
    wire T_177932 : UInt<2>[1]
    T_177932[0] := UInt<2>(3)
    wire T_177933 : UInt<3>[3]
    T_177933[0] := UInt<3>(0)
    T_177933[1] := UInt<3>(1)
    T_177933[2] := UInt<3>(2)
    wire T_177934 : UInt<2>[2]
    T_177934[0] := UInt<2>(0)
    T_177934[1] := UInt<2>(1)
    wire T_177935 : UInt<2>[3]
    T_177935[0] := UInt<2>(1)
    T_177935[1] := UInt<2>(2)
    T_177935[2] := UInt<2>(3)
    wire T_177936 : UInt<2>[2]
    T_177936[0] := UInt<2>(2)
    T_177936[1] := UInt<2>(3)
    wire T_177937 : UInt<2>[1]
    T_177937[0] := UInt<2>(3)
    wire T_177938 : UInt<3>[3]
    T_177938[0] := UInt<3>(0)
    T_177938[1] := UInt<3>(1)
    T_177938[2] := UInt<3>(2)
    wire T_177939 : UInt<0>[1]
    T_177939[0] := UInt<0>(0)
    wire T_177940 : UInt<2>[2]
    T_177940[0] := UInt<2>(1)
    T_177940[1] := UInt<2>(2)
    wire T_177941 : UInt<2>[2]
    T_177941[0] := UInt<2>(1)
    T_177941[1] := UInt<2>(2)
    wire T_177942 : UInt<2>[1]
    T_177942[0] := UInt<2>(2)
    wire T_177943 : UInt<3>[3]
    T_177943[0] := UInt<3>(0)
    T_177943[1] := UInt<3>(1)
    T_177943[2] := UInt<3>(2)
    wire T_177944 : UInt<2>[2]
    T_177944[0] := UInt<2>(0)
    T_177944[1] := UInt<2>(1)
    wire T_177945 : UInt<2>[3]
    T_177945[0] := UInt<2>(1)
    T_177945[1] := UInt<2>(2)
    T_177945[2] := UInt<2>(3)
    wire T_177946 : UInt<2>[2]
    T_177946[0] := UInt<2>(2)
    T_177946[1] := UInt<2>(3)
    wire T_177947 : UInt<2>[1]
    T_177947[0] := UInt<2>(3)
    wire T_177948 : UInt<3>[3]
    T_177948[0] := UInt<3>(0)
    T_177948[1] := UInt<3>(1)
    T_177948[2] := UInt<3>(2)
    wire T_177949 : UInt<2>[2]
    T_177949[0] := UInt<2>(0)
    T_177949[1] := UInt<2>(1)
    wire T_177950 : UInt<2>[3]
    T_177950[0] := UInt<2>(1)
    T_177950[1] := UInt<2>(2)
    T_177950[2] := UInt<2>(3)
    wire T_177951 : UInt<2>[2]
    T_177951[0] := UInt<2>(2)
    T_177951[1] := UInt<2>(3)
    wire T_177952 : UInt<2>[1]
    T_177952[0] := UInt<2>(3)
    wire T_177953 : UInt<3>[3]
    T_177953[0] := UInt<3>(0)
    T_177953[1] := UInt<3>(1)
    T_177953[2] := UInt<3>(2)
    wire T_177954 : UInt<0>[1]
    T_177954[0] := UInt<0>(0)
    wire T_177955 : UInt<2>[2]
    T_177955[0] := UInt<2>(1)
    T_177955[1] := UInt<2>(2)
    wire T_177956 : UInt<2>[2]
    T_177956[0] := UInt<2>(1)
    T_177956[1] := UInt<2>(2)
    wire T_177957 : UInt<2>[1]
    T_177957[0] := UInt<2>(2)
    wire T_177958 : UInt<3>[3]
    T_177958[0] := UInt<3>(0)
    T_177958[1] := UInt<3>(1)
    T_177958[2] := UInt<3>(2)
    wire T_177959 : UInt<2>[2]
    T_177959[0] := UInt<2>(0)
    T_177959[1] := UInt<2>(1)
    wire T_177960 : UInt<2>[3]
    T_177960[0] := UInt<2>(1)
    T_177960[1] := UInt<2>(2)
    T_177960[2] := UInt<2>(3)
    wire T_177961 : UInt<2>[2]
    T_177961[0] := UInt<2>(2)
    T_177961[1] := UInt<2>(3)
    wire T_177962 : UInt<2>[1]
    T_177962[0] := UInt<2>(3)
    wire T_177963 : UInt<3>[3]
    T_177963[0] := UInt<3>(0)
    T_177963[1] := UInt<3>(1)
    T_177963[2] := UInt<3>(2)
    wire T_177964 : UInt<2>[2]
    T_177964[0] := UInt<2>(0)
    T_177964[1] := UInt<2>(1)
    wire T_177965 : UInt<2>[3]
    T_177965[0] := UInt<2>(1)
    T_177965[1] := UInt<2>(2)
    T_177965[2] := UInt<2>(3)
    wire T_177966 : UInt<2>[2]
    T_177966[0] := UInt<2>(2)
    T_177966[1] := UInt<2>(3)
    wire T_177967 : UInt<2>[1]
    T_177967[0] := UInt<2>(3)
    wire T_177968 : UInt<3>[3]
    T_177968[0] := UInt<3>(0)
    T_177968[1] := UInt<3>(1)
    T_177968[2] := UInt<3>(2)
    wire T_177969 : UInt<0>[1]
    T_177969[0] := UInt<0>(0)
    wire T_177970 : UInt<2>[2]
    T_177970[0] := UInt<2>(1)
    T_177970[1] := UInt<2>(2)
    wire T_177971 : UInt<2>[2]
    T_177971[0] := UInt<2>(1)
    T_177971[1] := UInt<2>(2)
    wire T_177972 : UInt<2>[1]
    T_177972[0] := UInt<2>(2)
    wire T_177973 : UInt<3>[3]
    T_177973[0] := UInt<3>(0)
    T_177973[1] := UInt<3>(1)
    T_177973[2] := UInt<3>(2)
    wire T_177974 : UInt<2>[2]
    T_177974[0] := UInt<2>(0)
    T_177974[1] := UInt<2>(1)
    wire T_177975 : UInt<2>[3]
    T_177975[0] := UInt<2>(1)
    T_177975[1] := UInt<2>(2)
    T_177975[2] := UInt<2>(3)
    wire T_177976 : UInt<2>[2]
    T_177976[0] := UInt<2>(2)
    T_177976[1] := UInt<2>(3)
    wire T_177977 : UInt<2>[1]
    T_177977[0] := UInt<2>(3)
    wire T_177978 : UInt<3>[3]
    T_177978[0] := UInt<3>(0)
    T_177978[1] := UInt<3>(1)
    T_177978[2] := UInt<3>(2)
    wire T_177979 : UInt<2>[2]
    T_177979[0] := UInt<2>(0)
    T_177979[1] := UInt<2>(1)
    wire T_177980 : UInt<2>[3]
    T_177980[0] := UInt<2>(1)
    T_177980[1] := UInt<2>(2)
    T_177980[2] := UInt<2>(3)
    wire T_177981 : UInt<2>[2]
    T_177981[0] := UInt<2>(2)
    T_177981[1] := UInt<2>(3)
    wire T_177982 : UInt<2>[1]
    T_177982[0] := UInt<2>(3)
    wire T_177983 : UInt<3>[3]
    T_177983[0] := UInt<3>(0)
    T_177983[1] := UInt<3>(1)
    T_177983[2] := UInt<3>(2)
    wire T_177984 : UInt<0>[1]
    T_177984[0] := UInt<0>(0)
    wire T_177985 : UInt<2>[2]
    T_177985[0] := UInt<2>(1)
    T_177985[1] := UInt<2>(2)
    wire T_177986 : UInt<2>[2]
    T_177986[0] := UInt<2>(1)
    T_177986[1] := UInt<2>(2)
    wire T_177987 : UInt<2>[1]
    T_177987[0] := UInt<2>(2)
    wire T_177988 : UInt<3>[3]
    T_177988[0] := UInt<3>(0)
    T_177988[1] := UInt<3>(1)
    T_177988[2] := UInt<3>(2)
    wire T_177989 : UInt<2>[2]
    T_177989[0] := UInt<2>(0)
    T_177989[1] := UInt<2>(1)
    wire T_177990 : UInt<2>[3]
    T_177990[0] := UInt<2>(1)
    T_177990[1] := UInt<2>(2)
    T_177990[2] := UInt<2>(3)
    wire T_177991 : UInt<2>[2]
    T_177991[0] := UInt<2>(2)
    T_177991[1] := UInt<2>(3)
    wire T_177992 : UInt<2>[1]
    T_177992[0] := UInt<2>(3)
    wire T_177993 : UInt<3>[3]
    T_177993[0] := UInt<3>(0)
    T_177993[1] := UInt<3>(1)
    T_177993[2] := UInt<3>(2)
    wire T_177994 : UInt<2>[2]
    T_177994[0] := UInt<2>(0)
    T_177994[1] := UInt<2>(1)
    wire T_177995 : UInt<2>[3]
    T_177995[0] := UInt<2>(1)
    T_177995[1] := UInt<2>(2)
    T_177995[2] := UInt<2>(3)
    wire T_177996 : UInt<2>[2]
    T_177996[0] := UInt<2>(2)
    T_177996[1] := UInt<2>(3)
    wire T_177997 : UInt<2>[1]
    T_177997[0] := UInt<2>(3)
    wire T_177998 : UInt<3>[3]
    T_177998[0] := UInt<3>(0)
    T_177998[1] := UInt<3>(1)
    T_177998[2] := UInt<3>(2)
    wire T_177999 : UInt<0>[1]
    T_177999[0] := UInt<0>(0)
    wire T_178000 : UInt<2>[2]
    T_178000[0] := UInt<2>(1)
    T_178000[1] := UInt<2>(2)
    wire T_178001 : UInt<2>[2]
    T_178001[0] := UInt<2>(1)
    T_178001[1] := UInt<2>(2)
    wire T_178002 : UInt<2>[1]
    T_178002[0] := UInt<2>(2)
    wire T_178003 : UInt<2>
    reg T_178004 : UInt<2>
    onreset T_178004 := UInt<2>(0)
    node T_178005 = gt(UInt<1>(0), T_178004)
    node T_178006 = and(in[0].valid, T_178005)
    node T_178007 = gt(UInt<1>(1), T_178004)
    node T_178008 = and(in[1].valid, T_178007)
    node T_178009 = gt(UInt<2>(2), T_178004)
    node T_178010 = and(in[2].valid, T_178009)
    node T_178011 = or(UInt<1>(0), T_178006)
    node T_178012 = eq(T_178011, UInt<1>(0))
    node T_178013 = or(UInt<1>(0), T_178006)
    node T_178014 = or(T_178013, T_178008)
    node T_178015 = eq(T_178014, UInt<1>(0))
    node T_178016 = or(UInt<1>(0), T_178006)
    node T_178017 = or(T_178016, T_178008)
    node T_178018 = or(T_178017, T_178010)
    node T_178019 = eq(T_178018, UInt<1>(0))
    node T_178020 = or(UInt<1>(0), T_178006)
    node T_178021 = or(T_178020, T_178008)
    node T_178022 = or(T_178021, T_178010)
    node T_178023 = or(T_178022, in[0].valid)
    node T_178024 = eq(T_178023, UInt<1>(0))
    node T_178025 = or(UInt<1>(0), T_178006)
    node T_178026 = or(T_178025, T_178008)
    node T_178027 = or(T_178026, T_178010)
    node T_178028 = or(T_178027, in[0].valid)
    node T_178029 = or(T_178028, in[1].valid)
    node T_178030 = eq(T_178029, UInt<1>(0))
    node T_178031 = gt(UInt<1>(0), T_178004)
    node T_178032 = and(UInt<1>(1), T_178031)
    node T_178033 = or(T_178032, T_178019)
    node T_178034 = gt(UInt<1>(1), T_178004)
    node T_178035 = and(T_178012, T_178034)
    node T_178036 = or(T_178035, T_178024)
    node T_178037 = gt(UInt<2>(2), T_178004)
    node T_178038 = and(T_178015, T_178037)
    node T_178039 = or(T_178038, T_178030)
    node T_178040 = eq(UInt<2>(2), UInt<1>(0))
    wire T_178041 : UInt<1>
    T_178041 := T_178033
    when UInt<1>(0) : T_178041 := T_178040
    node T_178042 = and(T_178041, out.ready)
    in[0].ready := T_178042
    node T_178043 = eq(UInt<2>(2), UInt<1>(1))
    wire T_178044 : UInt<1>
    T_178044 := T_178036
    when UInt<1>(0) : T_178044 := T_178043
    node T_178045 = and(T_178044, out.ready)
    in[1].ready := T_178045
    node T_178046 = eq(UInt<2>(2), UInt<2>(2))
    wire T_178047 : UInt<1>
    T_178047 := T_178039
    when UInt<1>(0) : T_178047 := T_178046
    node T_178048 = and(T_178047, out.ready)
    in[2].ready := T_178048
    wire T_178049 : UInt<3>[3]
    T_178049[0] := UInt<3>(0)
    T_178049[1] := UInt<3>(1)
    T_178049[2] := UInt<3>(2)
    wire T_178050 : UInt<2>[2]
    T_178050[0] := UInt<2>(0)
    T_178050[1] := UInt<2>(1)
    wire T_178051 : UInt<2>[3]
    T_178051[0] := UInt<2>(1)
    T_178051[1] := UInt<2>(2)
    T_178051[2] := UInt<2>(3)
    wire T_178052 : UInt<2>[2]
    T_178052[0] := UInt<2>(2)
    T_178052[1] := UInt<2>(3)
    wire T_178053 : UInt<2>[1]
    T_178053[0] := UInt<2>(3)
    wire T_178054 : UInt<3>[3]
    T_178054[0] := UInt<3>(0)
    T_178054[1] := UInt<3>(1)
    T_178054[2] := UInt<3>(2)
    wire T_178055 : UInt<2>[2]
    T_178055[0] := UInt<2>(0)
    T_178055[1] := UInt<2>(1)
    wire T_178056 : UInt<2>[3]
    T_178056[0] := UInt<2>(1)
    T_178056[1] := UInt<2>(2)
    T_178056[2] := UInt<2>(3)
    wire T_178057 : UInt<2>[2]
    T_178057[0] := UInt<2>(2)
    T_178057[1] := UInt<2>(3)
    wire T_178058 : UInt<2>[1]
    T_178058[0] := UInt<2>(3)
    wire T_178059 : UInt<3>[3]
    T_178059[0] := UInt<3>(0)
    T_178059[1] := UInt<3>(1)
    T_178059[2] := UInt<3>(2)
    wire T_178060 : UInt<0>[1]
    T_178060[0] := UInt<0>(0)
    wire T_178061 : UInt<2>[2]
    T_178061[0] := UInt<2>(1)
    T_178061[1] := UInt<2>(2)
    wire T_178062 : UInt<2>[2]
    T_178062[0] := UInt<2>(1)
    T_178062[1] := UInt<2>(2)
    wire T_178063 : UInt<2>[1]
    T_178063[0] := UInt<2>(2)
    wire T_178064 : UInt<3>[3]
    T_178064[0] := UInt<3>(0)
    T_178064[1] := UInt<3>(1)
    T_178064[2] := UInt<3>(2)
    wire T_178065 : UInt<2>[2]
    T_178065[0] := UInt<2>(0)
    T_178065[1] := UInt<2>(1)
    wire T_178066 : UInt<2>[3]
    T_178066[0] := UInt<2>(1)
    T_178066[1] := UInt<2>(2)
    T_178066[2] := UInt<2>(3)
    wire T_178067 : UInt<2>[2]
    T_178067[0] := UInt<2>(2)
    T_178067[1] := UInt<2>(3)
    wire T_178068 : UInt<2>[1]
    T_178068[0] := UInt<2>(3)
    wire T_178069 : UInt<3>[3]
    T_178069[0] := UInt<3>(0)
    T_178069[1] := UInt<3>(1)
    T_178069[2] := UInt<3>(2)
    wire T_178070 : UInt<2>[2]
    T_178070[0] := UInt<2>(0)
    T_178070[1] := UInt<2>(1)
    wire T_178071 : UInt<2>[3]
    T_178071[0] := UInt<2>(1)
    T_178071[1] := UInt<2>(2)
    T_178071[2] := UInt<2>(3)
    wire T_178072 : UInt<2>[2]
    T_178072[0] := UInt<2>(2)
    T_178072[1] := UInt<2>(3)
    wire T_178073 : UInt<2>[1]
    T_178073[0] := UInt<2>(3)
    wire T_178074 : UInt<3>[3]
    T_178074[0] := UInt<3>(0)
    T_178074[1] := UInt<3>(1)
    T_178074[2] := UInt<3>(2)
    wire T_178075 : UInt<0>[1]
    T_178075[0] := UInt<0>(0)
    wire T_178076 : UInt<2>[2]
    T_178076[0] := UInt<2>(1)
    T_178076[1] := UInt<2>(2)
    wire T_178077 : UInt<2>[2]
    T_178077[0] := UInt<2>(1)
    T_178077[1] := UInt<2>(2)
    wire T_178078 : UInt<2>[1]
    T_178078[0] := UInt<2>(2)
    accessor T_178079 = in[T_178003]
    out.valid := T_178079.valid
    wire T_178080 : UInt<3>[3]
    T_178080[0] := UInt<3>(0)
    T_178080[1] := UInt<3>(1)
    T_178080[2] := UInt<3>(2)
    wire T_178081 : UInt<2>[2]
    T_178081[0] := UInt<2>(0)
    T_178081[1] := UInt<2>(1)
    wire T_178082 : UInt<2>[3]
    T_178082[0] := UInt<2>(1)
    T_178082[1] := UInt<2>(2)
    T_178082[2] := UInt<2>(3)
    wire T_178083 : UInt<2>[2]
    T_178083[0] := UInt<2>(2)
    T_178083[1] := UInt<2>(3)
    wire T_178084 : UInt<2>[1]
    T_178084[0] := UInt<2>(3)
    wire T_178085 : UInt<3>[3]
    T_178085[0] := UInt<3>(0)
    T_178085[1] := UInt<3>(1)
    T_178085[2] := UInt<3>(2)
    wire T_178086 : UInt<2>[2]
    T_178086[0] := UInt<2>(0)
    T_178086[1] := UInt<2>(1)
    wire T_178087 : UInt<2>[3]
    T_178087[0] := UInt<2>(1)
    T_178087[1] := UInt<2>(2)
    T_178087[2] := UInt<2>(3)
    wire T_178088 : UInt<2>[2]
    T_178088[0] := UInt<2>(2)
    T_178088[1] := UInt<2>(3)
    wire T_178089 : UInt<2>[1]
    T_178089[0] := UInt<2>(3)
    wire T_178090 : UInt<3>[3]
    T_178090[0] := UInt<3>(0)
    T_178090[1] := UInt<3>(1)
    T_178090[2] := UInt<3>(2)
    wire T_178091 : UInt<0>[1]
    T_178091[0] := UInt<0>(0)
    wire T_178092 : UInt<2>[2]
    T_178092[0] := UInt<2>(1)
    T_178092[1] := UInt<2>(2)
    wire T_178093 : UInt<2>[2]
    T_178093[0] := UInt<2>(1)
    T_178093[1] := UInt<2>(2)
    wire T_178094 : UInt<2>[1]
    T_178094[0] := UInt<2>(2)
    wire T_178095 : UInt<3>[3]
    T_178095[0] := UInt<3>(0)
    T_178095[1] := UInt<3>(1)
    T_178095[2] := UInt<3>(2)
    wire T_178096 : UInt<2>[2]
    T_178096[0] := UInt<2>(0)
    T_178096[1] := UInt<2>(1)
    wire T_178097 : UInt<2>[3]
    T_178097[0] := UInt<2>(1)
    T_178097[1] := UInt<2>(2)
    T_178097[2] := UInt<2>(3)
    wire T_178098 : UInt<2>[2]
    T_178098[0] := UInt<2>(2)
    T_178098[1] := UInt<2>(3)
    wire T_178099 : UInt<2>[1]
    T_178099[0] := UInt<2>(3)
    wire T_178100 : UInt<3>[3]
    T_178100[0] := UInt<3>(0)
    T_178100[1] := UInt<3>(1)
    T_178100[2] := UInt<3>(2)
    wire T_178101 : UInt<2>[2]
    T_178101[0] := UInt<2>(0)
    T_178101[1] := UInt<2>(1)
    wire T_178102 : UInt<2>[3]
    T_178102[0] := UInt<2>(1)
    T_178102[1] := UInt<2>(2)
    T_178102[2] := UInt<2>(3)
    wire T_178103 : UInt<2>[2]
    T_178103[0] := UInt<2>(2)
    T_178103[1] := UInt<2>(3)
    wire T_178104 : UInt<2>[1]
    T_178104[0] := UInt<2>(3)
    wire T_178105 : UInt<3>[3]
    T_178105[0] := UInt<3>(0)
    T_178105[1] := UInt<3>(1)
    T_178105[2] := UInt<3>(2)
    wire T_178106 : UInt<0>[1]
    T_178106[0] := UInt<0>(0)
    wire T_178107 : UInt<2>[2]
    T_178107[0] := UInt<2>(1)
    T_178107[1] := UInt<2>(2)
    wire T_178108 : UInt<2>[2]
    T_178108[0] := UInt<2>(1)
    T_178108[1] := UInt<2>(2)
    wire T_178109 : UInt<2>[1]
    T_178109[0] := UInt<2>(2)
    accessor T_178110 = in[T_178003]
    out.bits := T_178110.bits
    chosen := T_178003
    wire T_178111 : UInt<2>
    T_178111 := UInt<2>(2)
    when in[1].valid : T_178111 := UInt<1>(1)
    wire T_178112 : UInt<2>
    T_178112 := T_178111
    when in[0].valid : T_178112 := UInt<1>(0)
    node T_178113 = gt(UInt<2>(2), T_178004)
    node T_178114 = and(in[2].valid, T_178113)
    wire T_178115 : UInt<2>
    T_178115 := T_178112
    when T_178114 : T_178115 := UInt<2>(2)
    node T_178116 = gt(UInt<1>(1), T_178004)
    node T_178117 = and(in[1].valid, T_178116)
    wire T_178118 : UInt<2>
    T_178118 := T_178115
    when T_178117 : T_178118 := UInt<1>(1)
    wire T_178119 : UInt<2>
    T_178119 := T_178118
    when UInt<1>(0) : T_178119 := UInt<2>(2)
    T_178003 := T_178119
    
    node T_178120 = and(out.ready, out.valid)
    when T_178120 : T_178004 := T_178003
  module RRArbiter_107931 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}[4]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}
    output chosen : UInt<2>
    
    wire T_178121 : UInt<2>
    reg T_178122 : UInt<2>
    onreset T_178122 := UInt<2>(0)
    node T_178123 = gt(UInt<1>(0), T_178122)
    node T_178124 = and(in[0].valid, T_178123)
    node T_178125 = gt(UInt<1>(1), T_178122)
    node T_178126 = and(in[1].valid, T_178125)
    node T_178127 = gt(UInt<2>(2), T_178122)
    node T_178128 = and(in[2].valid, T_178127)
    node T_178129 = gt(UInt<2>(3), T_178122)
    node T_178130 = and(in[3].valid, T_178129)
    node T_178131 = or(UInt<1>(0), T_178124)
    node T_178132 = eq(T_178131, UInt<1>(0))
    node T_178133 = or(UInt<1>(0), T_178124)
    node T_178134 = or(T_178133, T_178126)
    node T_178135 = eq(T_178134, UInt<1>(0))
    node T_178136 = or(UInt<1>(0), T_178124)
    node T_178137 = or(T_178136, T_178126)
    node T_178138 = or(T_178137, T_178128)
    node T_178139 = eq(T_178138, UInt<1>(0))
    node T_178140 = or(UInt<1>(0), T_178124)
    node T_178141 = or(T_178140, T_178126)
    node T_178142 = or(T_178141, T_178128)
    node T_178143 = or(T_178142, T_178130)
    node T_178144 = eq(T_178143, UInt<1>(0))
    node T_178145 = or(UInt<1>(0), T_178124)
    node T_178146 = or(T_178145, T_178126)
    node T_178147 = or(T_178146, T_178128)
    node T_178148 = or(T_178147, T_178130)
    node T_178149 = or(T_178148, in[0].valid)
    node T_178150 = eq(T_178149, UInt<1>(0))
    node T_178151 = or(UInt<1>(0), T_178124)
    node T_178152 = or(T_178151, T_178126)
    node T_178153 = or(T_178152, T_178128)
    node T_178154 = or(T_178153, T_178130)
    node T_178155 = or(T_178154, in[0].valid)
    node T_178156 = or(T_178155, in[1].valid)
    node T_178157 = eq(T_178156, UInt<1>(0))
    node T_178158 = or(UInt<1>(0), T_178124)
    node T_178159 = or(T_178158, T_178126)
    node T_178160 = or(T_178159, T_178128)
    node T_178161 = or(T_178160, T_178130)
    node T_178162 = or(T_178161, in[0].valid)
    node T_178163 = or(T_178162, in[1].valid)
    node T_178164 = or(T_178163, in[2].valid)
    node T_178165 = eq(T_178164, UInt<1>(0))
    node T_178166 = gt(UInt<1>(0), T_178122)
    node T_178167 = and(UInt<1>(1), T_178166)
    node T_178168 = or(T_178167, T_178144)
    node T_178169 = gt(UInt<1>(1), T_178122)
    node T_178170 = and(T_178132, T_178169)
    node T_178171 = or(T_178170, T_178150)
    node T_178172 = gt(UInt<2>(2), T_178122)
    node T_178173 = and(T_178135, T_178172)
    node T_178174 = or(T_178173, T_178157)
    node T_178175 = gt(UInt<2>(3), T_178122)
    node T_178176 = and(T_178139, T_178175)
    node T_178177 = or(T_178176, T_178165)
    node T_178178 = eq(UInt<2>(3), UInt<1>(0))
    wire T_178179 : UInt<1>
    T_178179 := T_178168
    when UInt<1>(0) : T_178179 := T_178178
    node T_178180 = and(T_178179, out.ready)
    in[0].ready := T_178180
    node T_178181 = eq(UInt<2>(3), UInt<1>(1))
    wire T_178182 : UInt<1>
    T_178182 := T_178171
    when UInt<1>(0) : T_178182 := T_178181
    node T_178183 = and(T_178182, out.ready)
    in[1].ready := T_178183
    node T_178184 = eq(UInt<2>(3), UInt<2>(2))
    wire T_178185 : UInt<1>
    T_178185 := T_178174
    when UInt<1>(0) : T_178185 := T_178184
    node T_178186 = and(T_178185, out.ready)
    in[2].ready := T_178186
    node T_178187 = eq(UInt<2>(3), UInt<2>(3))
    wire T_178188 : UInt<1>
    T_178188 := T_178177
    when UInt<1>(0) : T_178188 := T_178187
    node T_178189 = and(T_178188, out.ready)
    in[3].ready := T_178189
    accessor T_178190 = in[T_178121]
    out.valid := T_178190.valid
    accessor T_178191 = in[T_178121]
    out.bits := T_178191.bits
    chosen := T_178121
    wire T_178192 : UInt<2>
    T_178192 := UInt<2>(3)
    when in[2].valid : T_178192 := UInt<2>(2)
    wire T_178193 : UInt<2>
    T_178193 := T_178192
    when in[1].valid : T_178193 := UInt<1>(1)
    wire T_178194 : UInt<2>
    T_178194 := T_178193
    when in[0].valid : T_178194 := UInt<1>(0)
    node T_178195 = gt(UInt<2>(3), T_178122)
    node T_178196 = and(in[3].valid, T_178195)
    wire T_178197 : UInt<2>
    T_178197 := T_178194
    when T_178196 : T_178197 := UInt<2>(3)
    node T_178198 = gt(UInt<2>(2), T_178122)
    node T_178199 = and(in[2].valid, T_178198)
    wire T_178200 : UInt<2>
    T_178200 := T_178197
    when T_178199 : T_178200 := UInt<2>(2)
    node T_178201 = gt(UInt<1>(1), T_178122)
    node T_178202 = and(in[1].valid, T_178201)
    wire T_178203 : UInt<2>
    T_178203 := T_178200
    when T_178202 : T_178203 := UInt<1>(1)
    wire T_178204 : UInt<2>
    T_178204 := T_178203
    when UInt<1>(0) : T_178204 := UInt<2>(3)
    T_178121 := T_178204
    
    node T_178205 = and(out.ready, out.valid)
    when T_178205 : T_178122 := T_178121
  module RRArbiter_108094 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}[3]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}
    output chosen : UInt<2>
    
    wire T_178206 : UInt<2>
    reg T_178207 : UInt<2>
    onreset T_178207 := UInt<2>(0)
    node T_178208 = gt(UInt<1>(0), T_178207)
    node T_178209 = and(in[0].valid, T_178208)
    node T_178210 = gt(UInt<1>(1), T_178207)
    node T_178211 = and(in[1].valid, T_178210)
    node T_178212 = gt(UInt<2>(2), T_178207)
    node T_178213 = and(in[2].valid, T_178212)
    node T_178214 = or(UInt<1>(0), T_178209)
    node T_178215 = eq(T_178214, UInt<1>(0))
    node T_178216 = or(UInt<1>(0), T_178209)
    node T_178217 = or(T_178216, T_178211)
    node T_178218 = eq(T_178217, UInt<1>(0))
    node T_178219 = or(UInt<1>(0), T_178209)
    node T_178220 = or(T_178219, T_178211)
    node T_178221 = or(T_178220, T_178213)
    node T_178222 = eq(T_178221, UInt<1>(0))
    node T_178223 = or(UInt<1>(0), T_178209)
    node T_178224 = or(T_178223, T_178211)
    node T_178225 = or(T_178224, T_178213)
    node T_178226 = or(T_178225, in[0].valid)
    node T_178227 = eq(T_178226, UInt<1>(0))
    node T_178228 = or(UInt<1>(0), T_178209)
    node T_178229 = or(T_178228, T_178211)
    node T_178230 = or(T_178229, T_178213)
    node T_178231 = or(T_178230, in[0].valid)
    node T_178232 = or(T_178231, in[1].valid)
    node T_178233 = eq(T_178232, UInt<1>(0))
    node T_178234 = gt(UInt<1>(0), T_178207)
    node T_178235 = and(UInt<1>(1), T_178234)
    node T_178236 = or(T_178235, T_178222)
    node T_178237 = gt(UInt<1>(1), T_178207)
    node T_178238 = and(T_178215, T_178237)
    node T_178239 = or(T_178238, T_178227)
    node T_178240 = gt(UInt<2>(2), T_178207)
    node T_178241 = and(T_178218, T_178240)
    node T_178242 = or(T_178241, T_178233)
    node T_178243 = eq(UInt<2>(2), UInt<1>(0))
    wire T_178244 : UInt<1>
    T_178244 := T_178236
    when UInt<1>(0) : T_178244 := T_178243
    node T_178245 = and(T_178244, out.ready)
    in[0].ready := T_178245
    node T_178246 = eq(UInt<2>(2), UInt<1>(1))
    wire T_178247 : UInt<1>
    T_178247 := T_178239
    when UInt<1>(0) : T_178247 := T_178246
    node T_178248 = and(T_178247, out.ready)
    in[1].ready := T_178248
    node T_178249 = eq(UInt<2>(2), UInt<2>(2))
    wire T_178250 : UInt<1>
    T_178250 := T_178242
    when UInt<1>(0) : T_178250 := T_178249
    node T_178251 = and(T_178250, out.ready)
    in[2].ready := T_178251
    accessor T_178252 = in[T_178206]
    out.valid := T_178252.valid
    accessor T_178253 = in[T_178206]
    out.bits := T_178253.bits
    chosen := T_178206
    wire T_178254 : UInt<2>
    T_178254 := UInt<2>(2)
    when in[1].valid : T_178254 := UInt<1>(1)
    wire T_178255 : UInt<2>
    T_178255 := T_178254
    when in[0].valid : T_178255 := UInt<1>(0)
    node T_178256 = gt(UInt<2>(2), T_178207)
    node T_178257 = and(in[2].valid, T_178256)
    wire T_178258 : UInt<2>
    T_178258 := T_178255
    when T_178257 : T_178258 := UInt<2>(2)
    node T_178259 = gt(UInt<1>(1), T_178207)
    node T_178260 = and(in[1].valid, T_178259)
    wire T_178261 : UInt<2>
    T_178261 := T_178258
    when T_178260 : T_178261 := UInt<1>(1)
    wire T_178262 : UInt<2>
    T_178262 := T_178261
    when UInt<1>(0) : T_178262 := UInt<2>(2)
    T_178206 := T_178262
    
    node T_178263 = and(out.ready, out.valid)
    when T_178263 : T_178207 := T_178206
  module TSHRFile : 
    output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input incoherent : UInt<1>[1]
    output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output meta : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, id : UInt<2>, tag : UInt<14>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, tag_match : UInt<1>, meta : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, way_en : UInt<8>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<12>, way_en : UInt<8>, data : {tag : UInt<14>, coh : {inner : {sharers : UInt<1>, makeGrant$default$3 : UInt<1>, makeGrant$default$4 : UInt<1>}, outer : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}, id : UInt<2>}}}
    output data : {read : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>}}, flip resp : {valid : UInt<1>, bits : {id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>}}, write : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, id : UInt<2>, addr_idx : UInt<12>, way_en : UInt<8>, data : UInt<128>, wmask : UInt<16>}}}
    
    wire T_178264 : UInt<3>[3]
    T_178264[0] := UInt<3>(0)
    T_178264[1] := UInt<3>(1)
    T_178264[2] := UInt<3>(2)
    wire T_178265 : UInt<2>[2]
    T_178265[0] := UInt<2>(0)
    T_178265[1] := UInt<2>(1)
    wire T_178266 : UInt<2>[3]
    T_178266[0] := UInt<2>(1)
    T_178266[1] := UInt<2>(2)
    T_178266[2] := UInt<2>(3)
    wire T_178267 : UInt<2>[2]
    T_178267[0] := UInt<2>(2)
    T_178267[1] := UInt<2>(3)
    wire T_178268 : UInt<2>[1]
    T_178268[0] := UInt<2>(3)
    wire T_178269 : UInt<3>[3]
    T_178269[0] := UInt<3>(0)
    T_178269[1] := UInt<3>(1)
    T_178269[2] := UInt<3>(2)
    wire T_178270 : UInt<2>[2]
    T_178270[0] := UInt<2>(0)
    T_178270[1] := UInt<2>(1)
    wire T_178271 : UInt<2>[3]
    T_178271[0] := UInt<2>(1)
    T_178271[1] := UInt<2>(2)
    T_178271[2] := UInt<2>(3)
    wire T_178272 : UInt<2>[2]
    T_178272[0] := UInt<2>(2)
    T_178272[1] := UInt<2>(3)
    wire T_178273 : UInt<2>[1]
    T_178273[0] := UInt<2>(3)
    wire T_178274 : UInt<3>[3]
    T_178274[0] := UInt<3>(0)
    T_178274[1] := UInt<3>(1)
    T_178274[2] := UInt<3>(2)
    wire T_178275 : UInt<2>[2]
    T_178275[0] := UInt<2>(0)
    T_178275[1] := UInt<2>(1)
    wire T_178276 : UInt<2>[3]
    T_178276[0] := UInt<2>(1)
    T_178276[1] := UInt<2>(2)
    T_178276[2] := UInt<2>(3)
    wire T_178277 : UInt<2>[2]
    T_178277[0] := UInt<2>(2)
    T_178277[1] := UInt<2>(3)
    wire T_178278 : UInt<2>[1]
    T_178278[0] := UInt<2>(3)
    wire T_178279 : UInt<3>[3]
    T_178279[0] := UInt<3>(0)
    T_178279[1] := UInt<3>(1)
    T_178279[2] := UInt<3>(2)
    wire T_178280 : UInt<2>[2]
    T_178280[0] := UInt<2>(0)
    T_178280[1] := UInt<2>(1)
    wire T_178281 : UInt<2>[3]
    T_178281[0] := UInt<2>(1)
    T_178281[1] := UInt<2>(2)
    T_178281[2] := UInt<2>(3)
    wire T_178282 : UInt<2>[2]
    T_178282[0] := UInt<2>(2)
    T_178282[1] := UInt<2>(3)
    wire T_178283 : UInt<2>[1]
    T_178283[0] := UInt<2>(3)
    wire T_178284 : UInt<3>[3]
    T_178284[0] := UInt<3>(0)
    T_178284[1] := UInt<3>(1)
    T_178284[2] := UInt<3>(2)
    wire T_178285 : UInt<2>[2]
    T_178285[0] := UInt<2>(0)
    T_178285[1] := UInt<2>(1)
    wire T_178286 : UInt<2>[3]
    T_178286[0] := UInt<2>(1)
    T_178286[1] := UInt<2>(2)
    T_178286[2] := UInt<2>(3)
    wire T_178287 : UInt<2>[2]
    T_178287[0] := UInt<2>(2)
    T_178287[1] := UInt<2>(3)
    wire T_178288 : UInt<2>[1]
    T_178288[0] := UInt<2>(3)
    wire T_178289 : UInt<3>[3]
    T_178289[0] := UInt<3>(0)
    T_178289[1] := UInt<3>(1)
    T_178289[2] := UInt<3>(2)
    wire T_178290 : UInt<2>[2]
    T_178290[0] := UInt<2>(0)
    T_178290[1] := UInt<2>(1)
    wire T_178291 : UInt<2>[3]
    T_178291[0] := UInt<2>(1)
    T_178291[1] := UInt<2>(2)
    T_178291[2] := UInt<2>(3)
    wire T_178292 : UInt<2>[2]
    T_178292[0] := UInt<2>(2)
    T_178292[1] := UInt<2>(3)
    wire T_178293 : UInt<2>[1]
    T_178293[0] := UInt<2>(3)
    wire T_178294 : UInt<3>[3]
    T_178294[0] := UInt<3>(0)
    T_178294[1] := UInt<3>(1)
    T_178294[2] := UInt<3>(2)
    wire T_178295 : UInt<2>[2]
    T_178295[0] := UInt<2>(0)
    T_178295[1] := UInt<2>(1)
    wire T_178296 : UInt<2>[3]
    T_178296[0] := UInt<2>(1)
    T_178296[1] := UInt<2>(2)
    T_178296[2] := UInt<2>(3)
    wire T_178297 : UInt<2>[2]
    T_178297[0] := UInt<2>(2)
    T_178297[1] := UInt<2>(3)
    wire T_178298 : UInt<2>[1]
    T_178298[0] := UInt<2>(3)
    wire T_178299 : UInt<3>[3]
    T_178299[0] := UInt<3>(0)
    T_178299[1] := UInt<3>(1)
    T_178299[2] := UInt<3>(2)
    wire T_178300 : UInt<2>[2]
    T_178300[0] := UInt<2>(0)
    T_178300[1] := UInt<2>(1)
    wire T_178301 : UInt<2>[3]
    T_178301[0] := UInt<2>(1)
    T_178301[1] := UInt<2>(2)
    T_178301[2] := UInt<2>(3)
    wire T_178302 : UInt<2>[2]
    T_178302[0] := UInt<2>(2)
    T_178302[1] := UInt<2>(3)
    wire T_178303 : UInt<2>[1]
    T_178303[0] := UInt<2>(3)
    wire T_178304 : UInt<3>[3]
    T_178304[0] := UInt<3>(0)
    T_178304[1] := UInt<3>(1)
    T_178304[2] := UInt<3>(2)
    wire T_178305 : UInt<2>[2]
    T_178305[0] := UInt<2>(0)
    T_178305[1] := UInt<2>(1)
    wire T_178306 : UInt<2>[3]
    T_178306[0] := UInt<2>(1)
    T_178306[1] := UInt<2>(2)
    T_178306[2] := UInt<2>(3)
    wire T_178307 : UInt<2>[2]
    T_178307[0] := UInt<2>(2)
    T_178307[1] := UInt<2>(3)
    wire T_178308 : UInt<2>[1]
    T_178308[0] := UInt<2>(3)
    wire T_178309 : UInt<3>[3]
    T_178309[0] := UInt<3>(0)
    T_178309[1] := UInt<3>(1)
    T_178309[2] := UInt<3>(2)
    wire T_178310 : UInt<2>[2]
    T_178310[0] := UInt<2>(0)
    T_178310[1] := UInt<2>(1)
    wire T_178311 : UInt<2>[3]
    T_178311[0] := UInt<2>(1)
    T_178311[1] := UInt<2>(2)
    T_178311[2] := UInt<2>(3)
    wire T_178312 : UInt<2>[2]
    T_178312[0] := UInt<2>(2)
    T_178312[1] := UInt<2>(3)
    wire T_178313 : UInt<2>[1]
    T_178313[0] := UInt<2>(3)
    wire T_178314 : UInt<3>[3]
    T_178314[0] := UInt<3>(0)
    T_178314[1] := UInt<3>(1)
    T_178314[2] := UInt<3>(2)
    wire T_178315 : UInt<2>[2]
    T_178315[0] := UInt<2>(0)
    T_178315[1] := UInt<2>(1)
    wire T_178316 : UInt<2>[3]
    T_178316[0] := UInt<2>(1)
    T_178316[1] := UInt<2>(2)
    T_178316[2] := UInt<2>(3)
    wire T_178317 : UInt<2>[2]
    T_178317[0] := UInt<2>(2)
    T_178317[1] := UInt<2>(3)
    wire T_178318 : UInt<2>[1]
    T_178318[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_178319
    wire T_178320 : UInt<3>[3]
    T_178320[0] := UInt<3>(0)
    T_178320[1] := UInt<3>(1)
    T_178320[2] := UInt<3>(2)
    wire T_178321 : UInt<0>[1]
    T_178321[0] := UInt<0>(0)
    wire T_178322 : UInt<2>[2]
    T_178322[0] := UInt<2>(1)
    T_178322[1] := UInt<2>(2)
    wire T_178323 : UInt<2>[2]
    T_178323[0] := UInt<2>(1)
    T_178323[1] := UInt<2>(2)
    wire T_178324 : UInt<2>[1]
    T_178324[0] := UInt<2>(2)
    wire T_178325 : UInt<3>[3]
    T_178325[0] := UInt<3>(0)
    T_178325[1] := UInt<3>(1)
    T_178325[2] := UInt<3>(2)
    wire T_178326 : UInt<0>[1]
    T_178326[0] := UInt<0>(0)
    wire T_178327 : UInt<2>[2]
    T_178327[0] := UInt<2>(1)
    T_178327[1] := UInt<2>(2)
    wire T_178328 : UInt<2>[2]
    T_178328[0] := UInt<2>(1)
    T_178328[1] := UInt<2>(2)
    wire T_178329 : UInt<2>[1]
    T_178329[0] := UInt<2>(2)
    wire T_178330 : UInt<3>[3]
    T_178330[0] := UInt<3>(0)
    T_178330[1] := UInt<3>(1)
    T_178330[2] := UInt<3>(2)
    wire T_178331 : UInt<0>[1]
    T_178331[0] := UInt<0>(0)
    wire T_178332 : UInt<2>[2]
    T_178332[0] := UInt<2>(1)
    T_178332[1] := UInt<2>(2)
    wire T_178333 : UInt<2>[2]
    T_178333[0] := UInt<2>(1)
    T_178333[1] := UInt<2>(2)
    wire T_178334 : UInt<2>[1]
    T_178334[0] := UInt<2>(2)
    wire T_178335 : UInt<3>[3]
    T_178335[0] := UInt<3>(0)
    T_178335[1] := UInt<3>(1)
    T_178335[2] := UInt<3>(2)
    wire T_178336 : UInt<0>[1]
    T_178336[0] := UInt<0>(0)
    wire T_178337 : UInt<2>[2]
    T_178337[0] := UInt<2>(1)
    T_178337[1] := UInt<2>(2)
    wire T_178338 : UInt<2>[2]
    T_178338[0] := UInt<2>(1)
    T_178338[1] := UInt<2>(2)
    wire T_178339 : UInt<2>[1]
    T_178339[0] := UInt<2>(2)
    wire T_178340 : UInt<3>[3]
    T_178340[0] := UInt<3>(0)
    T_178340[1] := UInt<3>(1)
    T_178340[2] := UInt<3>(2)
    wire T_178341 : UInt<0>[1]
    T_178341[0] := UInt<0>(0)
    wire T_178342 : UInt<2>[2]
    T_178342[0] := UInt<2>(1)
    T_178342[1] := UInt<2>(2)
    wire T_178343 : UInt<2>[2]
    T_178343[0] := UInt<2>(1)
    T_178343[1] := UInt<2>(2)
    wire T_178344 : UInt<2>[1]
    T_178344[0] := UInt<2>(2)
    wire T_178345 : UInt<3>[3]
    T_178345[0] := UInt<3>(0)
    T_178345[1] := UInt<3>(1)
    T_178345[2] := UInt<3>(2)
    wire T_178346 : UInt<0>[1]
    T_178346[0] := UInt<0>(0)
    wire T_178347 : UInt<2>[2]
    T_178347[0] := UInt<2>(1)
    T_178347[1] := UInt<2>(2)
    wire T_178348 : UInt<2>[2]
    T_178348[0] := UInt<2>(1)
    T_178348[1] := UInt<2>(2)
    wire T_178349 : UInt<2>[1]
    T_178349[0] := UInt<2>(2)
    wire T_178350 : UInt<3>[3]
    T_178350[0] := UInt<3>(0)
    T_178350[1] := UInt<3>(1)
    T_178350[2] := UInt<3>(2)
    wire T_178351 : UInt<0>[1]
    T_178351[0] := UInt<0>(0)
    wire T_178352 : UInt<2>[2]
    T_178352[0] := UInt<2>(1)
    T_178352[1] := UInt<2>(2)
    wire T_178353 : UInt<2>[2]
    T_178353[0] := UInt<2>(1)
    T_178353[1] := UInt<2>(2)
    wire T_178354 : UInt<2>[1]
    T_178354[0] := UInt<2>(2)
    wire T_178355 : UInt<3>[3]
    T_178355[0] := UInt<3>(0)
    T_178355[1] := UInt<3>(1)
    T_178355[2] := UInt<3>(2)
    wire T_178356 : UInt<0>[1]
    T_178356[0] := UInt<0>(0)
    wire T_178357 : UInt<2>[2]
    T_178357[0] := UInt<2>(1)
    T_178357[1] := UInt<2>(2)
    wire T_178358 : UInt<2>[2]
    T_178358[0] := UInt<2>(1)
    T_178358[1] := UInt<2>(2)
    wire T_178359 : UInt<2>[1]
    T_178359[0] := UInt<2>(2)
    wire T_178360 : UInt<3>[3]
    T_178360[0] := UInt<3>(0)
    T_178360[1] := UInt<3>(1)
    T_178360[2] := UInt<3>(2)
    wire T_178361 : UInt<0>[1]
    T_178361[0] := UInt<0>(0)
    wire T_178362 : UInt<2>[2]
    T_178362[0] := UInt<2>(1)
    T_178362[1] := UInt<2>(2)
    wire T_178363 : UInt<2>[2]
    T_178363[0] := UInt<2>(1)
    T_178363[1] := UInt<2>(2)
    wire T_178364 : UInt<2>[1]
    T_178364[0] := UInt<2>(2)
    wire T_178365 : UInt<3>[3]
    T_178365[0] := UInt<3>(0)
    T_178365[1] := UInt<3>(1)
    T_178365[2] := UInt<3>(2)
    wire T_178366 : UInt<2>[2]
    T_178366[0] := UInt<2>(0)
    T_178366[1] := UInt<2>(1)
    wire T_178367 : UInt<2>[3]
    T_178367[0] := UInt<2>(1)
    T_178367[1] := UInt<2>(2)
    T_178367[2] := UInt<2>(3)
    wire T_178368 : UInt<2>[2]
    T_178368[0] := UInt<2>(2)
    T_178368[1] := UInt<2>(3)
    wire T_178369 : UInt<2>[1]
    T_178369[0] := UInt<2>(3)
    wire T_178370 : UInt<3>[3]
    T_178370[0] := UInt<3>(0)
    T_178370[1] := UInt<3>(1)
    T_178370[2] := UInt<3>(2)
    wire T_178371 : UInt<2>[2]
    T_178371[0] := UInt<2>(0)
    T_178371[1] := UInt<2>(1)
    wire T_178372 : UInt<2>[3]
    T_178372[0] := UInt<2>(1)
    T_178372[1] := UInt<2>(2)
    T_178372[2] := UInt<2>(3)
    wire T_178373 : UInt<2>[2]
    T_178373[0] := UInt<2>(2)
    T_178373[1] := UInt<2>(3)
    wire T_178374 : UInt<2>[1]
    T_178374[0] := UInt<2>(3)
    wire T_178375 : UInt<3>[3]
    T_178375[0] := UInt<3>(0)
    T_178375[1] := UInt<3>(1)
    T_178375[2] := UInt<3>(2)
    wire T_178376 : UInt<0>[1]
    T_178376[0] := UInt<0>(0)
    wire T_178377 : UInt<2>[2]
    T_178377[0] := UInt<2>(1)
    T_178377[1] := UInt<2>(2)
    wire T_178378 : UInt<2>[2]
    T_178378[0] := UInt<2>(1)
    T_178378[1] := UInt<2>(2)
    wire T_178379 : UInt<2>[1]
    T_178379[0] := UInt<2>(2)
    wire T_178380 : UInt<3>[3]
    T_178380[0] := UInt<3>(0)
    T_178380[1] := UInt<3>(1)
    T_178380[2] := UInt<3>(2)
    wire T_178381 : UInt<2>[2]
    T_178381[0] := UInt<2>(0)
    T_178381[1] := UInt<2>(1)
    wire T_178382 : UInt<2>[3]
    T_178382[0] := UInt<2>(1)
    T_178382[1] := UInt<2>(2)
    T_178382[2] := UInt<2>(3)
    wire T_178383 : UInt<2>[2]
    T_178383[0] := UInt<2>(2)
    T_178383[1] := UInt<2>(3)
    wire T_178384 : UInt<2>[1]
    T_178384[0] := UInt<2>(3)
    wire T_178385 : UInt<3>[3]
    T_178385[0] := UInt<3>(0)
    T_178385[1] := UInt<3>(1)
    T_178385[2] := UInt<3>(2)
    wire T_178386 : UInt<2>[2]
    T_178386[0] := UInt<2>(0)
    T_178386[1] := UInt<2>(1)
    wire T_178387 : UInt<2>[3]
    T_178387[0] := UInt<2>(1)
    T_178387[1] := UInt<2>(2)
    T_178387[2] := UInt<2>(3)
    wire T_178388 : UInt<2>[2]
    T_178388[0] := UInt<2>(2)
    T_178388[1] := UInt<2>(3)
    wire T_178389 : UInt<2>[1]
    T_178389[0] := UInt<2>(3)
    wire T_178390 : UInt<3>[3]
    T_178390[0] := UInt<3>(0)
    T_178390[1] := UInt<3>(1)
    T_178390[2] := UInt<3>(2)
    wire T_178391 : UInt<0>[1]
    T_178391[0] := UInt<0>(0)
    wire T_178392 : UInt<2>[2]
    T_178392[0] := UInt<2>(1)
    T_178392[1] := UInt<2>(2)
    wire T_178393 : UInt<2>[2]
    T_178393[0] := UInt<2>(1)
    T_178393[1] := UInt<2>(2)
    wire T_178394 : UInt<2>[1]
    T_178394[0] := UInt<2>(2)
    wire T_178395 : UInt<3>[3]
    T_178395[0] := UInt<3>(0)
    T_178395[1] := UInt<3>(1)
    T_178395[2] := UInt<3>(2)
    wire T_178396 : UInt<2>[2]
    T_178396[0] := UInt<2>(0)
    T_178396[1] := UInt<2>(1)
    wire T_178397 : UInt<2>[3]
    T_178397[0] := UInt<2>(1)
    T_178397[1] := UInt<2>(2)
    T_178397[2] := UInt<2>(3)
    wire T_178398 : UInt<2>[2]
    T_178398[0] := UInt<2>(2)
    T_178398[1] := UInt<2>(3)
    wire T_178399 : UInt<2>[1]
    T_178399[0] := UInt<2>(3)
    wire T_178400 : UInt<3>[3]
    T_178400[0] := UInt<3>(0)
    T_178400[1] := UInt<3>(1)
    T_178400[2] := UInt<3>(2)
    wire T_178401 : UInt<2>[2]
    T_178401[0] := UInt<2>(0)
    T_178401[1] := UInt<2>(1)
    wire T_178402 : UInt<2>[3]
    T_178402[0] := UInt<2>(1)
    T_178402[1] := UInt<2>(2)
    T_178402[2] := UInt<2>(3)
    wire T_178403 : UInt<2>[2]
    T_178403[0] := UInt<2>(2)
    T_178403[1] := UInt<2>(3)
    wire T_178404 : UInt<2>[1]
    T_178404[0] := UInt<2>(3)
    wire T_178405 : UInt<3>[3]
    T_178405[0] := UInt<3>(0)
    T_178405[1] := UInt<3>(1)
    T_178405[2] := UInt<3>(2)
    wire T_178406 : UInt<0>[1]
    T_178406[0] := UInt<0>(0)
    wire T_178407 : UInt<2>[2]
    T_178407[0] := UInt<2>(1)
    T_178407[1] := UInt<2>(2)
    wire T_178408 : UInt<2>[2]
    T_178408[0] := UInt<2>(1)
    T_178408[1] := UInt<2>(2)
    wire T_178409 : UInt<2>[1]
    T_178409[0] := UInt<2>(2)
    wire T_178410 : UInt<3>[3]
    T_178410[0] := UInt<3>(0)
    T_178410[1] := UInt<3>(1)
    T_178410[2] := UInt<3>(2)
    wire T_178411 : UInt<2>[2]
    T_178411[0] := UInt<2>(0)
    T_178411[1] := UInt<2>(1)
    wire T_178412 : UInt<2>[3]
    T_178412[0] := UInt<2>(1)
    T_178412[1] := UInt<2>(2)
    T_178412[2] := UInt<2>(3)
    wire T_178413 : UInt<2>[2]
    T_178413[0] := UInt<2>(2)
    T_178413[1] := UInt<2>(3)
    wire T_178414 : UInt<2>[1]
    T_178414[0] := UInt<2>(3)
    wire T_178415 : UInt<3>[3]
    T_178415[0] := UInt<3>(0)
    T_178415[1] := UInt<3>(1)
    T_178415[2] := UInt<3>(2)
    wire T_178416 : UInt<2>[2]
    T_178416[0] := UInt<2>(0)
    T_178416[1] := UInt<2>(1)
    wire T_178417 : UInt<2>[3]
    T_178417[0] := UInt<2>(1)
    T_178417[1] := UInt<2>(2)
    T_178417[2] := UInt<2>(3)
    wire T_178418 : UInt<2>[2]
    T_178418[0] := UInt<2>(2)
    T_178418[1] := UInt<2>(3)
    wire T_178419 : UInt<2>[1]
    T_178419[0] := UInt<2>(3)
    wire T_178420 : UInt<3>[3]
    T_178420[0] := UInt<3>(0)
    T_178420[1] := UInt<3>(1)
    T_178420[2] := UInt<3>(2)
    wire T_178421 : UInt<0>[1]
    T_178421[0] := UInt<0>(0)
    wire T_178422 : UInt<2>[2]
    T_178422[0] := UInt<2>(1)
    T_178422[1] := UInt<2>(2)
    wire T_178423 : UInt<2>[2]
    T_178423[0] := UInt<2>(1)
    T_178423[1] := UInt<2>(2)
    wire T_178424 : UInt<2>[1]
    T_178424[0] := UInt<2>(2)
    wire T_178425 : UInt<3>[3]
    T_178425[0] := UInt<3>(0)
    T_178425[1] := UInt<3>(1)
    T_178425[2] := UInt<3>(2)
    wire T_178426 : UInt<2>[2]
    T_178426[0] := UInt<2>(0)
    T_178426[1] := UInt<2>(1)
    wire T_178427 : UInt<2>[3]
    T_178427[0] := UInt<2>(1)
    T_178427[1] := UInt<2>(2)
    T_178427[2] := UInt<2>(3)
    wire T_178428 : UInt<2>[2]
    T_178428[0] := UInt<2>(2)
    T_178428[1] := UInt<2>(3)
    wire T_178429 : UInt<2>[1]
    T_178429[0] := UInt<2>(3)
    wire T_178430 : UInt<3>[3]
    T_178430[0] := UInt<3>(0)
    T_178430[1] := UInt<3>(1)
    T_178430[2] := UInt<3>(2)
    wire T_178431 : UInt<2>[2]
    T_178431[0] := UInt<2>(0)
    T_178431[1] := UInt<2>(1)
    wire T_178432 : UInt<2>[3]
    T_178432[0] := UInt<2>(1)
    T_178432[1] := UInt<2>(2)
    T_178432[2] := UInt<2>(3)
    wire T_178433 : UInt<2>[2]
    T_178433[0] := UInt<2>(2)
    T_178433[1] := UInt<2>(3)
    wire T_178434 : UInt<2>[1]
    T_178434[0] := UInt<2>(3)
    wire T_178435 : UInt<3>[3]
    T_178435[0] := UInt<3>(0)
    T_178435[1] := UInt<3>(1)
    T_178435[2] := UInt<3>(2)
    wire T_178436 : UInt<0>[1]
    T_178436[0] := UInt<0>(0)
    wire T_178437 : UInt<2>[2]
    T_178437[0] := UInt<2>(1)
    T_178437[1] := UInt<2>(2)
    wire T_178438 : UInt<2>[2]
    T_178438[0] := UInt<2>(1)
    T_178438[1] := UInt<2>(2)
    wire T_178439 : UInt<2>[1]
    T_178439[0] := UInt<2>(2)
    wire T_178440 : UInt<3>[3]
    T_178440[0] := UInt<3>(0)
    T_178440[1] := UInt<3>(1)
    T_178440[2] := UInt<3>(2)
    wire T_178441 : UInt<2>[2]
    T_178441[0] := UInt<2>(0)
    T_178441[1] := UInt<2>(1)
    wire T_178442 : UInt<2>[3]
    T_178442[0] := UInt<2>(1)
    T_178442[1] := UInt<2>(2)
    T_178442[2] := UInt<2>(3)
    wire T_178443 : UInt<2>[2]
    T_178443[0] := UInt<2>(2)
    T_178443[1] := UInt<2>(3)
    wire T_178444 : UInt<2>[1]
    T_178444[0] := UInt<2>(3)
    wire T_178445 : UInt<3>[3]
    T_178445[0] := UInt<3>(0)
    T_178445[1] := UInt<3>(1)
    T_178445[2] := UInt<3>(2)
    wire T_178446 : UInt<2>[2]
    T_178446[0] := UInt<2>(0)
    T_178446[1] := UInt<2>(1)
    wire T_178447 : UInt<2>[3]
    T_178447[0] := UInt<2>(1)
    T_178447[1] := UInt<2>(2)
    T_178447[2] := UInt<2>(3)
    wire T_178448 : UInt<2>[2]
    T_178448[0] := UInt<2>(2)
    T_178448[1] := UInt<2>(3)
    wire T_178449 : UInt<2>[1]
    T_178449[0] := UInt<2>(3)
    wire T_178450 : UInt<3>[3]
    T_178450[0] := UInt<3>(0)
    T_178450[1] := UInt<3>(1)
    T_178450[2] := UInt<3>(2)
    wire T_178451 : UInt<0>[1]
    T_178451[0] := UInt<0>(0)
    wire T_178452 : UInt<2>[2]
    T_178452[0] := UInt<2>(1)
    T_178452[1] := UInt<2>(2)
    wire T_178453 : UInt<2>[2]
    T_178453[0] := UInt<2>(1)
    T_178453[1] := UInt<2>(2)
    wire T_178454 : UInt<2>[1]
    T_178454[0] := UInt<2>(2)
    inst T_178455 of L2VoluntaryReleaseTracker
    inst T_178456 of L2AcquireTracker
    inst T_178457 of L2AcquireTracker_93254
    inst wb of L2WritebackUnit
    inst T_178458 of RRArbiter_97606
    wb.wb.req <> T_178458.out
    T_178458.in[0] <> T_178455.wb.req
    T_178458.in[1] <> T_178456.wb.req
    T_178458.in[2] <> T_178457.wb.req
    T_178455.wb.resp.bits := wb.wb.resp.bits
    T_178456.wb.resp.bits := wb.wb.resp.bits
    T_178457.wb.resp.bits := wb.wb.resp.bits
    node T_178459 = eq(wb.wb.resp.bits.id, UInt<1>(0))
    node T_178460 = and(wb.wb.resp.valid, T_178459)
    T_178455.wb.resp.valid := T_178460
    node T_178461 = eq(wb.wb.resp.bits.id, UInt<1>(1))
    node T_178462 = and(wb.wb.resp.valid, T_178461)
    T_178456.wb.resp.valid := T_178462
    node T_178463 = eq(wb.wb.resp.bits.id, UInt<2>(2))
    node T_178464 = and(wb.wb.resp.valid, T_178463)
    T_178457.wb.resp.valid := T_178464
    T_178455.incoherent := incoherent[0]
    T_178456.incoherent := incoherent[0]
    T_178457.incoherent := incoherent[0]
    wb.incoherent := incoherent[0]
    wire T_178465 : UInt<1>[3]
    T_178465[0] := T_178455.has_acquire_conflict
    T_178465[1] := T_178456.has_acquire_conflict
    T_178465[2] := T_178457.has_acquire_conflict
    node T_178466 = cat(T_178465[1], T_178465[0])
    node acquireConflicts = cat(T_178465[2], T_178466)
    wire T_178467 : UInt<1>[3]
    T_178467[0] := T_178455.has_acquire_match
    T_178467[1] := T_178456.has_acquire_match
    T_178467[2] := T_178457.has_acquire_match
    node T_178468 = cat(T_178467[1], T_178467[0])
    node acquireMatches = cat(T_178467[2], T_178468)
    wire T_178469 : UInt<1>[3]
    T_178469[0] := T_178455.inner.acquire.ready
    T_178469[1] := T_178456.inner.acquire.ready
    T_178469[2] := T_178457.inner.acquire.ready
    node T_178470 = cat(T_178469[1], T_178469[0])
    node acquireReadys = cat(T_178469[2], T_178470)
    node T_178471 = eq(acquireMatches, UInt<1>(0))
    node T_178472 = eq(T_178471, UInt<1>(0))
    node T_178473 = bit(acquireMatches, 0)
    node T_178474 = bit(acquireMatches, 1)
    node T_178475 = bit(acquireMatches, 2)
    wire T_178476 : UInt<1>[3]
    T_178476[0] := T_178473
    T_178476[1] := T_178474
    T_178476[2] := T_178475
    wire T_178477 : UInt<2>
    T_178477 := UInt<2>(2)
    when T_178476[1] : T_178477 := UInt<1>(1)
    wire T_178478 : UInt<2>
    T_178478 := T_178477
    when T_178476[0] : T_178478 := UInt<1>(0)
    node T_178479 = bit(acquireReadys, 0)
    node T_178480 = bit(acquireReadys, 1)
    node T_178481 = bit(acquireReadys, 2)
    wire T_178482 : UInt<1>[3]
    T_178482[0] := T_178479
    T_178482[1] := T_178480
    T_178482[2] := T_178481
    wire T_178483 : UInt<2>
    T_178483 := UInt<2>(2)
    when T_178482[1] : T_178483 := UInt<1>(1)
    wire T_178484 : UInt<2>
    T_178484 := T_178483
    when T_178482[0] : T_178484 := UInt<1>(0)
    wire acquire_idx : UInt<2>
    acquire_idx := T_178484
    when T_178472 : acquire_idx := T_178478
    node T_178485 = eq(acquireConflicts, UInt<1>(0))
    node block_acquires = eq(T_178485, UInt<1>(0))
    node T_178486 = eq(acquireReadys, UInt<1>(0))
    node T_178487 = eq(T_178486, UInt<1>(0))
    node T_178488 = eq(block_acquires, UInt<1>(0))
    node T_178489 = and(T_178487, T_178488)
    inner.acquire.ready := T_178489
    T_178455.inner.acquire.bits := inner.acquire.bits
    node T_178490 = eq(block_acquires, UInt<1>(0))
    node T_178491 = and(inner.acquire.valid, T_178490)
    node T_178492 = eq(acquire_idx, UInt<1>(0))
    node T_178493 = and(T_178491, T_178492)
    T_178455.inner.acquire.valid := T_178493
    T_178456.inner.acquire.bits := inner.acquire.bits
    node T_178494 = eq(block_acquires, UInt<1>(0))
    node T_178495 = and(inner.acquire.valid, T_178494)
    node T_178496 = eq(acquire_idx, UInt<1>(1))
    node T_178497 = and(T_178495, T_178496)
    T_178456.inner.acquire.valid := T_178497
    T_178457.inner.acquire.bits := inner.acquire.bits
    node T_178498 = eq(block_acquires, UInt<1>(0))
    node T_178499 = and(inner.acquire.valid, T_178498)
    node T_178500 = eq(acquire_idx, UInt<2>(2))
    node T_178501 = and(T_178499, T_178500)
    T_178457.inner.acquire.valid := T_178501
    wire T_178502 : UInt<1>[4]
    T_178502[0] := T_178455.inner.release.ready
    T_178502[1] := T_178456.inner.release.ready
    T_178502[2] := T_178457.inner.release.ready
    T_178502[3] := wb.inner.release.ready
    node T_178503 = cat(T_178502[3], T_178502[2])
    node T_178504 = cat(T_178502[1], T_178502[0])
    node releaseReadys = cat(T_178503, T_178504)
    wire T_178505 : UInt<1>[4]
    T_178505[0] := T_178455.has_release_match
    T_178505[1] := T_178456.has_release_match
    T_178505[2] := T_178457.has_release_match
    T_178505[3] := wb.has_release_match
    node T_178506 = cat(T_178505[3], T_178505[2])
    node T_178507 = cat(T_178505[1], T_178505[0])
    node releaseMatches = cat(T_178506, T_178507)
    node T_178508 = bit(releaseMatches, 0)
    node T_178509 = bit(releaseMatches, 1)
    node T_178510 = bit(releaseMatches, 2)
    node T_178511 = bit(releaseMatches, 3)
    wire T_178512 : UInt<1>[4]
    T_178512[0] := T_178508
    T_178512[1] := T_178509
    T_178512[2] := T_178510
    T_178512[3] := T_178511
    wire T_178513 : UInt<2>
    T_178513 := UInt<2>(3)
    when T_178512[2] : T_178513 := UInt<2>(2)
    wire T_178514 : UInt<2>
    T_178514 := T_178513
    when T_178512[1] : T_178514 := UInt<1>(1)
    wire release_idx : UInt<2>
    release_idx := T_178514
    when T_178512[0] : release_idx := UInt<1>(0)
    node T_178515 = dshr(releaseReadys, release_idx)
    node T_178516 = bit(T_178515, 0)
    inner.release.ready := T_178516
    T_178455.inner.release.bits := inner.release.bits
    node T_178517 = eq(release_idx, UInt<1>(0))
    node T_178518 = and(inner.release.valid, T_178517)
    T_178455.inner.release.valid := T_178518
    T_178456.inner.release.bits := inner.release.bits
    node T_178519 = eq(release_idx, UInt<1>(1))
    node T_178520 = and(inner.release.valid, T_178519)
    T_178456.inner.release.valid := T_178520
    T_178457.inner.release.bits := inner.release.bits
    node T_178521 = eq(release_idx, UInt<2>(2))
    node T_178522 = and(inner.release.valid, T_178521)
    T_178457.inner.release.valid := T_178522
    wb.inner.release.bits := inner.release.bits
    node T_178523 = eq(release_idx, UInt<2>(3))
    node T_178524 = and(inner.release.valid, T_178523)
    wb.inner.release.valid := T_178524
    node T_178525 = eq(releaseMatches, UInt<1>(0))
    node T_178526 = eq(T_178525, UInt<1>(0))
    node T_178527 = eq(T_178526, UInt<1>(0))
    node T_178528 = and(inner.release.valid, T_178527)
    node T_178529 = eq(T_178528, UInt<1>(0))
    inst T_178530 of LockingRRArbiter_98418
    inner.probe <> T_178530.out
    T_178530.in[0] <> T_178455.inner.probe
    T_178530.in[1] <> T_178456.inner.probe
    T_178530.in[2] <> T_178457.inner.probe
    T_178530.in[3] <> wb.inner.probe
    inst T_178531 of LockingRRArbiter_99026
    inner.grant <> T_178531.out
    T_178531.in[0] <> T_178455.inner.grant
    T_178531.in[1] <> T_178456.inner.grant
    T_178531.in[2] <> T_178457.inner.grant
    T_178455.inner.finish.bits := inner.finish.bits
    T_178456.inner.finish.bits := inner.finish.bits
    T_178457.inner.finish.bits := inner.finish.bits
    node T_178532 = eq(inner.finish.bits.manager_xact_id, UInt<1>(0))
    node T_178533 = and(inner.finish.valid, T_178532)
    T_178455.inner.finish.valid := T_178533
    node T_178534 = eq(inner.finish.bits.manager_xact_id, UInt<1>(1))
    node T_178535 = and(inner.finish.valid, T_178534)
    T_178456.inner.finish.valid := T_178535
    node T_178536 = eq(inner.finish.bits.manager_xact_id, UInt<2>(2))
    node T_178537 = and(inner.finish.valid, T_178536)
    T_178457.inner.finish.valid := T_178537
    wire T_178538 : UInt<1>[3]
    T_178538[0] := T_178455.inner.finish.ready
    T_178538[1] := T_178456.inner.finish.ready
    T_178538[2] := T_178457.inner.finish.ready
    accessor T_178539 = T_178538[inner.finish.bits.manager_xact_id]
    inner.finish.ready := T_178539
    inst outer_arb of ClientTileLinkIOArbiter
    outer_arb.in[0] <> T_178455.outer
    outer_arb.in[1] <> T_178456.outer
    outer_arb.in[2] <> T_178457.outer
    outer_arb.in[3] <> wb.outer
    outer <> outer_arb.out
    inst T_178540 of RRArbiter_105103
    meta.read <> T_178540.out
    T_178540.in[0] <> T_178455.meta.read
    T_178540.in[1] <> T_178456.meta.read
    T_178540.in[2] <> T_178457.meta.read
    inst T_178541 of RRArbiter_107737
    meta.write <> T_178541.out
    T_178541.in[0] <> T_178455.meta.write
    T_178541.in[1] <> T_178456.meta.write
    T_178541.in[2] <> T_178457.meta.write
    inst T_178542 of RRArbiter_107931
    data.read <> T_178542.out
    T_178542.in[0] <> T_178455.data.read
    T_178542.in[1] <> T_178456.data.read
    T_178542.in[2] <> T_178457.data.read
    T_178542.in[3] <> wb.data.read
    inst T_178543 of RRArbiter_108094
    data.write <> T_178543.out
    T_178543.in[0] <> T_178455.data.write
    T_178543.in[1] <> T_178456.data.write
    T_178543.in[2] <> T_178457.data.write
    T_178455.meta.resp.bits := meta.resp.bits
    T_178456.meta.resp.bits := meta.resp.bits
    T_178457.meta.resp.bits := meta.resp.bits
    node T_178544 = eq(meta.resp.bits.id, UInt<1>(0))
    node T_178545 = and(meta.resp.valid, T_178544)
    T_178455.meta.resp.valid := T_178545
    node T_178546 = eq(meta.resp.bits.id, UInt<1>(1))
    node T_178547 = and(meta.resp.valid, T_178546)
    T_178456.meta.resp.valid := T_178547
    node T_178548 = eq(meta.resp.bits.id, UInt<2>(2))
    node T_178549 = and(meta.resp.valid, T_178548)
    T_178457.meta.resp.valid := T_178549
    T_178455.data.resp.bits := data.resp.bits
    T_178456.data.resp.bits := data.resp.bits
    T_178457.data.resp.bits := data.resp.bits
    wb.data.resp.bits := data.resp.bits
    node T_178550 = eq(data.resp.bits.id, UInt<1>(0))
    node T_178551 = and(data.resp.valid, T_178550)
    T_178455.data.resp.valid := T_178551
    node T_178552 = eq(data.resp.bits.id, UInt<1>(1))
    node T_178553 = and(data.resp.valid, T_178552)
    T_178456.data.resp.valid := T_178553
    node T_178554 = eq(data.resp.bits.id, UInt<2>(2))
    node T_178555 = and(data.resp.valid, T_178554)
    T_178457.data.resp.valid := T_178555
    node T_178556 = eq(data.resp.bits.id, UInt<2>(3))
    node T_178557 = and(data.resp.valid, T_178556)
    wb.data.resp.valid := T_178557
  module L2HellaCacheBank : 
    output inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<2>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<2>}}}
    input incoherent : UInt<1>[1]
    output outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    
    wire T_178558 : UInt<3>[3]
    T_178558[0] := UInt<3>(0)
    T_178558[1] := UInt<3>(1)
    T_178558[2] := UInt<3>(2)
    wire T_178559 : UInt<2>[2]
    T_178559[0] := UInt<2>(0)
    T_178559[1] := UInt<2>(1)
    wire T_178560 : UInt<2>[3]
    T_178560[0] := UInt<2>(1)
    T_178560[1] := UInt<2>(2)
    T_178560[2] := UInt<2>(3)
    wire T_178561 : UInt<2>[2]
    T_178561[0] := UInt<2>(2)
    T_178561[1] := UInt<2>(3)
    wire T_178562 : UInt<2>[1]
    T_178562[0] := UInt<2>(3)
    wire T_178563 : UInt<3>[3]
    T_178563[0] := UInt<3>(0)
    T_178563[1] := UInt<3>(1)
    T_178563[2] := UInt<3>(2)
    wire T_178564 : UInt<2>[2]
    T_178564[0] := UInt<2>(0)
    T_178564[1] := UInt<2>(1)
    wire T_178565 : UInt<2>[3]
    T_178565[0] := UInt<2>(1)
    T_178565[1] := UInt<2>(2)
    T_178565[2] := UInt<2>(3)
    wire T_178566 : UInt<2>[2]
    T_178566[0] := UInt<2>(2)
    T_178566[1] := UInt<2>(3)
    wire T_178567 : UInt<2>[1]
    T_178567[0] := UInt<2>(3)
    wire T_178568 : UInt<3>[3]
    T_178568[0] := UInt<3>(0)
    T_178568[1] := UInt<3>(1)
    T_178568[2] := UInt<3>(2)
    wire T_178569 : UInt<2>[2]
    T_178569[0] := UInt<2>(0)
    T_178569[1] := UInt<2>(1)
    wire T_178570 : UInt<2>[3]
    T_178570[0] := UInt<2>(1)
    T_178570[1] := UInt<2>(2)
    T_178570[2] := UInt<2>(3)
    wire T_178571 : UInt<2>[2]
    T_178571[0] := UInt<2>(2)
    T_178571[1] := UInt<2>(3)
    wire T_178572 : UInt<2>[1]
    T_178572[0] := UInt<2>(3)
    wire T_178573 : UInt<3>[3]
    T_178573[0] := UInt<3>(0)
    T_178573[1] := UInt<3>(1)
    T_178573[2] := UInt<3>(2)
    wire T_178574 : UInt<2>[2]
    T_178574[0] := UInt<2>(0)
    T_178574[1] := UInt<2>(1)
    wire T_178575 : UInt<2>[3]
    T_178575[0] := UInt<2>(1)
    T_178575[1] := UInt<2>(2)
    T_178575[2] := UInt<2>(3)
    wire T_178576 : UInt<2>[2]
    T_178576[0] := UInt<2>(2)
    T_178576[1] := UInt<2>(3)
    wire T_178577 : UInt<2>[1]
    T_178577[0] := UInt<2>(3)
    wire T_178578 : UInt<3>[3]
    T_178578[0] := UInt<3>(0)
    T_178578[1] := UInt<3>(1)
    T_178578[2] := UInt<3>(2)
    wire T_178579 : UInt<2>[2]
    T_178579[0] := UInt<2>(0)
    T_178579[1] := UInt<2>(1)
    wire T_178580 : UInt<2>[3]
    T_178580[0] := UInt<2>(1)
    T_178580[1] := UInt<2>(2)
    T_178580[2] := UInt<2>(3)
    wire T_178581 : UInt<2>[2]
    T_178581[0] := UInt<2>(2)
    T_178581[1] := UInt<2>(3)
    wire T_178582 : UInt<2>[1]
    T_178582[0] := UInt<2>(3)
    wire T_178583 : UInt<3>[3]
    T_178583[0] := UInt<3>(0)
    T_178583[1] := UInt<3>(1)
    T_178583[2] := UInt<3>(2)
    wire T_178584 : UInt<2>[2]
    T_178584[0] := UInt<2>(0)
    T_178584[1] := UInt<2>(1)
    wire T_178585 : UInt<2>[3]
    T_178585[0] := UInt<2>(1)
    T_178585[1] := UInt<2>(2)
    T_178585[2] := UInt<2>(3)
    wire T_178586 : UInt<2>[2]
    T_178586[0] := UInt<2>(2)
    T_178586[1] := UInt<2>(3)
    wire T_178587 : UInt<2>[1]
    T_178587[0] := UInt<2>(3)
    wire T_178588 : UInt<3>[3]
    T_178588[0] := UInt<3>(0)
    T_178588[1] := UInt<3>(1)
    T_178588[2] := UInt<3>(2)
    wire T_178589 : UInt<2>[2]
    T_178589[0] := UInt<2>(0)
    T_178589[1] := UInt<2>(1)
    wire T_178590 : UInt<2>[3]
    T_178590[0] := UInt<2>(1)
    T_178590[1] := UInt<2>(2)
    T_178590[2] := UInt<2>(3)
    wire T_178591 : UInt<2>[2]
    T_178591[0] := UInt<2>(2)
    T_178591[1] := UInt<2>(3)
    wire T_178592 : UInt<2>[1]
    T_178592[0] := UInt<2>(3)
    wire T_178593 : UInt<3>[3]
    T_178593[0] := UInt<3>(0)
    T_178593[1] := UInt<3>(1)
    T_178593[2] := UInt<3>(2)
    wire T_178594 : UInt<2>[2]
    T_178594[0] := UInt<2>(0)
    T_178594[1] := UInt<2>(1)
    wire T_178595 : UInt<2>[3]
    T_178595[0] := UInt<2>(1)
    T_178595[1] := UInt<2>(2)
    T_178595[2] := UInt<2>(3)
    wire T_178596 : UInt<2>[2]
    T_178596[0] := UInt<2>(2)
    T_178596[1] := UInt<2>(3)
    wire T_178597 : UInt<2>[1]
    T_178597[0] := UInt<2>(3)
    wire T_178598 : UInt<3>[3]
    T_178598[0] := UInt<3>(0)
    T_178598[1] := UInt<3>(1)
    T_178598[2] := UInt<3>(2)
    wire T_178599 : UInt<2>[2]
    T_178599[0] := UInt<2>(0)
    T_178599[1] := UInt<2>(1)
    wire T_178600 : UInt<2>[3]
    T_178600[0] := UInt<2>(1)
    T_178600[1] := UInt<2>(2)
    T_178600[2] := UInt<2>(3)
    wire T_178601 : UInt<2>[2]
    T_178601[0] := UInt<2>(2)
    T_178601[1] := UInt<2>(3)
    wire T_178602 : UInt<2>[1]
    T_178602[0] := UInt<2>(3)
    wire T_178603 : UInt<3>[3]
    T_178603[0] := UInt<3>(0)
    T_178603[1] := UInt<3>(1)
    T_178603[2] := UInt<3>(2)
    wire T_178604 : UInt<2>[2]
    T_178604[0] := UInt<2>(0)
    T_178604[1] := UInt<2>(1)
    wire T_178605 : UInt<2>[3]
    T_178605[0] := UInt<2>(1)
    T_178605[1] := UInt<2>(2)
    T_178605[2] := UInt<2>(3)
    wire T_178606 : UInt<2>[2]
    T_178606[0] := UInt<2>(2)
    T_178606[1] := UInt<2>(3)
    wire T_178607 : UInt<2>[1]
    T_178607[0] := UInt<2>(3)
    wire T_178608 : UInt<3>[3]
    T_178608[0] := UInt<3>(0)
    T_178608[1] := UInt<3>(1)
    T_178608[2] := UInt<3>(2)
    wire T_178609 : UInt<2>[2]
    T_178609[0] := UInt<2>(0)
    T_178609[1] := UInt<2>(1)
    wire T_178610 : UInt<2>[3]
    T_178610[0] := UInt<2>(1)
    T_178610[1] := UInt<2>(2)
    T_178610[2] := UInt<2>(3)
    wire T_178611 : UInt<2>[2]
    T_178611[0] := UInt<2>(2)
    T_178611[1] := UInt<2>(3)
    wire T_178612 : UInt<2>[1]
    T_178612[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_178613
    wire T_178614 : UInt<3>[3]
    T_178614[0] := UInt<3>(0)
    T_178614[1] := UInt<3>(1)
    T_178614[2] := UInt<3>(2)
    wire T_178615 : UInt<0>[1]
    T_178615[0] := UInt<0>(0)
    wire T_178616 : UInt<2>[2]
    T_178616[0] := UInt<2>(1)
    T_178616[1] := UInt<2>(2)
    wire T_178617 : UInt<2>[2]
    T_178617[0] := UInt<2>(1)
    T_178617[1] := UInt<2>(2)
    wire T_178618 : UInt<2>[1]
    T_178618[0] := UInt<2>(2)
    wire T_178619 : UInt<3>[3]
    T_178619[0] := UInt<3>(0)
    T_178619[1] := UInt<3>(1)
    T_178619[2] := UInt<3>(2)
    wire T_178620 : UInt<0>[1]
    T_178620[0] := UInt<0>(0)
    wire T_178621 : UInt<2>[2]
    T_178621[0] := UInt<2>(1)
    T_178621[1] := UInt<2>(2)
    wire T_178622 : UInt<2>[2]
    T_178622[0] := UInt<2>(1)
    T_178622[1] := UInt<2>(2)
    wire T_178623 : UInt<2>[1]
    T_178623[0] := UInt<2>(2)
    wire T_178624 : UInt<3>[3]
    T_178624[0] := UInt<3>(0)
    T_178624[1] := UInt<3>(1)
    T_178624[2] := UInt<3>(2)
    wire T_178625 : UInt<0>[1]
    T_178625[0] := UInt<0>(0)
    wire T_178626 : UInt<2>[2]
    T_178626[0] := UInt<2>(1)
    T_178626[1] := UInt<2>(2)
    wire T_178627 : UInt<2>[2]
    T_178627[0] := UInt<2>(1)
    T_178627[1] := UInt<2>(2)
    wire T_178628 : UInt<2>[1]
    T_178628[0] := UInt<2>(2)
    wire T_178629 : UInt<3>[3]
    T_178629[0] := UInt<3>(0)
    T_178629[1] := UInt<3>(1)
    T_178629[2] := UInt<3>(2)
    wire T_178630 : UInt<0>[1]
    T_178630[0] := UInt<0>(0)
    wire T_178631 : UInt<2>[2]
    T_178631[0] := UInt<2>(1)
    T_178631[1] := UInt<2>(2)
    wire T_178632 : UInt<2>[2]
    T_178632[0] := UInt<2>(1)
    T_178632[1] := UInt<2>(2)
    wire T_178633 : UInt<2>[1]
    T_178633[0] := UInt<2>(2)
    wire T_178634 : UInt<3>[3]
    T_178634[0] := UInt<3>(0)
    T_178634[1] := UInt<3>(1)
    T_178634[2] := UInt<3>(2)
    wire T_178635 : UInt<0>[1]
    T_178635[0] := UInt<0>(0)
    wire T_178636 : UInt<2>[2]
    T_178636[0] := UInt<2>(1)
    T_178636[1] := UInt<2>(2)
    wire T_178637 : UInt<2>[2]
    T_178637[0] := UInt<2>(1)
    T_178637[1] := UInt<2>(2)
    wire T_178638 : UInt<2>[1]
    T_178638[0] := UInt<2>(2)
    wire T_178639 : UInt<3>[3]
    T_178639[0] := UInt<3>(0)
    T_178639[1] := UInt<3>(1)
    T_178639[2] := UInt<3>(2)
    wire T_178640 : UInt<0>[1]
    T_178640[0] := UInt<0>(0)
    wire T_178641 : UInt<2>[2]
    T_178641[0] := UInt<2>(1)
    T_178641[1] := UInt<2>(2)
    wire T_178642 : UInt<2>[2]
    T_178642[0] := UInt<2>(1)
    T_178642[1] := UInt<2>(2)
    wire T_178643 : UInt<2>[1]
    T_178643[0] := UInt<2>(2)
    wire T_178644 : UInt<3>[3]
    T_178644[0] := UInt<3>(0)
    T_178644[1] := UInt<3>(1)
    T_178644[2] := UInt<3>(2)
    wire T_178645 : UInt<0>[1]
    T_178645[0] := UInt<0>(0)
    wire T_178646 : UInt<2>[2]
    T_178646[0] := UInt<2>(1)
    T_178646[1] := UInt<2>(2)
    wire T_178647 : UInt<2>[2]
    T_178647[0] := UInt<2>(1)
    T_178647[1] := UInt<2>(2)
    wire T_178648 : UInt<2>[1]
    T_178648[0] := UInt<2>(2)
    wire T_178649 : UInt<3>[3]
    T_178649[0] := UInt<3>(0)
    T_178649[1] := UInt<3>(1)
    T_178649[2] := UInt<3>(2)
    wire T_178650 : UInt<0>[1]
    T_178650[0] := UInt<0>(0)
    wire T_178651 : UInt<2>[2]
    T_178651[0] := UInt<2>(1)
    T_178651[1] := UInt<2>(2)
    wire T_178652 : UInt<2>[2]
    T_178652[0] := UInt<2>(1)
    T_178652[1] := UInt<2>(2)
    wire T_178653 : UInt<2>[1]
    T_178653[0] := UInt<2>(2)
    wire T_178654 : UInt<3>[3]
    T_178654[0] := UInt<3>(0)
    T_178654[1] := UInt<3>(1)
    T_178654[2] := UInt<3>(2)
    wire T_178655 : UInt<0>[1]
    T_178655[0] := UInt<0>(0)
    wire T_178656 : UInt<2>[2]
    T_178656[0] := UInt<2>(1)
    T_178656[1] := UInt<2>(2)
    wire T_178657 : UInt<2>[2]
    T_178657[0] := UInt<2>(1)
    T_178657[1] := UInt<2>(2)
    wire T_178658 : UInt<2>[1]
    T_178658[0] := UInt<2>(2)
    inst meta of L2MetadataArray
    inst data of L2DataArray
    inst tshrfile of TSHRFile
    tshrfile.inner <> inner
    outer <> tshrfile.outer
    incoherent[0] <> tshrfile.incoherent[0]
    tshrfile.meta <> meta
    tshrfile.data <> data
  module FinishQueue_113456 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}}
    output count : UInt<2>
    
    wire T_178659 : UInt<3>[3]
    T_178659[0] := UInt<3>(0)
    T_178659[1] := UInt<3>(1)
    T_178659[2] := UInt<3>(2)
    wire T_178660 : UInt<0>[1]
    T_178660[0] := UInt<0>(0)
    wire T_178661 : UInt<2>[2]
    T_178661[0] := UInt<2>(1)
    T_178661[1] := UInt<2>(2)
    wire T_178662 : UInt<2>[2]
    T_178662[0] := UInt<2>(1)
    T_178662[1] := UInt<2>(2)
    wire T_178663 : UInt<2>[1]
    T_178663[0] := UInt<2>(2)
    wire T_178664 : UInt<3>[3]
    T_178664[0] := UInt<3>(0)
    T_178664[1] := UInt<3>(1)
    T_178664[2] := UInt<3>(2)
    wire T_178665 : UInt<0>[1]
    T_178665[0] := UInt<0>(0)
    wire T_178666 : UInt<2>[2]
    T_178666[0] := UInt<2>(1)
    T_178666[1] := UInt<2>(2)
    wire T_178667 : UInt<2>[2]
    T_178667[0] := UInt<2>(1)
    T_178667[1] := UInt<2>(2)
    wire T_178668 : UInt<2>[1]
    T_178668[0] := UInt<2>(2)
    wire T_178669 : UInt<3>[3]
    T_178669[0] := UInt<3>(0)
    T_178669[1] := UInt<3>(1)
    T_178669[2] := UInt<3>(2)
    wire T_178670 : UInt<0>[1]
    T_178670[0] := UInt<0>(0)
    wire T_178671 : UInt<2>[2]
    T_178671[0] := UInt<2>(1)
    T_178671[1] := UInt<2>(2)
    wire T_178672 : UInt<2>[2]
    T_178672[0] := UInt<2>(1)
    T_178672[1] := UInt<2>(2)
    wire T_178673 : UInt<2>[1]
    T_178673[0] := UInt<2>(2)
    wire T_178674 : UInt<3>[3]
    T_178674[0] := UInt<3>(0)
    T_178674[1] := UInt<3>(1)
    T_178674[2] := UInt<3>(2)
    wire T_178675 : UInt<0>[1]
    T_178675[0] := UInt<0>(0)
    wire T_178676 : UInt<2>[2]
    T_178676[0] := UInt<2>(1)
    T_178676[1] := UInt<2>(2)
    wire T_178677 : UInt<2>[2]
    T_178677[0] := UInt<2>(1)
    T_178677[1] := UInt<2>(2)
    wire T_178678 : UInt<2>[1]
    T_178678[0] := UInt<2>(2)
    wire T_178679 : UInt<3>[3]
    T_178679[0] := UInt<3>(0)
    T_178679[1] := UInt<3>(1)
    T_178679[2] := UInt<3>(2)
    wire T_178680 : UInt<0>[1]
    T_178680[0] := UInt<0>(0)
    wire T_178681 : UInt<2>[2]
    T_178681[0] := UInt<2>(1)
    T_178681[1] := UInt<2>(2)
    wire T_178682 : UInt<2>[2]
    T_178682[0] := UInt<2>(1)
    T_178682[1] := UInt<2>(2)
    wire T_178683 : UInt<2>[1]
    T_178683[0] := UInt<2>(2)
    wire T_178684 : UInt<3>[3]
    T_178684[0] := UInt<3>(0)
    T_178684[1] := UInt<3>(1)
    T_178684[2] := UInt<3>(2)
    wire T_178685 : UInt<0>[1]
    T_178685[0] := UInt<0>(0)
    wire T_178686 : UInt<2>[2]
    T_178686[0] := UInt<2>(1)
    T_178686[1] := UInt<2>(2)
    wire T_178687 : UInt<2>[2]
    T_178687[0] := UInt<2>(1)
    T_178687[1] := UInt<2>(2)
    wire T_178688 : UInt<2>[1]
    T_178688[0] := UInt<2>(2)
    wire T_178689 : UInt<3>[3]
    T_178689[0] := UInt<3>(0)
    T_178689[1] := UInt<3>(1)
    T_178689[2] := UInt<3>(2)
    wire T_178690 : UInt<0>[1]
    T_178690[0] := UInt<0>(0)
    wire T_178691 : UInt<2>[2]
    T_178691[0] := UInt<2>(1)
    T_178691[1] := UInt<2>(2)
    wire T_178692 : UInt<2>[2]
    T_178692[0] := UInt<2>(1)
    T_178692[1] := UInt<2>(2)
    wire T_178693 : UInt<2>[1]
    T_178693[0] := UInt<2>(2)
    wire T_178694 : UInt<3>[3]
    T_178694[0] := UInt<3>(0)
    T_178694[1] := UInt<3>(1)
    T_178694[2] := UInt<3>(2)
    wire T_178695 : UInt<0>[1]
    T_178695[0] := UInt<0>(0)
    wire T_178696 : UInt<2>[2]
    T_178696[0] := UInt<2>(1)
    T_178696[1] := UInt<2>(2)
    wire T_178697 : UInt<2>[2]
    T_178697[0] := UInt<2>(1)
    T_178697[1] := UInt<2>(2)
    wire T_178698 : UInt<2>[1]
    T_178698[0] := UInt<2>(2)
    wire T_178699 : UInt<3>[3]
    T_178699[0] := UInt<3>(0)
    T_178699[1] := UInt<3>(1)
    T_178699[2] := UInt<3>(2)
    wire T_178700 : UInt<0>[1]
    T_178700[0] := UInt<0>(0)
    wire T_178701 : UInt<2>[2]
    T_178701[0] := UInt<2>(1)
    T_178701[1] := UInt<2>(2)
    wire T_178702 : UInt<2>[2]
    T_178702[0] := UInt<2>(1)
    T_178702[1] := UInt<2>(2)
    wire T_178703 : UInt<2>[1]
    T_178703[0] := UInt<2>(2)
    wire T_178704 : UInt<3>[3]
    T_178704[0] := UInt<3>(0)
    T_178704[1] := UInt<3>(1)
    T_178704[2] := UInt<3>(2)
    wire T_178705 : UInt<0>[1]
    T_178705[0] := UInt<0>(0)
    wire T_178706 : UInt<2>[2]
    T_178706[0] := UInt<2>(1)
    T_178706[1] := UInt<2>(2)
    wire T_178707 : UInt<2>[2]
    T_178707[0] := UInt<2>(1)
    T_178707[1] := UInt<2>(2)
    wire T_178708 : UInt<2>[1]
    T_178708[0] := UInt<2>(2)
    cmem T_178709 : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}[2]
    reg T_178710 : UInt<1>
    onreset T_178710 := UInt<1>(0)
    reg T_178711 : UInt<1>
    onreset T_178711 := UInt<1>(0)
    reg T_178712 : UInt<1>
    onreset T_178712 := UInt<1>(0)
    node T_178713 = eq(T_178710, T_178711)
    node T_178714 = eq(T_178712, UInt<1>(0))
    node T_178715 = and(T_178713, T_178714)
    node T_178716 = and(T_178713, T_178712)
    node T_178717 = and(UInt<1>(0), T_178715)
    node T_178718 = and(T_178717, deq.ready)
    node T_178719 = and(enq.ready, enq.valid)
    node T_178720 = eq(T_178718, UInt<1>(0))
    node T_178721 = and(T_178719, T_178720)
    node T_178722 = and(deq.ready, deq.valid)
    node T_178723 = eq(T_178718, UInt<1>(0))
    node T_178724 = and(T_178722, T_178723)
    when T_178721 : 
      wire T_178725 : UInt<3>[3]
      T_178725[0] := UInt<3>(0)
      T_178725[1] := UInt<3>(1)
      T_178725[2] := UInt<3>(2)
      wire T_178726 : UInt<0>[1]
      T_178726[0] := UInt<0>(0)
      wire T_178727 : UInt<2>[2]
      T_178727[0] := UInt<2>(1)
      T_178727[1] := UInt<2>(2)
      wire T_178728 : UInt<2>[2]
      T_178728[0] := UInt<2>(1)
      T_178728[1] := UInt<2>(2)
      wire T_178729 : UInt<2>[1]
      T_178729[0] := UInt<2>(2)
      wire T_178730 : UInt<3>[3]
      T_178730[0] := UInt<3>(0)
      T_178730[1] := UInt<3>(1)
      T_178730[2] := UInt<3>(2)
      wire T_178731 : UInt<0>[1]
      T_178731[0] := UInt<0>(0)
      wire T_178732 : UInt<2>[2]
      T_178732[0] := UInt<2>(1)
      T_178732[1] := UInt<2>(2)
      wire T_178733 : UInt<2>[2]
      T_178733[0] := UInt<2>(1)
      T_178733[1] := UInt<2>(2)
      wire T_178734 : UInt<2>[1]
      T_178734[0] := UInt<2>(2)
      accessor T_178735 = T_178709[T_178710]
      T_178735 := enq.bits
      node T_178736 = eq(T_178710, UInt<1>(1))
      node T_178737 = and(UInt<1>(0), T_178736)
      node T_178738 = addw(T_178710, UInt<1>(1))
      wire T_178739 : UInt<1>
      T_178739 := T_178738
      when T_178737 : T_178739 := UInt<1>(0)
      T_178710 := T_178739
    when T_178724 : 
      node T_178740 = eq(T_178711, UInt<1>(1))
      node T_178741 = and(UInt<1>(0), T_178740)
      node T_178742 = addw(T_178711, UInt<1>(1))
      wire T_178743 : UInt<1>
      T_178743 := T_178742
      when T_178741 : T_178743 := UInt<1>(0)
      T_178711 := T_178743
    
    node T_178744 = neq(T_178721, T_178724)
    when T_178744 : T_178712 := T_178721
    node T_178745 = eq(T_178715, UInt<1>(0))
    node T_178746 = and(UInt<1>(0), enq.valid)
    node T_178747 = or(T_178745, T_178746)
    deq.valid := T_178747
    node T_178748 = eq(T_178716, UInt<1>(0))
    node T_178749 = and(UInt<1>(0), deq.ready)
    node T_178750 = or(T_178748, T_178749)
    enq.ready := T_178750
    wire T_178751 : UInt<3>[3]
    T_178751[0] := UInt<3>(0)
    T_178751[1] := UInt<3>(1)
    T_178751[2] := UInt<3>(2)
    wire T_178752 : UInt<0>[1]
    T_178752[0] := UInt<0>(0)
    wire T_178753 : UInt<2>[2]
    T_178753[0] := UInt<2>(1)
    T_178753[1] := UInt<2>(2)
    wire T_178754 : UInt<2>[2]
    T_178754[0] := UInt<2>(1)
    T_178754[1] := UInt<2>(2)
    wire T_178755 : UInt<2>[1]
    T_178755[0] := UInt<2>(2)
    wire T_178756 : UInt<3>[3]
    T_178756[0] := UInt<3>(0)
    T_178756[1] := UInt<3>(1)
    T_178756[2] := UInt<3>(2)
    wire T_178757 : UInt<0>[1]
    T_178757[0] := UInt<0>(0)
    wire T_178758 : UInt<2>[2]
    T_178758[0] := UInt<2>(1)
    T_178758[1] := UInt<2>(2)
    wire T_178759 : UInt<2>[2]
    T_178759[0] := UInt<2>(1)
    T_178759[1] := UInt<2>(2)
    wire T_178760 : UInt<2>[1]
    T_178760[0] := UInt<2>(2)
    accessor T_178761 = T_178709[T_178711]
    wire T_178762 : UInt<3>[3]
    T_178762[0] := UInt<3>(0)
    T_178762[1] := UInt<3>(1)
    T_178762[2] := UInt<3>(2)
    wire T_178763 : UInt<0>[1]
    T_178763[0] := UInt<0>(0)
    wire T_178764 : UInt<2>[2]
    T_178764[0] := UInt<2>(1)
    T_178764[1] := UInt<2>(2)
    wire T_178765 : UInt<2>[2]
    T_178765[0] := UInt<2>(1)
    T_178765[1] := UInt<2>(2)
    wire T_178766 : UInt<2>[1]
    T_178766[0] := UInt<2>(2)
    wire T_178767 : UInt<3>[3]
    T_178767[0] := UInt<3>(0)
    T_178767[1] := UInt<3>(1)
    T_178767[2] := UInt<3>(2)
    wire T_178768 : UInt<0>[1]
    T_178768[0] := UInt<0>(0)
    wire T_178769 : UInt<2>[2]
    T_178769[0] := UInt<2>(1)
    T_178769[1] := UInt<2>(2)
    wire T_178770 : UInt<2>[2]
    T_178770[0] := UInt<2>(1)
    T_178770[1] := UInt<2>(2)
    wire T_178771 : UInt<2>[1]
    T_178771[0] := UInt<2>(2)
    wire T_178772 : {fin : {manager_xact_id : UInt<1>}, dst : UInt<1>}
    T_178772 := T_178761
    when T_178717 : T_178772 := enq.bits
    deq.bits := T_178772
    node T_178773 = subw(T_178710, T_178711)
    node T_178774 = and(T_178712, T_178713)
    node T_178775 = cat(T_178774, T_178773)
    count := T_178775
  module FinishUnit_113600 : 
    input grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}
    output ready : UInt<1>
    
    wire T_178776 : UInt<3>[3]
    T_178776[0] := UInt<3>(0)
    T_178776[1] := UInt<3>(1)
    T_178776[2] := UInt<3>(2)
    wire T_178777 : UInt<0>[1]
    T_178777[0] := UInt<0>(0)
    wire T_178778 : UInt<2>[2]
    T_178778[0] := UInt<2>(1)
    T_178778[1] := UInt<2>(2)
    wire T_178779 : UInt<2>[2]
    T_178779[0] := UInt<2>(1)
    T_178779[1] := UInt<2>(2)
    wire T_178780 : UInt<2>[1]
    T_178780[0] := UInt<2>(2)
    wire T_178781 : UInt<3>[3]
    T_178781[0] := UInt<3>(0)
    T_178781[1] := UInt<3>(1)
    T_178781[2] := UInt<3>(2)
    wire T_178782 : UInt<0>[1]
    T_178782[0] := UInt<0>(0)
    wire T_178783 : UInt<2>[2]
    T_178783[0] := UInt<2>(1)
    T_178783[1] := UInt<2>(2)
    wire T_178784 : UInt<2>[2]
    T_178784[0] := UInt<2>(1)
    T_178784[1] := UInt<2>(2)
    wire T_178785 : UInt<2>[1]
    T_178785[0] := UInt<2>(2)
    wire T_178786 : UInt<3>[3]
    T_178786[0] := UInt<3>(0)
    T_178786[1] := UInt<3>(1)
    T_178786[2] := UInt<3>(2)
    wire T_178787 : UInt<0>[1]
    T_178787[0] := UInt<0>(0)
    wire T_178788 : UInt<2>[2]
    T_178788[0] := UInt<2>(1)
    T_178788[1] := UInt<2>(2)
    wire T_178789 : UInt<2>[2]
    T_178789[0] := UInt<2>(1)
    T_178789[1] := UInt<2>(2)
    wire T_178790 : UInt<2>[1]
    T_178790[0] := UInt<2>(2)
    wire T_178791 : UInt<3>[3]
    T_178791[0] := UInt<3>(0)
    T_178791[1] := UInt<3>(1)
    T_178791[2] := UInt<3>(2)
    wire T_178792 : UInt<0>[1]
    T_178792[0] := UInt<0>(0)
    wire T_178793 : UInt<2>[2]
    T_178793[0] := UInt<2>(1)
    T_178793[1] := UInt<2>(2)
    wire T_178794 : UInt<2>[2]
    T_178794[0] := UInt<2>(1)
    T_178794[1] := UInt<2>(2)
    wire T_178795 : UInt<2>[1]
    T_178795[0] := UInt<2>(2)
    wire T_178796 : UInt<3>[3]
    T_178796[0] := UInt<3>(0)
    T_178796[1] := UInt<3>(1)
    T_178796[2] := UInt<3>(2)
    wire T_178797 : UInt<0>[1]
    T_178797[0] := UInt<0>(0)
    wire T_178798 : UInt<2>[2]
    T_178798[0] := UInt<2>(1)
    T_178798[1] := UInt<2>(2)
    wire T_178799 : UInt<2>[2]
    T_178799[0] := UInt<2>(1)
    T_178799[1] := UInt<2>(2)
    wire T_178800 : UInt<2>[1]
    T_178800[0] := UInt<2>(2)
    wire T_178801 : UInt<3>[3]
    T_178801[0] := UInt<3>(0)
    T_178801[1] := UInt<3>(1)
    T_178801[2] := UInt<3>(2)
    wire T_178802 : UInt<0>[1]
    T_178802[0] := UInt<0>(0)
    wire T_178803 : UInt<2>[2]
    T_178803[0] := UInt<2>(1)
    T_178803[1] := UInt<2>(2)
    wire T_178804 : UInt<2>[2]
    T_178804[0] := UInt<2>(1)
    T_178804[1] := UInt<2>(2)
    wire T_178805 : UInt<2>[1]
    T_178805[0] := UInt<2>(2)
    wire T_178806 : UInt<3>[3]
    T_178806[0] := UInt<3>(0)
    T_178806[1] := UInt<3>(1)
    T_178806[2] := UInt<3>(2)
    wire T_178807 : UInt<0>[1]
    T_178807[0] := UInt<0>(0)
    wire T_178808 : UInt<2>[2]
    T_178808[0] := UInt<2>(1)
    T_178808[1] := UInt<2>(2)
    wire T_178809 : UInt<2>[2]
    T_178809[0] := UInt<2>(1)
    T_178809[1] := UInt<2>(2)
    wire T_178810 : UInt<2>[1]
    T_178810[0] := UInt<2>(2)
    wire T_178811 : UInt<3>[3]
    T_178811[0] := UInt<3>(0)
    T_178811[1] := UInt<3>(1)
    T_178811[2] := UInt<3>(2)
    wire T_178812 : UInt<0>[1]
    T_178812[0] := UInt<0>(0)
    wire T_178813 : UInt<2>[2]
    T_178813[0] := UInt<2>(1)
    T_178813[1] := UInt<2>(2)
    wire T_178814 : UInt<2>[2]
    T_178814[0] := UInt<2>(1)
    T_178814[1] := UInt<2>(2)
    wire T_178815 : UInt<2>[1]
    T_178815[0] := UInt<2>(2)
    wire T_178816 : UInt<3>[3]
    T_178816[0] := UInt<3>(0)
    T_178816[1] := UInt<3>(1)
    T_178816[2] := UInt<3>(2)
    wire T_178817 : UInt<0>[1]
    T_178817[0] := UInt<0>(0)
    wire T_178818 : UInt<2>[2]
    T_178818[0] := UInt<2>(1)
    T_178818[1] := UInt<2>(2)
    wire T_178819 : UInt<2>[2]
    T_178819[0] := UInt<2>(1)
    T_178819[1] := UInt<2>(2)
    wire T_178820 : UInt<2>[1]
    T_178820[0] := UInt<2>(2)
    node T_178821 = and(grant.ready, grant.valid)
    wire T_178822 : UInt<3>[1]
    T_178822[0] := UInt<3>(5)
    node T_178823 = eq(T_178822[0], grant.bits.payload.g_type)
    node T_178824 = or(UInt<1>(0), T_178823)
    node T_178825 = eq(T_178792[0], grant.bits.payload.g_type)
    node T_178826 = or(UInt<1>(0), T_178825)
    wire T_178827 : UInt<1>
    T_178827 := T_178826
    when grant.bits.payload.is_builtin_type : T_178827 := T_178824
    node T_178828 = and(UInt<1>(1), T_178827)
    node T_178829 = and(T_178821, T_178828)
    reg T_178830 : UInt<2>
    onreset T_178830 := UInt<2>(0)
    when T_178829 : 
      node T_178831 = eq(T_178830, UInt<2>(3))
      node T_178832 = and(UInt<1>(0), T_178831)
      node T_178833 = addw(T_178830, UInt<1>(1))
      wire T_178834 : UInt<2>
      T_178834 := T_178833
      when T_178832 : T_178834 := UInt<1>(0)
      T_178830 := T_178834
    node T_178835 = and(T_178829, T_178831)
    wire T_178836 : UInt<1>
    T_178836 := UInt<1>(0)
    when T_178828 : T_178836 := T_178830
    wire T_178837 : UInt<1>
    T_178837 := T_178821
    when T_178828 : T_178837 := T_178835
    wire T_178838 : UInt<3>[3]
    T_178838[0] := UInt<3>(0)
    T_178838[1] := UInt<3>(1)
    T_178838[2] := UInt<3>(2)
    wire T_178839 : UInt<0>[1]
    T_178839[0] := UInt<0>(0)
    wire T_178840 : UInt<2>[2]
    T_178840[0] := UInt<2>(1)
    T_178840[1] := UInt<2>(2)
    wire T_178841 : UInt<2>[2]
    T_178841[0] := UInt<2>(1)
    T_178841[1] := UInt<2>(2)
    wire T_178842 : UInt<2>[1]
    T_178842[0] := UInt<2>(2)
    wire T_178843 : UInt<3>[3]
    T_178843[0] := UInt<3>(0)
    T_178843[1] := UInt<3>(1)
    T_178843[2] := UInt<3>(2)
    wire T_178844 : UInt<0>[1]
    T_178844[0] := UInt<0>(0)
    wire T_178845 : UInt<2>[2]
    T_178845[0] := UInt<2>(1)
    T_178845[1] := UInt<2>(2)
    wire T_178846 : UInt<2>[2]
    T_178846[0] := UInt<2>(1)
    T_178846[1] := UInt<2>(2)
    wire T_178847 : UInt<2>[1]
    T_178847[0] := UInt<2>(2)
    inst T_178848 of FinishQueue_113456
    node T_178849 = and(grant.ready, grant.valid)
    node T_178850 = eq(UInt<1>(0), UInt<1>(0))
    node T_178851 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_178852 = and(grant.bits.payload.is_builtin_type, T_178851)
    node T_178853 = eq(T_178852, UInt<1>(0))
    node T_178854 = and(T_178850, T_178853)
    node T_178855 = and(T_178849, T_178854)
    wire T_178856 : UInt<3>[1]
    T_178856[0] := UInt<3>(5)
    node T_178857 = eq(T_178856[0], grant.bits.payload.g_type)
    node T_178858 = or(UInt<1>(0), T_178857)
    node T_178859 = eq(T_178792[0], grant.bits.payload.g_type)
    node T_178860 = or(UInt<1>(0), T_178859)
    wire T_178861 : UInt<1>
    T_178861 := T_178860
    when grant.bits.payload.is_builtin_type : T_178861 := T_178858
    node T_178862 = and(UInt<1>(1), T_178861)
    node T_178863 = eq(T_178862, UInt<1>(0))
    node T_178864 = or(T_178863, T_178837)
    node T_178865 = and(T_178855, T_178864)
    T_178848.enq.valid := T_178865
    wire T_178866 : UInt<3>[3]
    T_178866[0] := UInt<3>(0)
    T_178866[1] := UInt<3>(1)
    T_178866[2] := UInt<3>(2)
    wire T_178867 : UInt<0>[1]
    T_178867[0] := UInt<0>(0)
    wire T_178868 : UInt<2>[2]
    T_178868[0] := UInt<2>(1)
    T_178868[1] := UInt<2>(2)
    wire T_178869 : UInt<2>[2]
    T_178869[0] := UInt<2>(1)
    T_178869[1] := UInt<2>(2)
    wire T_178870 : UInt<2>[1]
    T_178870[0] := UInt<2>(2)
    wire T_178871 : UInt<3>[3]
    T_178871[0] := UInt<3>(0)
    T_178871[1] := UInt<3>(1)
    T_178871[2] := UInt<3>(2)
    wire T_178872 : UInt<0>[1]
    T_178872[0] := UInt<0>(0)
    wire T_178873 : UInt<2>[2]
    T_178873[0] := UInt<2>(1)
    T_178873[1] := UInt<2>(2)
    wire T_178874 : UInt<2>[2]
    T_178874[0] := UInt<2>(1)
    T_178874[1] := UInt<2>(2)
    wire T_178875 : UInt<2>[1]
    T_178875[0] := UInt<2>(2)
    wire T_178876 : {manager_xact_id : UInt<1>}
    T_178876.manager_xact_id := grant.bits.payload.manager_xact_id
    T_178848.enq.bits.fin := T_178876
    T_178848.enq.bits.dst := grant.bits.header.src
    finish.bits.header.src := UInt<1>(0)
    finish.bits.header.dst := T_178848.deq.bits.dst
    finish.bits.payload := T_178848.deq.bits.fin
    finish.valid := T_178848.deq.valid
    T_178848.deq.ready := finish.ready
    refill.valid := grant.valid
    refill.bits := grant.bits.payload
    node T_178877 = eq(UInt<1>(0), UInt<1>(0))
    node T_178878 = eq(grant.bits.payload.g_type, UInt<3>(0))
    node T_178879 = and(grant.bits.payload.is_builtin_type, T_178878)
    node T_178880 = eq(T_178879, UInt<1>(0))
    node T_178881 = and(T_178877, T_178880)
    node T_178882 = eq(T_178881, UInt<1>(0))
    node T_178883 = or(T_178848.enq.ready, T_178882)
    node T_178884 = and(T_178883, refill.ready)
    grant.ready := T_178884
    ready := T_178848.enq.ready
  module ClientTileLinkNetworkPort_114092 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_178885 : UInt<3>[3]
    T_178885[0] := UInt<3>(0)
    T_178885[1] := UInt<3>(1)
    T_178885[2] := UInt<3>(2)
    wire T_178886 : UInt<0>[1]
    T_178886[0] := UInt<0>(0)
    wire T_178887 : UInt<2>[2]
    T_178887[0] := UInt<2>(1)
    T_178887[1] := UInt<2>(2)
    wire T_178888 : UInt<2>[2]
    T_178888[0] := UInt<2>(1)
    T_178888[1] := UInt<2>(2)
    wire T_178889 : UInt<2>[1]
    T_178889[0] := UInt<2>(2)
    wire T_178890 : UInt<3>[3]
    T_178890[0] := UInt<3>(0)
    T_178890[1] := UInt<3>(1)
    T_178890[2] := UInt<3>(2)
    wire T_178891 : UInt<0>[1]
    T_178891[0] := UInt<0>(0)
    wire T_178892 : UInt<2>[2]
    T_178892[0] := UInt<2>(1)
    T_178892[1] := UInt<2>(2)
    wire T_178893 : UInt<2>[2]
    T_178893[0] := UInt<2>(1)
    T_178893[1] := UInt<2>(2)
    wire T_178894 : UInt<2>[1]
    T_178894[0] := UInt<2>(2)
    wire T_178895 : UInt<3>[3]
    T_178895[0] := UInt<3>(0)
    T_178895[1] := UInt<3>(1)
    T_178895[2] := UInt<3>(2)
    wire T_178896 : UInt<0>[1]
    T_178896[0] := UInt<0>(0)
    wire T_178897 : UInt<2>[2]
    T_178897[0] := UInt<2>(1)
    T_178897[1] := UInt<2>(2)
    wire T_178898 : UInt<2>[2]
    T_178898[0] := UInt<2>(1)
    T_178898[1] := UInt<2>(2)
    wire T_178899 : UInt<2>[1]
    T_178899[0] := UInt<2>(2)
    wire T_178900 : UInt<3>[3]
    T_178900[0] := UInt<3>(0)
    T_178900[1] := UInt<3>(1)
    T_178900[2] := UInt<3>(2)
    wire T_178901 : UInt<0>[1]
    T_178901[0] := UInt<0>(0)
    wire T_178902 : UInt<2>[2]
    T_178902[0] := UInt<2>(1)
    T_178902[1] := UInt<2>(2)
    wire T_178903 : UInt<2>[2]
    T_178903[0] := UInt<2>(1)
    T_178903[1] := UInt<2>(2)
    wire T_178904 : UInt<2>[1]
    T_178904[0] := UInt<2>(2)
    wire T_178905 : UInt<3>[3]
    T_178905[0] := UInt<3>(0)
    T_178905[1] := UInt<3>(1)
    T_178905[2] := UInt<3>(2)
    wire T_178906 : UInt<0>[1]
    T_178906[0] := UInt<0>(0)
    wire T_178907 : UInt<2>[2]
    T_178907[0] := UInt<2>(1)
    T_178907[1] := UInt<2>(2)
    wire T_178908 : UInt<2>[2]
    T_178908[0] := UInt<2>(1)
    T_178908[1] := UInt<2>(2)
    wire T_178909 : UInt<2>[1]
    T_178909[0] := UInt<2>(2)
    wire T_178910 : UInt<3>[3]
    T_178910[0] := UInt<3>(0)
    T_178910[1] := UInt<3>(1)
    T_178910[2] := UInt<3>(2)
    wire T_178911 : UInt<0>[1]
    T_178911[0] := UInt<0>(0)
    wire T_178912 : UInt<2>[2]
    T_178912[0] := UInt<2>(1)
    T_178912[1] := UInt<2>(2)
    wire T_178913 : UInt<2>[2]
    T_178913[0] := UInt<2>(1)
    T_178913[1] := UInt<2>(2)
    wire T_178914 : UInt<2>[1]
    T_178914[0] := UInt<2>(2)
    wire T_178915 : UInt<3>[3]
    T_178915[0] := UInt<3>(0)
    T_178915[1] := UInt<3>(1)
    T_178915[2] := UInt<3>(2)
    wire T_178916 : UInt<0>[1]
    T_178916[0] := UInt<0>(0)
    wire T_178917 : UInt<2>[2]
    T_178917[0] := UInt<2>(1)
    T_178917[1] := UInt<2>(2)
    wire T_178918 : UInt<2>[2]
    T_178918[0] := UInt<2>(1)
    T_178918[1] := UInt<2>(2)
    wire T_178919 : UInt<2>[1]
    T_178919[0] := UInt<2>(2)
    wire T_178920 : UInt<3>[3]
    T_178920[0] := UInt<3>(0)
    T_178920[1] := UInt<3>(1)
    T_178920[2] := UInt<3>(2)
    wire T_178921 : UInt<0>[1]
    T_178921[0] := UInt<0>(0)
    wire T_178922 : UInt<2>[2]
    T_178922[0] := UInt<2>(1)
    T_178922[1] := UInt<2>(2)
    wire T_178923 : UInt<2>[2]
    T_178923[0] := UInt<2>(1)
    T_178923[1] := UInt<2>(2)
    wire T_178924 : UInt<2>[1]
    T_178924[0] := UInt<2>(2)
    wire T_178925 : UInt<3>[3]
    T_178925[0] := UInt<3>(0)
    T_178925[1] := UInt<3>(1)
    T_178925[2] := UInt<3>(2)
    wire T_178926 : UInt<0>[1]
    T_178926[0] := UInt<0>(0)
    wire T_178927 : UInt<2>[2]
    T_178927[0] := UInt<2>(1)
    T_178927[1] := UInt<2>(2)
    wire T_178928 : UInt<2>[2]
    T_178928[0] := UInt<2>(1)
    T_178928[1] := UInt<2>(2)
    wire T_178929 : UInt<2>[1]
    T_178929[0] := UInt<2>(2)
    wire T_178930 : UInt<3>[3]
    T_178930[0] := UInt<3>(0)
    T_178930[1] := UInt<3>(1)
    T_178930[2] := UInt<3>(2)
    wire T_178931 : UInt<0>[1]
    T_178931[0] := UInt<0>(0)
    wire T_178932 : UInt<2>[2]
    T_178932[0] := UInt<2>(1)
    T_178932[1] := UInt<2>(2)
    wire T_178933 : UInt<2>[2]
    T_178933[0] := UInt<2>(1)
    T_178933[1] := UInt<2>(2)
    wire T_178934 : UInt<2>[1]
    T_178934[0] := UInt<2>(2)
    wire T_178935 : UInt<3>[3]
    T_178935[0] := UInt<3>(0)
    T_178935[1] := UInt<3>(1)
    T_178935[2] := UInt<3>(2)
    wire T_178936 : UInt<0>[1]
    T_178936[0] := UInt<0>(0)
    wire T_178937 : UInt<2>[2]
    T_178937[0] := UInt<2>(1)
    T_178937[1] := UInt<2>(2)
    wire T_178938 : UInt<2>[2]
    T_178938[0] := UInt<2>(1)
    T_178938[1] := UInt<2>(2)
    wire T_178939 : UInt<2>[1]
    T_178939[0] := UInt<2>(2)
    wire T_178940 : UInt<3>[3]
    T_178940[0] := UInt<3>(0)
    T_178940[1] := UInt<3>(1)
    T_178940[2] := UInt<3>(2)
    wire T_178941 : UInt<0>[1]
    T_178941[0] := UInt<0>(0)
    wire T_178942 : UInt<2>[2]
    T_178942[0] := UInt<2>(1)
    T_178942[1] := UInt<2>(2)
    wire T_178943 : UInt<2>[2]
    T_178943[0] := UInt<2>(1)
    T_178943[1] := UInt<2>(2)
    wire T_178944 : UInt<2>[1]
    T_178944[0] := UInt<2>(2)
    wire T_178945 : UInt<3>[3]
    T_178945[0] := UInt<3>(0)
    T_178945[1] := UInt<3>(1)
    T_178945[2] := UInt<3>(2)
    wire T_178946 : UInt<0>[1]
    T_178946[0] := UInt<0>(0)
    wire T_178947 : UInt<2>[2]
    T_178947[0] := UInt<2>(1)
    T_178947[1] := UInt<2>(2)
    wire T_178948 : UInt<2>[2]
    T_178948[0] := UInt<2>(1)
    T_178948[1] := UInt<2>(2)
    wire T_178949 : UInt<2>[1]
    T_178949[0] := UInt<2>(2)
    wire T_178950 : UInt<3>[3]
    T_178950[0] := UInt<3>(0)
    T_178950[1] := UInt<3>(1)
    T_178950[2] := UInt<3>(2)
    wire T_178951 : UInt<0>[1]
    T_178951[0] := UInt<0>(0)
    wire T_178952 : UInt<2>[2]
    T_178952[0] := UInt<2>(1)
    T_178952[1] := UInt<2>(2)
    wire T_178953 : UInt<2>[2]
    T_178953[0] := UInt<2>(1)
    T_178953[1] := UInt<2>(2)
    wire T_178954 : UInt<2>[1]
    T_178954[0] := UInt<2>(2)
    wire T_178955 : UInt<3>[3]
    T_178955[0] := UInt<3>(0)
    T_178955[1] := UInt<3>(1)
    T_178955[2] := UInt<3>(2)
    wire T_178956 : UInt<0>[1]
    T_178956[0] := UInt<0>(0)
    wire T_178957 : UInt<2>[2]
    T_178957[0] := UInt<2>(1)
    T_178957[1] := UInt<2>(2)
    wire T_178958 : UInt<2>[2]
    T_178958[0] := UInt<2>(1)
    T_178958[1] := UInt<2>(2)
    wire T_178959 : UInt<2>[1]
    T_178959[0] := UInt<2>(2)
    wire T_178960 : UInt<3>[3]
    T_178960[0] := UInt<3>(0)
    T_178960[1] := UInt<3>(1)
    T_178960[2] := UInt<3>(2)
    wire T_178961 : UInt<0>[1]
    T_178961[0] := UInt<0>(0)
    wire T_178962 : UInt<2>[2]
    T_178962[0] := UInt<2>(1)
    T_178962[1] := UInt<2>(2)
    wire T_178963 : UInt<2>[2]
    T_178963[0] := UInt<2>(1)
    T_178963[1] := UInt<2>(2)
    wire T_178964 : UInt<2>[1]
    T_178964[0] := UInt<2>(2)
    wire T_178965 : UInt<3>[3]
    T_178965[0] := UInt<3>(0)
    T_178965[1] := UInt<3>(1)
    T_178965[2] := UInt<3>(2)
    wire T_178966 : UInt<0>[1]
    T_178966[0] := UInt<0>(0)
    wire T_178967 : UInt<2>[2]
    T_178967[0] := UInt<2>(1)
    T_178967[1] := UInt<2>(2)
    wire T_178968 : UInt<2>[2]
    T_178968[0] := UInt<2>(1)
    T_178968[1] := UInt<2>(2)
    wire T_178969 : UInt<2>[1]
    T_178969[0] := UInt<2>(2)
    wire T_178970 : UInt<3>[3]
    T_178970[0] := UInt<3>(0)
    T_178970[1] := UInt<3>(1)
    T_178970[2] := UInt<3>(2)
    wire T_178971 : UInt<0>[1]
    T_178971[0] := UInt<0>(0)
    wire T_178972 : UInt<2>[2]
    T_178972[0] := UInt<2>(1)
    T_178972[1] := UInt<2>(2)
    wire T_178973 : UInt<2>[2]
    T_178973[0] := UInt<2>(1)
    T_178973[1] := UInt<2>(2)
    wire T_178974 : UInt<2>[1]
    T_178974[0] := UInt<2>(2)
    wire T_178975 : UInt<3>[3]
    T_178975[0] := UInt<3>(0)
    T_178975[1] := UInt<3>(1)
    T_178975[2] := UInt<3>(2)
    wire T_178976 : UInt<0>[1]
    T_178976[0] := UInt<0>(0)
    wire T_178977 : UInt<2>[2]
    T_178977[0] := UInt<2>(1)
    T_178977[1] := UInt<2>(2)
    wire T_178978 : UInt<2>[2]
    T_178978[0] := UInt<2>(1)
    T_178978[1] := UInt<2>(2)
    wire T_178979 : UInt<2>[1]
    T_178979[0] := UInt<2>(2)
    wire T_178980 : UInt<3>[3]
    T_178980[0] := UInt<3>(0)
    T_178980[1] := UInt<3>(1)
    T_178980[2] := UInt<3>(2)
    wire T_178981 : UInt<0>[1]
    T_178981[0] := UInt<0>(0)
    wire T_178982 : UInt<2>[2]
    T_178982[0] := UInt<2>(1)
    T_178982[1] := UInt<2>(2)
    wire T_178983 : UInt<2>[2]
    T_178983[0] := UInt<2>(1)
    T_178983[1] := UInt<2>(2)
    wire T_178984 : UInt<2>[1]
    T_178984[0] := UInt<2>(2)
    wire T_178985 : UInt<3>[3]
    T_178985[0] := UInt<3>(0)
    T_178985[1] := UInt<3>(1)
    T_178985[2] := UInt<3>(2)
    wire T_178986 : UInt<0>[1]
    T_178986[0] := UInt<0>(0)
    wire T_178987 : UInt<2>[2]
    T_178987[0] := UInt<2>(1)
    T_178987[1] := UInt<2>(2)
    wire T_178988 : UInt<2>[2]
    T_178988[0] := UInt<2>(1)
    T_178988[1] := UInt<2>(2)
    wire T_178989 : UInt<2>[1]
    T_178989[0] := UInt<2>(2)
    wire T_178990 : UInt<3>[3]
    T_178990[0] := UInt<3>(0)
    T_178990[1] := UInt<3>(1)
    T_178990[2] := UInt<3>(2)
    wire T_178991 : UInt<0>[1]
    T_178991[0] := UInt<0>(0)
    wire T_178992 : UInt<2>[2]
    T_178992[0] := UInt<2>(1)
    T_178992[1] := UInt<2>(2)
    wire T_178993 : UInt<2>[2]
    T_178993[0] := UInt<2>(1)
    T_178993[1] := UInt<2>(2)
    wire T_178994 : UInt<2>[1]
    T_178994[0] := UInt<2>(2)
    wire T_178995 : UInt<3>[3]
    T_178995[0] := UInt<3>(0)
    T_178995[1] := UInt<3>(1)
    T_178995[2] := UInt<3>(2)
    wire T_178996 : UInt<0>[1]
    T_178996[0] := UInt<0>(0)
    wire T_178997 : UInt<2>[2]
    T_178997[0] := UInt<2>(1)
    T_178997[1] := UInt<2>(2)
    wire T_178998 : UInt<2>[2]
    T_178998[0] := UInt<2>(1)
    T_178998[1] := UInt<2>(2)
    wire T_178999 : UInt<2>[1]
    T_178999[0] := UInt<2>(2)
    wire T_179000 : UInt<3>[3]
    T_179000[0] := UInt<3>(0)
    T_179000[1] := UInt<3>(1)
    T_179000[2] := UInt<3>(2)
    wire T_179001 : UInt<0>[1]
    T_179001[0] := UInt<0>(0)
    wire T_179002 : UInt<2>[2]
    T_179002[0] := UInt<2>(1)
    T_179002[1] := UInt<2>(2)
    wire T_179003 : UInt<2>[2]
    T_179003[0] := UInt<2>(1)
    T_179003[1] := UInt<2>(2)
    wire T_179004 : UInt<2>[1]
    T_179004[0] := UInt<2>(2)
    wire T_179005 : UInt<3>[3]
    T_179005[0] := UInt<3>(0)
    T_179005[1] := UInt<3>(1)
    T_179005[2] := UInt<3>(2)
    wire T_179006 : UInt<0>[1]
    T_179006[0] := UInt<0>(0)
    wire T_179007 : UInt<2>[2]
    T_179007[0] := UInt<2>(1)
    T_179007[1] := UInt<2>(2)
    wire T_179008 : UInt<2>[2]
    T_179008[0] := UInt<2>(1)
    T_179008[1] := UInt<2>(2)
    wire T_179009 : UInt<2>[1]
    T_179009[0] := UInt<2>(2)
    wire T_179010 : UInt<3>[3]
    T_179010[0] := UInt<3>(0)
    T_179010[1] := UInt<3>(1)
    T_179010[2] := UInt<3>(2)
    wire T_179011 : UInt<0>[1]
    T_179011[0] := UInt<0>(0)
    wire T_179012 : UInt<2>[2]
    T_179012[0] := UInt<2>(1)
    T_179012[1] := UInt<2>(2)
    wire T_179013 : UInt<2>[2]
    T_179013[0] := UInt<2>(1)
    T_179013[1] := UInt<2>(2)
    wire T_179014 : UInt<2>[1]
    T_179014[0] := UInt<2>(2)
    inst finisher of FinishUnit_113600
    finisher.grant <> network.grant
    network.finish <> finisher.finish
    wire T_179015 : UInt<3>[3]
    T_179015[0] := UInt<3>(0)
    T_179015[1] := UInt<3>(1)
    T_179015[2] := UInt<3>(2)
    wire T_179016 : UInt<0>[1]
    T_179016[0] := UInt<0>(0)
    wire T_179017 : UInt<2>[2]
    T_179017[0] := UInt<2>(1)
    T_179017[1] := UInt<2>(2)
    wire T_179018 : UInt<2>[2]
    T_179018[0] := UInt<2>(1)
    T_179018[1] := UInt<2>(2)
    wire T_179019 : UInt<2>[1]
    T_179019[0] := UInt<2>(2)
    wire T_179020 : UInt<3>[3]
    T_179020[0] := UInt<3>(0)
    T_179020[1] := UInt<3>(1)
    T_179020[2] := UInt<3>(2)
    wire T_179021 : UInt<0>[1]
    T_179021[0] := UInt<0>(0)
    wire T_179022 : UInt<2>[2]
    T_179022[0] := UInt<2>(1)
    T_179022[1] := UInt<2>(2)
    wire T_179023 : UInt<2>[2]
    T_179023[0] := UInt<2>(1)
    T_179023[1] := UInt<2>(2)
    wire T_179024 : UInt<2>[1]
    T_179024[0] := UInt<2>(2)
    wire T_179025 : UInt<3>[3]
    T_179025[0] := UInt<3>(0)
    T_179025[1] := UInt<3>(1)
    T_179025[2] := UInt<3>(2)
    wire T_179026 : UInt<0>[1]
    T_179026[0] := UInt<0>(0)
    wire T_179027 : UInt<2>[2]
    T_179027[0] := UInt<2>(1)
    T_179027[1] := UInt<2>(2)
    wire T_179028 : UInt<2>[2]
    T_179028[0] := UInt<2>(1)
    T_179028[1] := UInt<2>(2)
    wire T_179029 : UInt<2>[1]
    T_179029[0] := UInt<2>(2)
    wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}
    acq_with_header.bits.payload := client.acquire.bits
    acq_with_header.bits.header.src := UInt<1>(0)
    acq_with_header.bits.header.dst := UInt<1>(0)
    acq_with_header.valid := client.acquire.valid
    client.acquire.ready := acq_with_header.ready
    wire T_179030 : UInt<3>[3]
    T_179030[0] := UInt<3>(0)
    T_179030[1] := UInt<3>(1)
    T_179030[2] := UInt<3>(2)
    wire T_179031 : UInt<0>[1]
    T_179031[0] := UInt<0>(0)
    wire T_179032 : UInt<2>[2]
    T_179032[0] := UInt<2>(1)
    T_179032[1] := UInt<2>(2)
    wire T_179033 : UInt<2>[2]
    T_179033[0] := UInt<2>(1)
    T_179033[1] := UInt<2>(2)
    wire T_179034 : UInt<2>[1]
    T_179034[0] := UInt<2>(2)
    wire T_179035 : UInt<3>[3]
    T_179035[0] := UInt<3>(0)
    T_179035[1] := UInt<3>(1)
    T_179035[2] := UInt<3>(2)
    wire T_179036 : UInt<0>[1]
    T_179036[0] := UInt<0>(0)
    wire T_179037 : UInt<2>[2]
    T_179037[0] := UInt<2>(1)
    T_179037[1] := UInt<2>(2)
    wire T_179038 : UInt<2>[2]
    T_179038[0] := UInt<2>(1)
    T_179038[1] := UInt<2>(2)
    wire T_179039 : UInt<2>[1]
    T_179039[0] := UInt<2>(2)
    wire T_179040 : UInt<3>[3]
    T_179040[0] := UInt<3>(0)
    T_179040[1] := UInt<3>(1)
    T_179040[2] := UInt<3>(2)
    wire T_179041 : UInt<0>[1]
    T_179041[0] := UInt<0>(0)
    wire T_179042 : UInt<2>[2]
    T_179042[0] := UInt<2>(1)
    T_179042[1] := UInt<2>(2)
    wire T_179043 : UInt<2>[2]
    T_179043[0] := UInt<2>(1)
    T_179043[1] := UInt<2>(2)
    wire T_179044 : UInt<2>[1]
    T_179044[0] := UInt<2>(2)
    wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    rel_with_header.bits.payload := client.release.bits
    rel_with_header.bits.header.src := UInt<1>(0)
    rel_with_header.bits.header.dst := UInt<1>(0)
    rel_with_header.valid := client.release.valid
    client.release.ready := rel_with_header.ready
    wire T_179045 : UInt<3>[3]
    T_179045[0] := UInt<3>(0)
    T_179045[1] := UInt<3>(1)
    T_179045[2] := UInt<3>(2)
    wire T_179046 : UInt<0>[1]
    T_179046[0] := UInt<0>(0)
    wire T_179047 : UInt<2>[2]
    T_179047[0] := UInt<2>(1)
    T_179047[1] := UInt<2>(2)
    wire T_179048 : UInt<2>[2]
    T_179048[0] := UInt<2>(1)
    T_179048[1] := UInt<2>(2)
    wire T_179049 : UInt<2>[1]
    T_179049[0] := UInt<2>(2)
    wire T_179050 : UInt<3>[3]
    T_179050[0] := UInt<3>(0)
    T_179050[1] := UInt<3>(1)
    T_179050[2] := UInt<3>(2)
    wire T_179051 : UInt<0>[1]
    T_179051[0] := UInt<0>(0)
    wire T_179052 : UInt<2>[2]
    T_179052[0] := UInt<2>(1)
    T_179052[1] := UInt<2>(2)
    wire T_179053 : UInt<2>[2]
    T_179053[0] := UInt<2>(1)
    T_179053[1] := UInt<2>(2)
    wire T_179054 : UInt<2>[1]
    T_179054[0] := UInt<2>(2)
    wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}
    prb_without_header.valid := network.probe.valid
    prb_without_header.bits := network.probe.bits.payload
    network.probe.ready := prb_without_header.ready
    network.acquire.bits := acq_with_header.bits
    node T_179055 = and(acq_with_header.valid, finisher.ready)
    network.acquire.valid := T_179055
    node T_179056 = and(network.acquire.ready, finisher.ready)
    acq_with_header.ready := T_179056
    network.release <> rel_with_header
    client.probe <> prb_without_header
    client.grant <> finisher.refill
  module TileLinkEnqueuer_115938 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_179057 : UInt<3>[3]
    T_179057[0] := UInt<3>(0)
    T_179057[1] := UInt<3>(1)
    T_179057[2] := UInt<3>(2)
    wire T_179058 : UInt<0>[1]
    T_179058[0] := UInt<0>(0)
    wire T_179059 : UInt<2>[2]
    T_179059[0] := UInt<2>(1)
    T_179059[1] := UInt<2>(2)
    wire T_179060 : UInt<2>[2]
    T_179060[0] := UInt<2>(1)
    T_179060[1] := UInt<2>(2)
    wire T_179061 : UInt<2>[1]
    T_179061[0] := UInt<2>(2)
    wire T_179062 : UInt<3>[3]
    T_179062[0] := UInt<3>(0)
    T_179062[1] := UInt<3>(1)
    T_179062[2] := UInt<3>(2)
    wire T_179063 : UInt<0>[1]
    T_179063[0] := UInt<0>(0)
    wire T_179064 : UInt<2>[2]
    T_179064[0] := UInt<2>(1)
    T_179064[1] := UInt<2>(2)
    wire T_179065 : UInt<2>[2]
    T_179065[0] := UInt<2>(1)
    T_179065[1] := UInt<2>(2)
    wire T_179066 : UInt<2>[1]
    T_179066[0] := UInt<2>(2)
    wire T_179067 : UInt<3>[3]
    T_179067[0] := UInt<3>(0)
    T_179067[1] := UInt<3>(1)
    T_179067[2] := UInt<3>(2)
    wire T_179068 : UInt<0>[1]
    T_179068[0] := UInt<0>(0)
    wire T_179069 : UInt<2>[2]
    T_179069[0] := UInt<2>(1)
    T_179069[1] := UInt<2>(2)
    wire T_179070 : UInt<2>[2]
    T_179070[0] := UInt<2>(1)
    T_179070[1] := UInt<2>(2)
    wire T_179071 : UInt<2>[1]
    T_179071[0] := UInt<2>(2)
    wire T_179072 : UInt<3>[3]
    T_179072[0] := UInt<3>(0)
    T_179072[1] := UInt<3>(1)
    T_179072[2] := UInt<3>(2)
    wire T_179073 : UInt<0>[1]
    T_179073[0] := UInt<0>(0)
    wire T_179074 : UInt<2>[2]
    T_179074[0] := UInt<2>(1)
    T_179074[1] := UInt<2>(2)
    wire T_179075 : UInt<2>[2]
    T_179075[0] := UInt<2>(1)
    T_179075[1] := UInt<2>(2)
    wire T_179076 : UInt<2>[1]
    T_179076[0] := UInt<2>(2)
    wire T_179077 : UInt<3>[3]
    T_179077[0] := UInt<3>(0)
    T_179077[1] := UInt<3>(1)
    T_179077[2] := UInt<3>(2)
    wire T_179078 : UInt<0>[1]
    T_179078[0] := UInt<0>(0)
    wire T_179079 : UInt<2>[2]
    T_179079[0] := UInt<2>(1)
    T_179079[1] := UInt<2>(2)
    wire T_179080 : UInt<2>[2]
    T_179080[0] := UInt<2>(1)
    T_179080[1] := UInt<2>(2)
    wire T_179081 : UInt<2>[1]
    T_179081[0] := UInt<2>(2)
    wire T_179082 : UInt<3>[3]
    T_179082[0] := UInt<3>(0)
    T_179082[1] := UInt<3>(1)
    T_179082[2] := UInt<3>(2)
    wire T_179083 : UInt<0>[1]
    T_179083[0] := UInt<0>(0)
    wire T_179084 : UInt<2>[2]
    T_179084[0] := UInt<2>(1)
    T_179084[1] := UInt<2>(2)
    wire T_179085 : UInt<2>[2]
    T_179085[0] := UInt<2>(1)
    T_179085[1] := UInt<2>(2)
    wire T_179086 : UInt<2>[1]
    T_179086[0] := UInt<2>(2)
    wire T_179087 : UInt<3>[3]
    T_179087[0] := UInt<3>(0)
    T_179087[1] := UInt<3>(1)
    T_179087[2] := UInt<3>(2)
    wire T_179088 : UInt<0>[1]
    T_179088[0] := UInt<0>(0)
    wire T_179089 : UInt<2>[2]
    T_179089[0] := UInt<2>(1)
    T_179089[1] := UInt<2>(2)
    wire T_179090 : UInt<2>[2]
    T_179090[0] := UInt<2>(1)
    T_179090[1] := UInt<2>(2)
    wire T_179091 : UInt<2>[1]
    T_179091[0] := UInt<2>(2)
    wire T_179092 : UInt<3>[3]
    T_179092[0] := UInt<3>(0)
    T_179092[1] := UInt<3>(1)
    T_179092[2] := UInt<3>(2)
    wire T_179093 : UInt<0>[1]
    T_179093[0] := UInt<0>(0)
    wire T_179094 : UInt<2>[2]
    T_179094[0] := UInt<2>(1)
    T_179094[1] := UInt<2>(2)
    wire T_179095 : UInt<2>[2]
    T_179095[0] := UInt<2>(1)
    T_179095[1] := UInt<2>(2)
    wire T_179096 : UInt<2>[1]
    T_179096[0] := UInt<2>(2)
    wire T_179097 : UInt<3>[3]
    T_179097[0] := UInt<3>(0)
    T_179097[1] := UInt<3>(1)
    T_179097[2] := UInt<3>(2)
    wire T_179098 : UInt<0>[1]
    T_179098[0] := UInt<0>(0)
    wire T_179099 : UInt<2>[2]
    T_179099[0] := UInt<2>(1)
    T_179099[1] := UInt<2>(2)
    wire T_179100 : UInt<2>[2]
    T_179100[0] := UInt<2>(1)
    T_179100[1] := UInt<2>(2)
    wire T_179101 : UInt<2>[1]
    T_179101[0] := UInt<2>(2)
    wire T_179102 : UInt<3>[3]
    T_179102[0] := UInt<3>(0)
    T_179102[1] := UInt<3>(1)
    T_179102[2] := UInt<3>(2)
    wire T_179103 : UInt<0>[1]
    T_179103[0] := UInt<0>(0)
    wire T_179104 : UInt<2>[2]
    T_179104[0] := UInt<2>(1)
    T_179104[1] := UInt<2>(2)
    wire T_179105 : UInt<2>[2]
    T_179105[0] := UInt<2>(1)
    T_179105[1] := UInt<2>(2)
    wire T_179106 : UInt<2>[1]
    T_179106[0] := UInt<2>(2)
    wire T_179107 : UInt<3>[3]
    T_179107[0] := UInt<3>(0)
    T_179107[1] := UInt<3>(1)
    T_179107[2] := UInt<3>(2)
    wire T_179108 : UInt<0>[1]
    T_179108[0] := UInt<0>(0)
    wire T_179109 : UInt<2>[2]
    T_179109[0] := UInt<2>(1)
    T_179109[1] := UInt<2>(2)
    wire T_179110 : UInt<2>[2]
    T_179110[0] := UInt<2>(1)
    T_179110[1] := UInt<2>(2)
    wire T_179111 : UInt<2>[1]
    T_179111[0] := UInt<2>(2)
    wire T_179112 : UInt<3>[3]
    T_179112[0] := UInt<3>(0)
    T_179112[1] := UInt<3>(1)
    T_179112[2] := UInt<3>(2)
    wire T_179113 : UInt<0>[1]
    T_179113[0] := UInt<0>(0)
    wire T_179114 : UInt<2>[2]
    T_179114[0] := UInt<2>(1)
    T_179114[1] := UInt<2>(2)
    wire T_179115 : UInt<2>[2]
    T_179115[0] := UInt<2>(1)
    T_179115[1] := UInt<2>(2)
    wire T_179116 : UInt<2>[1]
    T_179116[0] := UInt<2>(2)
    wire T_179117 : UInt<3>[3]
    T_179117[0] := UInt<3>(0)
    T_179117[1] := UInt<3>(1)
    T_179117[2] := UInt<3>(2)
    wire T_179118 : UInt<0>[1]
    T_179118[0] := UInt<0>(0)
    wire T_179119 : UInt<2>[2]
    T_179119[0] := UInt<2>(1)
    T_179119[1] := UInt<2>(2)
    wire T_179120 : UInt<2>[2]
    T_179120[0] := UInt<2>(1)
    T_179120[1] := UInt<2>(2)
    wire T_179121 : UInt<2>[1]
    T_179121[0] := UInt<2>(2)
    wire T_179122 : UInt<3>[3]
    T_179122[0] := UInt<3>(0)
    T_179122[1] := UInt<3>(1)
    T_179122[2] := UInt<3>(2)
    wire T_179123 : UInt<0>[1]
    T_179123[0] := UInt<0>(0)
    wire T_179124 : UInt<2>[2]
    T_179124[0] := UInt<2>(1)
    T_179124[1] := UInt<2>(2)
    wire T_179125 : UInt<2>[2]
    T_179125[0] := UInt<2>(1)
    T_179125[1] := UInt<2>(2)
    wire T_179126 : UInt<2>[1]
    T_179126[0] := UInt<2>(2)
    wire T_179127 : UInt<3>[3]
    T_179127[0] := UInt<3>(0)
    T_179127[1] := UInt<3>(1)
    T_179127[2] := UInt<3>(2)
    wire T_179128 : UInt<0>[1]
    T_179128[0] := UInt<0>(0)
    wire T_179129 : UInt<2>[2]
    T_179129[0] := UInt<2>(1)
    T_179129[1] := UInt<2>(2)
    wire T_179130 : UInt<2>[2]
    T_179130[0] := UInt<2>(1)
    T_179130[1] := UInt<2>(2)
    wire T_179131 : UInt<2>[1]
    T_179131[0] := UInt<2>(2)
    wire T_179132 : UInt<3>[3]
    T_179132[0] := UInt<3>(0)
    T_179132[1] := UInt<3>(1)
    T_179132[2] := UInt<3>(2)
    wire T_179133 : UInt<0>[1]
    T_179133[0] := UInt<0>(0)
    wire T_179134 : UInt<2>[2]
    T_179134[0] := UInt<2>(1)
    T_179134[1] := UInt<2>(2)
    wire T_179135 : UInt<2>[2]
    T_179135[0] := UInt<2>(1)
    T_179135[1] := UInt<2>(2)
    wire T_179136 : UInt<2>[1]
    T_179136[0] := UInt<2>(2)
    wire T_179137 : UInt<3>[3]
    T_179137[0] := UInt<3>(0)
    T_179137[1] := UInt<3>(1)
    T_179137[2] := UInt<3>(2)
    wire T_179138 : UInt<0>[1]
    T_179138[0] := UInt<0>(0)
    wire T_179139 : UInt<2>[2]
    T_179139[0] := UInt<2>(1)
    T_179139[1] := UInt<2>(2)
    wire T_179140 : UInt<2>[2]
    T_179140[0] := UInt<2>(1)
    T_179140[1] := UInt<2>(2)
    wire T_179141 : UInt<2>[1]
    T_179141[0] := UInt<2>(2)
    wire T_179142 : UInt<3>[3]
    T_179142[0] := UInt<3>(0)
    T_179142[1] := UInt<3>(1)
    T_179142[2] := UInt<3>(2)
    wire T_179143 : UInt<0>[1]
    T_179143[0] := UInt<0>(0)
    wire T_179144 : UInt<2>[2]
    T_179144[0] := UInt<2>(1)
    T_179144[1] := UInt<2>(2)
    wire T_179145 : UInt<2>[2]
    T_179145[0] := UInt<2>(1)
    T_179145[1] := UInt<2>(2)
    wire T_179146 : UInt<2>[1]
    T_179146[0] := UInt<2>(2)
    wire T_179147 : UInt<3>[3]
    T_179147[0] := UInt<3>(0)
    T_179147[1] := UInt<3>(1)
    T_179147[2] := UInt<3>(2)
    wire T_179148 : UInt<0>[1]
    T_179148[0] := UInt<0>(0)
    wire T_179149 : UInt<2>[2]
    T_179149[0] := UInt<2>(1)
    T_179149[1] := UInt<2>(2)
    wire T_179150 : UInt<2>[2]
    T_179150[0] := UInt<2>(1)
    T_179150[1] := UInt<2>(2)
    wire T_179151 : UInt<2>[1]
    T_179151[0] := UInt<2>(2)
    wire T_179152 : UInt<3>[3]
    T_179152[0] := UInt<3>(0)
    T_179152[1] := UInt<3>(1)
    T_179152[2] := UInt<3>(2)
    wire T_179153 : UInt<0>[1]
    T_179153[0] := UInt<0>(0)
    wire T_179154 : UInt<2>[2]
    T_179154[0] := UInt<2>(1)
    T_179154[1] := UInt<2>(2)
    wire T_179155 : UInt<2>[2]
    T_179155[0] := UInt<2>(1)
    T_179155[1] := UInt<2>(2)
    wire T_179156 : UInt<2>[1]
    T_179156[0] := UInt<2>(2)
    wire T_179157 : UInt<3>[3]
    T_179157[0] := UInt<3>(0)
    T_179157[1] := UInt<3>(1)
    T_179157[2] := UInt<3>(2)
    wire T_179158 : UInt<0>[1]
    T_179158[0] := UInt<0>(0)
    wire T_179159 : UInt<2>[2]
    T_179159[0] := UInt<2>(1)
    T_179159[1] := UInt<2>(2)
    wire T_179160 : UInt<2>[2]
    T_179160[0] := UInt<2>(1)
    T_179160[1] := UInt<2>(2)
    wire T_179161 : UInt<2>[1]
    T_179161[0] := UInt<2>(2)
    wire T_179162 : UInt<3>[3]
    T_179162[0] := UInt<3>(0)
    T_179162[1] := UInt<3>(1)
    T_179162[2] := UInt<3>(2)
    wire T_179163 : UInt<0>[1]
    T_179163[0] := UInt<0>(0)
    wire T_179164 : UInt<2>[2]
    T_179164[0] := UInt<2>(1)
    T_179164[1] := UInt<2>(2)
    wire T_179165 : UInt<2>[2]
    T_179165[0] := UInt<2>(1)
    T_179165[1] := UInt<2>(2)
    wire T_179166 : UInt<2>[1]
    T_179166[0] := UInt<2>(2)
    wire T_179167 : UInt<3>[3]
    T_179167[0] := UInt<3>(0)
    T_179167[1] := UInt<3>(1)
    T_179167[2] := UInt<3>(2)
    wire T_179168 : UInt<0>[1]
    T_179168[0] := UInt<0>(0)
    wire T_179169 : UInt<2>[2]
    T_179169[0] := UInt<2>(1)
    T_179169[1] := UInt<2>(2)
    wire T_179170 : UInt<2>[2]
    T_179170[0] := UInt<2>(1)
    T_179170[1] := UInt<2>(2)
    wire T_179171 : UInt<2>[1]
    T_179171[0] := UInt<2>(2)
    wire T_179172 : UInt<3>[3]
    T_179172[0] := UInt<3>(0)
    T_179172[1] := UInt<3>(1)
    T_179172[2] := UInt<3>(2)
    wire T_179173 : UInt<0>[1]
    T_179173[0] := UInt<0>(0)
    wire T_179174 : UInt<2>[2]
    T_179174[0] := UInt<2>(1)
    T_179174[1] := UInt<2>(2)
    wire T_179175 : UInt<2>[2]
    T_179175[0] := UInt<2>(1)
    T_179175[1] := UInt<2>(2)
    wire T_179176 : UInt<2>[1]
    T_179176[0] := UInt<2>(2)
    wire T_179177 : UInt<3>[3]
    T_179177[0] := UInt<3>(0)
    T_179177[1] := UInt<3>(1)
    T_179177[2] := UInt<3>(2)
    wire T_179178 : UInt<0>[1]
    T_179178[0] := UInt<0>(0)
    wire T_179179 : UInt<2>[2]
    T_179179[0] := UInt<2>(1)
    T_179179[1] := UInt<2>(2)
    wire T_179180 : UInt<2>[2]
    T_179180[0] := UInt<2>(1)
    T_179180[1] := UInt<2>(2)
    wire T_179181 : UInt<2>[1]
    T_179181[0] := UInt<2>(2)
    wire T_179182 : UInt<3>[3]
    T_179182[0] := UInt<3>(0)
    T_179182[1] := UInt<3>(1)
    T_179182[2] := UInt<3>(2)
    wire T_179183 : UInt<0>[1]
    T_179183[0] := UInt<0>(0)
    wire T_179184 : UInt<2>[2]
    T_179184[0] := UInt<2>(1)
    T_179184[1] := UInt<2>(2)
    wire T_179185 : UInt<2>[2]
    T_179185[0] := UInt<2>(1)
    T_179185[1] := UInt<2>(2)
    wire T_179186 : UInt<2>[1]
    T_179186[0] := UInt<2>(2)
    wire T_179187 : UInt<3>[3]
    T_179187[0] := UInt<3>(0)
    T_179187[1] := UInt<3>(1)
    T_179187[2] := UInt<3>(2)
    wire T_179188 : UInt<0>[1]
    T_179188[0] := UInt<0>(0)
    wire T_179189 : UInt<2>[2]
    T_179189[0] := UInt<2>(1)
    T_179189[1] := UInt<2>(2)
    wire T_179190 : UInt<2>[2]
    T_179190[0] := UInt<2>(1)
    T_179190[1] := UInt<2>(2)
    wire T_179191 : UInt<2>[1]
    T_179191[0] := UInt<2>(2)
    wire T_179192 : UInt<3>[3]
    T_179192[0] := UInt<3>(0)
    T_179192[1] := UInt<3>(1)
    T_179192[2] := UInt<3>(2)
    wire T_179193 : UInt<0>[1]
    T_179193[0] := UInt<0>(0)
    wire T_179194 : UInt<2>[2]
    T_179194[0] := UInt<2>(1)
    T_179194[1] := UInt<2>(2)
    wire T_179195 : UInt<2>[2]
    T_179195[0] := UInt<2>(1)
    T_179195[1] := UInt<2>(2)
    wire T_179196 : UInt<2>[1]
    T_179196[0] := UInt<2>(2)
    wire T_179197 : UInt<3>[3]
    T_179197[0] := UInt<3>(0)
    T_179197[1] := UInt<3>(1)
    T_179197[2] := UInt<3>(2)
    wire T_179198 : UInt<0>[1]
    T_179198[0] := UInt<0>(0)
    wire T_179199 : UInt<2>[2]
    T_179199[0] := UInt<2>(1)
    T_179199[1] := UInt<2>(2)
    wire T_179200 : UInt<2>[2]
    T_179200[0] := UInt<2>(1)
    T_179200[1] := UInt<2>(2)
    wire T_179201 : UInt<2>[1]
    T_179201[0] := UInt<2>(2)
    wire T_179202 : UInt<3>[3]
    T_179202[0] := UInt<3>(0)
    T_179202[1] := UInt<3>(1)
    T_179202[2] := UInt<3>(2)
    wire T_179203 : UInt<0>[1]
    T_179203[0] := UInt<0>(0)
    wire T_179204 : UInt<2>[2]
    T_179204[0] := UInt<2>(1)
    T_179204[1] := UInt<2>(2)
    wire T_179205 : UInt<2>[2]
    T_179205[0] := UInt<2>(1)
    T_179205[1] := UInt<2>(2)
    wire T_179206 : UInt<2>[1]
    T_179206[0] := UInt<2>(2)
    wire T_179207 : UInt<3>[3]
    T_179207[0] := UInt<3>(0)
    T_179207[1] := UInt<3>(1)
    T_179207[2] := UInt<3>(2)
    wire T_179208 : UInt<0>[1]
    T_179208[0] := UInt<0>(0)
    wire T_179209 : UInt<2>[2]
    T_179209[0] := UInt<2>(1)
    T_179209[1] := UInt<2>(2)
    wire T_179210 : UInt<2>[2]
    T_179210[0] := UInt<2>(1)
    T_179210[1] := UInt<2>(2)
    wire T_179211 : UInt<2>[1]
    T_179211[0] := UInt<2>(2)
    wire T_179212 : UInt<3>[3]
    T_179212[0] := UInt<3>(0)
    T_179212[1] := UInt<3>(1)
    T_179212[2] := UInt<3>(2)
    wire T_179213 : UInt<0>[1]
    T_179213[0] := UInt<0>(0)
    wire T_179214 : UInt<2>[2]
    T_179214[0] := UInt<2>(1)
    T_179214[1] := UInt<2>(2)
    wire T_179215 : UInt<2>[2]
    T_179215[0] := UInt<2>(1)
    T_179215[1] := UInt<2>(2)
    wire T_179216 : UInt<2>[1]
    T_179216[0] := UInt<2>(2)
    manager.acquire <> client.acquire
    client.probe <> manager.probe
    manager.release <> client.release
    client.grant <> manager.grant
    manager.finish <> client.finish
  module ManagerTileLinkNetworkPort_118243 : 
    input manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}
    input network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_179217 : UInt<3>[3]
    T_179217[0] := UInt<3>(0)
    T_179217[1] := UInt<3>(1)
    T_179217[2] := UInt<3>(2)
    wire T_179218 : UInt<0>[1]
    T_179218[0] := UInt<0>(0)
    wire T_179219 : UInt<2>[2]
    T_179219[0] := UInt<2>(1)
    T_179219[1] := UInt<2>(2)
    wire T_179220 : UInt<2>[2]
    T_179220[0] := UInt<2>(1)
    T_179220[1] := UInt<2>(2)
    wire T_179221 : UInt<2>[1]
    T_179221[0] := UInt<2>(2)
    wire T_179222 : UInt<3>[3]
    T_179222[0] := UInt<3>(0)
    T_179222[1] := UInt<3>(1)
    T_179222[2] := UInt<3>(2)
    wire T_179223 : UInt<0>[1]
    T_179223[0] := UInt<0>(0)
    wire T_179224 : UInt<2>[2]
    T_179224[0] := UInt<2>(1)
    T_179224[1] := UInt<2>(2)
    wire T_179225 : UInt<2>[2]
    T_179225[0] := UInt<2>(1)
    T_179225[1] := UInt<2>(2)
    wire T_179226 : UInt<2>[1]
    T_179226[0] := UInt<2>(2)
    wire T_179227 : UInt<3>[3]
    T_179227[0] := UInt<3>(0)
    T_179227[1] := UInt<3>(1)
    T_179227[2] := UInt<3>(2)
    wire T_179228 : UInt<0>[1]
    T_179228[0] := UInt<0>(0)
    wire T_179229 : UInt<2>[2]
    T_179229[0] := UInt<2>(1)
    T_179229[1] := UInt<2>(2)
    wire T_179230 : UInt<2>[2]
    T_179230[0] := UInt<2>(1)
    T_179230[1] := UInt<2>(2)
    wire T_179231 : UInt<2>[1]
    T_179231[0] := UInt<2>(2)
    wire T_179232 : UInt<3>[3]
    T_179232[0] := UInt<3>(0)
    T_179232[1] := UInt<3>(1)
    T_179232[2] := UInt<3>(2)
    wire T_179233 : UInt<0>[1]
    T_179233[0] := UInt<0>(0)
    wire T_179234 : UInt<2>[2]
    T_179234[0] := UInt<2>(1)
    T_179234[1] := UInt<2>(2)
    wire T_179235 : UInt<2>[2]
    T_179235[0] := UInt<2>(1)
    T_179235[1] := UInt<2>(2)
    wire T_179236 : UInt<2>[1]
    T_179236[0] := UInt<2>(2)
    wire T_179237 : UInt<3>[3]
    T_179237[0] := UInt<3>(0)
    T_179237[1] := UInt<3>(1)
    T_179237[2] := UInt<3>(2)
    wire T_179238 : UInt<0>[1]
    T_179238[0] := UInt<0>(0)
    wire T_179239 : UInt<2>[2]
    T_179239[0] := UInt<2>(1)
    T_179239[1] := UInt<2>(2)
    wire T_179240 : UInt<2>[2]
    T_179240[0] := UInt<2>(1)
    T_179240[1] := UInt<2>(2)
    wire T_179241 : UInt<2>[1]
    T_179241[0] := UInt<2>(2)
    wire T_179242 : UInt<3>[3]
    T_179242[0] := UInt<3>(0)
    T_179242[1] := UInt<3>(1)
    T_179242[2] := UInt<3>(2)
    wire T_179243 : UInt<0>[1]
    T_179243[0] := UInt<0>(0)
    wire T_179244 : UInt<2>[2]
    T_179244[0] := UInt<2>(1)
    T_179244[1] := UInt<2>(2)
    wire T_179245 : UInt<2>[2]
    T_179245[0] := UInt<2>(1)
    T_179245[1] := UInt<2>(2)
    wire T_179246 : UInt<2>[1]
    T_179246[0] := UInt<2>(2)
    wire T_179247 : UInt<3>[3]
    T_179247[0] := UInt<3>(0)
    T_179247[1] := UInt<3>(1)
    T_179247[2] := UInt<3>(2)
    wire T_179248 : UInt<0>[1]
    T_179248[0] := UInt<0>(0)
    wire T_179249 : UInt<2>[2]
    T_179249[0] := UInt<2>(1)
    T_179249[1] := UInt<2>(2)
    wire T_179250 : UInt<2>[2]
    T_179250[0] := UInt<2>(1)
    T_179250[1] := UInt<2>(2)
    wire T_179251 : UInt<2>[1]
    T_179251[0] := UInt<2>(2)
    wire T_179252 : UInt<3>[3]
    T_179252[0] := UInt<3>(0)
    T_179252[1] := UInt<3>(1)
    T_179252[2] := UInt<3>(2)
    wire T_179253 : UInt<0>[1]
    T_179253[0] := UInt<0>(0)
    wire T_179254 : UInt<2>[2]
    T_179254[0] := UInt<2>(1)
    T_179254[1] := UInt<2>(2)
    wire T_179255 : UInt<2>[2]
    T_179255[0] := UInt<2>(1)
    T_179255[1] := UInt<2>(2)
    wire T_179256 : UInt<2>[1]
    T_179256[0] := UInt<2>(2)
    wire T_179257 : UInt<3>[3]
    T_179257[0] := UInt<3>(0)
    T_179257[1] := UInt<3>(1)
    T_179257[2] := UInt<3>(2)
    wire T_179258 : UInt<0>[1]
    T_179258[0] := UInt<0>(0)
    wire T_179259 : UInt<2>[2]
    T_179259[0] := UInt<2>(1)
    T_179259[1] := UInt<2>(2)
    wire T_179260 : UInt<2>[2]
    T_179260[0] := UInt<2>(1)
    T_179260[1] := UInt<2>(2)
    wire T_179261 : UInt<2>[1]
    T_179261[0] := UInt<2>(2)
    wire T_179262 : UInt<3>[3]
    T_179262[0] := UInt<3>(0)
    T_179262[1] := UInt<3>(1)
    T_179262[2] := UInt<3>(2)
    wire T_179263 : UInt<0>[1]
    T_179263[0] := UInt<0>(0)
    wire T_179264 : UInt<2>[2]
    T_179264[0] := UInt<2>(1)
    T_179264[1] := UInt<2>(2)
    wire T_179265 : UInt<2>[2]
    T_179265[0] := UInt<2>(1)
    T_179265[1] := UInt<2>(2)
    wire T_179266 : UInt<2>[1]
    T_179266[0] := UInt<2>(2)
    wire T_179267 : UInt<3>[3]
    T_179267[0] := UInt<3>(0)
    T_179267[1] := UInt<3>(1)
    T_179267[2] := UInt<3>(2)
    wire T_179268 : UInt<0>[1]
    T_179268[0] := UInt<0>(0)
    wire T_179269 : UInt<2>[2]
    T_179269[0] := UInt<2>(1)
    T_179269[1] := UInt<2>(2)
    wire T_179270 : UInt<2>[2]
    T_179270[0] := UInt<2>(1)
    T_179270[1] := UInt<2>(2)
    wire T_179271 : UInt<2>[1]
    T_179271[0] := UInt<2>(2)
    wire T_179272 : UInt<3>[3]
    T_179272[0] := UInt<3>(0)
    T_179272[1] := UInt<3>(1)
    T_179272[2] := UInt<3>(2)
    wire T_179273 : UInt<0>[1]
    T_179273[0] := UInt<0>(0)
    wire T_179274 : UInt<2>[2]
    T_179274[0] := UInt<2>(1)
    T_179274[1] := UInt<2>(2)
    wire T_179275 : UInt<2>[2]
    T_179275[0] := UInt<2>(1)
    T_179275[1] := UInt<2>(2)
    wire T_179276 : UInt<2>[1]
    T_179276[0] := UInt<2>(2)
    wire T_179277 : UInt<3>[3]
    T_179277[0] := UInt<3>(0)
    T_179277[1] := UInt<3>(1)
    T_179277[2] := UInt<3>(2)
    wire T_179278 : UInt<0>[1]
    T_179278[0] := UInt<0>(0)
    wire T_179279 : UInt<2>[2]
    T_179279[0] := UInt<2>(1)
    T_179279[1] := UInt<2>(2)
    wire T_179280 : UInt<2>[2]
    T_179280[0] := UInt<2>(1)
    T_179280[1] := UInt<2>(2)
    wire T_179281 : UInt<2>[1]
    T_179281[0] := UInt<2>(2)
    wire T_179282 : UInt<3>[3]
    T_179282[0] := UInt<3>(0)
    T_179282[1] := UInt<3>(1)
    T_179282[2] := UInt<3>(2)
    wire T_179283 : UInt<0>[1]
    T_179283[0] := UInt<0>(0)
    wire T_179284 : UInt<2>[2]
    T_179284[0] := UInt<2>(1)
    T_179284[1] := UInt<2>(2)
    wire T_179285 : UInt<2>[2]
    T_179285[0] := UInt<2>(1)
    T_179285[1] := UInt<2>(2)
    wire T_179286 : UInt<2>[1]
    T_179286[0] := UInt<2>(2)
    wire T_179287 : UInt<3>[3]
    T_179287[0] := UInt<3>(0)
    T_179287[1] := UInt<3>(1)
    T_179287[2] := UInt<3>(2)
    wire T_179288 : UInt<0>[1]
    T_179288[0] := UInt<0>(0)
    wire T_179289 : UInt<2>[2]
    T_179289[0] := UInt<2>(1)
    T_179289[1] := UInt<2>(2)
    wire T_179290 : UInt<2>[2]
    T_179290[0] := UInt<2>(1)
    T_179290[1] := UInt<2>(2)
    wire T_179291 : UInt<2>[1]
    T_179291[0] := UInt<2>(2)
    wire T_179292 : UInt<3>[3]
    T_179292[0] := UInt<3>(0)
    T_179292[1] := UInt<3>(1)
    T_179292[2] := UInt<3>(2)
    wire T_179293 : UInt<0>[1]
    T_179293[0] := UInt<0>(0)
    wire T_179294 : UInt<2>[2]
    T_179294[0] := UInt<2>(1)
    T_179294[1] := UInt<2>(2)
    wire T_179295 : UInt<2>[2]
    T_179295[0] := UInt<2>(1)
    T_179295[1] := UInt<2>(2)
    wire T_179296 : UInt<2>[1]
    T_179296[0] := UInt<2>(2)
    wire T_179297 : UInt<3>[3]
    T_179297[0] := UInt<3>(0)
    T_179297[1] := UInt<3>(1)
    T_179297[2] := UInt<3>(2)
    wire T_179298 : UInt<0>[1]
    T_179298[0] := UInt<0>(0)
    wire T_179299 : UInt<2>[2]
    T_179299[0] := UInt<2>(1)
    T_179299[1] := UInt<2>(2)
    wire T_179300 : UInt<2>[2]
    T_179300[0] := UInt<2>(1)
    T_179300[1] := UInt<2>(2)
    wire T_179301 : UInt<2>[1]
    T_179301[0] := UInt<2>(2)
    wire T_179302 : UInt<3>[3]
    T_179302[0] := UInt<3>(0)
    T_179302[1] := UInt<3>(1)
    T_179302[2] := UInt<3>(2)
    wire T_179303 : UInt<0>[1]
    T_179303[0] := UInt<0>(0)
    wire T_179304 : UInt<2>[2]
    T_179304[0] := UInt<2>(1)
    T_179304[1] := UInt<2>(2)
    wire T_179305 : UInt<2>[2]
    T_179305[0] := UInt<2>(1)
    T_179305[1] := UInt<2>(2)
    wire T_179306 : UInt<2>[1]
    T_179306[0] := UInt<2>(2)
    wire T_179307 : UInt<3>[3]
    T_179307[0] := UInt<3>(0)
    T_179307[1] := UInt<3>(1)
    T_179307[2] := UInt<3>(2)
    wire T_179308 : UInt<0>[1]
    T_179308[0] := UInt<0>(0)
    wire T_179309 : UInt<2>[2]
    T_179309[0] := UInt<2>(1)
    T_179309[1] := UInt<2>(2)
    wire T_179310 : UInt<2>[2]
    T_179310[0] := UInt<2>(1)
    T_179310[1] := UInt<2>(2)
    wire T_179311 : UInt<2>[1]
    T_179311[0] := UInt<2>(2)
    wire T_179312 : UInt<3>[3]
    T_179312[0] := UInt<3>(0)
    T_179312[1] := UInt<3>(1)
    T_179312[2] := UInt<3>(2)
    wire T_179313 : UInt<0>[1]
    T_179313[0] := UInt<0>(0)
    wire T_179314 : UInt<2>[2]
    T_179314[0] := UInt<2>(1)
    T_179314[1] := UInt<2>(2)
    wire T_179315 : UInt<2>[2]
    T_179315[0] := UInt<2>(1)
    T_179315[1] := UInt<2>(2)
    wire T_179316 : UInt<2>[1]
    T_179316[0] := UInt<2>(2)
    wire T_179317 : UInt<3>[3]
    T_179317[0] := UInt<3>(0)
    T_179317[1] := UInt<3>(1)
    T_179317[2] := UInt<3>(2)
    wire T_179318 : UInt<0>[1]
    T_179318[0] := UInt<0>(0)
    wire T_179319 : UInt<2>[2]
    T_179319[0] := UInt<2>(1)
    T_179319[1] := UInt<2>(2)
    wire T_179320 : UInt<2>[2]
    T_179320[0] := UInt<2>(1)
    T_179320[1] := UInt<2>(2)
    wire T_179321 : UInt<2>[1]
    T_179321[0] := UInt<2>(2)
    wire T_179322 : UInt<3>[3]
    T_179322[0] := UInt<3>(0)
    T_179322[1] := UInt<3>(1)
    T_179322[2] := UInt<3>(2)
    wire T_179323 : UInt<0>[1]
    T_179323[0] := UInt<0>(0)
    wire T_179324 : UInt<2>[2]
    T_179324[0] := UInt<2>(1)
    T_179324[1] := UInt<2>(2)
    wire T_179325 : UInt<2>[2]
    T_179325[0] := UInt<2>(1)
    T_179325[1] := UInt<2>(2)
    wire T_179326 : UInt<2>[1]
    T_179326[0] := UInt<2>(2)
    wire T_179327 : UInt<3>[3]
    T_179327[0] := UInt<3>(0)
    T_179327[1] := UInt<3>(1)
    T_179327[2] := UInt<3>(2)
    wire T_179328 : UInt<0>[1]
    T_179328[0] := UInt<0>(0)
    wire T_179329 : UInt<2>[2]
    T_179329[0] := UInt<2>(1)
    T_179329[1] := UInt<2>(2)
    wire T_179330 : UInt<2>[2]
    T_179330[0] := UInt<2>(1)
    T_179330[1] := UInt<2>(2)
    wire T_179331 : UInt<2>[1]
    T_179331[0] := UInt<2>(2)
    wire T_179332 : UInt<3>[3]
    T_179332[0] := UInt<3>(0)
    T_179332[1] := UInt<3>(1)
    T_179332[2] := UInt<3>(2)
    wire T_179333 : UInt<0>[1]
    T_179333[0] := UInt<0>(0)
    wire T_179334 : UInt<2>[2]
    T_179334[0] := UInt<2>(1)
    T_179334[1] := UInt<2>(2)
    wire T_179335 : UInt<2>[2]
    T_179335[0] := UInt<2>(1)
    T_179335[1] := UInt<2>(2)
    wire T_179336 : UInt<2>[1]
    T_179336[0] := UInt<2>(2)
    wire T_179337 : UInt<3>[3]
    T_179337[0] := UInt<3>(0)
    T_179337[1] := UInt<3>(1)
    T_179337[2] := UInt<3>(2)
    wire T_179338 : UInt<0>[1]
    T_179338[0] := UInt<0>(0)
    wire T_179339 : UInt<2>[2]
    T_179339[0] := UInt<2>(1)
    T_179339[1] := UInt<2>(2)
    wire T_179340 : UInt<2>[2]
    T_179340[0] := UInt<2>(1)
    T_179340[1] := UInt<2>(2)
    wire T_179341 : UInt<2>[1]
    T_179341[0] := UInt<2>(2)
    wire T_179342 : UInt<3>[3]
    T_179342[0] := UInt<3>(0)
    T_179342[1] := UInt<3>(1)
    T_179342[2] := UInt<3>(2)
    wire T_179343 : UInt<0>[1]
    T_179343[0] := UInt<0>(0)
    wire T_179344 : UInt<2>[2]
    T_179344[0] := UInt<2>(1)
    T_179344[1] := UInt<2>(2)
    wire T_179345 : UInt<2>[2]
    T_179345[0] := UInt<2>(1)
    T_179345[1] := UInt<2>(2)
    wire T_179346 : UInt<2>[1]
    T_179346[0] := UInt<2>(2)
    wire T_179347 : UInt<3>[3]
    T_179347[0] := UInt<3>(0)
    T_179347[1] := UInt<3>(1)
    T_179347[2] := UInt<3>(2)
    wire T_179348 : UInt<0>[1]
    T_179348[0] := UInt<0>(0)
    wire T_179349 : UInt<2>[2]
    T_179349[0] := UInt<2>(1)
    T_179349[1] := UInt<2>(2)
    wire T_179350 : UInt<2>[2]
    T_179350[0] := UInt<2>(1)
    T_179350[1] := UInt<2>(2)
    wire T_179351 : UInt<2>[1]
    T_179351[0] := UInt<2>(2)
    wire T_179352 : UInt<3>[3]
    T_179352[0] := UInt<3>(0)
    T_179352[1] := UInt<3>(1)
    T_179352[2] := UInt<3>(2)
    wire T_179353 : UInt<0>[1]
    T_179353[0] := UInt<0>(0)
    wire T_179354 : UInt<2>[2]
    T_179354[0] := UInt<2>(1)
    T_179354[1] := UInt<2>(2)
    wire T_179355 : UInt<2>[2]
    T_179355[0] := UInt<2>(1)
    T_179355[1] := UInt<2>(2)
    wire T_179356 : UInt<2>[1]
    T_179356[0] := UInt<2>(2)
    wire T_179357 : UInt<3>[3]
    T_179357[0] := UInt<3>(0)
    T_179357[1] := UInt<3>(1)
    T_179357[2] := UInt<3>(2)
    wire T_179358 : UInt<0>[1]
    T_179358[0] := UInt<0>(0)
    wire T_179359 : UInt<2>[2]
    T_179359[0] := UInt<2>(1)
    T_179359[1] := UInt<2>(2)
    wire T_179360 : UInt<2>[2]
    T_179360[0] := UInt<2>(1)
    T_179360[1] := UInt<2>(2)
    wire T_179361 : UInt<2>[1]
    T_179361[0] := UInt<2>(2)
    wire T_179362 : UInt<3>[3]
    T_179362[0] := UInt<3>(0)
    T_179362[1] := UInt<3>(1)
    T_179362[2] := UInt<3>(2)
    wire T_179363 : UInt<0>[1]
    T_179363[0] := UInt<0>(0)
    wire T_179364 : UInt<2>[2]
    T_179364[0] := UInt<2>(1)
    T_179364[1] := UInt<2>(2)
    wire T_179365 : UInt<2>[2]
    T_179365[0] := UInt<2>(1)
    T_179365[1] := UInt<2>(2)
    wire T_179366 : UInt<2>[1]
    T_179366[0] := UInt<2>(2)
    wire T_179367 : UInt<3>[3]
    T_179367[0] := UInt<3>(0)
    T_179367[1] := UInt<3>(1)
    T_179367[2] := UInt<3>(2)
    wire T_179368 : UInt<0>[1]
    T_179368[0] := UInt<0>(0)
    wire T_179369 : UInt<2>[2]
    T_179369[0] := UInt<2>(1)
    T_179369[1] := UInt<2>(2)
    wire T_179370 : UInt<2>[2]
    T_179370[0] := UInt<2>(1)
    T_179370[1] := UInt<2>(2)
    wire T_179371 : UInt<2>[1]
    T_179371[0] := UInt<2>(2)
    wire T_179372 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}}
    T_179372.bits.payload := manager.grant.bits
    T_179372.bits.header.src := UInt<1>(0)
    T_179372.bits.header.dst := manager.grant.bits.client_id
    T_179372.valid := manager.grant.valid
    manager.grant.ready := T_179372.ready
    network.grant <> T_179372
    wire T_179373 : UInt<3>[3]
    T_179373[0] := UInt<3>(0)
    T_179373[1] := UInt<3>(1)
    T_179373[2] := UInt<3>(2)
    wire T_179374 : UInt<0>[1]
    T_179374[0] := UInt<0>(0)
    wire T_179375 : UInt<2>[2]
    T_179375[0] := UInt<2>(1)
    T_179375[1] := UInt<2>(2)
    wire T_179376 : UInt<2>[2]
    T_179376[0] := UInt<2>(1)
    T_179376[1] := UInt<2>(2)
    wire T_179377 : UInt<2>[1]
    T_179377[0] := UInt<2>(2)
    wire T_179378 : UInt<3>[3]
    T_179378[0] := UInt<3>(0)
    T_179378[1] := UInt<3>(1)
    T_179378[2] := UInt<3>(2)
    wire T_179379 : UInt<0>[1]
    T_179379[0] := UInt<0>(0)
    wire T_179380 : UInt<2>[2]
    T_179380[0] := UInt<2>(1)
    T_179380[1] := UInt<2>(2)
    wire T_179381 : UInt<2>[2]
    T_179381[0] := UInt<2>(1)
    T_179381[1] := UInt<2>(2)
    wire T_179382 : UInt<2>[1]
    T_179382[0] := UInt<2>(2)
    wire T_179383 : UInt<3>[3]
    T_179383[0] := UInt<3>(0)
    T_179383[1] := UInt<3>(1)
    T_179383[2] := UInt<3>(2)
    wire T_179384 : UInt<0>[1]
    T_179384[0] := UInt<0>(0)
    wire T_179385 : UInt<2>[2]
    T_179385[0] := UInt<2>(1)
    T_179385[1] := UInt<2>(2)
    wire T_179386 : UInt<2>[2]
    T_179386[0] := UInt<2>(1)
    T_179386[1] := UInt<2>(2)
    wire T_179387 : UInt<2>[1]
    T_179387[0] := UInt<2>(2)
    wire T_179388 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}}
    T_179388.bits.payload := manager.probe.bits
    T_179388.bits.header.src := UInt<1>(0)
    T_179388.bits.header.dst := manager.probe.bits.client_id
    T_179388.valid := manager.probe.valid
    manager.probe.ready := T_179388.ready
    network.probe <> T_179388
    manager.acquire.bits.client_id := network.acquire.bits.header.src
    wire T_179389 : UInt<3>[3]
    T_179389[0] := UInt<3>(0)
    T_179389[1] := UInt<3>(1)
    T_179389[2] := UInt<3>(2)
    wire T_179390 : UInt<0>[1]
    T_179390[0] := UInt<0>(0)
    wire T_179391 : UInt<2>[2]
    T_179391[0] := UInt<2>(1)
    T_179391[1] := UInt<2>(2)
    wire T_179392 : UInt<2>[2]
    T_179392[0] := UInt<2>(1)
    T_179392[1] := UInt<2>(2)
    wire T_179393 : UInt<2>[1]
    T_179393[0] := UInt<2>(2)
    wire T_179394 : UInt<3>[3]
    T_179394[0] := UInt<3>(0)
    T_179394[1] := UInt<3>(1)
    T_179394[2] := UInt<3>(2)
    wire T_179395 : UInt<0>[1]
    T_179395[0] := UInt<0>(0)
    wire T_179396 : UInt<2>[2]
    T_179396[0] := UInt<2>(1)
    T_179396[1] := UInt<2>(2)
    wire T_179397 : UInt<2>[2]
    T_179397[0] := UInt<2>(1)
    T_179397[1] := UInt<2>(2)
    wire T_179398 : UInt<2>[1]
    T_179398[0] := UInt<2>(2)
    wire T_179399 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    T_179399.valid := network.acquire.valid
    T_179399.bits := network.acquire.bits.payload
    network.acquire.ready := T_179399.ready
    manager.acquire <> T_179399
    manager.release.bits.client_id := network.release.bits.header.src
    wire T_179400 : UInt<3>[3]
    T_179400[0] := UInt<3>(0)
    T_179400[1] := UInt<3>(1)
    T_179400[2] := UInt<3>(2)
    wire T_179401 : UInt<0>[1]
    T_179401[0] := UInt<0>(0)
    wire T_179402 : UInt<2>[2]
    T_179402[0] := UInt<2>(1)
    T_179402[1] := UInt<2>(2)
    wire T_179403 : UInt<2>[2]
    T_179403[0] := UInt<2>(1)
    T_179403[1] := UInt<2>(2)
    wire T_179404 : UInt<2>[1]
    T_179404[0] := UInt<2>(2)
    wire T_179405 : UInt<3>[3]
    T_179405[0] := UInt<3>(0)
    T_179405[1] := UInt<3>(1)
    T_179405[2] := UInt<3>(2)
    wire T_179406 : UInt<0>[1]
    T_179406[0] := UInt<0>(0)
    wire T_179407 : UInt<2>[2]
    T_179407[0] := UInt<2>(1)
    T_179407[1] := UInt<2>(2)
    wire T_179408 : UInt<2>[2]
    T_179408[0] := UInt<2>(1)
    T_179408[1] := UInt<2>(2)
    wire T_179409 : UInt<2>[1]
    T_179409[0] := UInt<2>(2)
    wire T_179410 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    T_179410.valid := network.release.valid
    T_179410.bits := network.release.bits.payload
    network.release.ready := T_179410.ready
    manager.release <> T_179410
    wire T_179411 : UInt<3>[3]
    T_179411[0] := UInt<3>(0)
    T_179411[1] := UInt<3>(1)
    T_179411[2] := UInt<3>(2)
    wire T_179412 : UInt<0>[1]
    T_179412[0] := UInt<0>(0)
    wire T_179413 : UInt<2>[2]
    T_179413[0] := UInt<2>(1)
    T_179413[1] := UInt<2>(2)
    wire T_179414 : UInt<2>[2]
    T_179414[0] := UInt<2>(1)
    T_179414[1] := UInt<2>(2)
    wire T_179415 : UInt<2>[1]
    T_179415[0] := UInt<2>(2)
    wire T_179416 : UInt<3>[3]
    T_179416[0] := UInt<3>(0)
    T_179416[1] := UInt<3>(1)
    T_179416[2] := UInt<3>(2)
    wire T_179417 : UInt<0>[1]
    T_179417[0] := UInt<0>(0)
    wire T_179418 : UInt<2>[2]
    T_179418[0] := UInt<2>(1)
    T_179418[1] := UInt<2>(2)
    wire T_179419 : UInt<2>[2]
    T_179419[0] := UInt<2>(1)
    T_179419[1] := UInt<2>(2)
    wire T_179420 : UInt<2>[1]
    T_179420[0] := UInt<2>(2)
    wire T_179421 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}
    T_179421.valid := network.finish.valid
    T_179421.bits := network.finish.bits.payload
    network.finish.ready := T_179421.ready
    manager.finish <> T_179421
  module TileLinkEnqueuer_120089 : 
    input client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    output manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {manager_xact_id : UInt<1>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<1>, dst : UInt<1>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}}
    
    wire T_179422 : UInt<3>[3]
    T_179422[0] := UInt<3>(0)
    T_179422[1] := UInt<3>(1)
    T_179422[2] := UInt<3>(2)
    wire T_179423 : UInt<0>[1]
    T_179423[0] := UInt<0>(0)
    wire T_179424 : UInt<2>[2]
    T_179424[0] := UInt<2>(1)
    T_179424[1] := UInt<2>(2)
    wire T_179425 : UInt<2>[2]
    T_179425[0] := UInt<2>(1)
    T_179425[1] := UInt<2>(2)
    wire T_179426 : UInt<2>[1]
    T_179426[0] := UInt<2>(2)
    wire T_179427 : UInt<3>[3]
    T_179427[0] := UInt<3>(0)
    T_179427[1] := UInt<3>(1)
    T_179427[2] := UInt<3>(2)
    wire T_179428 : UInt<0>[1]
    T_179428[0] := UInt<0>(0)
    wire T_179429 : UInt<2>[2]
    T_179429[0] := UInt<2>(1)
    T_179429[1] := UInt<2>(2)
    wire T_179430 : UInt<2>[2]
    T_179430[0] := UInt<2>(1)
    T_179430[1] := UInt<2>(2)
    wire T_179431 : UInt<2>[1]
    T_179431[0] := UInt<2>(2)
    wire T_179432 : UInt<3>[3]
    T_179432[0] := UInt<3>(0)
    T_179432[1] := UInt<3>(1)
    T_179432[2] := UInt<3>(2)
    wire T_179433 : UInt<0>[1]
    T_179433[0] := UInt<0>(0)
    wire T_179434 : UInt<2>[2]
    T_179434[0] := UInt<2>(1)
    T_179434[1] := UInt<2>(2)
    wire T_179435 : UInt<2>[2]
    T_179435[0] := UInt<2>(1)
    T_179435[1] := UInt<2>(2)
    wire T_179436 : UInt<2>[1]
    T_179436[0] := UInt<2>(2)
    wire T_179437 : UInt<3>[3]
    T_179437[0] := UInt<3>(0)
    T_179437[1] := UInt<3>(1)
    T_179437[2] := UInt<3>(2)
    wire T_179438 : UInt<0>[1]
    T_179438[0] := UInt<0>(0)
    wire T_179439 : UInt<2>[2]
    T_179439[0] := UInt<2>(1)
    T_179439[1] := UInt<2>(2)
    wire T_179440 : UInt<2>[2]
    T_179440[0] := UInt<2>(1)
    T_179440[1] := UInt<2>(2)
    wire T_179441 : UInt<2>[1]
    T_179441[0] := UInt<2>(2)
    wire T_179442 : UInt<3>[3]
    T_179442[0] := UInt<3>(0)
    T_179442[1] := UInt<3>(1)
    T_179442[2] := UInt<3>(2)
    wire T_179443 : UInt<0>[1]
    T_179443[0] := UInt<0>(0)
    wire T_179444 : UInt<2>[2]
    T_179444[0] := UInt<2>(1)
    T_179444[1] := UInt<2>(2)
    wire T_179445 : UInt<2>[2]
    T_179445[0] := UInt<2>(1)
    T_179445[1] := UInt<2>(2)
    wire T_179446 : UInt<2>[1]
    T_179446[0] := UInt<2>(2)
    wire T_179447 : UInt<3>[3]
    T_179447[0] := UInt<3>(0)
    T_179447[1] := UInt<3>(1)
    T_179447[2] := UInt<3>(2)
    wire T_179448 : UInt<0>[1]
    T_179448[0] := UInt<0>(0)
    wire T_179449 : UInt<2>[2]
    T_179449[0] := UInt<2>(1)
    T_179449[1] := UInt<2>(2)
    wire T_179450 : UInt<2>[2]
    T_179450[0] := UInt<2>(1)
    T_179450[1] := UInt<2>(2)
    wire T_179451 : UInt<2>[1]
    T_179451[0] := UInt<2>(2)
    wire T_179452 : UInt<3>[3]
    T_179452[0] := UInt<3>(0)
    T_179452[1] := UInt<3>(1)
    T_179452[2] := UInt<3>(2)
    wire T_179453 : UInt<0>[1]
    T_179453[0] := UInt<0>(0)
    wire T_179454 : UInt<2>[2]
    T_179454[0] := UInt<2>(1)
    T_179454[1] := UInt<2>(2)
    wire T_179455 : UInt<2>[2]
    T_179455[0] := UInt<2>(1)
    T_179455[1] := UInt<2>(2)
    wire T_179456 : UInt<2>[1]
    T_179456[0] := UInt<2>(2)
    wire T_179457 : UInt<3>[3]
    T_179457[0] := UInt<3>(0)
    T_179457[1] := UInt<3>(1)
    T_179457[2] := UInt<3>(2)
    wire T_179458 : UInt<0>[1]
    T_179458[0] := UInt<0>(0)
    wire T_179459 : UInt<2>[2]
    T_179459[0] := UInt<2>(1)
    T_179459[1] := UInt<2>(2)
    wire T_179460 : UInt<2>[2]
    T_179460[0] := UInt<2>(1)
    T_179460[1] := UInt<2>(2)
    wire T_179461 : UInt<2>[1]
    T_179461[0] := UInt<2>(2)
    wire T_179462 : UInt<3>[3]
    T_179462[0] := UInt<3>(0)
    T_179462[1] := UInt<3>(1)
    T_179462[2] := UInt<3>(2)
    wire T_179463 : UInt<0>[1]
    T_179463[0] := UInt<0>(0)
    wire T_179464 : UInt<2>[2]
    T_179464[0] := UInt<2>(1)
    T_179464[1] := UInt<2>(2)
    wire T_179465 : UInt<2>[2]
    T_179465[0] := UInt<2>(1)
    T_179465[1] := UInt<2>(2)
    wire T_179466 : UInt<2>[1]
    T_179466[0] := UInt<2>(2)
    wire T_179467 : UInt<3>[3]
    T_179467[0] := UInt<3>(0)
    T_179467[1] := UInt<3>(1)
    T_179467[2] := UInt<3>(2)
    wire T_179468 : UInt<0>[1]
    T_179468[0] := UInt<0>(0)
    wire T_179469 : UInt<2>[2]
    T_179469[0] := UInt<2>(1)
    T_179469[1] := UInt<2>(2)
    wire T_179470 : UInt<2>[2]
    T_179470[0] := UInt<2>(1)
    T_179470[1] := UInt<2>(2)
    wire T_179471 : UInt<2>[1]
    T_179471[0] := UInt<2>(2)
    wire T_179472 : UInt<3>[3]
    T_179472[0] := UInt<3>(0)
    T_179472[1] := UInt<3>(1)
    T_179472[2] := UInt<3>(2)
    wire T_179473 : UInt<0>[1]
    T_179473[0] := UInt<0>(0)
    wire T_179474 : UInt<2>[2]
    T_179474[0] := UInt<2>(1)
    T_179474[1] := UInt<2>(2)
    wire T_179475 : UInt<2>[2]
    T_179475[0] := UInt<2>(1)
    T_179475[1] := UInt<2>(2)
    wire T_179476 : UInt<2>[1]
    T_179476[0] := UInt<2>(2)
    wire T_179477 : UInt<3>[3]
    T_179477[0] := UInt<3>(0)
    T_179477[1] := UInt<3>(1)
    T_179477[2] := UInt<3>(2)
    wire T_179478 : UInt<0>[1]
    T_179478[0] := UInt<0>(0)
    wire T_179479 : UInt<2>[2]
    T_179479[0] := UInt<2>(1)
    T_179479[1] := UInt<2>(2)
    wire T_179480 : UInt<2>[2]
    T_179480[0] := UInt<2>(1)
    T_179480[1] := UInt<2>(2)
    wire T_179481 : UInt<2>[1]
    T_179481[0] := UInt<2>(2)
    wire T_179482 : UInt<3>[3]
    T_179482[0] := UInt<3>(0)
    T_179482[1] := UInt<3>(1)
    T_179482[2] := UInt<3>(2)
    wire T_179483 : UInt<0>[1]
    T_179483[0] := UInt<0>(0)
    wire T_179484 : UInt<2>[2]
    T_179484[0] := UInt<2>(1)
    T_179484[1] := UInt<2>(2)
    wire T_179485 : UInt<2>[2]
    T_179485[0] := UInt<2>(1)
    T_179485[1] := UInt<2>(2)
    wire T_179486 : UInt<2>[1]
    T_179486[0] := UInt<2>(2)
    wire T_179487 : UInt<3>[3]
    T_179487[0] := UInt<3>(0)
    T_179487[1] := UInt<3>(1)
    T_179487[2] := UInt<3>(2)
    wire T_179488 : UInt<0>[1]
    T_179488[0] := UInt<0>(0)
    wire T_179489 : UInt<2>[2]
    T_179489[0] := UInt<2>(1)
    T_179489[1] := UInt<2>(2)
    wire T_179490 : UInt<2>[2]
    T_179490[0] := UInt<2>(1)
    T_179490[1] := UInt<2>(2)
    wire T_179491 : UInt<2>[1]
    T_179491[0] := UInt<2>(2)
    wire T_179492 : UInt<3>[3]
    T_179492[0] := UInt<3>(0)
    T_179492[1] := UInt<3>(1)
    T_179492[2] := UInt<3>(2)
    wire T_179493 : UInt<0>[1]
    T_179493[0] := UInt<0>(0)
    wire T_179494 : UInt<2>[2]
    T_179494[0] := UInt<2>(1)
    T_179494[1] := UInt<2>(2)
    wire T_179495 : UInt<2>[2]
    T_179495[0] := UInt<2>(1)
    T_179495[1] := UInt<2>(2)
    wire T_179496 : UInt<2>[1]
    T_179496[0] := UInt<2>(2)
    wire T_179497 : UInt<3>[3]
    T_179497[0] := UInt<3>(0)
    T_179497[1] := UInt<3>(1)
    T_179497[2] := UInt<3>(2)
    wire T_179498 : UInt<0>[1]
    T_179498[0] := UInt<0>(0)
    wire T_179499 : UInt<2>[2]
    T_179499[0] := UInt<2>(1)
    T_179499[1] := UInt<2>(2)
    wire T_179500 : UInt<2>[2]
    T_179500[0] := UInt<2>(1)
    T_179500[1] := UInt<2>(2)
    wire T_179501 : UInt<2>[1]
    T_179501[0] := UInt<2>(2)
    wire T_179502 : UInt<3>[3]
    T_179502[0] := UInt<3>(0)
    T_179502[1] := UInt<3>(1)
    T_179502[2] := UInt<3>(2)
    wire T_179503 : UInt<0>[1]
    T_179503[0] := UInt<0>(0)
    wire T_179504 : UInt<2>[2]
    T_179504[0] := UInt<2>(1)
    T_179504[1] := UInt<2>(2)
    wire T_179505 : UInt<2>[2]
    T_179505[0] := UInt<2>(1)
    T_179505[1] := UInt<2>(2)
    wire T_179506 : UInt<2>[1]
    T_179506[0] := UInt<2>(2)
    wire T_179507 : UInt<3>[3]
    T_179507[0] := UInt<3>(0)
    T_179507[1] := UInt<3>(1)
    T_179507[2] := UInt<3>(2)
    wire T_179508 : UInt<0>[1]
    T_179508[0] := UInt<0>(0)
    wire T_179509 : UInt<2>[2]
    T_179509[0] := UInt<2>(1)
    T_179509[1] := UInt<2>(2)
    wire T_179510 : UInt<2>[2]
    T_179510[0] := UInt<2>(1)
    T_179510[1] := UInt<2>(2)
    wire T_179511 : UInt<2>[1]
    T_179511[0] := UInt<2>(2)
    wire T_179512 : UInt<3>[3]
    T_179512[0] := UInt<3>(0)
    T_179512[1] := UInt<3>(1)
    T_179512[2] := UInt<3>(2)
    wire T_179513 : UInt<0>[1]
    T_179513[0] := UInt<0>(0)
    wire T_179514 : UInt<2>[2]
    T_179514[0] := UInt<2>(1)
    T_179514[1] := UInt<2>(2)
    wire T_179515 : UInt<2>[2]
    T_179515[0] := UInt<2>(1)
    T_179515[1] := UInt<2>(2)
    wire T_179516 : UInt<2>[1]
    T_179516[0] := UInt<2>(2)
    wire T_179517 : UInt<3>[3]
    T_179517[0] := UInt<3>(0)
    T_179517[1] := UInt<3>(1)
    T_179517[2] := UInt<3>(2)
    wire T_179518 : UInt<0>[1]
    T_179518[0] := UInt<0>(0)
    wire T_179519 : UInt<2>[2]
    T_179519[0] := UInt<2>(1)
    T_179519[1] := UInt<2>(2)
    wire T_179520 : UInt<2>[2]
    T_179520[0] := UInt<2>(1)
    T_179520[1] := UInt<2>(2)
    wire T_179521 : UInt<2>[1]
    T_179521[0] := UInt<2>(2)
    wire T_179522 : UInt<3>[3]
    T_179522[0] := UInt<3>(0)
    T_179522[1] := UInt<3>(1)
    T_179522[2] := UInt<3>(2)
    wire T_179523 : UInt<0>[1]
    T_179523[0] := UInt<0>(0)
    wire T_179524 : UInt<2>[2]
    T_179524[0] := UInt<2>(1)
    T_179524[1] := UInt<2>(2)
    wire T_179525 : UInt<2>[2]
    T_179525[0] := UInt<2>(1)
    T_179525[1] := UInt<2>(2)
    wire T_179526 : UInt<2>[1]
    T_179526[0] := UInt<2>(2)
    wire T_179527 : UInt<3>[3]
    T_179527[0] := UInt<3>(0)
    T_179527[1] := UInt<3>(1)
    T_179527[2] := UInt<3>(2)
    wire T_179528 : UInt<0>[1]
    T_179528[0] := UInt<0>(0)
    wire T_179529 : UInt<2>[2]
    T_179529[0] := UInt<2>(1)
    T_179529[1] := UInt<2>(2)
    wire T_179530 : UInt<2>[2]
    T_179530[0] := UInt<2>(1)
    T_179530[1] := UInt<2>(2)
    wire T_179531 : UInt<2>[1]
    T_179531[0] := UInt<2>(2)
    wire T_179532 : UInt<3>[3]
    T_179532[0] := UInt<3>(0)
    T_179532[1] := UInt<3>(1)
    T_179532[2] := UInt<3>(2)
    wire T_179533 : UInt<0>[1]
    T_179533[0] := UInt<0>(0)
    wire T_179534 : UInt<2>[2]
    T_179534[0] := UInt<2>(1)
    T_179534[1] := UInt<2>(2)
    wire T_179535 : UInt<2>[2]
    T_179535[0] := UInt<2>(1)
    T_179535[1] := UInt<2>(2)
    wire T_179536 : UInt<2>[1]
    T_179536[0] := UInt<2>(2)
    wire T_179537 : UInt<3>[3]
    T_179537[0] := UInt<3>(0)
    T_179537[1] := UInt<3>(1)
    T_179537[2] := UInt<3>(2)
    wire T_179538 : UInt<0>[1]
    T_179538[0] := UInt<0>(0)
    wire T_179539 : UInt<2>[2]
    T_179539[0] := UInt<2>(1)
    T_179539[1] := UInt<2>(2)
    wire T_179540 : UInt<2>[2]
    T_179540[0] := UInt<2>(1)
    T_179540[1] := UInt<2>(2)
    wire T_179541 : UInt<2>[1]
    T_179541[0] := UInt<2>(2)
    wire T_179542 : UInt<3>[3]
    T_179542[0] := UInt<3>(0)
    T_179542[1] := UInt<3>(1)
    T_179542[2] := UInt<3>(2)
    wire T_179543 : UInt<0>[1]
    T_179543[0] := UInt<0>(0)
    wire T_179544 : UInt<2>[2]
    T_179544[0] := UInt<2>(1)
    T_179544[1] := UInt<2>(2)
    wire T_179545 : UInt<2>[2]
    T_179545[0] := UInt<2>(1)
    T_179545[1] := UInt<2>(2)
    wire T_179546 : UInt<2>[1]
    T_179546[0] := UInt<2>(2)
    wire T_179547 : UInt<3>[3]
    T_179547[0] := UInt<3>(0)
    T_179547[1] := UInt<3>(1)
    T_179547[2] := UInt<3>(2)
    wire T_179548 : UInt<0>[1]
    T_179548[0] := UInt<0>(0)
    wire T_179549 : UInt<2>[2]
    T_179549[0] := UInt<2>(1)
    T_179549[1] := UInt<2>(2)
    wire T_179550 : UInt<2>[2]
    T_179550[0] := UInt<2>(1)
    T_179550[1] := UInt<2>(2)
    wire T_179551 : UInt<2>[1]
    T_179551[0] := UInt<2>(2)
    wire T_179552 : UInt<3>[3]
    T_179552[0] := UInt<3>(0)
    T_179552[1] := UInt<3>(1)
    T_179552[2] := UInt<3>(2)
    wire T_179553 : UInt<0>[1]
    T_179553[0] := UInt<0>(0)
    wire T_179554 : UInt<2>[2]
    T_179554[0] := UInt<2>(1)
    T_179554[1] := UInt<2>(2)
    wire T_179555 : UInt<2>[2]
    T_179555[0] := UInt<2>(1)
    T_179555[1] := UInt<2>(2)
    wire T_179556 : UInt<2>[1]
    T_179556[0] := UInt<2>(2)
    wire T_179557 : UInt<3>[3]
    T_179557[0] := UInt<3>(0)
    T_179557[1] := UInt<3>(1)
    T_179557[2] := UInt<3>(2)
    wire T_179558 : UInt<0>[1]
    T_179558[0] := UInt<0>(0)
    wire T_179559 : UInt<2>[2]
    T_179559[0] := UInt<2>(1)
    T_179559[1] := UInt<2>(2)
    wire T_179560 : UInt<2>[2]
    T_179560[0] := UInt<2>(1)
    T_179560[1] := UInt<2>(2)
    wire T_179561 : UInt<2>[1]
    T_179561[0] := UInt<2>(2)
    wire T_179562 : UInt<3>[3]
    T_179562[0] := UInt<3>(0)
    T_179562[1] := UInt<3>(1)
    T_179562[2] := UInt<3>(2)
    wire T_179563 : UInt<0>[1]
    T_179563[0] := UInt<0>(0)
    wire T_179564 : UInt<2>[2]
    T_179564[0] := UInt<2>(1)
    T_179564[1] := UInt<2>(2)
    wire T_179565 : UInt<2>[2]
    T_179565[0] := UInt<2>(1)
    T_179565[1] := UInt<2>(2)
    wire T_179566 : UInt<2>[1]
    T_179566[0] := UInt<2>(2)
    wire T_179567 : UInt<3>[3]
    T_179567[0] := UInt<3>(0)
    T_179567[1] := UInt<3>(1)
    T_179567[2] := UInt<3>(2)
    wire T_179568 : UInt<0>[1]
    T_179568[0] := UInt<0>(0)
    wire T_179569 : UInt<2>[2]
    T_179569[0] := UInt<2>(1)
    T_179569[1] := UInt<2>(2)
    wire T_179570 : UInt<2>[2]
    T_179570[0] := UInt<2>(1)
    T_179570[1] := UInt<2>(2)
    wire T_179571 : UInt<2>[1]
    T_179571[0] := UInt<2>(2)
    wire T_179572 : UInt<3>[3]
    T_179572[0] := UInt<3>(0)
    T_179572[1] := UInt<3>(1)
    T_179572[2] := UInt<3>(2)
    wire T_179573 : UInt<0>[1]
    T_179573[0] := UInt<0>(0)
    wire T_179574 : UInt<2>[2]
    T_179574[0] := UInt<2>(1)
    T_179574[1] := UInt<2>(2)
    wire T_179575 : UInt<2>[2]
    T_179575[0] := UInt<2>(1)
    T_179575[1] := UInt<2>(2)
    wire T_179576 : UInt<2>[1]
    T_179576[0] := UInt<2>(2)
    wire T_179577 : UInt<3>[3]
    T_179577[0] := UInt<3>(0)
    T_179577[1] := UInt<3>(1)
    T_179577[2] := UInt<3>(2)
    wire T_179578 : UInt<0>[1]
    T_179578[0] := UInt<0>(0)
    wire T_179579 : UInt<2>[2]
    T_179579[0] := UInt<2>(1)
    T_179579[1] := UInt<2>(2)
    wire T_179580 : UInt<2>[2]
    T_179580[0] := UInt<2>(1)
    T_179580[1] := UInt<2>(2)
    wire T_179581 : UInt<2>[1]
    T_179581[0] := UInt<2>(2)
    manager.acquire <> client.acquire
    client.probe <> manager.probe
    manager.release <> client.release
    client.grant <> manager.grant
    manager.finish <> client.finish
  module RocketChipTileLinkArbiter_120090 : 
    input clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1]
    input managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}[1]
    
    wire T_179582 : UInt<3>[3]
    T_179582[0] := UInt<3>(0)
    T_179582[1] := UInt<3>(1)
    T_179582[2] := UInt<3>(2)
    wire T_179583 : UInt<0>[1]
    T_179583[0] := UInt<0>(0)
    wire T_179584 : UInt<2>[2]
    T_179584[0] := UInt<2>(1)
    T_179584[1] := UInt<2>(2)
    wire T_179585 : UInt<2>[2]
    T_179585[0] := UInt<2>(1)
    T_179585[1] := UInt<2>(2)
    wire T_179586 : UInt<2>[1]
    T_179586[0] := UInt<2>(2)
    wire T_179587 : UInt<3>[3]
    T_179587[0] := UInt<3>(0)
    T_179587[1] := UInt<3>(1)
    T_179587[2] := UInt<3>(2)
    wire T_179588 : UInt<0>[1]
    T_179588[0] := UInt<0>(0)
    wire T_179589 : UInt<2>[2]
    T_179589[0] := UInt<2>(1)
    T_179589[1] := UInt<2>(2)
    wire T_179590 : UInt<2>[2]
    T_179590[0] := UInt<2>(1)
    T_179590[1] := UInt<2>(2)
    wire T_179591 : UInt<2>[1]
    T_179591[0] := UInt<2>(2)
    wire T_179592 : UInt<3>[3]
    T_179592[0] := UInt<3>(0)
    T_179592[1] := UInt<3>(1)
    T_179592[2] := UInt<3>(2)
    wire T_179593 : UInt<0>[1]
    T_179593[0] := UInt<0>(0)
    wire T_179594 : UInt<2>[2]
    T_179594[0] := UInt<2>(1)
    T_179594[1] := UInt<2>(2)
    wire T_179595 : UInt<2>[2]
    T_179595[0] := UInt<2>(1)
    T_179595[1] := UInt<2>(2)
    wire T_179596 : UInt<2>[1]
    T_179596[0] := UInt<2>(2)
    wire T_179597 : UInt<3>[3]
    T_179597[0] := UInt<3>(0)
    T_179597[1] := UInt<3>(1)
    T_179597[2] := UInt<3>(2)
    wire T_179598 : UInt<0>[1]
    T_179598[0] := UInt<0>(0)
    wire T_179599 : UInt<2>[2]
    T_179599[0] := UInt<2>(1)
    T_179599[1] := UInt<2>(2)
    wire T_179600 : UInt<2>[2]
    T_179600[0] := UInt<2>(1)
    T_179600[1] := UInt<2>(2)
    wire T_179601 : UInt<2>[1]
    T_179601[0] := UInt<2>(2)
    wire T_179602 : UInt<3>[3]
    T_179602[0] := UInt<3>(0)
    T_179602[1] := UInt<3>(1)
    T_179602[2] := UInt<3>(2)
    wire T_179603 : UInt<0>[1]
    T_179603[0] := UInt<0>(0)
    wire T_179604 : UInt<2>[2]
    T_179604[0] := UInt<2>(1)
    T_179604[1] := UInt<2>(2)
    wire T_179605 : UInt<2>[2]
    T_179605[0] := UInt<2>(1)
    T_179605[1] := UInt<2>(2)
    wire T_179606 : UInt<2>[1]
    T_179606[0] := UInt<2>(2)
    wire T_179607 : UInt<3>[3]
    T_179607[0] := UInt<3>(0)
    T_179607[1] := UInt<3>(1)
    T_179607[2] := UInt<3>(2)
    wire T_179608 : UInt<0>[1]
    T_179608[0] := UInt<0>(0)
    wire T_179609 : UInt<2>[2]
    T_179609[0] := UInt<2>(1)
    T_179609[1] := UInt<2>(2)
    wire T_179610 : UInt<2>[2]
    T_179610[0] := UInt<2>(1)
    T_179610[1] := UInt<2>(2)
    wire T_179611 : UInt<2>[1]
    T_179611[0] := UInt<2>(2)
    wire T_179612 : UInt<3>[3]
    T_179612[0] := UInt<3>(0)
    T_179612[1] := UInt<3>(1)
    T_179612[2] := UInt<3>(2)
    wire T_179613 : UInt<0>[1]
    T_179613[0] := UInt<0>(0)
    wire T_179614 : UInt<2>[2]
    T_179614[0] := UInt<2>(1)
    T_179614[1] := UInt<2>(2)
    wire T_179615 : UInt<2>[2]
    T_179615[0] := UInt<2>(1)
    T_179615[1] := UInt<2>(2)
    wire T_179616 : UInt<2>[1]
    T_179616[0] := UInt<2>(2)
    wire T_179617 : UInt<3>[3]
    T_179617[0] := UInt<3>(0)
    T_179617[1] := UInt<3>(1)
    T_179617[2] := UInt<3>(2)
    wire T_179618 : UInt<0>[1]
    T_179618[0] := UInt<0>(0)
    wire T_179619 : UInt<2>[2]
    T_179619[0] := UInt<2>(1)
    T_179619[1] := UInt<2>(2)
    wire T_179620 : UInt<2>[2]
    T_179620[0] := UInt<2>(1)
    T_179620[1] := UInt<2>(2)
    wire T_179621 : UInt<2>[1]
    T_179621[0] := UInt<2>(2)
    wire T_179622 : UInt<3>[3]
    T_179622[0] := UInt<3>(0)
    T_179622[1] := UInt<3>(1)
    T_179622[2] := UInt<3>(2)
    wire T_179623 : UInt<0>[1]
    T_179623[0] := UInt<0>(0)
    wire T_179624 : UInt<2>[2]
    T_179624[0] := UInt<2>(1)
    T_179624[1] := UInt<2>(2)
    wire T_179625 : UInt<2>[2]
    T_179625[0] := UInt<2>(1)
    T_179625[1] := UInt<2>(2)
    wire T_179626 : UInt<2>[1]
    T_179626[0] := UInt<2>(2)
    wire T_179627 : UInt<3>[3]
    T_179627[0] := UInt<3>(0)
    T_179627[1] := UInt<3>(1)
    T_179627[2] := UInt<3>(2)
    wire T_179628 : UInt<0>[1]
    T_179628[0] := UInt<0>(0)
    wire T_179629 : UInt<2>[2]
    T_179629[0] := UInt<2>(1)
    T_179629[1] := UInt<2>(2)
    wire T_179630 : UInt<2>[2]
    T_179630[0] := UInt<2>(1)
    T_179630[1] := UInt<2>(2)
    wire T_179631 : UInt<2>[1]
    T_179631[0] := UInt<2>(2)
    wire T_179632 : UInt<3>[3]
    T_179632[0] := UInt<3>(0)
    T_179632[1] := UInt<3>(1)
    T_179632[2] := UInt<3>(2)
    wire T_179633 : UInt<0>[1]
    T_179633[0] := UInt<0>(0)
    wire T_179634 : UInt<2>[2]
    T_179634[0] := UInt<2>(1)
    T_179634[1] := UInt<2>(2)
    wire T_179635 : UInt<2>[2]
    T_179635[0] := UInt<2>(1)
    T_179635[1] := UInt<2>(2)
    wire T_179636 : UInt<2>[1]
    T_179636[0] := UInt<2>(2)
    wire T_179637 : UInt<3>[3]
    T_179637[0] := UInt<3>(0)
    T_179637[1] := UInt<3>(1)
    T_179637[2] := UInt<3>(2)
    wire T_179638 : UInt<0>[1]
    T_179638[0] := UInt<0>(0)
    wire T_179639 : UInt<2>[2]
    T_179639[0] := UInt<2>(1)
    T_179639[1] := UInt<2>(2)
    wire T_179640 : UInt<2>[2]
    T_179640[0] := UInt<2>(1)
    T_179640[1] := UInt<2>(2)
    wire T_179641 : UInt<2>[1]
    T_179641[0] := UInt<2>(2)
    wire T_179642 : UInt<3>[3]
    T_179642[0] := UInt<3>(0)
    T_179642[1] := UInt<3>(1)
    T_179642[2] := UInt<3>(2)
    wire T_179643 : UInt<0>[1]
    T_179643[0] := UInt<0>(0)
    wire T_179644 : UInt<2>[2]
    T_179644[0] := UInt<2>(1)
    T_179644[1] := UInt<2>(2)
    wire T_179645 : UInt<2>[2]
    T_179645[0] := UInt<2>(1)
    T_179645[1] := UInt<2>(2)
    wire T_179646 : UInt<2>[1]
    T_179646[0] := UInt<2>(2)
    wire T_179647 : UInt<3>[3]
    T_179647[0] := UInt<3>(0)
    T_179647[1] := UInt<3>(1)
    T_179647[2] := UInt<3>(2)
    wire T_179648 : UInt<0>[1]
    T_179648[0] := UInt<0>(0)
    wire T_179649 : UInt<2>[2]
    T_179649[0] := UInt<2>(1)
    T_179649[1] := UInt<2>(2)
    wire T_179650 : UInt<2>[2]
    T_179650[0] := UInt<2>(1)
    T_179650[1] := UInt<2>(2)
    wire T_179651 : UInt<2>[1]
    T_179651[0] := UInt<2>(2)
    wire T_179652 : UInt<3>[3]
    T_179652[0] := UInt<3>(0)
    T_179652[1] := UInt<3>(1)
    T_179652[2] := UInt<3>(2)
    wire T_179653 : UInt<0>[1]
    T_179653[0] := UInt<0>(0)
    wire T_179654 : UInt<2>[2]
    T_179654[0] := UInt<2>(1)
    T_179654[1] := UInt<2>(2)
    wire T_179655 : UInt<2>[2]
    T_179655[0] := UInt<2>(1)
    T_179655[1] := UInt<2>(2)
    wire T_179656 : UInt<2>[1]
    T_179656[0] := UInt<2>(2)
    wire T_179657 : UInt<3>[3]
    T_179657[0] := UInt<3>(0)
    T_179657[1] := UInt<3>(1)
    T_179657[2] := UInt<3>(2)
    wire T_179658 : UInt<0>[1]
    T_179658[0] := UInt<0>(0)
    wire T_179659 : UInt<2>[2]
    T_179659[0] := UInt<2>(1)
    T_179659[1] := UInt<2>(2)
    wire T_179660 : UInt<2>[2]
    T_179660[0] := UInt<2>(1)
    T_179660[1] := UInt<2>(2)
    wire T_179661 : UInt<2>[1]
    T_179661[0] := UInt<2>(2)
    wire T_179662 : UInt<3>[3]
    T_179662[0] := UInt<3>(0)
    T_179662[1] := UInt<3>(1)
    T_179662[2] := UInt<3>(2)
    wire T_179663 : UInt<0>[1]
    T_179663[0] := UInt<0>(0)
    wire T_179664 : UInt<2>[2]
    T_179664[0] := UInt<2>(1)
    T_179664[1] := UInt<2>(2)
    wire T_179665 : UInt<2>[2]
    T_179665[0] := UInt<2>(1)
    T_179665[1] := UInt<2>(2)
    wire T_179666 : UInt<2>[1]
    T_179666[0] := UInt<2>(2)
    wire T_179667 : UInt<3>[3]
    T_179667[0] := UInt<3>(0)
    T_179667[1] := UInt<3>(1)
    T_179667[2] := UInt<3>(2)
    wire T_179668 : UInt<0>[1]
    T_179668[0] := UInt<0>(0)
    wire T_179669 : UInt<2>[2]
    T_179669[0] := UInt<2>(1)
    T_179669[1] := UInt<2>(2)
    wire T_179670 : UInt<2>[2]
    T_179670[0] := UInt<2>(1)
    T_179670[1] := UInt<2>(2)
    wire T_179671 : UInt<2>[1]
    T_179671[0] := UInt<2>(2)
    wire T_179672 : UInt<3>[3]
    T_179672[0] := UInt<3>(0)
    T_179672[1] := UInt<3>(1)
    T_179672[2] := UInt<3>(2)
    wire T_179673 : UInt<0>[1]
    T_179673[0] := UInt<0>(0)
    wire T_179674 : UInt<2>[2]
    T_179674[0] := UInt<2>(1)
    T_179674[1] := UInt<2>(2)
    wire T_179675 : UInt<2>[2]
    T_179675[0] := UInt<2>(1)
    T_179675[1] := UInt<2>(2)
    wire T_179676 : UInt<2>[1]
    T_179676[0] := UInt<2>(2)
    wire clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1]
    clients[0] := T_179677
    wire T_179678 : UInt<3>[3]
    T_179678[0] := UInt<3>(0)
    T_179678[1] := UInt<3>(1)
    T_179678[2] := UInt<3>(2)
    wire T_179679 : UInt<0>[1]
    T_179679[0] := UInt<0>(0)
    wire T_179680 : UInt<2>[2]
    T_179680[0] := UInt<2>(1)
    T_179680[1] := UInt<2>(2)
    wire T_179681 : UInt<2>[2]
    T_179681[0] := UInt<2>(1)
    T_179681[1] := UInt<2>(2)
    wire T_179682 : UInt<2>[1]
    T_179682[0] := UInt<2>(2)
    wire T_179683 : UInt<3>[3]
    T_179683[0] := UInt<3>(0)
    T_179683[1] := UInt<3>(1)
    T_179683[2] := UInt<3>(2)
    wire T_179684 : UInt<0>[1]
    T_179684[0] := UInt<0>(0)
    wire T_179685 : UInt<2>[2]
    T_179685[0] := UInt<2>(1)
    T_179685[1] := UInt<2>(2)
    wire T_179686 : UInt<2>[2]
    T_179686[0] := UInt<2>(1)
    T_179686[1] := UInt<2>(2)
    wire T_179687 : UInt<2>[1]
    T_179687[0] := UInt<2>(2)
    wire T_179688 : UInt<3>[3]
    T_179688[0] := UInt<3>(0)
    T_179688[1] := UInt<3>(1)
    T_179688[2] := UInt<3>(2)
    wire T_179689 : UInt<0>[1]
    T_179689[0] := UInt<0>(0)
    wire T_179690 : UInt<2>[2]
    T_179690[0] := UInt<2>(1)
    T_179690[1] := UInt<2>(2)
    wire T_179691 : UInt<2>[2]
    T_179691[0] := UInt<2>(1)
    T_179691[1] := UInt<2>(2)
    wire T_179692 : UInt<2>[1]
    T_179692[0] := UInt<2>(2)
    wire T_179693 : UInt<3>[3]
    T_179693[0] := UInt<3>(0)
    T_179693[1] := UInt<3>(1)
    T_179693[2] := UInt<3>(2)
    wire T_179694 : UInt<0>[1]
    T_179694[0] := UInt<0>(0)
    wire T_179695 : UInt<2>[2]
    T_179695[0] := UInt<2>(1)
    T_179695[1] := UInt<2>(2)
    wire T_179696 : UInt<2>[2]
    T_179696[0] := UInt<2>(1)
    T_179696[1] := UInt<2>(2)
    wire T_179697 : UInt<2>[1]
    T_179697[0] := UInt<2>(2)
    wire T_179698 : UInt<3>[3]
    T_179698[0] := UInt<3>(0)
    T_179698[1] := UInt<3>(1)
    T_179698[2] := UInt<3>(2)
    wire T_179699 : UInt<0>[1]
    T_179699[0] := UInt<0>(0)
    wire T_179700 : UInt<2>[2]
    T_179700[0] := UInt<2>(1)
    T_179700[1] := UInt<2>(2)
    wire T_179701 : UInt<2>[2]
    T_179701[0] := UInt<2>(1)
    T_179701[1] := UInt<2>(2)
    wire T_179702 : UInt<2>[1]
    T_179702[0] := UInt<2>(2)
    wire T_179703 : UInt<3>[3]
    T_179703[0] := UInt<3>(0)
    T_179703[1] := UInt<3>(1)
    T_179703[2] := UInt<3>(2)
    wire T_179704 : UInt<0>[1]
    T_179704[0] := UInt<0>(0)
    wire T_179705 : UInt<2>[2]
    T_179705[0] := UInt<2>(1)
    T_179705[1] := UInt<2>(2)
    wire T_179706 : UInt<2>[2]
    T_179706[0] := UInt<2>(1)
    T_179706[1] := UInt<2>(2)
    wire T_179707 : UInt<2>[1]
    T_179707[0] := UInt<2>(2)
    wire T_179708 : UInt<3>[3]
    T_179708[0] := UInt<3>(0)
    T_179708[1] := UInt<3>(1)
    T_179708[2] := UInt<3>(2)
    wire T_179709 : UInt<0>[1]
    T_179709[0] := UInt<0>(0)
    wire T_179710 : UInt<2>[2]
    T_179710[0] := UInt<2>(1)
    T_179710[1] := UInt<2>(2)
    wire T_179711 : UInt<2>[2]
    T_179711[0] := UInt<2>(1)
    T_179711[1] := UInt<2>(2)
    wire T_179712 : UInt<2>[1]
    T_179712[0] := UInt<2>(2)
    wire T_179713 : UInt<3>[3]
    T_179713[0] := UInt<3>(0)
    T_179713[1] := UInt<3>(1)
    T_179713[2] := UInt<3>(2)
    wire T_179714 : UInt<0>[1]
    T_179714[0] := UInt<0>(0)
    wire T_179715 : UInt<2>[2]
    T_179715[0] := UInt<2>(1)
    T_179715[1] := UInt<2>(2)
    wire T_179716 : UInt<2>[2]
    T_179716[0] := UInt<2>(1)
    T_179716[1] := UInt<2>(2)
    wire T_179717 : UInt<2>[1]
    T_179717[0] := UInt<2>(2)
    wire T_179718 : UInt<3>[3]
    T_179718[0] := UInt<3>(0)
    T_179718[1] := UInt<3>(1)
    T_179718[2] := UInt<3>(2)
    wire T_179719 : UInt<0>[1]
    T_179719[0] := UInt<0>(0)
    wire T_179720 : UInt<2>[2]
    T_179720[0] := UInt<2>(1)
    T_179720[1] := UInt<2>(2)
    wire T_179721 : UInt<2>[2]
    T_179721[0] := UInt<2>(1)
    T_179721[1] := UInt<2>(2)
    wire T_179722 : UInt<2>[1]
    T_179722[0] := UInt<2>(2)
    wire T_179723 : UInt<3>[3]
    T_179723[0] := UInt<3>(0)
    T_179723[1] := UInt<3>(1)
    T_179723[2] := UInt<3>(2)
    wire T_179724 : UInt<0>[1]
    T_179724[0] := UInt<0>(0)
    wire T_179725 : UInt<2>[2]
    T_179725[0] := UInt<2>(1)
    T_179725[1] := UInt<2>(2)
    wire T_179726 : UInt<2>[2]
    T_179726[0] := UInt<2>(1)
    T_179726[1] := UInt<2>(2)
    wire T_179727 : UInt<2>[1]
    T_179727[0] := UInt<2>(2)
    wire T_179728 : UInt<3>[3]
    T_179728[0] := UInt<3>(0)
    T_179728[1] := UInt<3>(1)
    T_179728[2] := UInt<3>(2)
    wire T_179729 : UInt<0>[1]
    T_179729[0] := UInt<0>(0)
    wire T_179730 : UInt<2>[2]
    T_179730[0] := UInt<2>(1)
    T_179730[1] := UInt<2>(2)
    wire T_179731 : UInt<2>[2]
    T_179731[0] := UInt<2>(1)
    T_179731[1] := UInt<2>(2)
    wire T_179732 : UInt<2>[1]
    T_179732[0] := UInt<2>(2)
    wire T_179733 : UInt<3>[3]
    T_179733[0] := UInt<3>(0)
    T_179733[1] := UInt<3>(1)
    T_179733[2] := UInt<3>(2)
    wire T_179734 : UInt<0>[1]
    T_179734[0] := UInt<0>(0)
    wire T_179735 : UInt<2>[2]
    T_179735[0] := UInt<2>(1)
    T_179735[1] := UInt<2>(2)
    wire T_179736 : UInt<2>[2]
    T_179736[0] := UInt<2>(1)
    T_179736[1] := UInt<2>(2)
    wire T_179737 : UInt<2>[1]
    T_179737[0] := UInt<2>(2)
    wire T_179738 : UInt<3>[3]
    T_179738[0] := UInt<3>(0)
    T_179738[1] := UInt<3>(1)
    T_179738[2] := UInt<3>(2)
    wire T_179739 : UInt<0>[1]
    T_179739[0] := UInt<0>(0)
    wire T_179740 : UInt<2>[2]
    T_179740[0] := UInt<2>(1)
    T_179740[1] := UInt<2>(2)
    wire T_179741 : UInt<2>[2]
    T_179741[0] := UInt<2>(1)
    T_179741[1] := UInt<2>(2)
    wire T_179742 : UInt<2>[1]
    T_179742[0] := UInt<2>(2)
    wire T_179743 : UInt<3>[3]
    T_179743[0] := UInt<3>(0)
    T_179743[1] := UInt<3>(1)
    T_179743[2] := UInt<3>(2)
    wire T_179744 : UInt<0>[1]
    T_179744[0] := UInt<0>(0)
    wire T_179745 : UInt<2>[2]
    T_179745[0] := UInt<2>(1)
    T_179745[1] := UInt<2>(2)
    wire T_179746 : UInt<2>[2]
    T_179746[0] := UInt<2>(1)
    T_179746[1] := UInt<2>(2)
    wire T_179747 : UInt<2>[1]
    T_179747[0] := UInt<2>(2)
    wire T_179748 : UInt<3>[3]
    T_179748[0] := UInt<3>(0)
    T_179748[1] := UInt<3>(1)
    T_179748[2] := UInt<3>(2)
    wire T_179749 : UInt<0>[1]
    T_179749[0] := UInt<0>(0)
    wire T_179750 : UInt<2>[2]
    T_179750[0] := UInt<2>(1)
    T_179750[1] := UInt<2>(2)
    wire T_179751 : UInt<2>[2]
    T_179751[0] := UInt<2>(1)
    T_179751[1] := UInt<2>(2)
    wire T_179752 : UInt<2>[1]
    T_179752[0] := UInt<2>(2)
    wire T_179753 : UInt<3>[3]
    T_179753[0] := UInt<3>(0)
    T_179753[1] := UInt<3>(1)
    T_179753[2] := UInt<3>(2)
    wire T_179754 : UInt<0>[1]
    T_179754[0] := UInt<0>(0)
    wire T_179755 : UInt<2>[2]
    T_179755[0] := UInt<2>(1)
    T_179755[1] := UInt<2>(2)
    wire T_179756 : UInt<2>[2]
    T_179756[0] := UInt<2>(1)
    T_179756[1] := UInt<2>(2)
    wire T_179757 : UInt<2>[1]
    T_179757[0] := UInt<2>(2)
    wire T_179758 : UInt<3>[3]
    T_179758[0] := UInt<3>(0)
    T_179758[1] := UInt<3>(1)
    T_179758[2] := UInt<3>(2)
    wire T_179759 : UInt<0>[1]
    T_179759[0] := UInt<0>(0)
    wire T_179760 : UInt<2>[2]
    T_179760[0] := UInt<2>(1)
    T_179760[1] := UInt<2>(2)
    wire T_179761 : UInt<2>[2]
    T_179761[0] := UInt<2>(1)
    T_179761[1] := UInt<2>(2)
    wire T_179762 : UInt<2>[1]
    T_179762[0] := UInt<2>(2)
    wire T_179763 : UInt<3>[3]
    T_179763[0] := UInt<3>(0)
    T_179763[1] := UInt<3>(1)
    T_179763[2] := UInt<3>(2)
    wire T_179764 : UInt<0>[1]
    T_179764[0] := UInt<0>(0)
    wire T_179765 : UInt<2>[2]
    T_179765[0] := UInt<2>(1)
    T_179765[1] := UInt<2>(2)
    wire T_179766 : UInt<2>[2]
    T_179766[0] := UInt<2>(1)
    T_179766[1] := UInt<2>(2)
    wire T_179767 : UInt<2>[1]
    T_179767[0] := UInt<2>(2)
    wire T_179768 : UInt<3>[3]
    T_179768[0] := UInt<3>(0)
    T_179768[1] := UInt<3>(1)
    T_179768[2] := UInt<3>(2)
    wire T_179769 : UInt<0>[1]
    T_179769[0] := UInt<0>(0)
    wire T_179770 : UInt<2>[2]
    T_179770[0] := UInt<2>(1)
    T_179770[1] := UInt<2>(2)
    wire T_179771 : UInt<2>[2]
    T_179771[0] := UInt<2>(1)
    T_179771[1] := UInt<2>(2)
    wire T_179772 : UInt<2>[1]
    T_179772[0] := UInt<2>(2)
    wire T_179773 : UInt<3>[3]
    T_179773[0] := UInt<3>(0)
    T_179773[1] := UInt<3>(1)
    T_179773[2] := UInt<3>(2)
    wire T_179774 : UInt<0>[1]
    T_179774[0] := UInt<0>(0)
    wire T_179775 : UInt<2>[2]
    T_179775[0] := UInt<2>(1)
    T_179775[1] := UInt<2>(2)
    wire T_179776 : UInt<2>[2]
    T_179776[0] := UInt<2>(1)
    T_179776[1] := UInt<2>(2)
    wire T_179777 : UInt<2>[1]
    T_179777[0] := UInt<2>(2)
    wire T_179778 : UInt<3>[3]
    T_179778[0] := UInt<3>(0)
    T_179778[1] := UInt<3>(1)
    T_179778[2] := UInt<3>(2)
    wire T_179779 : UInt<0>[1]
    T_179779[0] := UInt<0>(0)
    wire T_179780 : UInt<2>[2]
    T_179780[0] := UInt<2>(1)
    T_179780[1] := UInt<2>(2)
    wire T_179781 : UInt<2>[2]
    T_179781[0] := UInt<2>(1)
    T_179781[1] := UInt<2>(2)
    wire T_179782 : UInt<2>[1]
    T_179782[0] := UInt<2>(2)
    wire T_179783 : UInt<3>[3]
    T_179783[0] := UInt<3>(0)
    T_179783[1] := UInt<3>(1)
    T_179783[2] := UInt<3>(2)
    wire T_179784 : UInt<0>[1]
    T_179784[0] := UInt<0>(0)
    wire T_179785 : UInt<2>[2]
    T_179785[0] := UInt<2>(1)
    T_179785[1] := UInt<2>(2)
    wire T_179786 : UInt<2>[2]
    T_179786[0] := UInt<2>(1)
    T_179786[1] := UInt<2>(2)
    wire T_179787 : UInt<2>[1]
    T_179787[0] := UInt<2>(2)
    wire managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}[1]
    managers[0] := T_179788
    inst T_179789 of ClientTileLinkNetworkPort_114092
    inst T_179790 of TileLinkEnqueuer_115938
    T_179789.client <> clients[0]
    T_179790.client <> T_179789.network
    inst T_179791 of ManagerTileLinkNetworkPort_118243
    inst T_179792 of TileLinkEnqueuer_120089
    managers[0] <> T_179791.manager
    T_179791.network <> T_179792.manager
    T_179792.client <> T_179790.manager
  module Arbiter : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}
    output chosen : UInt<1>
    
    wire T_179793 : UInt<3>[3]
    T_179793[0] := UInt<3>(0)
    T_179793[1] := UInt<3>(1)
    T_179793[2] := UInt<3>(2)
    wire T_179794 : UInt<0>[1]
    T_179794[0] := UInt<0>(0)
    wire T_179795 : UInt<2>[2]
    T_179795[0] := UInt<2>(1)
    T_179795[1] := UInt<2>(2)
    wire T_179796 : UInt<2>[2]
    T_179796[0] := UInt<2>(1)
    T_179796[1] := UInt<2>(2)
    wire T_179797 : UInt<2>[1]
    T_179797[0] := UInt<2>(2)
    wire T_179798 : UInt<3>[3]
    T_179798[0] := UInt<3>(0)
    T_179798[1] := UInt<3>(1)
    T_179798[2] := UInt<3>(2)
    wire T_179799 : UInt<0>[1]
    T_179799[0] := UInt<0>(0)
    wire T_179800 : UInt<2>[2]
    T_179800[0] := UInt<2>(1)
    T_179800[1] := UInt<2>(2)
    wire T_179801 : UInt<2>[2]
    T_179801[0] := UInt<2>(1)
    T_179801[1] := UInt<2>(2)
    wire T_179802 : UInt<2>[1]
    T_179802[0] := UInt<2>(2)
    wire T_179803 : UInt<3>[3]
    T_179803[0] := UInt<3>(0)
    T_179803[1] := UInt<3>(1)
    T_179803[2] := UInt<3>(2)
    wire T_179804 : UInt<0>[1]
    T_179804[0] := UInt<0>(0)
    wire T_179805 : UInt<2>[2]
    T_179805[0] := UInt<2>(1)
    T_179805[1] := UInt<2>(2)
    wire T_179806 : UInt<2>[2]
    T_179806[0] := UInt<2>(1)
    T_179806[1] := UInt<2>(2)
    wire T_179807 : UInt<2>[1]
    T_179807[0] := UInt<2>(2)
    wire T_179808 : UInt<3>[3]
    T_179808[0] := UInt<3>(0)
    T_179808[1] := UInt<3>(1)
    T_179808[2] := UInt<3>(2)
    wire T_179809 : UInt<0>[1]
    T_179809[0] := UInt<0>(0)
    wire T_179810 : UInt<2>[2]
    T_179810[0] := UInt<2>(1)
    T_179810[1] := UInt<2>(2)
    wire T_179811 : UInt<2>[2]
    T_179811[0] := UInt<2>(1)
    T_179811[1] := UInt<2>(2)
    wire T_179812 : UInt<2>[1]
    T_179812[0] := UInt<2>(2)
    wire T_179813 : UInt<1>
    node T_179814 = or(UInt<1>(0), in[0].valid)
    node T_179815 = eq(T_179814, UInt<1>(0))
    node T_179816 = eq(UInt<1>(1), UInt<1>(0))
    wire T_179817 : UInt<1>
    T_179817 := UInt<1>(1)
    when UInt<1>(0) : T_179817 := T_179816
    node T_179818 = and(T_179817, out.ready)
    in[0].ready := T_179818
    node T_179819 = eq(UInt<1>(1), UInt<1>(1))
    wire T_179820 : UInt<1>
    T_179820 := T_179815
    when UInt<1>(0) : T_179820 := T_179819
    node T_179821 = and(T_179820, out.ready)
    in[1].ready := T_179821
    wire T_179822 : UInt<3>[3]
    T_179822[0] := UInt<3>(0)
    T_179822[1] := UInt<3>(1)
    T_179822[2] := UInt<3>(2)
    wire T_179823 : UInt<0>[1]
    T_179823[0] := UInt<0>(0)
    wire T_179824 : UInt<2>[2]
    T_179824[0] := UInt<2>(1)
    T_179824[1] := UInt<2>(2)
    wire T_179825 : UInt<2>[2]
    T_179825[0] := UInt<2>(1)
    T_179825[1] := UInt<2>(2)
    wire T_179826 : UInt<2>[1]
    T_179826[0] := UInt<2>(2)
    accessor T_179827 = in[T_179813]
    out.valid := T_179827.valid
    wire T_179828 : UInt<3>[3]
    T_179828[0] := UInt<3>(0)
    T_179828[1] := UInt<3>(1)
    T_179828[2] := UInt<3>(2)
    wire T_179829 : UInt<0>[1]
    T_179829[0] := UInt<0>(0)
    wire T_179830 : UInt<2>[2]
    T_179830[0] := UInt<2>(1)
    T_179830[1] := UInt<2>(2)
    wire T_179831 : UInt<2>[2]
    T_179831[0] := UInt<2>(1)
    T_179831[1] := UInt<2>(2)
    wire T_179832 : UInt<2>[1]
    T_179832[0] := UInt<2>(2)
    accessor T_179833 = in[T_179813]
    out.bits := T_179833.bits
    chosen := T_179813
    wire T_179834 : UInt<1>
    T_179834 := UInt<1>(1)
    when in[0].valid : T_179834 := UInt<1>(0)
    wire T_179835 : UInt<1>
    T_179835 := T_179834
    when UInt<1>(0) : T_179835 := UInt<1>(1)
    T_179813 := T_179835
  module MemIOTileLinkIOConverter : 
    output tl : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    
    wire T_179836 : UInt<3>[3]
    T_179836[0] := UInt<3>(0)
    T_179836[1] := UInt<3>(1)
    T_179836[2] := UInt<3>(2)
    wire T_179837 : UInt<0>[1]
    T_179837[0] := UInt<0>(0)
    wire T_179838 : UInt<2>[2]
    T_179838[0] := UInt<2>(1)
    T_179838[1] := UInt<2>(2)
    wire T_179839 : UInt<2>[2]
    T_179839[0] := UInt<2>(1)
    T_179839[1] := UInt<2>(2)
    wire T_179840 : UInt<2>[1]
    T_179840[0] := UInt<2>(2)
    wire T_179841 : UInt<3>[3]
    T_179841[0] := UInt<3>(0)
    T_179841[1] := UInt<3>(1)
    T_179841[2] := UInt<3>(2)
    wire T_179842 : UInt<0>[1]
    T_179842[0] := UInt<0>(0)
    wire T_179843 : UInt<2>[2]
    T_179843[0] := UInt<2>(1)
    T_179843[1] := UInt<2>(2)
    wire T_179844 : UInt<2>[2]
    T_179844[0] := UInt<2>(1)
    T_179844[1] := UInt<2>(2)
    wire T_179845 : UInt<2>[1]
    T_179845[0] := UInt<2>(2)
    wire T_179846 : UInt<3>[3]
    T_179846[0] := UInt<3>(0)
    T_179846[1] := UInt<3>(1)
    T_179846[2] := UInt<3>(2)
    wire T_179847 : UInt<0>[1]
    T_179847[0] := UInt<0>(0)
    wire T_179848 : UInt<2>[2]
    T_179848[0] := UInt<2>(1)
    T_179848[1] := UInt<2>(2)
    wire T_179849 : UInt<2>[2]
    T_179849[0] := UInt<2>(1)
    T_179849[1] := UInt<2>(2)
    wire T_179850 : UInt<2>[1]
    T_179850[0] := UInt<2>(2)
    wire T_179851 : UInt<3>[3]
    T_179851[0] := UInt<3>(0)
    T_179851[1] := UInt<3>(1)
    T_179851[2] := UInt<3>(2)
    wire T_179852 : UInt<0>[1]
    T_179852[0] := UInt<0>(0)
    wire T_179853 : UInt<2>[2]
    T_179853[0] := UInt<2>(1)
    T_179853[1] := UInt<2>(2)
    wire T_179854 : UInt<2>[2]
    T_179854[0] := UInt<2>(1)
    T_179854[1] := UInt<2>(2)
    wire T_179855 : UInt<2>[1]
    T_179855[0] := UInt<2>(2)
    wire T_179856 : UInt<3>[3]
    T_179856[0] := UInt<3>(0)
    T_179856[1] := UInt<3>(1)
    T_179856[2] := UInt<3>(2)
    wire T_179857 : UInt<0>[1]
    T_179857[0] := UInt<0>(0)
    wire T_179858 : UInt<2>[2]
    T_179858[0] := UInt<2>(1)
    T_179858[1] := UInt<2>(2)
    wire T_179859 : UInt<2>[2]
    T_179859[0] := UInt<2>(1)
    T_179859[1] := UInt<2>(2)
    wire T_179860 : UInt<2>[1]
    T_179860[0] := UInt<2>(2)
    wire T_179861 : UInt<3>[3]
    T_179861[0] := UInt<3>(0)
    T_179861[1] := UInt<3>(1)
    T_179861[2] := UInt<3>(2)
    wire T_179862 : UInt<0>[1]
    T_179862[0] := UInt<0>(0)
    wire T_179863 : UInt<2>[2]
    T_179863[0] := UInt<2>(1)
    T_179863[1] := UInt<2>(2)
    wire T_179864 : UInt<2>[2]
    T_179864[0] := UInt<2>(1)
    T_179864[1] := UInt<2>(2)
    wire T_179865 : UInt<2>[1]
    T_179865[0] := UInt<2>(2)
    wire T_179866 : UInt<3>[3]
    T_179866[0] := UInt<3>(0)
    T_179866[1] := UInt<3>(1)
    T_179866[2] := UInt<3>(2)
    wire T_179867 : UInt<0>[1]
    T_179867[0] := UInt<0>(0)
    wire T_179868 : UInt<2>[2]
    T_179868[0] := UInt<2>(1)
    T_179868[1] := UInt<2>(2)
    wire T_179869 : UInt<2>[2]
    T_179869[0] := UInt<2>(1)
    T_179869[1] := UInt<2>(2)
    wire T_179870 : UInt<2>[1]
    T_179870[0] := UInt<2>(2)
    wire T_179871 : UInt<3>[3]
    T_179871[0] := UInt<3>(0)
    T_179871[1] := UInt<3>(1)
    T_179871[2] := UInt<3>(2)
    wire T_179872 : UInt<0>[1]
    T_179872[0] := UInt<0>(0)
    wire T_179873 : UInt<2>[2]
    T_179873[0] := UInt<2>(1)
    T_179873[1] := UInt<2>(2)
    wire T_179874 : UInt<2>[2]
    T_179874[0] := UInt<2>(1)
    T_179874[1] := UInt<2>(2)
    wire T_179875 : UInt<2>[1]
    T_179875[0] := UInt<2>(2)
    wire T_179876 : UInt<3>[3]
    T_179876[0] := UInt<3>(0)
    T_179876[1] := UInt<3>(1)
    T_179876[2] := UInt<3>(2)
    wire T_179877 : UInt<0>[1]
    T_179877[0] := UInt<0>(0)
    wire T_179878 : UInt<2>[2]
    T_179878[0] := UInt<2>(1)
    T_179878[1] := UInt<2>(2)
    wire T_179879 : UInt<2>[2]
    T_179879[0] := UInt<2>(1)
    T_179879[1] := UInt<2>(2)
    wire T_179880 : UInt<2>[1]
    T_179880[0] := UInt<2>(2)
    wire T_179881 : UInt<3>[3]
    T_179881[0] := UInt<3>(0)
    T_179881[1] := UInt<3>(1)
    T_179881[2] := UInt<3>(2)
    wire T_179882 : UInt<0>[1]
    T_179882[0] := UInt<0>(0)
    wire T_179883 : UInt<2>[2]
    T_179883[0] := UInt<2>(1)
    T_179883[1] := UInt<2>(2)
    wire T_179884 : UInt<2>[2]
    T_179884[0] := UInt<2>(1)
    T_179884[1] := UInt<2>(2)
    wire T_179885 : UInt<2>[1]
    T_179885[0] := UInt<2>(2)
    wire T_179886 : UInt<3>[3]
    T_179886[0] := UInt<3>(0)
    T_179886[1] := UInt<3>(1)
    T_179886[2] := UInt<3>(2)
    wire T_179887 : UInt<0>[1]
    T_179887[0] := UInt<0>(0)
    wire T_179888 : UInt<2>[2]
    T_179888[0] := UInt<2>(1)
    T_179888[1] := UInt<2>(2)
    wire T_179889 : UInt<2>[2]
    T_179889[0] := UInt<2>(1)
    T_179889[1] := UInt<2>(2)
    wire T_179890 : UInt<2>[1]
    T_179890[0] := UInt<2>(2)
    wire T_179891 : UInt<3>[3]
    T_179891[0] := UInt<3>(0)
    T_179891[1] := UInt<3>(1)
    T_179891[2] := UInt<3>(2)
    wire T_179892 : UInt<0>[1]
    T_179892[0] := UInt<0>(0)
    wire T_179893 : UInt<2>[2]
    T_179893[0] := UInt<2>(1)
    T_179893[1] := UInt<2>(2)
    wire T_179894 : UInt<2>[2]
    T_179894[0] := UInt<2>(1)
    T_179894[1] := UInt<2>(2)
    wire T_179895 : UInt<2>[1]
    T_179895[0] := UInt<2>(2)
    tl.acquire.ready := UInt<1>(0)
    tl.probe.valid := UInt<1>(0)
    tl.release.ready := UInt<1>(0)
    tl.finish.ready := UInt<1>(1)
    mem__.resp.ready := UInt<1>(0)
    wire T_179896 : UInt<3>[3]
    T_179896[0] := UInt<3>(0)
    T_179896[1] := UInt<3>(1)
    T_179896[2] := UInt<3>(2)
    wire T_179897 : UInt<0>[1]
    T_179897[0] := UInt<0>(0)
    wire T_179898 : UInt<2>[2]
    T_179898[0] := UInt<2>(1)
    T_179898[1] := UInt<2>(2)
    wire T_179899 : UInt<2>[2]
    T_179899[0] := UInt<2>(1)
    T_179899[1] := UInt<2>(2)
    wire T_179900 : UInt<2>[1]
    T_179900[0] := UInt<2>(2)
    inst gnt_arb of Arbiter
    tl.grant <> gnt_arb.out
    wire T_179901 : UInt<3>[3]
    T_179901[0] := UInt<3>(2)
    T_179901[1] := UInt<3>(3)
    T_179901[2] := UInt<3>(4)
    node T_179902 = eq(T_179901[0], tl.acquire.bits.a_type)
    node T_179903 = eq(T_179901[1], tl.acquire.bits.a_type)
    node T_179904 = eq(T_179901[2], tl.acquire.bits.a_type)
    node T_179905 = or(UInt<1>(0), T_179902)
    node T_179906 = or(T_179905, T_179903)
    node T_179907 = or(T_179906, T_179904)
    node acq_has_data = and(tl.acquire.bits.is_builtin_type, T_179907)
    node T_179908 = eq(T_179891[0], tl.release.bits.r_type)
    node T_179909 = eq(T_179891[1], tl.release.bits.r_type)
    node T_179910 = eq(T_179891[2], tl.release.bits.r_type)
    node T_179911 = or(UInt<1>(0), T_179908)
    node T_179912 = or(T_179911, T_179909)
    node rel_has_data = or(T_179912, T_179910)
    reg active_out : UInt<1>
    onreset active_out := UInt<1>(0)
    reg cmd_sent_out : UInt<1>
    onreset cmd_sent_out := UInt<1>(0)
    reg tag_out : UInt<5>
    reg addr_out : UInt<26>
    reg has_data : UInt<1>
    onreset has_data := UInt<1>(0)
    reg data_from_rel : UInt<1>
    onreset data_from_rel := UInt<1>(0)
    node T_179913 = and(tl.acquire.ready, tl.acquire.valid)
    node T_179914 = and(T_179913, acq_has_data)
    node T_179915 = and(tl.release.ready, tl.release.valid)
    node T_179916 = and(T_179915, rel_has_data)
    node T_179917 = or(T_179914, T_179916)
    reg tl_cnt_out : UInt<2>
    onreset tl_cnt_out := UInt<2>(0)
    when T_179917 : 
      node T_179918 = eq(tl_cnt_out, UInt<2>(3))
      node T_179919 = and(UInt<1>(0), T_179918)
      node T_179920 = addw(tl_cnt_out, UInt<1>(1))
      wire T_179921 : UInt<2>
      T_179921 := T_179920
      when T_179919 : T_179921 := UInt<1>(0)
      tl_cnt_out := T_179921
    node tl_wrap_out = and(T_179917, T_179918)
    reg tl_done_out : UInt<1>
    onreset tl_done_out := UInt<1>(0)
    reg make_grant_ack : UInt<1>
    onreset make_grant_ack := UInt<1>(0)
    gnt_arb.in[1].valid := UInt<1>(0)
    node T_179922 = bits(tag_out, 3, 3)
    wire T_179923 : UInt<3>
    T_179923 := UInt<3>(3)
    when data_from_rel : T_179923 := UInt<3>(0)
    node T_179924 = dshr(tag_out, UInt<1>(1))
    wire T_179925 : UInt<3>[3]
    T_179925[0] := UInt<3>(0)
    T_179925[1] := UInt<3>(1)
    T_179925[2] := UInt<3>(2)
    wire T_179926 : UInt<0>[1]
    T_179926[0] := UInt<0>(0)
    wire T_179927 : UInt<2>[2]
    T_179927[0] := UInt<2>(1)
    T_179927[1] := UInt<2>(2)
    wire T_179928 : UInt<2>[2]
    T_179928[0] := UInt<2>(1)
    T_179928[1] := UInt<2>(2)
    wire T_179929 : UInt<2>[1]
    T_179929[0] := UInt<2>(2)
    wire T_179930 : UInt<3>[3]
    T_179930[0] := UInt<3>(0)
    T_179930[1] := UInt<3>(1)
    T_179930[2] := UInt<3>(2)
    wire T_179931 : UInt<0>[1]
    T_179931[0] := UInt<0>(0)
    wire T_179932 : UInt<2>[2]
    T_179932[0] := UInt<2>(1)
    T_179932[1] := UInt<2>(2)
    wire T_179933 : UInt<2>[2]
    T_179933[0] := UInt<2>(1)
    T_179933[1] := UInt<2>(2)
    wire T_179934 : UInt<2>[1]
    T_179934[0] := UInt<2>(2)
    wire T_179935 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}
    T_179935.client_id := T_179922
    T_179935.is_builtin_type := UInt<1>(1)
    T_179935.g_type := T_179923
    T_179935.client_xact_id := T_179924
    T_179935.manager_xact_id := UInt<1>(0)
    T_179935.addr_beat := UInt<1>(0)
    T_179935.data := UInt<1>(0)
    gnt_arb.in[1].bits := T_179935
    mem__.req_cmd.valid := UInt<1>(0)
    mem__.req_data.valid := UInt<1>(0)
    mem__.req_cmd.bits.rw := has_data
    mem__.req_cmd.bits.tag := tag_out
    mem__.req_cmd.bits.addr := addr_out
    wire T_179936 : UInt<128>
    T_179936 := tl.acquire.bits.data
    when data_from_rel : T_179936 := tl.release.bits.data
    mem__.req_data.bits.data := T_179936
    
    node T_179937 = eq(active_out, UInt<1>(0))
    when T_179937 : 
      tl.release.ready := mem__.req_data.ready
      node T_179938 = eq(tl.release.valid, UInt<1>(0))
      node T_179939 = and(mem__.req_data.ready, T_179938)
      tl.acquire.ready := T_179939
      node T_179940 = and(tl.release.valid, rel_has_data)
      node T_179941 = and(tl.acquire.valid, acq_has_data)
      node T_179942 = or(T_179940, T_179941)
      mem__.req_data.valid := T_179942
      
      
      node T_179943 = or(tl.release.valid, tl.acquire.valid)
      node T_179944 = and(mem__.req_data.ready, T_179943)
      when T_179944 : 
        node T_179945 = eq(mem__.req_cmd.ready, UInt<1>(0))
        node T_179946 = or(T_179945, mem__.req_data.valid)
        active_out := T_179946
        mem__.req_cmd.valid := UInt<1>(1)
        cmd_sent_out := mem__.req_cmd.ready
        tl_done_out := tl_wrap_out
        when tl.release.valid : 
          data_from_rel := UInt<1>(1)
          node T_179949 = eq(UInt<1>(0), UInt<1>(0))
          make_grant_ack := T_179949
          mem__.req_data.bits.data := tl.release.bits.data
          node T_179950 = cat(tl.release.bits.client_xact_id, tl.release.bits.voluntary)
          node T_179951 = cat(tl.release.bits.client_id, T_179950)
          mem__.req_cmd.bits.tag := T_179951
          mem__.req_cmd.bits.addr := tl.release.bits.addr_block
          mem__.req_cmd.bits.rw := rel_has_data
          tag_out := T_179951
          addr_out := tl.release.bits.addr_block
          has_data := rel_has_data
        else : 
          when tl.acquire.valid : 
            data_from_rel := UInt<1>(0)
            make_grant_ack := acq_has_data
            mem__.req_data.bits.data := tl.acquire.bits.data
            mem__.req_cmd.bits.rw := acq_has_data
            node T_179947 = cat(tl.acquire.bits.client_xact_id, tl.acquire.bits.is_builtin_type)
            node T_179948 = cat(tl.acquire.bits.client_id, T_179947)
            mem__.req_cmd.bits.tag := T_179948
            mem__.req_cmd.bits.addr := tl.acquire.bits.addr_block
            mem__.req_cmd.bits.rw := acq_has_data
            tag_out := T_179948
            addr_out := tl.acquire.bits.addr_block
            has_data := acq_has_data
    when active_out : 
      node T_179952 = eq(cmd_sent_out, UInt<1>(0))
      mem__.req_cmd.valid := T_179952
      node T_179953 = and(mem__.req_cmd.ready, mem__.req_cmd.valid)
      node T_179954 = or(cmd_sent_out, T_179953)
      cmd_sent_out := T_179954
      
      
      node T_179955 = eq(tl_done_out, UInt<1>(0))
      node T_179956 = and(has_data, T_179955)
      when T_179956 : when data_from_rel : 
          tl.release.ready := mem__.req_data.ready
          mem__.req_data.valid := tl.release.valid
        else : 
          
          tl.acquire.ready := mem__.req_data.ready
          mem__.req_data.valid := tl.acquire.valid
      when tl_wrap_out : tl_done_out := UInt<1>(1)
      
      node T_179957 = and(tl_done_out, make_grant_ack)
      when T_179957 : 
        gnt_arb.in[1].valid := UInt<1>(1)
        when gnt_arb.in[1].ready : make_grant_ack := UInt<1>(0)
      
      
      node T_179958 = eq(has_data, UInt<1>(0))
      node T_179959 = or(T_179958, tl_done_out)
      node T_179960 = and(cmd_sent_out, T_179959)
      node T_179961 = eq(make_grant_ack, UInt<1>(0))
      node T_179962 = and(T_179960, T_179961)
      when T_179962 : active_out := UInt<1>(0)
    reg active_in : UInt<1>
    onreset active_in := UInt<1>(0)
    node T_179963 = and(tl.grant.ready, tl.grant.valid)
    wire T_179964 : UInt<3>[1]
    T_179964[0] := UInt<3>(5)
    node T_179965 = eq(T_179964[0], tl.grant.bits.g_type)
    node T_179966 = or(UInt<1>(0), T_179965)
    node T_179967 = eq(T_179862[0], tl.grant.bits.g_type)
    node T_179968 = or(UInt<1>(0), T_179967)
    wire T_179969 : UInt<1>
    T_179969 := T_179968
    when tl.grant.bits.is_builtin_type : T_179969 := T_179966
    node T_179970 = and(UInt<1>(1), T_179969)
    node T_179971 = and(T_179963, T_179970)
    reg tl_cnt_in : UInt<2>
    onreset tl_cnt_in := UInt<2>(0)
    when T_179971 : 
      node T_179972 = eq(tl_cnt_in, UInt<2>(3))
      node T_179973 = and(UInt<1>(0), T_179972)
      node T_179974 = addw(tl_cnt_in, UInt<1>(1))
      wire T_179975 : UInt<2>
      T_179975 := T_179974
      when T_179973 : T_179975 := UInt<1>(0)
      tl_cnt_in := T_179975
    node tl_wrap_in = and(T_179971, T_179972)
    reg tag_in : UInt<5>
    gnt_arb.in[0].valid := mem__.resp.valid
    mem__.resp.ready := gnt_arb.in[0].ready
    node T_179976 = bits(mem__.resp.bits.tag, 3, 3)
    node T_179977 = bit(mem__.resp.bits.tag, 0)
    node T_179978 = bit(mem__.resp.bits.tag, 0)
    wire T_179979 : UInt<1>
    T_179979 := UInt<1>(0)
    when T_179978 : T_179979 := UInt<3>(5)
    node T_179980 = dshr(mem__.resp.bits.tag, UInt<1>(1))
    wire T_179981 : UInt<3>[3]
    T_179981[0] := UInt<3>(0)
    T_179981[1] := UInt<3>(1)
    T_179981[2] := UInt<3>(2)
    wire T_179982 : UInt<0>[1]
    T_179982[0] := UInt<0>(0)
    wire T_179983 : UInt<2>[2]
    T_179983[0] := UInt<2>(1)
    T_179983[1] := UInt<2>(2)
    wire T_179984 : UInt<2>[2]
    T_179984[0] := UInt<2>(1)
    T_179984[1] := UInt<2>(2)
    wire T_179985 : UInt<2>[1]
    T_179985[0] := UInt<2>(2)
    wire T_179986 : UInt<3>[3]
    T_179986[0] := UInt<3>(0)
    T_179986[1] := UInt<3>(1)
    T_179986[2] := UInt<3>(2)
    wire T_179987 : UInt<0>[1]
    T_179987[0] := UInt<0>(0)
    wire T_179988 : UInt<2>[2]
    T_179988[0] := UInt<2>(1)
    T_179988[1] := UInt<2>(2)
    wire T_179989 : UInt<2>[2]
    T_179989[0] := UInt<2>(1)
    T_179989[1] := UInt<2>(2)
    wire T_179990 : UInt<2>[1]
    T_179990[0] := UInt<2>(2)
    wire T_179991 : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}
    T_179991.client_id := T_179976
    T_179991.is_builtin_type := T_179977
    T_179991.g_type := T_179979
    T_179991.client_xact_id := T_179980
    T_179991.manager_xact_id := UInt<1>(0)
    T_179991.addr_beat := tl_cnt_in
    T_179991.data := mem__.resp.bits.data
    gnt_arb.in[0].bits := T_179991
  module HellaFlowQueue : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output count : UInt<5>
    
    wire do_flow : UInt<1>
    node T_179992 = and(enq.ready, enq.valid)
    node T_179993 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_179992, T_179993)
    node T_179994 = and(deq.ready, deq.valid)
    node T_179995 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_179994, T_179995)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    reg enq_ptr : UInt<4>
    onreset enq_ptr := UInt<4>(0)
    when do_enq : 
      node T_179996 = eq(enq_ptr, UInt<4>(15))
      node T_179997 = and(UInt<1>(0), T_179996)
      node T_179998 = addw(enq_ptr, UInt<1>(1))
      wire T_179999 : UInt<4>
      T_179999 := T_179998
      when T_179997 : T_179999 := UInt<1>(0)
      enq_ptr := T_179999
    node T_180000 = and(do_enq, T_179996)
    reg deq_ptr : UInt<4>
    onreset deq_ptr := UInt<4>(0)
    when do_deq : 
      node T_180001 = eq(deq_ptr, UInt<4>(15))
      node T_180002 = and(UInt<1>(0), T_180001)
      node T_180003 = addw(deq_ptr, UInt<1>(1))
      wire T_180004 : UInt<4>
      T_180004 := T_180003
      when T_180002 : T_180004 := UInt<1>(0)
      deq_ptr := T_180004
    node deq_done = and(do_deq, T_180001)
    
    node T_180005 = neq(do_enq, do_deq)
    when T_180005 : maybe_full := do_enq
    node ptr_match = eq(enq_ptr, deq_ptr)
    node T_180006 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180006)
    node full = and(ptr_match, maybe_full)
    node T_180007 = subw(enq_ptr, deq_ptr)
    node T_180008 = geq(T_180007, UInt<2>(2))
    node atLeastTwo = or(full, T_180008)
    node T_180009 = and(empty, deq.ready)
    do_flow := T_180009
    cmem T_180010 : {data : UInt<128>}[16]
    when do_enq : 
      accessor T_180011 = T_180010[enq_ptr]
      T_180011 := enq.bits
    node T_180012 = eq(deq.valid, UInt<1>(0))
    node T_180013 = eq(empty, UInt<1>(0))
    node T_180014 = and(T_180012, T_180013)
    node T_180015 = or(atLeastTwo, T_180014)
    node ren = and(deq.ready, T_180015)
    node T_180016 = addw(deq_ptr, UInt<1>(1))
    wire T_180017 : UInt<4>
    T_180017 := T_180016
    when deq_done : T_180017 := UInt<1>(0)
    wire raddr : UInt<4>
    raddr := deq_ptr
    when deq.valid : raddr := T_180017
    reg ram_out_valid : UInt<1>
    ram_out_valid := ren
    wire T_180018 : UInt<1>
    T_180018 := ram_out_valid
    when empty : T_180018 := enq.valid
    deq.valid := T_180018
    node T_180019 = eq(full, UInt<1>(0))
    enq.ready := T_180019
    reg T_180020 : UInt<4>
    when ren : T_180020 := raddr
    accessor T_180021 = T_180010[T_180020]
    wire T_180022 : {data : UInt<128>}
    T_180022 := T_180021
    when empty : T_180022 := enq.bits
    deq.bits := T_180022
  module Queue_122517 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output count : UInt<1>
    
    cmem ram : {data : UInt<128>}[1]
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(UInt<1>(0), UInt<1>(0))
    node T_180023 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180023)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_180024 = and(enq.ready, enq.valid)
    node T_180025 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180024, T_180025)
    node T_180026 = and(deq.ready, deq.valid)
    node T_180027 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180026, T_180027)
    when do_enq : 
      accessor T_180028 = ram[UInt<1>(0)]
      T_180028 := enq.bits
    when do_deq : skip
    
    node T_180029 = neq(do_enq, do_deq)
    when T_180029 : maybe_full := do_enq
    node T_180030 = eq(empty, UInt<1>(0))
    node T_180031 = and(UInt<1>(0), enq.valid)
    node T_180032 = or(T_180030, T_180031)
    deq.valid := T_180032
    node T_180033 = eq(full, UInt<1>(0))
    node T_180034 = and(UInt<1>(1), deq.ready)
    node T_180035 = or(T_180033, T_180034)
    enq.ready := T_180035
    accessor T_180036 = ram[UInt<1>(0)]
    wire T_180037 : {data : UInt<128>}
    T_180037 := T_180036
    when maybe_flow : T_180037 := enq.bits
    deq.bits := T_180037
    node ptr_diff = subw(UInt<1>(0), UInt<1>(0))
    node T_180038 = and(maybe_full, ptr_match)
    node T_180039 = cat(T_180038, ptr_diff)
    count := T_180039
  module HellaQueue : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output count : UInt<5>
    
    inst fq of HellaFlowQueue
    enq <> fq.enq
    inst T_180040 of Queue_122517
    T_180040.enq.valid := fq.deq.valid
    T_180040.enq.bits := fq.deq.bits
    fq.deq.ready := T_180040.enq.ready
    deq <> T_180040.deq
  module HellaFlowQueue_122630 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<5>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<5>}}
    output count : UInt<5>
    
    wire do_flow : UInt<1>
    node T_180041 = and(enq.ready, enq.valid)
    node T_180042 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180041, T_180042)
    node T_180043 = and(deq.ready, deq.valid)
    node T_180044 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180043, T_180044)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    reg enq_ptr : UInt<4>
    onreset enq_ptr := UInt<4>(0)
    when do_enq : 
      node T_180045 = eq(enq_ptr, UInt<4>(15))
      node T_180046 = and(UInt<1>(0), T_180045)
      node T_180047 = addw(enq_ptr, UInt<1>(1))
      wire T_180048 : UInt<4>
      T_180048 := T_180047
      when T_180046 : T_180048 := UInt<1>(0)
      enq_ptr := T_180048
    node T_180049 = and(do_enq, T_180045)
    reg deq_ptr : UInt<4>
    onreset deq_ptr := UInt<4>(0)
    when do_deq : 
      node T_180050 = eq(deq_ptr, UInt<4>(15))
      node T_180051 = and(UInt<1>(0), T_180050)
      node T_180052 = addw(deq_ptr, UInt<1>(1))
      wire T_180053 : UInt<4>
      T_180053 := T_180052
      when T_180051 : T_180053 := UInt<1>(0)
      deq_ptr := T_180053
    node deq_done = and(do_deq, T_180050)
    
    node T_180054 = neq(do_enq, do_deq)
    when T_180054 : maybe_full := do_enq
    node ptr_match = eq(enq_ptr, deq_ptr)
    node T_180055 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180055)
    node full = and(ptr_match, maybe_full)
    node T_180056 = subw(enq_ptr, deq_ptr)
    node T_180057 = geq(T_180056, UInt<2>(2))
    node atLeastTwo = or(full, T_180057)
    node T_180058 = and(empty, deq.ready)
    do_flow := T_180058
    cmem T_180059 : {tag : UInt<5>}[16]
    when do_enq : 
      accessor T_180060 = T_180059[enq_ptr]
      T_180060 := enq.bits
    node T_180061 = eq(deq.valid, UInt<1>(0))
    node T_180062 = eq(empty, UInt<1>(0))
    node T_180063 = and(T_180061, T_180062)
    node T_180064 = or(atLeastTwo, T_180063)
    node ren = and(deq.ready, T_180064)
    node T_180065 = addw(deq_ptr, UInt<1>(1))
    wire T_180066 : UInt<4>
    T_180066 := T_180065
    when deq_done : T_180066 := UInt<1>(0)
    wire raddr : UInt<4>
    raddr := deq_ptr
    when deq.valid : raddr := T_180066
    reg ram_out_valid : UInt<1>
    ram_out_valid := ren
    wire T_180067 : UInt<1>
    T_180067 := ram_out_valid
    when empty : T_180067 := enq.valid
    deq.valid := T_180067
    node T_180068 = eq(full, UInt<1>(0))
    enq.ready := T_180068
    reg T_180069 : UInt<4>
    when ren : T_180069 := raddr
    accessor T_180070 = T_180059[T_180069]
    wire T_180071 : {tag : UInt<5>}
    T_180071 := T_180070
    when empty : T_180071 := enq.bits
    deq.bits := T_180071
  module Queue_122695 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<5>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<5>}}
    output count : UInt<1>
    
    cmem ram : {tag : UInt<5>}[1]
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(UInt<1>(0), UInt<1>(0))
    node T_180072 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180072)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_180073 = and(enq.ready, enq.valid)
    node T_180074 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180073, T_180074)
    node T_180075 = and(deq.ready, deq.valid)
    node T_180076 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180075, T_180076)
    when do_enq : 
      accessor T_180077 = ram[UInt<1>(0)]
      T_180077 := enq.bits
    when do_deq : skip
    
    node T_180078 = neq(do_enq, do_deq)
    when T_180078 : maybe_full := do_enq
    node T_180079 = eq(empty, UInt<1>(0))
    node T_180080 = and(UInt<1>(0), enq.valid)
    node T_180081 = or(T_180079, T_180080)
    deq.valid := T_180081
    node T_180082 = eq(full, UInt<1>(0))
    node T_180083 = and(UInt<1>(1), deq.ready)
    node T_180084 = or(T_180082, T_180083)
    enq.ready := T_180084
    accessor T_180085 = ram[UInt<1>(0)]
    wire T_180086 : {tag : UInt<5>}
    T_180086 := T_180085
    when maybe_flow : T_180086 := enq.bits
    deq.bits := T_180086
    node ptr_diff = subw(UInt<1>(0), UInt<1>(0))
    node T_180087 = and(maybe_full, ptr_match)
    node T_180088 = cat(T_180087, ptr_diff)
    count := T_180088
  module HellaQueue_122696 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<5>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {tag : UInt<5>}}
    output count : UInt<5>
    
    inst fq of HellaFlowQueue_122630
    enq <> fq.enq
    inst T_180089 of Queue_122695
    T_180089.enq.valid := fq.deq.valid
    T_180089.enq.bits := fq.deq.bits
    fq.deq.ready := T_180089.enq.ready
    deq <> T_180089.deq
  module MemPipeIOMemIOConverter : 
    input cpu : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    
    wire inc : UInt<1>
    wire dec : UInt<1>
    reg count : UInt<5>
    onreset count := UInt<5>(16)
    node watermark = geq(count, UInt<3>(4))
    
    
    node T_180090 = eq(dec, UInt<1>(0))
    node T_180091 = and(inc, T_180090)
    when T_180091 : 
      node T_180092 = addw(count, UInt<1>(1))
      count := T_180092
    
    
    node T_180093 = eq(inc, UInt<1>(0))
    node T_180094 = and(T_180093, dec)
    when T_180094 : 
      node T_180095 = subw(count, UInt<3>(4))
      count := T_180095
    
    node T_180096 = and(inc, dec)
    when T_180096 : 
      node T_180097 = subw(count, UInt<2>(3))
      count := T_180097
    node cmdq_mask = or(cpu.req_cmd.bits.rw, watermark)
    node T_180098 = and(cpu.req_cmd.valid, cmdq_mask)
    mem__.req_cmd.valid := T_180098
    node T_180099 = and(mem__.req_cmd.ready, cmdq_mask)
    cpu.req_cmd.ready := T_180099
    mem__.req_cmd.bits := cpu.req_cmd.bits
    mem__.req_data <> cpu.req_data
    inst resp_data_q of HellaQueue
    resp_data_q.enq.valid := mem__.resp.valid
    resp_data_q.enq.bits.data := mem__.resp.bits.data
    inst resp_tag_q of HellaQueue_122696
    resp_tag_q.enq.valid := mem__.resp.valid
    resp_tag_q.enq.bits.tag := mem__.resp.bits.tag
    node T_180100 = and(resp_data_q.deq.valid, resp_tag_q.deq.valid)
    cpu.resp.valid := T_180100
    cpu.resp.bits.data := resp_data_q.deq.bits.data
    cpu.resp.bits.tag := resp_tag_q.deq.bits.tag
    resp_data_q.deq.ready := cpu.resp.ready
    resp_tag_q.deq.ready := cpu.resp.ready
    node T_180101 = and(resp_data_q.deq.ready, resp_data_q.deq.valid)
    node T_180102 = and(resp_tag_q.deq.ready, resp_tag_q.deq.valid)
    node T_180103 = and(T_180101, T_180102)
    inc := T_180103
    node T_180104 = and(mem__.req_cmd.ready, mem__.req_cmd.valid)
    node T_180105 = eq(mem__.req_cmd.bits.rw, UInt<1>(0))
    node T_180106 = and(T_180104, T_180105)
    dec := T_180106
  module Queue_122803 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}
    output count : UInt<2>
    
    cmem ram : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}[2]
    reg T_180107 : UInt<1>
    onreset T_180107 := UInt<1>(0)
    reg T_180108 : UInt<1>
    onreset T_180108 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_180107, T_180108)
    node T_180109 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180109)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_180110 = and(enq.ready, enq.valid)
    node T_180111 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180110, T_180111)
    node T_180112 = and(deq.ready, deq.valid)
    node T_180113 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180112, T_180113)
    when do_enq : 
      accessor T_180114 = ram[T_180107]
      T_180114 := enq.bits
      node T_180115 = eq(T_180107, UInt<1>(1))
      node T_180116 = and(UInt<1>(0), T_180115)
      node T_180117 = addw(T_180107, UInt<1>(1))
      wire T_180118 : UInt<1>
      T_180118 := T_180117
      when T_180116 : T_180118 := UInt<1>(0)
      T_180107 := T_180118
    when do_deq : 
      node T_180119 = eq(T_180108, UInt<1>(1))
      node T_180120 = and(UInt<1>(0), T_180119)
      node T_180121 = addw(T_180108, UInt<1>(1))
      wire T_180122 : UInt<1>
      T_180122 := T_180121
      when T_180120 : T_180122 := UInt<1>(0)
      T_180108 := T_180122
    
    node T_180123 = neq(do_enq, do_deq)
    when T_180123 : maybe_full := do_enq
    node T_180124 = eq(empty, UInt<1>(0))
    node T_180125 = and(UInt<1>(0), enq.valid)
    node T_180126 = or(T_180124, T_180125)
    deq.valid := T_180126
    node T_180127 = eq(full, UInt<1>(0))
    node T_180128 = and(UInt<1>(1), deq.ready)
    node T_180129 = or(T_180127, T_180128)
    enq.ready := T_180129
    accessor T_180130 = ram[T_180108]
    wire T_180131 : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}
    T_180131 := T_180130
    when maybe_flow : T_180131 := enq.bits
    deq.bits := T_180131
    node ptr_diff = subw(T_180107, T_180108)
    node T_180132 = and(maybe_full, ptr_match)
    node T_180133 = cat(T_180132, ptr_diff)
    count := T_180133
  module Queue_122884 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}
    output count : UInt<3>
    
    cmem ram : {data : UInt<128>}[4]
    reg T_180134 : UInt<2>
    onreset T_180134 := UInt<2>(0)
    reg T_180135 : UInt<2>
    onreset T_180135 := UInt<2>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_180134, T_180135)
    node T_180136 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180136)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_180137 = and(enq.ready, enq.valid)
    node T_180138 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180137, T_180138)
    node T_180139 = and(deq.ready, deq.valid)
    node T_180140 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180139, T_180140)
    when do_enq : 
      accessor T_180141 = ram[T_180134]
      T_180141 := enq.bits
      node T_180142 = eq(T_180134, UInt<2>(3))
      node T_180143 = and(UInt<1>(0), T_180142)
      node T_180144 = addw(T_180134, UInt<1>(1))
      wire T_180145 : UInt<2>
      T_180145 := T_180144
      when T_180143 : T_180145 := UInt<1>(0)
      T_180134 := T_180145
    when do_deq : 
      node T_180146 = eq(T_180135, UInt<2>(3))
      node T_180147 = and(UInt<1>(0), T_180146)
      node T_180148 = addw(T_180135, UInt<1>(1))
      wire T_180149 : UInt<2>
      T_180149 := T_180148
      when T_180147 : T_180149 := UInt<1>(0)
      T_180135 := T_180149
    
    node T_180150 = neq(do_enq, do_deq)
    when T_180150 : maybe_full := do_enq
    node T_180151 = eq(empty, UInt<1>(0))
    node T_180152 = and(UInt<1>(0), enq.valid)
    node T_180153 = or(T_180151, T_180152)
    deq.valid := T_180153
    node T_180154 = eq(full, UInt<1>(0))
    node T_180155 = and(UInt<1>(1), deq.ready)
    node T_180156 = or(T_180154, T_180155)
    enq.ready := T_180156
    accessor T_180157 = ram[T_180135]
    wire T_180158 : {data : UInt<128>}
    T_180158 := T_180157
    when maybe_flow : T_180158 := enq.bits
    deq.bits := T_180158
    node ptr_diff = subw(T_180134, T_180135)
    node T_180159 = and(maybe_full, ptr_match)
    node T_180160 = cat(T_180159, ptr_diff)
    count := T_180160
  module MemPipeIOTileLinkIOConverter : 
    output tl : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, client_id : UInt<1>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<2>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, client_id : UInt<1>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<1>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<1>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, client_id : UInt<1>}}}
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    
    wire T_180161 : UInt<3>[3]
    T_180161[0] := UInt<3>(0)
    T_180161[1] := UInt<3>(1)
    T_180161[2] := UInt<3>(2)
    wire T_180162 : UInt<0>[1]
    T_180162[0] := UInt<0>(0)
    wire T_180163 : UInt<2>[2]
    T_180163[0] := UInt<2>(1)
    T_180163[1] := UInt<2>(2)
    wire T_180164 : UInt<2>[2]
    T_180164[0] := UInt<2>(1)
    T_180164[1] := UInt<2>(2)
    wire T_180165 : UInt<2>[1]
    T_180165[0] := UInt<2>(2)
    wire T_180166 : UInt<3>[3]
    T_180166[0] := UInt<3>(0)
    T_180166[1] := UInt<3>(1)
    T_180166[2] := UInt<3>(2)
    wire T_180167 : UInt<0>[1]
    T_180167[0] := UInt<0>(0)
    wire T_180168 : UInt<2>[2]
    T_180168[0] := UInt<2>(1)
    T_180168[1] := UInt<2>(2)
    wire T_180169 : UInt<2>[2]
    T_180169[0] := UInt<2>(1)
    T_180169[1] := UInt<2>(2)
    wire T_180170 : UInt<2>[1]
    T_180170[0] := UInt<2>(2)
    wire T_180171 : UInt<3>[3]
    T_180171[0] := UInt<3>(0)
    T_180171[1] := UInt<3>(1)
    T_180171[2] := UInt<3>(2)
    wire T_180172 : UInt<0>[1]
    T_180172[0] := UInt<0>(0)
    wire T_180173 : UInt<2>[2]
    T_180173[0] := UInt<2>(1)
    T_180173[1] := UInt<2>(2)
    wire T_180174 : UInt<2>[2]
    T_180174[0] := UInt<2>(1)
    T_180174[1] := UInt<2>(2)
    wire T_180175 : UInt<2>[1]
    T_180175[0] := UInt<2>(2)
    wire T_180176 : UInt<3>[3]
    T_180176[0] := UInt<3>(0)
    T_180176[1] := UInt<3>(1)
    T_180176[2] := UInt<3>(2)
    wire T_180177 : UInt<0>[1]
    T_180177[0] := UInt<0>(0)
    wire T_180178 : UInt<2>[2]
    T_180178[0] := UInt<2>(1)
    T_180178[1] := UInt<2>(2)
    wire T_180179 : UInt<2>[2]
    T_180179[0] := UInt<2>(1)
    T_180179[1] := UInt<2>(2)
    wire T_180180 : UInt<2>[1]
    T_180180[0] := UInt<2>(2)
    wire T_180181 : UInt<3>[3]
    T_180181[0] := UInt<3>(0)
    T_180181[1] := UInt<3>(1)
    T_180181[2] := UInt<3>(2)
    wire T_180182 : UInt<0>[1]
    T_180182[0] := UInt<0>(0)
    wire T_180183 : UInt<2>[2]
    T_180183[0] := UInt<2>(1)
    T_180183[1] := UInt<2>(2)
    wire T_180184 : UInt<2>[2]
    T_180184[0] := UInt<2>(1)
    T_180184[1] := UInt<2>(2)
    wire T_180185 : UInt<2>[1]
    T_180185[0] := UInt<2>(2)
    wire T_180186 : UInt<3>[3]
    T_180186[0] := UInt<3>(0)
    T_180186[1] := UInt<3>(1)
    T_180186[2] := UInt<3>(2)
    wire T_180187 : UInt<0>[1]
    T_180187[0] := UInt<0>(0)
    wire T_180188 : UInt<2>[2]
    T_180188[0] := UInt<2>(1)
    T_180188[1] := UInt<2>(2)
    wire T_180189 : UInt<2>[2]
    T_180189[0] := UInt<2>(1)
    T_180189[1] := UInt<2>(2)
    wire T_180190 : UInt<2>[1]
    T_180190[0] := UInt<2>(2)
    wire T_180191 : UInt<3>[3]
    T_180191[0] := UInt<3>(0)
    T_180191[1] := UInt<3>(1)
    T_180191[2] := UInt<3>(2)
    wire T_180192 : UInt<0>[1]
    T_180192[0] := UInt<0>(0)
    wire T_180193 : UInt<2>[2]
    T_180193[0] := UInt<2>(1)
    T_180193[1] := UInt<2>(2)
    wire T_180194 : UInt<2>[2]
    T_180194[0] := UInt<2>(1)
    T_180194[1] := UInt<2>(2)
    wire T_180195 : UInt<2>[1]
    T_180195[0] := UInt<2>(2)
    wire T_180196 : UInt<3>[3]
    T_180196[0] := UInt<3>(0)
    T_180196[1] := UInt<3>(1)
    T_180196[2] := UInt<3>(2)
    wire T_180197 : UInt<0>[1]
    T_180197[0] := UInt<0>(0)
    wire T_180198 : UInt<2>[2]
    T_180198[0] := UInt<2>(1)
    T_180198[1] := UInt<2>(2)
    wire T_180199 : UInt<2>[2]
    T_180199[0] := UInt<2>(1)
    T_180199[1] := UInt<2>(2)
    wire T_180200 : UInt<2>[1]
    T_180200[0] := UInt<2>(2)
    wire T_180201 : UInt<3>[3]
    T_180201[0] := UInt<3>(0)
    T_180201[1] := UInt<3>(1)
    T_180201[2] := UInt<3>(2)
    wire T_180202 : UInt<0>[1]
    T_180202[0] := UInt<0>(0)
    wire T_180203 : UInt<2>[2]
    T_180203[0] := UInt<2>(1)
    T_180203[1] := UInt<2>(2)
    wire T_180204 : UInt<2>[2]
    T_180204[0] := UInt<2>(1)
    T_180204[1] := UInt<2>(2)
    wire T_180205 : UInt<2>[1]
    T_180205[0] := UInt<2>(2)
    wire T_180206 : UInt<3>[3]
    T_180206[0] := UInt<3>(0)
    T_180206[1] := UInt<3>(1)
    T_180206[2] := UInt<3>(2)
    wire T_180207 : UInt<0>[1]
    T_180207[0] := UInt<0>(0)
    wire T_180208 : UInt<2>[2]
    T_180208[0] := UInt<2>(1)
    T_180208[1] := UInt<2>(2)
    wire T_180209 : UInt<2>[2]
    T_180209[0] := UInt<2>(1)
    T_180209[1] := UInt<2>(2)
    wire T_180210 : UInt<2>[1]
    T_180210[0] := UInt<2>(2)
    wire T_180211 : UInt<3>[3]
    T_180211[0] := UInt<3>(0)
    T_180211[1] := UInt<3>(1)
    T_180211[2] := UInt<3>(2)
    wire T_180212 : UInt<0>[1]
    T_180212[0] := UInt<0>(0)
    wire T_180213 : UInt<2>[2]
    T_180213[0] := UInt<2>(1)
    T_180213[1] := UInt<2>(2)
    wire T_180214 : UInt<2>[2]
    T_180214[0] := UInt<2>(1)
    T_180214[1] := UInt<2>(2)
    wire T_180215 : UInt<2>[1]
    T_180215[0] := UInt<2>(2)
    inst a of MemIOTileLinkIOConverter
    inst b of MemPipeIOMemIOConverter
    a.tl <> tl
    inst T_180216 of Queue_122803
    T_180216.enq.valid := a.mem__.req_cmd.valid
    T_180216.enq.bits := a.mem__.req_cmd.bits
    a.mem__.req_cmd.ready := T_180216.enq.ready
    b.cpu.req_cmd <> T_180216.deq
    inst T_180217 of Queue_122884
    T_180217.enq.valid := a.mem__.req_data.valid
    T_180217.enq.bits := a.mem__.req_data.bits
    a.mem__.req_data.ready := T_180217.enq.ready
    b.cpu.req_data <> T_180217.deq
    a.mem__.resp <> b.cpu.resp
    b.mem__ <> mem__
  module MemIOArbiter : 
    input inner : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    output outer : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    
    wire inner : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    inner[0] := T_180218
    inner[0] <> outer
  module MemSerdes : 
    input wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    output narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}
    
    node T_180219 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw)
    node T_180220 = cat(wide.req_cmd.bits.addr, T_180219)
    reg out_buf : UInt
    reg in_buf : UInt
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    reg send_cnt : UInt<3>
    onreset send_cnt := UInt<3>(0)
    reg data_send_cnt : UInt<2>
    onreset data_send_cnt := UInt<2>(0)
    node T_180221 = eq(send_cnt, UInt<1>(1))
    node adone = and(narrow.req.ready, T_180221)
    node T_180222 = eq(send_cnt, UInt<3>(7))
    node ddone = and(narrow.req.ready, T_180222)
    
    node T_180223 = and(narrow.req.valid, narrow.req.ready)
    when T_180223 : 
      node T_180224 = addw(send_cnt, UInt<1>(1))
      send_cnt := T_180224
      node T_180225 = dshr(out_buf, UInt<5>(16))
      out_buf := T_180225
    
    node T_180226 = and(wide.req_cmd.valid, wide.req_cmd.ready)
    when T_180226 : 
      node T_180227 = cat(wide.req_cmd.bits.tag, wide.req_cmd.bits.rw)
      node T_180228 = cat(wide.req_cmd.bits.addr, T_180227)
      out_buf := T_180228
    
    node T_180229 = and(wide.req_data.valid, wide.req_data.ready)
    when T_180229 : out_buf := wide.req_data.bits.data
    node T_180230 = eq(state, UInt<3>(0))
    wide.req_cmd.ready := T_180230
    node T_180231 = eq(state, UInt<3>(3))
    wide.req_data.ready := T_180231
    node T_180232 = eq(state, UInt<3>(1))
    node T_180233 = eq(state, UInt<3>(2))
    node T_180234 = or(T_180232, T_180233)
    node T_180235 = eq(state, UInt<3>(4))
    node T_180236 = or(T_180234, T_180235)
    narrow.req.valid := T_180236
    narrow.req.bits := out_buf
    
    
    node T_180237 = eq(state, UInt<3>(0))
    node T_180238 = and(T_180237, wide.req_cmd.valid)
    when T_180238 : 
      wire T_180239 : UInt<3>
      T_180239 := UInt<3>(1)
      when wide.req_cmd.bits.rw : T_180239 := UInt<3>(2)
      state := T_180239
    
    
    node T_180240 = eq(state, UInt<3>(1))
    node T_180241 = and(T_180240, adone)
    when T_180241 : 
      state := UInt<3>(0)
      send_cnt := UInt<1>(0)
    
    
    node T_180242 = eq(state, UInt<3>(2))
    node T_180243 = and(T_180242, adone)
    when T_180243 : 
      state := UInt<3>(3)
      send_cnt := UInt<1>(0)
    
    
    node T_180244 = eq(state, UInt<3>(3))
    node T_180245 = and(T_180244, wide.req_data.valid)
    when T_180245 : state := UInt<3>(4)
    
    
    node T_180246 = eq(state, UInt<3>(4))
    node T_180247 = and(T_180246, ddone)
    when T_180247 : 
      node T_180248 = addw(data_send_cnt, UInt<1>(1))
      data_send_cnt := T_180248
      node T_180249 = eq(data_send_cnt, UInt<2>(3))
      wire T_180250 : UInt<3>
      T_180250 := UInt<3>(3)
      when T_180249 : T_180250 := UInt<3>(0)
      state := T_180250
      send_cnt := UInt<1>(0)
    reg recv_cnt : UInt<4>
    onreset recv_cnt := UInt<4>(0)
    reg data_recv_cnt : UInt<2>
    onreset data_recv_cnt := UInt<2>(0)
    reg resp_val : UInt<1>
    onreset resp_val := UInt<1>(0)
    resp_val := UInt<1>(0)
    when narrow.resp.valid : 
      node T_180251 = addw(recv_cnt, UInt<1>(1))
      recv_cnt := T_180251
      
      node T_180252 = eq(recv_cnt, UInt<4>(8))
      when T_180252 : 
        recv_cnt := UInt<1>(0)
        node T_180253 = addw(data_recv_cnt, UInt<1>(1))
        data_recv_cnt := T_180253
        resp_val := UInt<1>(1)
      node T_180254 = bits(in_buf, 143, 16)
      node T_180255 = cat(narrow.resp.bits, T_180254)
      in_buf := T_180255
    wide.resp.valid := resp_val
    wire T_180256 : {data : UInt<128>, tag : UInt<5>}
    node T_180257 = bits(in_buf, 4, 0)
    T_180256.tag := T_180257
    node T_180258 = bits(in_buf, 132, 5)
    T_180256.data := T_180258
    wide.resp.bits := T_180256
  module OuterMemorySystem : 
    input tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1]
    input tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1]
    input htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    input incoherent : UInt<1>[1]
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    output mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}
    input mem_backup_en : UInt<1>
    
    wire T_180259 : UInt<3>[3]
    T_180259[0] := UInt<3>(0)
    T_180259[1] := UInt<3>(1)
    T_180259[2] := UInt<3>(2)
    wire T_180260 : UInt<2>[2]
    T_180260[0] := UInt<2>(0)
    T_180260[1] := UInt<2>(1)
    wire T_180261 : UInt<2>[3]
    T_180261[0] := UInt<2>(1)
    T_180261[1] := UInt<2>(2)
    T_180261[2] := UInt<2>(3)
    wire T_180262 : UInt<2>[2]
    T_180262[0] := UInt<2>(2)
    T_180262[1] := UInt<2>(3)
    wire T_180263 : UInt<2>[1]
    T_180263[0] := UInt<2>(3)
    wire T_180264 : UInt<3>[3]
    T_180264[0] := UInt<3>(0)
    T_180264[1] := UInt<3>(1)
    T_180264[2] := UInt<3>(2)
    wire T_180265 : UInt<2>[2]
    T_180265[0] := UInt<2>(0)
    T_180265[1] := UInt<2>(1)
    wire T_180266 : UInt<2>[3]
    T_180266[0] := UInt<2>(1)
    T_180266[1] := UInt<2>(2)
    T_180266[2] := UInt<2>(3)
    wire T_180267 : UInt<2>[2]
    T_180267[0] := UInt<2>(2)
    T_180267[1] := UInt<2>(3)
    wire T_180268 : UInt<2>[1]
    T_180268[0] := UInt<2>(3)
    wire T_180269 : UInt<3>[3]
    T_180269[0] := UInt<3>(0)
    T_180269[1] := UInt<3>(1)
    T_180269[2] := UInt<3>(2)
    wire T_180270 : UInt<2>[2]
    T_180270[0] := UInt<2>(0)
    T_180270[1] := UInt<2>(1)
    wire T_180271 : UInt<2>[3]
    T_180271[0] := UInt<2>(1)
    T_180271[1] := UInt<2>(2)
    T_180271[2] := UInt<2>(3)
    wire T_180272 : UInt<2>[2]
    T_180272[0] := UInt<2>(2)
    T_180272[1] := UInt<2>(3)
    wire T_180273 : UInt<2>[1]
    T_180273[0] := UInt<2>(3)
    wire T_180274 : UInt<3>[3]
    T_180274[0] := UInt<3>(0)
    T_180274[1] := UInt<3>(1)
    T_180274[2] := UInt<3>(2)
    wire T_180275 : UInt<2>[2]
    T_180275[0] := UInt<2>(0)
    T_180275[1] := UInt<2>(1)
    wire T_180276 : UInt<2>[3]
    T_180276[0] := UInt<2>(1)
    T_180276[1] := UInt<2>(2)
    T_180276[2] := UInt<2>(3)
    wire T_180277 : UInt<2>[2]
    T_180277[0] := UInt<2>(2)
    T_180277[1] := UInt<2>(3)
    wire T_180278 : UInt<2>[1]
    T_180278[0] := UInt<2>(3)
    wire T_180279 : UInt<3>[3]
    T_180279[0] := UInt<3>(0)
    T_180279[1] := UInt<3>(1)
    T_180279[2] := UInt<3>(2)
    wire T_180280 : UInt<2>[2]
    T_180280[0] := UInt<2>(0)
    T_180280[1] := UInt<2>(1)
    wire T_180281 : UInt<2>[3]
    T_180281[0] := UInt<2>(1)
    T_180281[1] := UInt<2>(2)
    T_180281[2] := UInt<2>(3)
    wire T_180282 : UInt<2>[2]
    T_180282[0] := UInt<2>(2)
    T_180282[1] := UInt<2>(3)
    wire T_180283 : UInt<2>[1]
    T_180283[0] := UInt<2>(3)
    wire T_180284 : UInt<3>[3]
    T_180284[0] := UInt<3>(0)
    T_180284[1] := UInt<3>(1)
    T_180284[2] := UInt<3>(2)
    wire T_180285 : UInt<2>[2]
    T_180285[0] := UInt<2>(0)
    T_180285[1] := UInt<2>(1)
    wire T_180286 : UInt<2>[3]
    T_180286[0] := UInt<2>(1)
    T_180286[1] := UInt<2>(2)
    T_180286[2] := UInt<2>(3)
    wire T_180287 : UInt<2>[2]
    T_180287[0] := UInt<2>(2)
    T_180287[1] := UInt<2>(3)
    wire T_180288 : UInt<2>[1]
    T_180288[0] := UInt<2>(3)
    wire T_180289 : UInt<3>[3]
    T_180289[0] := UInt<3>(0)
    T_180289[1] := UInt<3>(1)
    T_180289[2] := UInt<3>(2)
    wire T_180290 : UInt<2>[2]
    T_180290[0] := UInt<2>(0)
    T_180290[1] := UInt<2>(1)
    wire T_180291 : UInt<2>[3]
    T_180291[0] := UInt<2>(1)
    T_180291[1] := UInt<2>(2)
    T_180291[2] := UInt<2>(3)
    wire T_180292 : UInt<2>[2]
    T_180292[0] := UInt<2>(2)
    T_180292[1] := UInt<2>(3)
    wire T_180293 : UInt<2>[1]
    T_180293[0] := UInt<2>(3)
    wire T_180294 : UInt<3>[3]
    T_180294[0] := UInt<3>(0)
    T_180294[1] := UInt<3>(1)
    T_180294[2] := UInt<3>(2)
    wire T_180295 : UInt<2>[2]
    T_180295[0] := UInt<2>(0)
    T_180295[1] := UInt<2>(1)
    wire T_180296 : UInt<2>[3]
    T_180296[0] := UInt<2>(1)
    T_180296[1] := UInt<2>(2)
    T_180296[2] := UInt<2>(3)
    wire T_180297 : UInt<2>[2]
    T_180297[0] := UInt<2>(2)
    T_180297[1] := UInt<2>(3)
    wire T_180298 : UInt<2>[1]
    T_180298[0] := UInt<2>(3)
    wire T_180299 : UInt<3>[3]
    T_180299[0] := UInt<3>(0)
    T_180299[1] := UInt<3>(1)
    T_180299[2] := UInt<3>(2)
    wire T_180300 : UInt<2>[2]
    T_180300[0] := UInt<2>(0)
    T_180300[1] := UInt<2>(1)
    wire T_180301 : UInt<2>[3]
    T_180301[0] := UInt<2>(1)
    T_180301[1] := UInt<2>(2)
    T_180301[2] := UInt<2>(3)
    wire T_180302 : UInt<2>[2]
    T_180302[0] := UInt<2>(2)
    T_180302[1] := UInt<2>(3)
    wire T_180303 : UInt<2>[1]
    T_180303[0] := UInt<2>(3)
    wire T_180304 : UInt<3>[3]
    T_180304[0] := UInt<3>(0)
    T_180304[1] := UInt<3>(1)
    T_180304[2] := UInt<3>(2)
    wire T_180305 : UInt<2>[2]
    T_180305[0] := UInt<2>(0)
    T_180305[1] := UInt<2>(1)
    wire T_180306 : UInt<2>[3]
    T_180306[0] := UInt<2>(1)
    T_180306[1] := UInt<2>(2)
    T_180306[2] := UInt<2>(3)
    wire T_180307 : UInt<2>[2]
    T_180307[0] := UInt<2>(2)
    T_180307[1] := UInt<2>(3)
    wire T_180308 : UInt<2>[1]
    T_180308[0] := UInt<2>(3)
    wire T_180309 : UInt<3>[3]
    T_180309[0] := UInt<3>(0)
    T_180309[1] := UInt<3>(1)
    T_180309[2] := UInt<3>(2)
    wire T_180310 : UInt<2>[2]
    T_180310[0] := UInt<2>(0)
    T_180310[1] := UInt<2>(1)
    wire T_180311 : UInt<2>[3]
    T_180311[0] := UInt<2>(1)
    T_180311[1] := UInt<2>(2)
    T_180311[2] := UInt<2>(3)
    wire T_180312 : UInt<2>[2]
    T_180312[0] := UInt<2>(2)
    T_180312[1] := UInt<2>(3)
    wire T_180313 : UInt<2>[1]
    T_180313[0] := UInt<2>(3)
    wire T_180314 : UInt<3>[3]
    T_180314[0] := UInt<3>(0)
    T_180314[1] := UInt<3>(1)
    T_180314[2] := UInt<3>(2)
    wire T_180315 : UInt<2>[2]
    T_180315[0] := UInt<2>(0)
    T_180315[1] := UInt<2>(1)
    wire T_180316 : UInt<2>[3]
    T_180316[0] := UInt<2>(1)
    T_180316[1] := UInt<2>(2)
    T_180316[2] := UInt<2>(3)
    wire T_180317 : UInt<2>[2]
    T_180317[0] := UInt<2>(2)
    T_180317[1] := UInt<2>(3)
    wire T_180318 : UInt<2>[1]
    T_180318[0] := UInt<2>(3)
    wire T_180319 : UInt<3>[3]
    T_180319[0] := UInt<3>(0)
    T_180319[1] := UInt<3>(1)
    T_180319[2] := UInt<3>(2)
    wire T_180320 : UInt<2>[2]
    T_180320[0] := UInt<2>(0)
    T_180320[1] := UInt<2>(1)
    wire T_180321 : UInt<2>[3]
    T_180321[0] := UInt<2>(1)
    T_180321[1] := UInt<2>(2)
    T_180321[2] := UInt<2>(3)
    wire T_180322 : UInt<2>[2]
    T_180322[0] := UInt<2>(2)
    T_180322[1] := UInt<2>(3)
    wire T_180323 : UInt<2>[1]
    T_180323[0] := UInt<2>(3)
    wire T_180324 : UInt<3>[3]
    T_180324[0] := UInt<3>(0)
    T_180324[1] := UInt<3>(1)
    T_180324[2] := UInt<3>(2)
    wire T_180325 : UInt<2>[2]
    T_180325[0] := UInt<2>(0)
    T_180325[1] := UInt<2>(1)
    wire T_180326 : UInt<2>[3]
    T_180326[0] := UInt<2>(1)
    T_180326[1] := UInt<2>(2)
    T_180326[2] := UInt<2>(3)
    wire T_180327 : UInt<2>[2]
    T_180327[0] := UInt<2>(2)
    T_180327[1] := UInt<2>(3)
    wire T_180328 : UInt<2>[1]
    T_180328[0] := UInt<2>(3)
    wire T_180329 : UInt<3>[3]
    T_180329[0] := UInt<3>(0)
    T_180329[1] := UInt<3>(1)
    T_180329[2] := UInt<3>(2)
    wire T_180330 : UInt<2>[2]
    T_180330[0] := UInt<2>(0)
    T_180330[1] := UInt<2>(1)
    wire T_180331 : UInt<2>[3]
    T_180331[0] := UInt<2>(1)
    T_180331[1] := UInt<2>(2)
    T_180331[2] := UInt<2>(3)
    wire T_180332 : UInt<2>[2]
    T_180332[0] := UInt<2>(2)
    T_180332[1] := UInt<2>(3)
    wire T_180333 : UInt<2>[1]
    T_180333[0] := UInt<2>(3)
    wire T_180334 : UInt<3>[3]
    T_180334[0] := UInt<3>(0)
    T_180334[1] := UInt<3>(1)
    T_180334[2] := UInt<3>(2)
    wire T_180335 : UInt<2>[2]
    T_180335[0] := UInt<2>(0)
    T_180335[1] := UInt<2>(1)
    wire T_180336 : UInt<2>[3]
    T_180336[0] := UInt<2>(1)
    T_180336[1] := UInt<2>(2)
    T_180336[2] := UInt<2>(3)
    wire T_180337 : UInt<2>[2]
    T_180337[0] := UInt<2>(2)
    T_180337[1] := UInt<2>(3)
    wire T_180338 : UInt<2>[1]
    T_180338[0] := UInt<2>(3)
    wire T_180339 : UInt<3>[3]
    T_180339[0] := UInt<3>(0)
    T_180339[1] := UInt<3>(1)
    T_180339[2] := UInt<3>(2)
    wire T_180340 : UInt<2>[2]
    T_180340[0] := UInt<2>(0)
    T_180340[1] := UInt<2>(1)
    wire T_180341 : UInt<2>[3]
    T_180341[0] := UInt<2>(1)
    T_180341[1] := UInt<2>(2)
    T_180341[2] := UInt<2>(3)
    wire T_180342 : UInt<2>[2]
    T_180342[0] := UInt<2>(2)
    T_180342[1] := UInt<2>(3)
    wire T_180343 : UInt<2>[1]
    T_180343[0] := UInt<2>(3)
    wire T_180344 : UInt<3>[3]
    T_180344[0] := UInt<3>(0)
    T_180344[1] := UInt<3>(1)
    T_180344[2] := UInt<3>(2)
    wire T_180345 : UInt<2>[2]
    T_180345[0] := UInt<2>(0)
    T_180345[1] := UInt<2>(1)
    wire T_180346 : UInt<2>[3]
    T_180346[0] := UInt<2>(1)
    T_180346[1] := UInt<2>(2)
    T_180346[2] := UInt<2>(3)
    wire T_180347 : UInt<2>[2]
    T_180347[0] := UInt<2>(2)
    T_180347[1] := UInt<2>(3)
    wire T_180348 : UInt<2>[1]
    T_180348[0] := UInt<2>(3)
    wire tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1]
    tiles_cached[0] := T_180349
    wire T_180350 : UInt<3>[3]
    T_180350[0] := UInt<3>(0)
    T_180350[1] := UInt<3>(1)
    T_180350[2] := UInt<3>(2)
    wire T_180351 : UInt<2>[2]
    T_180351[0] := UInt<2>(0)
    T_180351[1] := UInt<2>(1)
    wire T_180352 : UInt<2>[3]
    T_180352[0] := UInt<2>(1)
    T_180352[1] := UInt<2>(2)
    T_180352[2] := UInt<2>(3)
    wire T_180353 : UInt<2>[2]
    T_180353[0] := UInt<2>(2)
    T_180353[1] := UInt<2>(3)
    wire T_180354 : UInt<2>[1]
    T_180354[0] := UInt<2>(3)
    wire T_180355 : UInt<3>[3]
    T_180355[0] := UInt<3>(0)
    T_180355[1] := UInt<3>(1)
    T_180355[2] := UInt<3>(2)
    wire T_180356 : UInt<2>[2]
    T_180356[0] := UInt<2>(0)
    T_180356[1] := UInt<2>(1)
    wire T_180357 : UInt<2>[3]
    T_180357[0] := UInt<2>(1)
    T_180357[1] := UInt<2>(2)
    T_180357[2] := UInt<2>(3)
    wire T_180358 : UInt<2>[2]
    T_180358[0] := UInt<2>(2)
    T_180358[1] := UInt<2>(3)
    wire T_180359 : UInt<2>[1]
    T_180359[0] := UInt<2>(3)
    wire T_180360 : UInt<3>[3]
    T_180360[0] := UInt<3>(0)
    T_180360[1] := UInt<3>(1)
    T_180360[2] := UInt<3>(2)
    wire T_180361 : UInt<2>[2]
    T_180361[0] := UInt<2>(0)
    T_180361[1] := UInt<2>(1)
    wire T_180362 : UInt<2>[3]
    T_180362[0] := UInt<2>(1)
    T_180362[1] := UInt<2>(2)
    T_180362[2] := UInt<2>(3)
    wire T_180363 : UInt<2>[2]
    T_180363[0] := UInt<2>(2)
    T_180363[1] := UInt<2>(3)
    wire T_180364 : UInt<2>[1]
    T_180364[0] := UInt<2>(3)
    wire T_180365 : UInt<3>[3]
    T_180365[0] := UInt<3>(0)
    T_180365[1] := UInt<3>(1)
    T_180365[2] := UInt<3>(2)
    wire T_180366 : UInt<2>[2]
    T_180366[0] := UInt<2>(0)
    T_180366[1] := UInt<2>(1)
    wire T_180367 : UInt<2>[3]
    T_180367[0] := UInt<2>(1)
    T_180367[1] := UInt<2>(2)
    T_180367[2] := UInt<2>(3)
    wire T_180368 : UInt<2>[2]
    T_180368[0] := UInt<2>(2)
    T_180368[1] := UInt<2>(3)
    wire T_180369 : UInt<2>[1]
    T_180369[0] := UInt<2>(3)
    wire T_180370 : UInt<3>[3]
    T_180370[0] := UInt<3>(0)
    T_180370[1] := UInt<3>(1)
    T_180370[2] := UInt<3>(2)
    wire T_180371 : UInt<2>[2]
    T_180371[0] := UInt<2>(0)
    T_180371[1] := UInt<2>(1)
    wire T_180372 : UInt<2>[3]
    T_180372[0] := UInt<2>(1)
    T_180372[1] := UInt<2>(2)
    T_180372[2] := UInt<2>(3)
    wire T_180373 : UInt<2>[2]
    T_180373[0] := UInt<2>(2)
    T_180373[1] := UInt<2>(3)
    wire T_180374 : UInt<2>[1]
    T_180374[0] := UInt<2>(3)
    wire T_180375 : UInt<3>[3]
    T_180375[0] := UInt<3>(0)
    T_180375[1] := UInt<3>(1)
    T_180375[2] := UInt<3>(2)
    wire T_180376 : UInt<2>[2]
    T_180376[0] := UInt<2>(0)
    T_180376[1] := UInt<2>(1)
    wire T_180377 : UInt<2>[3]
    T_180377[0] := UInt<2>(1)
    T_180377[1] := UInt<2>(2)
    T_180377[2] := UInt<2>(3)
    wire T_180378 : UInt<2>[2]
    T_180378[0] := UInt<2>(2)
    T_180378[1] := UInt<2>(3)
    wire T_180379 : UInt<2>[1]
    T_180379[0] := UInt<2>(3)
    wire T_180380 : UInt<3>[3]
    T_180380[0] := UInt<3>(0)
    T_180380[1] := UInt<3>(1)
    T_180380[2] := UInt<3>(2)
    wire T_180381 : UInt<2>[2]
    T_180381[0] := UInt<2>(0)
    T_180381[1] := UInt<2>(1)
    wire T_180382 : UInt<2>[3]
    T_180382[0] := UInt<2>(1)
    T_180382[1] := UInt<2>(2)
    T_180382[2] := UInt<2>(3)
    wire T_180383 : UInt<2>[2]
    T_180383[0] := UInt<2>(2)
    T_180383[1] := UInt<2>(3)
    wire T_180384 : UInt<2>[1]
    T_180384[0] := UInt<2>(3)
    wire T_180385 : UInt<3>[3]
    T_180385[0] := UInt<3>(0)
    T_180385[1] := UInt<3>(1)
    T_180385[2] := UInt<3>(2)
    wire T_180386 : UInt<2>[2]
    T_180386[0] := UInt<2>(0)
    T_180386[1] := UInt<2>(1)
    wire T_180387 : UInt<2>[3]
    T_180387[0] := UInt<2>(1)
    T_180387[1] := UInt<2>(2)
    T_180387[2] := UInt<2>(3)
    wire T_180388 : UInt<2>[2]
    T_180388[0] := UInt<2>(2)
    T_180388[1] := UInt<2>(3)
    wire T_180389 : UInt<2>[1]
    T_180389[0] := UInt<2>(3)
    wire T_180390 : UInt<3>[3]
    T_180390[0] := UInt<3>(0)
    T_180390[1] := UInt<3>(1)
    T_180390[2] := UInt<3>(2)
    wire T_180391 : UInt<2>[2]
    T_180391[0] := UInt<2>(0)
    T_180391[1] := UInt<2>(1)
    wire T_180392 : UInt<2>[3]
    T_180392[0] := UInt<2>(1)
    T_180392[1] := UInt<2>(2)
    T_180392[2] := UInt<2>(3)
    wire T_180393 : UInt<2>[2]
    T_180393[0] := UInt<2>(2)
    T_180393[1] := UInt<2>(3)
    wire T_180394 : UInt<2>[1]
    T_180394[0] := UInt<2>(3)
    wire T_180395 : UInt<3>[3]
    T_180395[0] := UInt<3>(0)
    T_180395[1] := UInt<3>(1)
    T_180395[2] := UInt<3>(2)
    wire T_180396 : UInt<2>[2]
    T_180396[0] := UInt<2>(0)
    T_180396[1] := UInt<2>(1)
    wire T_180397 : UInt<2>[3]
    T_180397[0] := UInt<2>(1)
    T_180397[1] := UInt<2>(2)
    T_180397[2] := UInt<2>(3)
    wire T_180398 : UInt<2>[2]
    T_180398[0] := UInt<2>(2)
    T_180398[1] := UInt<2>(3)
    wire T_180399 : UInt<2>[1]
    T_180399[0] := UInt<2>(3)
    wire tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1]
    tiles_uncached[0] := T_180400
    wire T_180401 : UInt<3>[3]
    T_180401[0] := UInt<3>(0)
    T_180401[1] := UInt<3>(1)
    T_180401[2] := UInt<3>(2)
    wire T_180402 : UInt<2>[2]
    T_180402[0] := UInt<2>(0)
    T_180402[1] := UInt<2>(1)
    wire T_180403 : UInt<2>[3]
    T_180403[0] := UInt<2>(1)
    T_180403[1] := UInt<2>(2)
    T_180403[2] := UInt<2>(3)
    wire T_180404 : UInt<2>[2]
    T_180404[0] := UInt<2>(2)
    T_180404[1] := UInt<2>(3)
    wire T_180405 : UInt<2>[1]
    T_180405[0] := UInt<2>(3)
    wire T_180406 : UInt<3>[3]
    T_180406[0] := UInt<3>(0)
    T_180406[1] := UInt<3>(1)
    T_180406[2] := UInt<3>(2)
    wire T_180407 : UInt<2>[2]
    T_180407[0] := UInt<2>(0)
    T_180407[1] := UInt<2>(1)
    wire T_180408 : UInt<2>[3]
    T_180408[0] := UInt<2>(1)
    T_180408[1] := UInt<2>(2)
    T_180408[2] := UInt<2>(3)
    wire T_180409 : UInt<2>[2]
    T_180409[0] := UInt<2>(2)
    T_180409[1] := UInt<2>(3)
    wire T_180410 : UInt<2>[1]
    T_180410[0] := UInt<2>(3)
    wire T_180411 : UInt<3>[3]
    T_180411[0] := UInt<3>(0)
    T_180411[1] := UInt<3>(1)
    T_180411[2] := UInt<3>(2)
    wire T_180412 : UInt<2>[2]
    T_180412[0] := UInt<2>(0)
    T_180412[1] := UInt<2>(1)
    wire T_180413 : UInt<2>[3]
    T_180413[0] := UInt<2>(1)
    T_180413[1] := UInt<2>(2)
    T_180413[2] := UInt<2>(3)
    wire T_180414 : UInt<2>[2]
    T_180414[0] := UInt<2>(2)
    T_180414[1] := UInt<2>(3)
    wire T_180415 : UInt<2>[1]
    T_180415[0] := UInt<2>(3)
    wire T_180416 : UInt<3>[3]
    T_180416[0] := UInt<3>(0)
    T_180416[1] := UInt<3>(1)
    T_180416[2] := UInt<3>(2)
    wire T_180417 : UInt<2>[2]
    T_180417[0] := UInt<2>(0)
    T_180417[1] := UInt<2>(1)
    wire T_180418 : UInt<2>[3]
    T_180418[0] := UInt<2>(1)
    T_180418[1] := UInt<2>(2)
    T_180418[2] := UInt<2>(3)
    wire T_180419 : UInt<2>[2]
    T_180419[0] := UInt<2>(2)
    T_180419[1] := UInt<2>(3)
    wire T_180420 : UInt<2>[1]
    T_180420[0] := UInt<2>(3)
    wire T_180421 : UInt<3>[3]
    T_180421[0] := UInt<3>(0)
    T_180421[1] := UInt<3>(1)
    T_180421[2] := UInt<3>(2)
    wire T_180422 : UInt<2>[2]
    T_180422[0] := UInt<2>(0)
    T_180422[1] := UInt<2>(1)
    wire T_180423 : UInt<2>[3]
    T_180423[0] := UInt<2>(1)
    T_180423[1] := UInt<2>(2)
    T_180423[2] := UInt<2>(3)
    wire T_180424 : UInt<2>[2]
    T_180424[0] := UInt<2>(2)
    T_180424[1] := UInt<2>(3)
    wire T_180425 : UInt<2>[1]
    T_180425[0] := UInt<2>(3)
    wire incoherent : UInt<1>[1]
    incoherent[0] := T_180426
    wire mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    mem__[0] := T_180427
    inst T_180428 of ClientTileLinkIOWrapper
    T_180428.in <> tiles_uncached[0]
    inst T_180429 of ClientTileLinkIOWrapper_7600
    T_180429.in <> htif_uncached
    inst l1tol2net of RocketChipTileLinkArbiter
    inst T_180430 of L2HellaCacheBank
    T_180430.incoherent[0] := incoherent[0]
    l1tol2net.clients[0] <> tiles_cached[0]
    l1tol2net.clients[1] <> T_180428.out
    l1tol2net.clients[2] <> T_180429.out
    l1tol2net.managers[0] <> T_180430.inner
    inst T_180431 of RocketChipTileLinkArbiter_120090
    inst T_180432 of MemPipeIOTileLinkIOConverter
    T_180431.clients[0] <> T_180430.outer
    T_180432.tl <> T_180431.managers[0]
    wire T_180433 : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    T_180432.mem__.resp.valid := T_180433.resp.valid
    T_180432.mem__.resp.bits := T_180433.resp.bits
    T_180433.resp.ready := UInt<1>(1)
    T_180433.req_cmd.valid := T_180432.mem__.req_cmd.valid
    T_180433.req_cmd.bits := T_180432.mem__.req_cmd.bits
    T_180432.mem__.req_cmd.ready := T_180433.req_cmd.ready
    T_180433.req_data.valid := T_180432.mem__.req_data.valid
    T_180433.req_data.bits := T_180432.mem__.req_data.bits
    T_180432.mem__.req_data.ready := T_180433.req_data.ready
    inst T_180434 of MemIOArbiter
    inst T_180435 of MemSerdes
    T_180435.wide <> T_180434.outer
    T_180435.narrow <> mem_backup
    wire T_180436 : UInt<1>
    T_180436 := mem__[0].req_cmd.ready
    when mem_backup_en : T_180436 := T_180434.inner[0].req_cmd.ready
    T_180433.req_cmd.ready := T_180436
    node T_180437 = eq(mem_backup_en, UInt<1>(0))
    node T_180438 = and(T_180433.req_cmd.valid, T_180437)
    mem__[0].req_cmd.valid := T_180438
    mem__[0].req_cmd.bits := T_180433.req_cmd.bits
    node T_180439 = and(T_180433.req_cmd.valid, mem_backup_en)
    T_180434.inner[0].req_cmd.valid := T_180439
    T_180434.inner[0].req_cmd.bits := T_180433.req_cmd.bits
    wire T_180440 : UInt<1>
    T_180440 := mem__[0].req_data.ready
    when mem_backup_en : T_180440 := T_180434.inner[0].req_data.ready
    T_180433.req_data.ready := T_180440
    node T_180441 = eq(mem_backup_en, UInt<1>(0))
    node T_180442 = and(T_180433.req_data.valid, T_180441)
    mem__[0].req_data.valid := T_180442
    mem__[0].req_data.bits := T_180433.req_data.bits
    node T_180443 = and(T_180433.req_data.valid, mem_backup_en)
    T_180434.inner[0].req_data.valid := T_180443
    T_180434.inner[0].req_data.bits := T_180433.req_data.bits
    wire T_180444 : UInt<1>
    T_180444 := mem__[0].resp.valid
    when mem_backup_en : T_180444 := T_180434.inner[0].resp.valid
    T_180433.resp.valid := T_180444
    wire T_180445 : {data : UInt<128>, tag : UInt<5>}
    T_180445 := mem__[0].resp.bits
    when mem_backup_en : T_180445 := T_180434.inner[0].resp.bits
    T_180433.resp.bits := T_180445
    node T_180446 = eq(mem_backup_en, UInt<1>(0))
    node T_180447 = and(T_180433.resp.ready, T_180446)
    mem__[0].resp.ready := T_180447
    node T_180448 = and(T_180433.resp.ready, mem_backup_en)
    T_180434.inner[0].resp.ready := T_180448
  module Queue_123297 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output count : UInt<1>
    
    cmem ram : UInt<17>[1]
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(UInt<1>(0), UInt<1>(0))
    node T_180449 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180449)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_180450 = and(enq.ready, enq.valid)
    node T_180451 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180450, T_180451)
    node T_180452 = and(deq.ready, deq.valid)
    node T_180453 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180452, T_180453)
    when do_enq : 
      accessor T_180454 = ram[UInt<1>(0)]
      T_180454 := enq.bits
    when do_deq : skip
    
    node T_180455 = neq(do_enq, do_deq)
    when T_180455 : maybe_full := do_enq
    node T_180456 = eq(empty, UInt<1>(0))
    node T_180457 = and(UInt<1>(0), enq.valid)
    node T_180458 = or(T_180456, T_180457)
    deq.valid := T_180458
    node T_180459 = eq(full, UInt<1>(0))
    node T_180460 = and(UInt<1>(0), deq.ready)
    node T_180461 = or(T_180459, T_180460)
    enq.ready := T_180461
    accessor T_180462 = ram[UInt<1>(0)]
    wire T_180463 : UInt<17>
    T_180463 := T_180462
    when maybe_flow : T_180463 := enq.bits
    deq.bits := T_180463
    node ptr_diff = subw(UInt<1>(0), UInt<1>(0))
    node T_180464 = and(maybe_full, ptr_match)
    node T_180465 = cat(T_180464, ptr_diff)
    count := T_180465
  module Queue_123356 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output count : UInt<1>
    
    cmem ram : UInt<17>[1]
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(UInt<1>(0), UInt<1>(0))
    node T_180466 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_180466)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_180467 = and(enq.ready, enq.valid)
    node T_180468 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_180467, T_180468)
    node T_180469 = and(deq.ready, deq.valid)
    node T_180470 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_180469, T_180470)
    when do_enq : 
      accessor T_180471 = ram[UInt<1>(0)]
      T_180471 := enq.bits
    when do_deq : skip
    
    node T_180472 = neq(do_enq, do_deq)
    when T_180472 : maybe_full := do_enq
    node T_180473 = eq(empty, UInt<1>(0))
    node T_180474 = and(UInt<1>(0), enq.valid)
    node T_180475 = or(T_180473, T_180474)
    deq.valid := T_180475
    node T_180476 = eq(full, UInt<1>(0))
    node T_180477 = and(UInt<1>(0), deq.ready)
    node T_180478 = or(T_180476, T_180477)
    enq.ready := T_180478
    accessor T_180479 = ram[UInt<1>(0)]
    wire T_180480 : UInt<17>
    T_180480 := T_180479
    when maybe_flow : T_180480 := enq.bits
    deq.bits := T_180480
    node ptr_diff = subw(UInt<1>(0), UInt<1>(0))
    node T_180481 = and(maybe_full, ptr_match)
    node T_180482 = cat(T_180481, ptr_diff)
    count := T_180482
  module SlowIO : 
    input out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    input in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}
    output clk_slow : UInt<1>
    input set_divisor : {valid : UInt<1>, bits : UInt<32>}
    output divisor : UInt<32>
    
    reg divisor : UInt<9>
    onreset divisor := UInt<9>(511)
    reg d_shadow : UInt<9>
    onreset d_shadow := UInt<9>(511)
    reg hold : UInt<7>
    onreset hold := UInt<7>(127)
    reg h_shadow : UInt<7>
    onreset h_shadow := UInt<7>(127)
    when set_divisor.valid : 
      node T_180483 = bits(set_divisor.bits, 8, 0)
      d_shadow := T_180483
      node T_180484 = bits(set_divisor.bits, 24, 16)
      h_shadow := T_180484
    node T_180485 = dshl(hold, UInt<5>(16))
    node T_180486 = or(T_180485, divisor)
    divisor := T_180486
    reg count : UInt<9>
    reg myclock : UInt<1>
    node T_180487 = addw(count, UInt<1>(1))
    count := T_180487
    node T_180488 = dshr(divisor, UInt<1>(1))
    node rising = eq(count, T_180488)
    node falling = eq(count, divisor)
    node T_180489 = dshr(divisor, UInt<1>(1))
    node T_180490 = addw(T_180489, hold)
    node held = eq(count, T_180490)
    when falling : 
      divisor := d_shadow
      hold := h_shadow
      count := UInt<1>(0)
      myclock := UInt<1>(0)
    when rising : myclock := UInt<1>(1)
    reg in_slow_rdy : UInt<1>
    onreset in_slow_rdy := UInt<1>(0)
    reg out_slow_val : UInt<1>
    onreset out_slow_val := UInt<1>(0)
    reg out_slow_bits : UInt<17>
    inst fromhost_q of Queue_123297
    node T_180491 = and(in_slow.valid, in_slow_rdy)
    node T_180492 = or(T_180491, reset)
    node T_180493 = and(rising, T_180492)
    fromhost_q.enq.valid := T_180493
    fromhost_q.enq.bits := in_slow.bits
    fromhost_q.deq <> in_fast
    inst tohost_q of Queue_123356
    tohost_q.enq <> out_fast
    node T_180494 = and(rising, out_slow.ready)
    node T_180495 = and(T_180494, out_slow_val)
    tohost_q.deq.ready := T_180495
    when held : 
      in_slow_rdy := fromhost_q.enq.ready
      out_slow_val := tohost_q.deq.valid
      wire T_180496 : UInt<17>
      T_180496 := tohost_q.deq.bits
      when reset : T_180496 := fromhost_q.deq.bits
      out_slow_bits := T_180496
    in_slow.ready := in_slow_rdy
    out_slow.valid := out_slow_val
    out_slow.bits := out_slow_bits
    clk_slow := myclock
  module Uncore : 
    output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    input tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1]
    input tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1]
    input htif : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1]
    output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}
    
    wire mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    mem__[0] := T_180497
    wire T_180498 : UInt<3>[3]
    T_180498[0] := UInt<3>(0)
    T_180498[1] := UInt<3>(1)
    T_180498[2] := UInt<3>(2)
    wire T_180499 : UInt<2>[2]
    T_180499[0] := UInt<2>(0)
    T_180499[1] := UInt<2>(1)
    wire T_180500 : UInt<2>[3]
    T_180500[0] := UInt<2>(1)
    T_180500[1] := UInt<2>(2)
    T_180500[2] := UInt<2>(3)
    wire T_180501 : UInt<2>[2]
    T_180501[0] := UInt<2>(2)
    T_180501[1] := UInt<2>(3)
    wire T_180502 : UInt<2>[1]
    T_180502[0] := UInt<2>(3)
    wire T_180503 : UInt<3>[3]
    T_180503[0] := UInt<3>(0)
    T_180503[1] := UInt<3>(1)
    T_180503[2] := UInt<3>(2)
    wire T_180504 : UInt<2>[2]
    T_180504[0] := UInt<2>(0)
    T_180504[1] := UInt<2>(1)
    wire T_180505 : UInt<2>[3]
    T_180505[0] := UInt<2>(1)
    T_180505[1] := UInt<2>(2)
    T_180505[2] := UInt<2>(3)
    wire T_180506 : UInt<2>[2]
    T_180506[0] := UInt<2>(2)
    T_180506[1] := UInt<2>(3)
    wire T_180507 : UInt<2>[1]
    T_180507[0] := UInt<2>(3)
    wire T_180508 : UInt<3>[3]
    T_180508[0] := UInt<3>(0)
    T_180508[1] := UInt<3>(1)
    T_180508[2] := UInt<3>(2)
    wire T_180509 : UInt<2>[2]
    T_180509[0] := UInt<2>(0)
    T_180509[1] := UInt<2>(1)
    wire T_180510 : UInt<2>[3]
    T_180510[0] := UInt<2>(1)
    T_180510[1] := UInt<2>(2)
    T_180510[2] := UInt<2>(3)
    wire T_180511 : UInt<2>[2]
    T_180511[0] := UInt<2>(2)
    T_180511[1] := UInt<2>(3)
    wire T_180512 : UInt<2>[1]
    T_180512[0] := UInt<2>(3)
    wire T_180513 : UInt<3>[3]
    T_180513[0] := UInt<3>(0)
    T_180513[1] := UInt<3>(1)
    T_180513[2] := UInt<3>(2)
    wire T_180514 : UInt<2>[2]
    T_180514[0] := UInt<2>(0)
    T_180514[1] := UInt<2>(1)
    wire T_180515 : UInt<2>[3]
    T_180515[0] := UInt<2>(1)
    T_180515[1] := UInt<2>(2)
    T_180515[2] := UInt<2>(3)
    wire T_180516 : UInt<2>[2]
    T_180516[0] := UInt<2>(2)
    T_180516[1] := UInt<2>(3)
    wire T_180517 : UInt<2>[1]
    T_180517[0] := UInt<2>(3)
    wire T_180518 : UInt<3>[3]
    T_180518[0] := UInt<3>(0)
    T_180518[1] := UInt<3>(1)
    T_180518[2] := UInt<3>(2)
    wire T_180519 : UInt<2>[2]
    T_180519[0] := UInt<2>(0)
    T_180519[1] := UInt<2>(1)
    wire T_180520 : UInt<2>[3]
    T_180520[0] := UInt<2>(1)
    T_180520[1] := UInt<2>(2)
    T_180520[2] := UInt<2>(3)
    wire T_180521 : UInt<2>[2]
    T_180521[0] := UInt<2>(2)
    T_180521[1] := UInt<2>(3)
    wire T_180522 : UInt<2>[1]
    T_180522[0] := UInt<2>(3)
    wire T_180523 : UInt<3>[3]
    T_180523[0] := UInt<3>(0)
    T_180523[1] := UInt<3>(1)
    T_180523[2] := UInt<3>(2)
    wire T_180524 : UInt<2>[2]
    T_180524[0] := UInt<2>(0)
    T_180524[1] := UInt<2>(1)
    wire T_180525 : UInt<2>[3]
    T_180525[0] := UInt<2>(1)
    T_180525[1] := UInt<2>(2)
    T_180525[2] := UInt<2>(3)
    wire T_180526 : UInt<2>[2]
    T_180526[0] := UInt<2>(2)
    T_180526[1] := UInt<2>(3)
    wire T_180527 : UInt<2>[1]
    T_180527[0] := UInt<2>(3)
    wire T_180528 : UInt<3>[3]
    T_180528[0] := UInt<3>(0)
    T_180528[1] := UInt<3>(1)
    T_180528[2] := UInt<3>(2)
    wire T_180529 : UInt<2>[2]
    T_180529[0] := UInt<2>(0)
    T_180529[1] := UInt<2>(1)
    wire T_180530 : UInt<2>[3]
    T_180530[0] := UInt<2>(1)
    T_180530[1] := UInt<2>(2)
    T_180530[2] := UInt<2>(3)
    wire T_180531 : UInt<2>[2]
    T_180531[0] := UInt<2>(2)
    T_180531[1] := UInt<2>(3)
    wire T_180532 : UInt<2>[1]
    T_180532[0] := UInt<2>(3)
    wire T_180533 : UInt<3>[3]
    T_180533[0] := UInt<3>(0)
    T_180533[1] := UInt<3>(1)
    T_180533[2] := UInt<3>(2)
    wire T_180534 : UInt<2>[2]
    T_180534[0] := UInt<2>(0)
    T_180534[1] := UInt<2>(1)
    wire T_180535 : UInt<2>[3]
    T_180535[0] := UInt<2>(1)
    T_180535[1] := UInt<2>(2)
    T_180535[2] := UInt<2>(3)
    wire T_180536 : UInt<2>[2]
    T_180536[0] := UInt<2>(2)
    T_180536[1] := UInt<2>(3)
    wire T_180537 : UInt<2>[1]
    T_180537[0] := UInt<2>(3)
    wire T_180538 : UInt<3>[3]
    T_180538[0] := UInt<3>(0)
    T_180538[1] := UInt<3>(1)
    T_180538[2] := UInt<3>(2)
    wire T_180539 : UInt<2>[2]
    T_180539[0] := UInt<2>(0)
    T_180539[1] := UInt<2>(1)
    wire T_180540 : UInt<2>[3]
    T_180540[0] := UInt<2>(1)
    T_180540[1] := UInt<2>(2)
    T_180540[2] := UInt<2>(3)
    wire T_180541 : UInt<2>[2]
    T_180541[0] := UInt<2>(2)
    T_180541[1] := UInt<2>(3)
    wire T_180542 : UInt<2>[1]
    T_180542[0] := UInt<2>(3)
    wire T_180543 : UInt<3>[3]
    T_180543[0] := UInt<3>(0)
    T_180543[1] := UInt<3>(1)
    T_180543[2] := UInt<3>(2)
    wire T_180544 : UInt<2>[2]
    T_180544[0] := UInt<2>(0)
    T_180544[1] := UInt<2>(1)
    wire T_180545 : UInt<2>[3]
    T_180545[0] := UInt<2>(1)
    T_180545[1] := UInt<2>(2)
    T_180545[2] := UInt<2>(3)
    wire T_180546 : UInt<2>[2]
    T_180546[0] := UInt<2>(2)
    T_180546[1] := UInt<2>(3)
    wire T_180547 : UInt<2>[1]
    T_180547[0] := UInt<2>(3)
    wire T_180548 : UInt<3>[3]
    T_180548[0] := UInt<3>(0)
    T_180548[1] := UInt<3>(1)
    T_180548[2] := UInt<3>(2)
    wire T_180549 : UInt<2>[2]
    T_180549[0] := UInt<2>(0)
    T_180549[1] := UInt<2>(1)
    wire T_180550 : UInt<2>[3]
    T_180550[0] := UInt<2>(1)
    T_180550[1] := UInt<2>(2)
    T_180550[2] := UInt<2>(3)
    wire T_180551 : UInt<2>[2]
    T_180551[0] := UInt<2>(2)
    T_180551[1] := UInt<2>(3)
    wire T_180552 : UInt<2>[1]
    T_180552[0] := UInt<2>(3)
    wire T_180553 : UInt<3>[3]
    T_180553[0] := UInt<3>(0)
    T_180553[1] := UInt<3>(1)
    T_180553[2] := UInt<3>(2)
    wire T_180554 : UInt<2>[2]
    T_180554[0] := UInt<2>(0)
    T_180554[1] := UInt<2>(1)
    wire T_180555 : UInt<2>[3]
    T_180555[0] := UInt<2>(1)
    T_180555[1] := UInt<2>(2)
    T_180555[2] := UInt<2>(3)
    wire T_180556 : UInt<2>[2]
    T_180556[0] := UInt<2>(2)
    T_180556[1] := UInt<2>(3)
    wire T_180557 : UInt<2>[1]
    T_180557[0] := UInt<2>(3)
    wire T_180558 : UInt<3>[3]
    T_180558[0] := UInt<3>(0)
    T_180558[1] := UInt<3>(1)
    T_180558[2] := UInt<3>(2)
    wire T_180559 : UInt<2>[2]
    T_180559[0] := UInt<2>(0)
    T_180559[1] := UInt<2>(1)
    wire T_180560 : UInt<2>[3]
    T_180560[0] := UInt<2>(1)
    T_180560[1] := UInt<2>(2)
    T_180560[2] := UInt<2>(3)
    wire T_180561 : UInt<2>[2]
    T_180561[0] := UInt<2>(2)
    T_180561[1] := UInt<2>(3)
    wire T_180562 : UInt<2>[1]
    T_180562[0] := UInt<2>(3)
    wire T_180563 : UInt<3>[3]
    T_180563[0] := UInt<3>(0)
    T_180563[1] := UInt<3>(1)
    T_180563[2] := UInt<3>(2)
    wire T_180564 : UInt<2>[2]
    T_180564[0] := UInt<2>(0)
    T_180564[1] := UInt<2>(1)
    wire T_180565 : UInt<2>[3]
    T_180565[0] := UInt<2>(1)
    T_180565[1] := UInt<2>(2)
    T_180565[2] := UInt<2>(3)
    wire T_180566 : UInt<2>[2]
    T_180566[0] := UInt<2>(2)
    T_180566[1] := UInt<2>(3)
    wire T_180567 : UInt<2>[1]
    T_180567[0] := UInt<2>(3)
    wire T_180568 : UInt<3>[3]
    T_180568[0] := UInt<3>(0)
    T_180568[1] := UInt<3>(1)
    T_180568[2] := UInt<3>(2)
    wire T_180569 : UInt<2>[2]
    T_180569[0] := UInt<2>(0)
    T_180569[1] := UInt<2>(1)
    wire T_180570 : UInt<2>[3]
    T_180570[0] := UInt<2>(1)
    T_180570[1] := UInt<2>(2)
    T_180570[2] := UInt<2>(3)
    wire T_180571 : UInt<2>[2]
    T_180571[0] := UInt<2>(2)
    T_180571[1] := UInt<2>(3)
    wire T_180572 : UInt<2>[1]
    T_180572[0] := UInt<2>(3)
    wire T_180573 : UInt<3>[3]
    T_180573[0] := UInt<3>(0)
    T_180573[1] := UInt<3>(1)
    T_180573[2] := UInt<3>(2)
    wire T_180574 : UInt<2>[2]
    T_180574[0] := UInt<2>(0)
    T_180574[1] := UInt<2>(1)
    wire T_180575 : UInt<2>[3]
    T_180575[0] := UInt<2>(1)
    T_180575[1] := UInt<2>(2)
    T_180575[2] := UInt<2>(3)
    wire T_180576 : UInt<2>[2]
    T_180576[0] := UInt<2>(2)
    T_180576[1] := UInt<2>(3)
    wire T_180577 : UInt<2>[1]
    T_180577[0] := UInt<2>(3)
    wire T_180578 : UInt<3>[3]
    T_180578[0] := UInt<3>(0)
    T_180578[1] := UInt<3>(1)
    T_180578[2] := UInt<3>(2)
    wire T_180579 : UInt<2>[2]
    T_180579[0] := UInt<2>(0)
    T_180579[1] := UInt<2>(1)
    wire T_180580 : UInt<2>[3]
    T_180580[0] := UInt<2>(1)
    T_180580[1] := UInt<2>(2)
    T_180580[2] := UInt<2>(3)
    wire T_180581 : UInt<2>[2]
    T_180581[0] := UInt<2>(2)
    T_180581[1] := UInt<2>(3)
    wire T_180582 : UInt<2>[1]
    T_180582[0] := UInt<2>(3)
    wire T_180583 : UInt<3>[3]
    T_180583[0] := UInt<3>(0)
    T_180583[1] := UInt<3>(1)
    T_180583[2] := UInt<3>(2)
    wire T_180584 : UInt<2>[2]
    T_180584[0] := UInt<2>(0)
    T_180584[1] := UInt<2>(1)
    wire T_180585 : UInt<2>[3]
    T_180585[0] := UInt<2>(1)
    T_180585[1] := UInt<2>(2)
    T_180585[2] := UInt<2>(3)
    wire T_180586 : UInt<2>[2]
    T_180586[0] := UInt<2>(2)
    T_180586[1] := UInt<2>(3)
    wire T_180587 : UInt<2>[1]
    T_180587[0] := UInt<2>(3)
    wire tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}[1]
    tiles_cached[0] := T_180588
    wire T_180589 : UInt<3>[3]
    T_180589[0] := UInt<3>(0)
    T_180589[1] := UInt<3>(1)
    T_180589[2] := UInt<3>(2)
    wire T_180590 : UInt<2>[2]
    T_180590[0] := UInt<2>(0)
    T_180590[1] := UInt<2>(1)
    wire T_180591 : UInt<2>[3]
    T_180591[0] := UInt<2>(1)
    T_180591[1] := UInt<2>(2)
    T_180591[2] := UInt<2>(3)
    wire T_180592 : UInt<2>[2]
    T_180592[0] := UInt<2>(2)
    T_180592[1] := UInt<2>(3)
    wire T_180593 : UInt<2>[1]
    T_180593[0] := UInt<2>(3)
    wire T_180594 : UInt<3>[3]
    T_180594[0] := UInt<3>(0)
    T_180594[1] := UInt<3>(1)
    T_180594[2] := UInt<3>(2)
    wire T_180595 : UInt<2>[2]
    T_180595[0] := UInt<2>(0)
    T_180595[1] := UInt<2>(1)
    wire T_180596 : UInt<2>[3]
    T_180596[0] := UInt<2>(1)
    T_180596[1] := UInt<2>(2)
    T_180596[2] := UInt<2>(3)
    wire T_180597 : UInt<2>[2]
    T_180597[0] := UInt<2>(2)
    T_180597[1] := UInt<2>(3)
    wire T_180598 : UInt<2>[1]
    T_180598[0] := UInt<2>(3)
    wire T_180599 : UInt<3>[3]
    T_180599[0] := UInt<3>(0)
    T_180599[1] := UInt<3>(1)
    T_180599[2] := UInt<3>(2)
    wire T_180600 : UInt<2>[2]
    T_180600[0] := UInt<2>(0)
    T_180600[1] := UInt<2>(1)
    wire T_180601 : UInt<2>[3]
    T_180601[0] := UInt<2>(1)
    T_180601[1] := UInt<2>(2)
    T_180601[2] := UInt<2>(3)
    wire T_180602 : UInt<2>[2]
    T_180602[0] := UInt<2>(2)
    T_180602[1] := UInt<2>(3)
    wire T_180603 : UInt<2>[1]
    T_180603[0] := UInt<2>(3)
    wire T_180604 : UInt<3>[3]
    T_180604[0] := UInt<3>(0)
    T_180604[1] := UInt<3>(1)
    T_180604[2] := UInt<3>(2)
    wire T_180605 : UInt<2>[2]
    T_180605[0] := UInt<2>(0)
    T_180605[1] := UInt<2>(1)
    wire T_180606 : UInt<2>[3]
    T_180606[0] := UInt<2>(1)
    T_180606[1] := UInt<2>(2)
    T_180606[2] := UInt<2>(3)
    wire T_180607 : UInt<2>[2]
    T_180607[0] := UInt<2>(2)
    T_180607[1] := UInt<2>(3)
    wire T_180608 : UInt<2>[1]
    T_180608[0] := UInt<2>(3)
    wire T_180609 : UInt<3>[3]
    T_180609[0] := UInt<3>(0)
    T_180609[1] := UInt<3>(1)
    T_180609[2] := UInt<3>(2)
    wire T_180610 : UInt<2>[2]
    T_180610[0] := UInt<2>(0)
    T_180610[1] := UInt<2>(1)
    wire T_180611 : UInt<2>[3]
    T_180611[0] := UInt<2>(1)
    T_180611[1] := UInt<2>(2)
    T_180611[2] := UInt<2>(3)
    wire T_180612 : UInt<2>[2]
    T_180612[0] := UInt<2>(2)
    T_180612[1] := UInt<2>(3)
    wire T_180613 : UInt<2>[1]
    T_180613[0] := UInt<2>(3)
    wire T_180614 : UInt<3>[3]
    T_180614[0] := UInt<3>(0)
    T_180614[1] := UInt<3>(1)
    T_180614[2] := UInt<3>(2)
    wire T_180615 : UInt<2>[2]
    T_180615[0] := UInt<2>(0)
    T_180615[1] := UInt<2>(1)
    wire T_180616 : UInt<2>[3]
    T_180616[0] := UInt<2>(1)
    T_180616[1] := UInt<2>(2)
    T_180616[2] := UInt<2>(3)
    wire T_180617 : UInt<2>[2]
    T_180617[0] := UInt<2>(2)
    T_180617[1] := UInt<2>(3)
    wire T_180618 : UInt<2>[1]
    T_180618[0] := UInt<2>(3)
    wire T_180619 : UInt<3>[3]
    T_180619[0] := UInt<3>(0)
    T_180619[1] := UInt<3>(1)
    T_180619[2] := UInt<3>(2)
    wire T_180620 : UInt<2>[2]
    T_180620[0] := UInt<2>(0)
    T_180620[1] := UInt<2>(1)
    wire T_180621 : UInt<2>[3]
    T_180621[0] := UInt<2>(1)
    T_180621[1] := UInt<2>(2)
    T_180621[2] := UInt<2>(3)
    wire T_180622 : UInt<2>[2]
    T_180622[0] := UInt<2>(2)
    T_180622[1] := UInt<2>(3)
    wire T_180623 : UInt<2>[1]
    T_180623[0] := UInt<2>(3)
    wire T_180624 : UInt<3>[3]
    T_180624[0] := UInt<3>(0)
    T_180624[1] := UInt<3>(1)
    T_180624[2] := UInt<3>(2)
    wire T_180625 : UInt<2>[2]
    T_180625[0] := UInt<2>(0)
    T_180625[1] := UInt<2>(1)
    wire T_180626 : UInt<2>[3]
    T_180626[0] := UInt<2>(1)
    T_180626[1] := UInt<2>(2)
    T_180626[2] := UInt<2>(3)
    wire T_180627 : UInt<2>[2]
    T_180627[0] := UInt<2>(2)
    T_180627[1] := UInt<2>(3)
    wire T_180628 : UInt<2>[1]
    T_180628[0] := UInt<2>(3)
    wire T_180629 : UInt<3>[3]
    T_180629[0] := UInt<3>(0)
    T_180629[1] := UInt<3>(1)
    T_180629[2] := UInt<3>(2)
    wire T_180630 : UInt<2>[2]
    T_180630[0] := UInt<2>(0)
    T_180630[1] := UInt<2>(1)
    wire T_180631 : UInt<2>[3]
    T_180631[0] := UInt<2>(1)
    T_180631[1] := UInt<2>(2)
    T_180631[2] := UInt<2>(3)
    wire T_180632 : UInt<2>[2]
    T_180632[0] := UInt<2>(2)
    T_180632[1] := UInt<2>(3)
    wire T_180633 : UInt<2>[1]
    T_180633[0] := UInt<2>(3)
    wire T_180634 : UInt<3>[3]
    T_180634[0] := UInt<3>(0)
    T_180634[1] := UInt<3>(1)
    T_180634[2] := UInt<3>(2)
    wire T_180635 : UInt<2>[2]
    T_180635[0] := UInt<2>(0)
    T_180635[1] := UInt<2>(1)
    wire T_180636 : UInt<2>[3]
    T_180636[0] := UInt<2>(1)
    T_180636[1] := UInt<2>(2)
    T_180636[2] := UInt<2>(3)
    wire T_180637 : UInt<2>[2]
    T_180637[0] := UInt<2>(2)
    T_180637[1] := UInt<2>(3)
    wire T_180638 : UInt<2>[1]
    T_180638[0] := UInt<2>(3)
    wire tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}[1]
    tiles_uncached[0] := T_180639
    wire htif : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}[1]
    htif[0] := T_180640
    inst htif of HTIF
    inst outmemsys of OuterMemorySystem
    outmemsys.incoherent[0] := htif.cpu[0].reset
    outmemsys.htif_uncached <> htif.mem__
    outmemsys.tiles_uncached[0] <> tiles_uncached[0]
    outmemsys.tiles_cached[0] <> tiles_cached[0]
    host.debug_stats_pcr := htif.host.debug_stats_pcr
    htif.cpu[0] <> htif[0]
    outmemsys.mem__[0] <> mem__[0]
    outmemsys.mem_backup_en := mem_backup_ctrl.en
    inst T_180641 of SlowIO
    node T_180642 = eq(htif.scr.waddr, UInt<6>(63))
    node T_180643 = and(htif.scr.wen, T_180642)
    T_180641.set_divisor.valid := T_180643
    T_180641.set_divisor.bits := htif.scr.wdata
    htif.scr.rdata[63] := T_180641.divisor
    node T_180644 = or(htif.host.out.valid, outmemsys.mem_backup.req.valid)
    T_180641.out_fast.valid := T_180644
    wire T_180645 : UInt<16>
    T_180645 := outmemsys.mem_backup.req.bits
    when htif.host.out.valid : T_180645 := htif.host.out.bits
    node T_180646 = cat(htif.host.out.valid, T_180645)
    T_180641.out_fast.bits := T_180646
    htif.host.out.ready := T_180641.out_fast.ready
    node T_180647 = eq(htif.host.out.valid, UInt<1>(0))
    node T_180648 = and(T_180641.out_fast.ready, T_180647)
    outmemsys.mem_backup.req.ready := T_180648
    node T_180649 = bit(T_180641.out_slow.bits, 16)
    node T_180650 = and(T_180641.out_slow.valid, T_180649)
    host.out.valid := T_180650
    host.out.bits := T_180641.out_slow.bits
    node T_180651 = bit(T_180641.out_slow.bits, 16)
    node T_180652 = eq(T_180651, UInt<1>(0))
    node T_180653 = and(T_180641.out_slow.valid, T_180652)
    mem_backup_ctrl.out_valid := T_180653
    node T_180654 = bit(T_180641.out_slow.bits, 16)
    wire T_180655 : UInt<1>
    T_180655 := mem_backup_ctrl.out_ready
    when T_180654 : T_180655 := host.out.ready
    T_180641.out_slow.ready := T_180655
    node T_180656 = and(mem_backup_ctrl.en, mem_backup_ctrl.in_valid)
    node T_180657 = or(T_180656, host.in.valid)
    T_180641.in_slow.valid := T_180657
    node T_180658 = cat(T_180656, host.in.bits)
    T_180641.in_slow.bits := T_180658
    host.in.ready := T_180641.in_slow.ready
    node T_180659 = bit(T_180641.in_fast.bits, 16)
    node T_180660 = and(T_180641.in_fast.valid, T_180659)
    outmemsys.mem_backup.resp.valid := T_180660
    outmemsys.mem_backup.resp.bits := T_180641.in_fast.bits
    node T_180661 = bit(T_180641.in_fast.bits, 16)
    node T_180662 = eq(T_180661, UInt<1>(0))
    node T_180663 = and(T_180641.in_fast.valid, T_180662)
    htif.host.in.valid := T_180663
    htif.host.in.bits := T_180641.in_fast.bits
    node T_180664 = bit(T_180641.in_fast.bits, 16)
    wire T_180665 : UInt<1>
    T_180665 := htif.host.in.ready
    when T_180664 : T_180665 := UInt<1>(1)
    T_180641.in_fast.ready := T_180665
    host.clk := T_180641.clk_slow
    reg T_180666 : UInt<1>
    T_180666 := host.clk
    node T_180667 = eq(T_180666, UInt<1>(0))
    node T_180668 = and(host.clk, T_180667)
    reg T_180669 : UInt<1>
    T_180669 := T_180668
    host.clk_edge := T_180669
  module BTB : 
    input req : {valid : UInt<1>, bits : {addr : UInt<39>}}
    output resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}
    input btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}
    input bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}
    input ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}
    input invalidate : UInt<1>
    
    reg idxValid : UInt<1>[62]
    cmem idxs : UInt<12>[62]
    cmem idxPages : UInt<3>[62]
    cmem tgts : UInt<12>[62]
    cmem tgtPages : UInt<3>[62]
    cmem pages : UInt<27>[6]
    reg pageValid : UInt<6>
    onreset pageValid := UInt<6>(0)
    accessor T_180670 = idxPages[UInt<1>(0)]
    node T_180671 = dshl(UInt<1>(1), T_180670)
    node T_180672 = bits(T_180671, 5, 0)
    accessor T_180673 = idxPages[UInt<1>(1)]
    node T_180674 = dshl(UInt<1>(1), T_180673)
    node T_180675 = bits(T_180674, 5, 0)
    accessor T_180676 = idxPages[UInt<2>(2)]
    node T_180677 = dshl(UInt<1>(1), T_180676)
    node T_180678 = bits(T_180677, 5, 0)
    accessor T_180679 = idxPages[UInt<2>(3)]
    node T_180680 = dshl(UInt<1>(1), T_180679)
    node T_180681 = bits(T_180680, 5, 0)
    accessor T_180682 = idxPages[UInt<3>(4)]
    node T_180683 = dshl(UInt<1>(1), T_180682)
    node T_180684 = bits(T_180683, 5, 0)
    accessor T_180685 = idxPages[UInt<3>(5)]
    node T_180686 = dshl(UInt<1>(1), T_180685)
    node T_180687 = bits(T_180686, 5, 0)
    accessor T_180688 = idxPages[UInt<3>(6)]
    node T_180689 = dshl(UInt<1>(1), T_180688)
    node T_180690 = bits(T_180689, 5, 0)
    accessor T_180691 = idxPages[UInt<3>(7)]
    node T_180692 = dshl(UInt<1>(1), T_180691)
    node T_180693 = bits(T_180692, 5, 0)
    accessor T_180694 = idxPages[UInt<4>(8)]
    node T_180695 = dshl(UInt<1>(1), T_180694)
    node T_180696 = bits(T_180695, 5, 0)
    accessor T_180697 = idxPages[UInt<4>(9)]
    node T_180698 = dshl(UInt<1>(1), T_180697)
    node T_180699 = bits(T_180698, 5, 0)
    accessor T_180700 = idxPages[UInt<4>(10)]
    node T_180701 = dshl(UInt<1>(1), T_180700)
    node T_180702 = bits(T_180701, 5, 0)
    accessor T_180703 = idxPages[UInt<4>(11)]
    node T_180704 = dshl(UInt<1>(1), T_180703)
    node T_180705 = bits(T_180704, 5, 0)
    accessor T_180706 = idxPages[UInt<4>(12)]
    node T_180707 = dshl(UInt<1>(1), T_180706)
    node T_180708 = bits(T_180707, 5, 0)
    accessor T_180709 = idxPages[UInt<4>(13)]
    node T_180710 = dshl(UInt<1>(1), T_180709)
    node T_180711 = bits(T_180710, 5, 0)
    accessor T_180712 = idxPages[UInt<4>(14)]
    node T_180713 = dshl(UInt<1>(1), T_180712)
    node T_180714 = bits(T_180713, 5, 0)
    accessor T_180715 = idxPages[UInt<4>(15)]
    node T_180716 = dshl(UInt<1>(1), T_180715)
    node T_180717 = bits(T_180716, 5, 0)
    accessor T_180718 = idxPages[UInt<5>(16)]
    node T_180719 = dshl(UInt<1>(1), T_180718)
    node T_180720 = bits(T_180719, 5, 0)
    accessor T_180721 = idxPages[UInt<5>(17)]
    node T_180722 = dshl(UInt<1>(1), T_180721)
    node T_180723 = bits(T_180722, 5, 0)
    accessor T_180724 = idxPages[UInt<5>(18)]
    node T_180725 = dshl(UInt<1>(1), T_180724)
    node T_180726 = bits(T_180725, 5, 0)
    accessor T_180727 = idxPages[UInt<5>(19)]
    node T_180728 = dshl(UInt<1>(1), T_180727)
    node T_180729 = bits(T_180728, 5, 0)
    accessor T_180730 = idxPages[UInt<5>(20)]
    node T_180731 = dshl(UInt<1>(1), T_180730)
    node T_180732 = bits(T_180731, 5, 0)
    accessor T_180733 = idxPages[UInt<5>(21)]
    node T_180734 = dshl(UInt<1>(1), T_180733)
    node T_180735 = bits(T_180734, 5, 0)
    accessor T_180736 = idxPages[UInt<5>(22)]
    node T_180737 = dshl(UInt<1>(1), T_180736)
    node T_180738 = bits(T_180737, 5, 0)
    accessor T_180739 = idxPages[UInt<5>(23)]
    node T_180740 = dshl(UInt<1>(1), T_180739)
    node T_180741 = bits(T_180740, 5, 0)
    accessor T_180742 = idxPages[UInt<5>(24)]
    node T_180743 = dshl(UInt<1>(1), T_180742)
    node T_180744 = bits(T_180743, 5, 0)
    accessor T_180745 = idxPages[UInt<5>(25)]
    node T_180746 = dshl(UInt<1>(1), T_180745)
    node T_180747 = bits(T_180746, 5, 0)
    accessor T_180748 = idxPages[UInt<5>(26)]
    node T_180749 = dshl(UInt<1>(1), T_180748)
    node T_180750 = bits(T_180749, 5, 0)
    accessor T_180751 = idxPages[UInt<5>(27)]
    node T_180752 = dshl(UInt<1>(1), T_180751)
    node T_180753 = bits(T_180752, 5, 0)
    accessor T_180754 = idxPages[UInt<5>(28)]
    node T_180755 = dshl(UInt<1>(1), T_180754)
    node T_180756 = bits(T_180755, 5, 0)
    accessor T_180757 = idxPages[UInt<5>(29)]
    node T_180758 = dshl(UInt<1>(1), T_180757)
    node T_180759 = bits(T_180758, 5, 0)
    accessor T_180760 = idxPages[UInt<5>(30)]
    node T_180761 = dshl(UInt<1>(1), T_180760)
    node T_180762 = bits(T_180761, 5, 0)
    accessor T_180763 = idxPages[UInt<5>(31)]
    node T_180764 = dshl(UInt<1>(1), T_180763)
    node T_180765 = bits(T_180764, 5, 0)
    accessor T_180766 = idxPages[UInt<6>(32)]
    node T_180767 = dshl(UInt<1>(1), T_180766)
    node T_180768 = bits(T_180767, 5, 0)
    accessor T_180769 = idxPages[UInt<6>(33)]
    node T_180770 = dshl(UInt<1>(1), T_180769)
    node T_180771 = bits(T_180770, 5, 0)
    accessor T_180772 = idxPages[UInt<6>(34)]
    node T_180773 = dshl(UInt<1>(1), T_180772)
    node T_180774 = bits(T_180773, 5, 0)
    accessor T_180775 = idxPages[UInt<6>(35)]
    node T_180776 = dshl(UInt<1>(1), T_180775)
    node T_180777 = bits(T_180776, 5, 0)
    accessor T_180778 = idxPages[UInt<6>(36)]
    node T_180779 = dshl(UInt<1>(1), T_180778)
    node T_180780 = bits(T_180779, 5, 0)
    accessor T_180781 = idxPages[UInt<6>(37)]
    node T_180782 = dshl(UInt<1>(1), T_180781)
    node T_180783 = bits(T_180782, 5, 0)
    accessor T_180784 = idxPages[UInt<6>(38)]
    node T_180785 = dshl(UInt<1>(1), T_180784)
    node T_180786 = bits(T_180785, 5, 0)
    accessor T_180787 = idxPages[UInt<6>(39)]
    node T_180788 = dshl(UInt<1>(1), T_180787)
    node T_180789 = bits(T_180788, 5, 0)
    accessor T_180790 = idxPages[UInt<6>(40)]
    node T_180791 = dshl(UInt<1>(1), T_180790)
    node T_180792 = bits(T_180791, 5, 0)
    accessor T_180793 = idxPages[UInt<6>(41)]
    node T_180794 = dshl(UInt<1>(1), T_180793)
    node T_180795 = bits(T_180794, 5, 0)
    accessor T_180796 = idxPages[UInt<6>(42)]
    node T_180797 = dshl(UInt<1>(1), T_180796)
    node T_180798 = bits(T_180797, 5, 0)
    accessor T_180799 = idxPages[UInt<6>(43)]
    node T_180800 = dshl(UInt<1>(1), T_180799)
    node T_180801 = bits(T_180800, 5, 0)
    accessor T_180802 = idxPages[UInt<6>(44)]
    node T_180803 = dshl(UInt<1>(1), T_180802)
    node T_180804 = bits(T_180803, 5, 0)
    accessor T_180805 = idxPages[UInt<6>(45)]
    node T_180806 = dshl(UInt<1>(1), T_180805)
    node T_180807 = bits(T_180806, 5, 0)
    accessor T_180808 = idxPages[UInt<6>(46)]
    node T_180809 = dshl(UInt<1>(1), T_180808)
    node T_180810 = bits(T_180809, 5, 0)
    accessor T_180811 = idxPages[UInt<6>(47)]
    node T_180812 = dshl(UInt<1>(1), T_180811)
    node T_180813 = bits(T_180812, 5, 0)
    accessor T_180814 = idxPages[UInt<6>(48)]
    node T_180815 = dshl(UInt<1>(1), T_180814)
    node T_180816 = bits(T_180815, 5, 0)
    accessor T_180817 = idxPages[UInt<6>(49)]
    node T_180818 = dshl(UInt<1>(1), T_180817)
    node T_180819 = bits(T_180818, 5, 0)
    accessor T_180820 = idxPages[UInt<6>(50)]
    node T_180821 = dshl(UInt<1>(1), T_180820)
    node T_180822 = bits(T_180821, 5, 0)
    accessor T_180823 = idxPages[UInt<6>(51)]
    node T_180824 = dshl(UInt<1>(1), T_180823)
    node T_180825 = bits(T_180824, 5, 0)
    accessor T_180826 = idxPages[UInt<6>(52)]
    node T_180827 = dshl(UInt<1>(1), T_180826)
    node T_180828 = bits(T_180827, 5, 0)
    accessor T_180829 = idxPages[UInt<6>(53)]
    node T_180830 = dshl(UInt<1>(1), T_180829)
    node T_180831 = bits(T_180830, 5, 0)
    accessor T_180832 = idxPages[UInt<6>(54)]
    node T_180833 = dshl(UInt<1>(1), T_180832)
    node T_180834 = bits(T_180833, 5, 0)
    accessor T_180835 = idxPages[UInt<6>(55)]
    node T_180836 = dshl(UInt<1>(1), T_180835)
    node T_180837 = bits(T_180836, 5, 0)
    accessor T_180838 = idxPages[UInt<6>(56)]
    node T_180839 = dshl(UInt<1>(1), T_180838)
    node T_180840 = bits(T_180839, 5, 0)
    accessor T_180841 = idxPages[UInt<6>(57)]
    node T_180842 = dshl(UInt<1>(1), T_180841)
    node T_180843 = bits(T_180842, 5, 0)
    accessor T_180844 = idxPages[UInt<6>(58)]
    node T_180845 = dshl(UInt<1>(1), T_180844)
    node T_180846 = bits(T_180845, 5, 0)
    accessor T_180847 = idxPages[UInt<6>(59)]
    node T_180848 = dshl(UInt<1>(1), T_180847)
    node T_180849 = bits(T_180848, 5, 0)
    accessor T_180850 = idxPages[UInt<6>(60)]
    node T_180851 = dshl(UInt<1>(1), T_180850)
    node T_180852 = bits(T_180851, 5, 0)
    accessor T_180853 = idxPages[UInt<6>(61)]
    node T_180854 = dshl(UInt<1>(1), T_180853)
    node T_180855 = bits(T_180854, 5, 0)
    accessor T_180856 = tgtPages[UInt<1>(0)]
    node T_180857 = dshl(UInt<1>(1), T_180856)
    node T_180858 = bits(T_180857, 5, 0)
    accessor T_180859 = tgtPages[UInt<1>(1)]
    node T_180860 = dshl(UInt<1>(1), T_180859)
    node T_180861 = bits(T_180860, 5, 0)
    accessor T_180862 = tgtPages[UInt<2>(2)]
    node T_180863 = dshl(UInt<1>(1), T_180862)
    node T_180864 = bits(T_180863, 5, 0)
    accessor T_180865 = tgtPages[UInt<2>(3)]
    node T_180866 = dshl(UInt<1>(1), T_180865)
    node T_180867 = bits(T_180866, 5, 0)
    accessor T_180868 = tgtPages[UInt<3>(4)]
    node T_180869 = dshl(UInt<1>(1), T_180868)
    node T_180870 = bits(T_180869, 5, 0)
    accessor T_180871 = tgtPages[UInt<3>(5)]
    node T_180872 = dshl(UInt<1>(1), T_180871)
    node T_180873 = bits(T_180872, 5, 0)
    accessor T_180874 = tgtPages[UInt<3>(6)]
    node T_180875 = dshl(UInt<1>(1), T_180874)
    node T_180876 = bits(T_180875, 5, 0)
    accessor T_180877 = tgtPages[UInt<3>(7)]
    node T_180878 = dshl(UInt<1>(1), T_180877)
    node T_180879 = bits(T_180878, 5, 0)
    accessor T_180880 = tgtPages[UInt<4>(8)]
    node T_180881 = dshl(UInt<1>(1), T_180880)
    node T_180882 = bits(T_180881, 5, 0)
    accessor T_180883 = tgtPages[UInt<4>(9)]
    node T_180884 = dshl(UInt<1>(1), T_180883)
    node T_180885 = bits(T_180884, 5, 0)
    accessor T_180886 = tgtPages[UInt<4>(10)]
    node T_180887 = dshl(UInt<1>(1), T_180886)
    node T_180888 = bits(T_180887, 5, 0)
    accessor T_180889 = tgtPages[UInt<4>(11)]
    node T_180890 = dshl(UInt<1>(1), T_180889)
    node T_180891 = bits(T_180890, 5, 0)
    accessor T_180892 = tgtPages[UInt<4>(12)]
    node T_180893 = dshl(UInt<1>(1), T_180892)
    node T_180894 = bits(T_180893, 5, 0)
    accessor T_180895 = tgtPages[UInt<4>(13)]
    node T_180896 = dshl(UInt<1>(1), T_180895)
    node T_180897 = bits(T_180896, 5, 0)
    accessor T_180898 = tgtPages[UInt<4>(14)]
    node T_180899 = dshl(UInt<1>(1), T_180898)
    node T_180900 = bits(T_180899, 5, 0)
    accessor T_180901 = tgtPages[UInt<4>(15)]
    node T_180902 = dshl(UInt<1>(1), T_180901)
    node T_180903 = bits(T_180902, 5, 0)
    accessor T_180904 = tgtPages[UInt<5>(16)]
    node T_180905 = dshl(UInt<1>(1), T_180904)
    node T_180906 = bits(T_180905, 5, 0)
    accessor T_180907 = tgtPages[UInt<5>(17)]
    node T_180908 = dshl(UInt<1>(1), T_180907)
    node T_180909 = bits(T_180908, 5, 0)
    accessor T_180910 = tgtPages[UInt<5>(18)]
    node T_180911 = dshl(UInt<1>(1), T_180910)
    node T_180912 = bits(T_180911, 5, 0)
    accessor T_180913 = tgtPages[UInt<5>(19)]
    node T_180914 = dshl(UInt<1>(1), T_180913)
    node T_180915 = bits(T_180914, 5, 0)
    accessor T_180916 = tgtPages[UInt<5>(20)]
    node T_180917 = dshl(UInt<1>(1), T_180916)
    node T_180918 = bits(T_180917, 5, 0)
    accessor T_180919 = tgtPages[UInt<5>(21)]
    node T_180920 = dshl(UInt<1>(1), T_180919)
    node T_180921 = bits(T_180920, 5, 0)
    accessor T_180922 = tgtPages[UInt<5>(22)]
    node T_180923 = dshl(UInt<1>(1), T_180922)
    node T_180924 = bits(T_180923, 5, 0)
    accessor T_180925 = tgtPages[UInt<5>(23)]
    node T_180926 = dshl(UInt<1>(1), T_180925)
    node T_180927 = bits(T_180926, 5, 0)
    accessor T_180928 = tgtPages[UInt<5>(24)]
    node T_180929 = dshl(UInt<1>(1), T_180928)
    node T_180930 = bits(T_180929, 5, 0)
    accessor T_180931 = tgtPages[UInt<5>(25)]
    node T_180932 = dshl(UInt<1>(1), T_180931)
    node T_180933 = bits(T_180932, 5, 0)
    accessor T_180934 = tgtPages[UInt<5>(26)]
    node T_180935 = dshl(UInt<1>(1), T_180934)
    node T_180936 = bits(T_180935, 5, 0)
    accessor T_180937 = tgtPages[UInt<5>(27)]
    node T_180938 = dshl(UInt<1>(1), T_180937)
    node T_180939 = bits(T_180938, 5, 0)
    accessor T_180940 = tgtPages[UInt<5>(28)]
    node T_180941 = dshl(UInt<1>(1), T_180940)
    node T_180942 = bits(T_180941, 5, 0)
    accessor T_180943 = tgtPages[UInt<5>(29)]
    node T_180944 = dshl(UInt<1>(1), T_180943)
    node T_180945 = bits(T_180944, 5, 0)
    accessor T_180946 = tgtPages[UInt<5>(30)]
    node T_180947 = dshl(UInt<1>(1), T_180946)
    node T_180948 = bits(T_180947, 5, 0)
    accessor T_180949 = tgtPages[UInt<5>(31)]
    node T_180950 = dshl(UInt<1>(1), T_180949)
    node T_180951 = bits(T_180950, 5, 0)
    accessor T_180952 = tgtPages[UInt<6>(32)]
    node T_180953 = dshl(UInt<1>(1), T_180952)
    node T_180954 = bits(T_180953, 5, 0)
    accessor T_180955 = tgtPages[UInt<6>(33)]
    node T_180956 = dshl(UInt<1>(1), T_180955)
    node T_180957 = bits(T_180956, 5, 0)
    accessor T_180958 = tgtPages[UInt<6>(34)]
    node T_180959 = dshl(UInt<1>(1), T_180958)
    node T_180960 = bits(T_180959, 5, 0)
    accessor T_180961 = tgtPages[UInt<6>(35)]
    node T_180962 = dshl(UInt<1>(1), T_180961)
    node T_180963 = bits(T_180962, 5, 0)
    accessor T_180964 = tgtPages[UInt<6>(36)]
    node T_180965 = dshl(UInt<1>(1), T_180964)
    node T_180966 = bits(T_180965, 5, 0)
    accessor T_180967 = tgtPages[UInt<6>(37)]
    node T_180968 = dshl(UInt<1>(1), T_180967)
    node T_180969 = bits(T_180968, 5, 0)
    accessor T_180970 = tgtPages[UInt<6>(38)]
    node T_180971 = dshl(UInt<1>(1), T_180970)
    node T_180972 = bits(T_180971, 5, 0)
    accessor T_180973 = tgtPages[UInt<6>(39)]
    node T_180974 = dshl(UInt<1>(1), T_180973)
    node T_180975 = bits(T_180974, 5, 0)
    accessor T_180976 = tgtPages[UInt<6>(40)]
    node T_180977 = dshl(UInt<1>(1), T_180976)
    node T_180978 = bits(T_180977, 5, 0)
    accessor T_180979 = tgtPages[UInt<6>(41)]
    node T_180980 = dshl(UInt<1>(1), T_180979)
    node T_180981 = bits(T_180980, 5, 0)
    accessor T_180982 = tgtPages[UInt<6>(42)]
    node T_180983 = dshl(UInt<1>(1), T_180982)
    node T_180984 = bits(T_180983, 5, 0)
    accessor T_180985 = tgtPages[UInt<6>(43)]
    node T_180986 = dshl(UInt<1>(1), T_180985)
    node T_180987 = bits(T_180986, 5, 0)
    accessor T_180988 = tgtPages[UInt<6>(44)]
    node T_180989 = dshl(UInt<1>(1), T_180988)
    node T_180990 = bits(T_180989, 5, 0)
    accessor T_180991 = tgtPages[UInt<6>(45)]
    node T_180992 = dshl(UInt<1>(1), T_180991)
    node T_180993 = bits(T_180992, 5, 0)
    accessor T_180994 = tgtPages[UInt<6>(46)]
    node T_180995 = dshl(UInt<1>(1), T_180994)
    node T_180996 = bits(T_180995, 5, 0)
    accessor T_180997 = tgtPages[UInt<6>(47)]
    node T_180998 = dshl(UInt<1>(1), T_180997)
    node T_180999 = bits(T_180998, 5, 0)
    accessor T_181000 = tgtPages[UInt<6>(48)]
    node T_181001 = dshl(UInt<1>(1), T_181000)
    node T_181002 = bits(T_181001, 5, 0)
    accessor T_181003 = tgtPages[UInt<6>(49)]
    node T_181004 = dshl(UInt<1>(1), T_181003)
    node T_181005 = bits(T_181004, 5, 0)
    accessor T_181006 = tgtPages[UInt<6>(50)]
    node T_181007 = dshl(UInt<1>(1), T_181006)
    node T_181008 = bits(T_181007, 5, 0)
    accessor T_181009 = tgtPages[UInt<6>(51)]
    node T_181010 = dshl(UInt<1>(1), T_181009)
    node T_181011 = bits(T_181010, 5, 0)
    accessor T_181012 = tgtPages[UInt<6>(52)]
    node T_181013 = dshl(UInt<1>(1), T_181012)
    node T_181014 = bits(T_181013, 5, 0)
    accessor T_181015 = tgtPages[UInt<6>(53)]
    node T_181016 = dshl(UInt<1>(1), T_181015)
    node T_181017 = bits(T_181016, 5, 0)
    accessor T_181018 = tgtPages[UInt<6>(54)]
    node T_181019 = dshl(UInt<1>(1), T_181018)
    node T_181020 = bits(T_181019, 5, 0)
    accessor T_181021 = tgtPages[UInt<6>(55)]
    node T_181022 = dshl(UInt<1>(1), T_181021)
    node T_181023 = bits(T_181022, 5, 0)
    accessor T_181024 = tgtPages[UInt<6>(56)]
    node T_181025 = dshl(UInt<1>(1), T_181024)
    node T_181026 = bits(T_181025, 5, 0)
    accessor T_181027 = tgtPages[UInt<6>(57)]
    node T_181028 = dshl(UInt<1>(1), T_181027)
    node T_181029 = bits(T_181028, 5, 0)
    accessor T_181030 = tgtPages[UInt<6>(58)]
    node T_181031 = dshl(UInt<1>(1), T_181030)
    node T_181032 = bits(T_181031, 5, 0)
    accessor T_181033 = tgtPages[UInt<6>(59)]
    node T_181034 = dshl(UInt<1>(1), T_181033)
    node T_181035 = bits(T_181034, 5, 0)
    accessor T_181036 = tgtPages[UInt<6>(60)]
    node T_181037 = dshl(UInt<1>(1), T_181036)
    node T_181038 = bits(T_181037, 5, 0)
    accessor T_181039 = tgtPages[UInt<6>(61)]
    node T_181040 = dshl(UInt<1>(1), T_181039)
    node T_181041 = bits(T_181040, 5, 0)
    reg useRAS : UInt<1>[62]
    reg isJump : UInt<1>[62]
    cmem brIdx : UInt<1>[62]
    reg T_181042 : UInt<1>
    onreset T_181042 := UInt<1>(0)
    T_181042 := btb_update.valid
    reg T_181043 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}
    when btb_update.valid : T_181043 := btb_update.bits
    r_btb_update.valid <> T_181042
    r_btb_update.bits <> T_181043
    node T_181044 = shr(req.bits.addr, 12)
    accessor T_181045 = pages[UInt<1>(0)]
    node T_181046 = eq(T_181045, T_181044)
    accessor T_181047 = pages[UInt<1>(1)]
    node T_181048 = eq(T_181047, T_181044)
    accessor T_181049 = pages[UInt<2>(2)]
    node T_181050 = eq(T_181049, T_181044)
    accessor T_181051 = pages[UInt<2>(3)]
    node T_181052 = eq(T_181051, T_181044)
    accessor T_181053 = pages[UInt<3>(4)]
    node T_181054 = eq(T_181053, T_181044)
    accessor T_181055 = pages[UInt<3>(5)]
    node T_181056 = eq(T_181055, T_181044)
    wire T_181057 : UInt<1>[6]
    T_181057[0] := T_181046
    T_181057[1] := T_181048
    T_181057[2] := T_181050
    T_181057[3] := T_181052
    T_181057[4] := T_181054
    T_181057[5] := T_181056
    node T_181058 = cat(T_181057[4], T_181057[3])
    node T_181059 = cat(T_181057[5], T_181058)
    node T_181060 = cat(T_181057[1], T_181057[0])
    node T_181061 = cat(T_181057[2], T_181060)
    node T_181062 = cat(T_181059, T_181061)
    node pageHit = and(T_181062, pageValid)
    node T_181063 = bits(req.bits.addr, 11, 0)
    accessor T_181064 = idxs[UInt<1>(0)]
    node T_181065 = eq(T_181064, T_181063)
    accessor T_181066 = idxs[UInt<1>(1)]
    node T_181067 = eq(T_181066, T_181063)
    accessor T_181068 = idxs[UInt<2>(2)]
    node T_181069 = eq(T_181068, T_181063)
    accessor T_181070 = idxs[UInt<2>(3)]
    node T_181071 = eq(T_181070, T_181063)
    accessor T_181072 = idxs[UInt<3>(4)]
    node T_181073 = eq(T_181072, T_181063)
    accessor T_181074 = idxs[UInt<3>(5)]
    node T_181075 = eq(T_181074, T_181063)
    accessor T_181076 = idxs[UInt<3>(6)]
    node T_181077 = eq(T_181076, T_181063)
    accessor T_181078 = idxs[UInt<3>(7)]
    node T_181079 = eq(T_181078, T_181063)
    accessor T_181080 = idxs[UInt<4>(8)]
    node T_181081 = eq(T_181080, T_181063)
    accessor T_181082 = idxs[UInt<4>(9)]
    node T_181083 = eq(T_181082, T_181063)
    accessor T_181084 = idxs[UInt<4>(10)]
    node T_181085 = eq(T_181084, T_181063)
    accessor T_181086 = idxs[UInt<4>(11)]
    node T_181087 = eq(T_181086, T_181063)
    accessor T_181088 = idxs[UInt<4>(12)]
    node T_181089 = eq(T_181088, T_181063)
    accessor T_181090 = idxs[UInt<4>(13)]
    node T_181091 = eq(T_181090, T_181063)
    accessor T_181092 = idxs[UInt<4>(14)]
    node T_181093 = eq(T_181092, T_181063)
    accessor T_181094 = idxs[UInt<4>(15)]
    node T_181095 = eq(T_181094, T_181063)
    accessor T_181096 = idxs[UInt<5>(16)]
    node T_181097 = eq(T_181096, T_181063)
    accessor T_181098 = idxs[UInt<5>(17)]
    node T_181099 = eq(T_181098, T_181063)
    accessor T_181100 = idxs[UInt<5>(18)]
    node T_181101 = eq(T_181100, T_181063)
    accessor T_181102 = idxs[UInt<5>(19)]
    node T_181103 = eq(T_181102, T_181063)
    accessor T_181104 = idxs[UInt<5>(20)]
    node T_181105 = eq(T_181104, T_181063)
    accessor T_181106 = idxs[UInt<5>(21)]
    node T_181107 = eq(T_181106, T_181063)
    accessor T_181108 = idxs[UInt<5>(22)]
    node T_181109 = eq(T_181108, T_181063)
    accessor T_181110 = idxs[UInt<5>(23)]
    node T_181111 = eq(T_181110, T_181063)
    accessor T_181112 = idxs[UInt<5>(24)]
    node T_181113 = eq(T_181112, T_181063)
    accessor T_181114 = idxs[UInt<5>(25)]
    node T_181115 = eq(T_181114, T_181063)
    accessor T_181116 = idxs[UInt<5>(26)]
    node T_181117 = eq(T_181116, T_181063)
    accessor T_181118 = idxs[UInt<5>(27)]
    node T_181119 = eq(T_181118, T_181063)
    accessor T_181120 = idxs[UInt<5>(28)]
    node T_181121 = eq(T_181120, T_181063)
    accessor T_181122 = idxs[UInt<5>(29)]
    node T_181123 = eq(T_181122, T_181063)
    accessor T_181124 = idxs[UInt<5>(30)]
    node T_181125 = eq(T_181124, T_181063)
    accessor T_181126 = idxs[UInt<5>(31)]
    node T_181127 = eq(T_181126, T_181063)
    accessor T_181128 = idxs[UInt<6>(32)]
    node T_181129 = eq(T_181128, T_181063)
    accessor T_181130 = idxs[UInt<6>(33)]
    node T_181131 = eq(T_181130, T_181063)
    accessor T_181132 = idxs[UInt<6>(34)]
    node T_181133 = eq(T_181132, T_181063)
    accessor T_181134 = idxs[UInt<6>(35)]
    node T_181135 = eq(T_181134, T_181063)
    accessor T_181136 = idxs[UInt<6>(36)]
    node T_181137 = eq(T_181136, T_181063)
    accessor T_181138 = idxs[UInt<6>(37)]
    node T_181139 = eq(T_181138, T_181063)
    accessor T_181140 = idxs[UInt<6>(38)]
    node T_181141 = eq(T_181140, T_181063)
    accessor T_181142 = idxs[UInt<6>(39)]
    node T_181143 = eq(T_181142, T_181063)
    accessor T_181144 = idxs[UInt<6>(40)]
    node T_181145 = eq(T_181144, T_181063)
    accessor T_181146 = idxs[UInt<6>(41)]
    node T_181147 = eq(T_181146, T_181063)
    accessor T_181148 = idxs[UInt<6>(42)]
    node T_181149 = eq(T_181148, T_181063)
    accessor T_181150 = idxs[UInt<6>(43)]
    node T_181151 = eq(T_181150, T_181063)
    accessor T_181152 = idxs[UInt<6>(44)]
    node T_181153 = eq(T_181152, T_181063)
    accessor T_181154 = idxs[UInt<6>(45)]
    node T_181155 = eq(T_181154, T_181063)
    accessor T_181156 = idxs[UInt<6>(46)]
    node T_181157 = eq(T_181156, T_181063)
    accessor T_181158 = idxs[UInt<6>(47)]
    node T_181159 = eq(T_181158, T_181063)
    accessor T_181160 = idxs[UInt<6>(48)]
    node T_181161 = eq(T_181160, T_181063)
    accessor T_181162 = idxs[UInt<6>(49)]
    node T_181163 = eq(T_181162, T_181063)
    accessor T_181164 = idxs[UInt<6>(50)]
    node T_181165 = eq(T_181164, T_181063)
    accessor T_181166 = idxs[UInt<6>(51)]
    node T_181167 = eq(T_181166, T_181063)
    accessor T_181168 = idxs[UInt<6>(52)]
    node T_181169 = eq(T_181168, T_181063)
    accessor T_181170 = idxs[UInt<6>(53)]
    node T_181171 = eq(T_181170, T_181063)
    accessor T_181172 = idxs[UInt<6>(54)]
    node T_181173 = eq(T_181172, T_181063)
    accessor T_181174 = idxs[UInt<6>(55)]
    node T_181175 = eq(T_181174, T_181063)
    accessor T_181176 = idxs[UInt<6>(56)]
    node T_181177 = eq(T_181176, T_181063)
    accessor T_181178 = idxs[UInt<6>(57)]
    node T_181179 = eq(T_181178, T_181063)
    accessor T_181180 = idxs[UInt<6>(58)]
    node T_181181 = eq(T_181180, T_181063)
    accessor T_181182 = idxs[UInt<6>(59)]
    node T_181183 = eq(T_181182, T_181063)
    accessor T_181184 = idxs[UInt<6>(60)]
    node T_181185 = eq(T_181184, T_181063)
    accessor T_181186 = idxs[UInt<6>(61)]
    node T_181187 = eq(T_181186, T_181063)
    wire T_181188 : UInt<1>[62]
    T_181188[0] := T_181065
    T_181188[1] := T_181067
    T_181188[2] := T_181069
    T_181188[3] := T_181071
    T_181188[4] := T_181073
    T_181188[5] := T_181075
    T_181188[6] := T_181077
    T_181188[7] := T_181079
    T_181188[8] := T_181081
    T_181188[9] := T_181083
    T_181188[10] := T_181085
    T_181188[11] := T_181087
    T_181188[12] := T_181089
    T_181188[13] := T_181091
    T_181188[14] := T_181093
    T_181188[15] := T_181095
    T_181188[16] := T_181097
    T_181188[17] := T_181099
    T_181188[18] := T_181101
    T_181188[19] := T_181103
    T_181188[20] := T_181105
    T_181188[21] := T_181107
    T_181188[22] := T_181109
    T_181188[23] := T_181111
    T_181188[24] := T_181113
    T_181188[25] := T_181115
    T_181188[26] := T_181117
    T_181188[27] := T_181119
    T_181188[28] := T_181121
    T_181188[29] := T_181123
    T_181188[30] := T_181125
    T_181188[31] := T_181127
    T_181188[32] := T_181129
    T_181188[33] := T_181131
    T_181188[34] := T_181133
    T_181188[35] := T_181135
    T_181188[36] := T_181137
    T_181188[37] := T_181139
    T_181188[38] := T_181141
    T_181188[39] := T_181143
    T_181188[40] := T_181145
    T_181188[41] := T_181147
    T_181188[42] := T_181149
    T_181188[43] := T_181151
    T_181188[44] := T_181153
    T_181188[45] := T_181155
    T_181188[46] := T_181157
    T_181188[47] := T_181159
    T_181188[48] := T_181161
    T_181188[49] := T_181163
    T_181188[50] := T_181165
    T_181188[51] := T_181167
    T_181188[52] := T_181169
    T_181188[53] := T_181171
    T_181188[54] := T_181173
    T_181188[55] := T_181175
    T_181188[56] := T_181177
    T_181188[57] := T_181179
    T_181188[58] := T_181181
    T_181188[59] := T_181183
    T_181188[60] := T_181185
    T_181188[61] := T_181187
    node T_181189 = cat(T_181188[60], T_181188[59])
    node T_181190 = cat(T_181188[61], T_181189)
    node T_181191 = cat(T_181188[58], T_181188[57])
    node T_181192 = cat(T_181188[56], T_181188[55])
    node T_181193 = cat(T_181191, T_181192)
    node T_181194 = cat(T_181190, T_181193)
    node T_181195 = cat(T_181188[54], T_181188[53])
    node T_181196 = cat(T_181188[52], T_181188[51])
    node T_181197 = cat(T_181195, T_181196)
    node T_181198 = cat(T_181188[50], T_181188[49])
    node T_181199 = cat(T_181188[48], T_181188[47])
    node T_181200 = cat(T_181198, T_181199)
    node T_181201 = cat(T_181197, T_181200)
    node T_181202 = cat(T_181194, T_181201)
    node T_181203 = cat(T_181188[46], T_181188[45])
    node T_181204 = cat(T_181188[44], T_181188[43])
    node T_181205 = cat(T_181203, T_181204)
    node T_181206 = cat(T_181188[42], T_181188[41])
    node T_181207 = cat(T_181188[40], T_181188[39])
    node T_181208 = cat(T_181206, T_181207)
    node T_181209 = cat(T_181205, T_181208)
    node T_181210 = cat(T_181188[38], T_181188[37])
    node T_181211 = cat(T_181188[36], T_181188[35])
    node T_181212 = cat(T_181210, T_181211)
    node T_181213 = cat(T_181188[34], T_181188[33])
    node T_181214 = cat(T_181188[32], T_181188[31])
    node T_181215 = cat(T_181213, T_181214)
    node T_181216 = cat(T_181212, T_181215)
    node T_181217 = cat(T_181209, T_181216)
    node T_181218 = cat(T_181202, T_181217)
    node T_181219 = cat(T_181188[29], T_181188[28])
    node T_181220 = cat(T_181188[30], T_181219)
    node T_181221 = cat(T_181188[27], T_181188[26])
    node T_181222 = cat(T_181188[25], T_181188[24])
    node T_181223 = cat(T_181221, T_181222)
    node T_181224 = cat(T_181220, T_181223)
    node T_181225 = cat(T_181188[23], T_181188[22])
    node T_181226 = cat(T_181188[21], T_181188[20])
    node T_181227 = cat(T_181225, T_181226)
    node T_181228 = cat(T_181188[19], T_181188[18])
    node T_181229 = cat(T_181188[17], T_181188[16])
    node T_181230 = cat(T_181228, T_181229)
    node T_181231 = cat(T_181227, T_181230)
    node T_181232 = cat(T_181224, T_181231)
    node T_181233 = cat(T_181188[15], T_181188[14])
    node T_181234 = cat(T_181188[13], T_181188[12])
    node T_181235 = cat(T_181233, T_181234)
    node T_181236 = cat(T_181188[11], T_181188[10])
    node T_181237 = cat(T_181188[9], T_181188[8])
    node T_181238 = cat(T_181236, T_181237)
    node T_181239 = cat(T_181235, T_181238)
    node T_181240 = cat(T_181188[7], T_181188[6])
    node T_181241 = cat(T_181188[5], T_181188[4])
    node T_181242 = cat(T_181240, T_181241)
    node T_181243 = cat(T_181188[3], T_181188[2])
    node T_181244 = cat(T_181188[1], T_181188[0])
    node T_181245 = cat(T_181243, T_181244)
    node T_181246 = cat(T_181242, T_181245)
    node T_181247 = cat(T_181239, T_181246)
    node T_181248 = cat(T_181232, T_181247)
    node T_181249 = cat(T_181218, T_181248)
    node T_181250 = and(T_180672, pageHit)
    node T_181251 = and(T_180675, pageHit)
    node T_181252 = and(T_180678, pageHit)
    node T_181253 = and(T_180681, pageHit)
    node T_181254 = and(T_180684, pageHit)
    node T_181255 = and(T_180687, pageHit)
    node T_181256 = and(T_180690, pageHit)
    node T_181257 = and(T_180693, pageHit)
    node T_181258 = and(T_180696, pageHit)
    node T_181259 = and(T_180699, pageHit)
    node T_181260 = and(T_180702, pageHit)
    node T_181261 = and(T_180705, pageHit)
    node T_181262 = and(T_180708, pageHit)
    node T_181263 = and(T_180711, pageHit)
    node T_181264 = and(T_180714, pageHit)
    node T_181265 = and(T_180717, pageHit)
    node T_181266 = and(T_180720, pageHit)
    node T_181267 = and(T_180723, pageHit)
    node T_181268 = and(T_180726, pageHit)
    node T_181269 = and(T_180729, pageHit)
    node T_181270 = and(T_180732, pageHit)
    node T_181271 = and(T_180735, pageHit)
    node T_181272 = and(T_180738, pageHit)
    node T_181273 = and(T_180741, pageHit)
    node T_181274 = and(T_180744, pageHit)
    node T_181275 = and(T_180747, pageHit)
    node T_181276 = and(T_180750, pageHit)
    node T_181277 = and(T_180753, pageHit)
    node T_181278 = and(T_180756, pageHit)
    node T_181279 = and(T_180759, pageHit)
    node T_181280 = and(T_180762, pageHit)
    node T_181281 = and(T_180765, pageHit)
    node T_181282 = and(T_180768, pageHit)
    node T_181283 = and(T_180771, pageHit)
    node T_181284 = and(T_180774, pageHit)
    node T_181285 = and(T_180777, pageHit)
    node T_181286 = and(T_180780, pageHit)
    node T_181287 = and(T_180783, pageHit)
    node T_181288 = and(T_180786, pageHit)
    node T_181289 = and(T_180789, pageHit)
    node T_181290 = and(T_180792, pageHit)
    node T_181291 = and(T_180795, pageHit)
    node T_181292 = and(T_180798, pageHit)
    node T_181293 = and(T_180801, pageHit)
    node T_181294 = and(T_180804, pageHit)
    node T_181295 = and(T_180807, pageHit)
    node T_181296 = and(T_180810, pageHit)
    node T_181297 = and(T_180813, pageHit)
    node T_181298 = and(T_180816, pageHit)
    node T_181299 = and(T_180819, pageHit)
    node T_181300 = and(T_180822, pageHit)
    node T_181301 = and(T_180825, pageHit)
    node T_181302 = and(T_180828, pageHit)
    node T_181303 = and(T_180831, pageHit)
    node T_181304 = and(T_180834, pageHit)
    node T_181305 = and(T_180837, pageHit)
    node T_181306 = and(T_180840, pageHit)
    node T_181307 = and(T_180843, pageHit)
    node T_181308 = and(T_180846, pageHit)
    node T_181309 = and(T_180849, pageHit)
    node T_181310 = and(T_180852, pageHit)
    node T_181311 = and(T_180855, pageHit)
    node T_181312 = eq(T_181250, UInt<1>(0))
    node T_181313 = eq(T_181312, UInt<1>(0))
    node T_181314 = eq(T_181251, UInt<1>(0))
    node T_181315 = eq(T_181314, UInt<1>(0))
    node T_181316 = eq(T_181252, UInt<1>(0))
    node T_181317 = eq(T_181316, UInt<1>(0))
    node T_181318 = eq(T_181253, UInt<1>(0))
    node T_181319 = eq(T_181318, UInt<1>(0))
    node T_181320 = eq(T_181254, UInt<1>(0))
    node T_181321 = eq(T_181320, UInt<1>(0))
    node T_181322 = eq(T_181255, UInt<1>(0))
    node T_181323 = eq(T_181322, UInt<1>(0))
    node T_181324 = eq(T_181256, UInt<1>(0))
    node T_181325 = eq(T_181324, UInt<1>(0))
    node T_181326 = eq(T_181257, UInt<1>(0))
    node T_181327 = eq(T_181326, UInt<1>(0))
    node T_181328 = eq(T_181258, UInt<1>(0))
    node T_181329 = eq(T_181328, UInt<1>(0))
    node T_181330 = eq(T_181259, UInt<1>(0))
    node T_181331 = eq(T_181330, UInt<1>(0))
    node T_181332 = eq(T_181260, UInt<1>(0))
    node T_181333 = eq(T_181332, UInt<1>(0))
    node T_181334 = eq(T_181261, UInt<1>(0))
    node T_181335 = eq(T_181334, UInt<1>(0))
    node T_181336 = eq(T_181262, UInt<1>(0))
    node T_181337 = eq(T_181336, UInt<1>(0))
    node T_181338 = eq(T_181263, UInt<1>(0))
    node T_181339 = eq(T_181338, UInt<1>(0))
    node T_181340 = eq(T_181264, UInt<1>(0))
    node T_181341 = eq(T_181340, UInt<1>(0))
    node T_181342 = eq(T_181265, UInt<1>(0))
    node T_181343 = eq(T_181342, UInt<1>(0))
    node T_181344 = eq(T_181266, UInt<1>(0))
    node T_181345 = eq(T_181344, UInt<1>(0))
    node T_181346 = eq(T_181267, UInt<1>(0))
    node T_181347 = eq(T_181346, UInt<1>(0))
    node T_181348 = eq(T_181268, UInt<1>(0))
    node T_181349 = eq(T_181348, UInt<1>(0))
    node T_181350 = eq(T_181269, UInt<1>(0))
    node T_181351 = eq(T_181350, UInt<1>(0))
    node T_181352 = eq(T_181270, UInt<1>(0))
    node T_181353 = eq(T_181352, UInt<1>(0))
    node T_181354 = eq(T_181271, UInt<1>(0))
    node T_181355 = eq(T_181354, UInt<1>(0))
    node T_181356 = eq(T_181272, UInt<1>(0))
    node T_181357 = eq(T_181356, UInt<1>(0))
    node T_181358 = eq(T_181273, UInt<1>(0))
    node T_181359 = eq(T_181358, UInt<1>(0))
    node T_181360 = eq(T_181274, UInt<1>(0))
    node T_181361 = eq(T_181360, UInt<1>(0))
    node T_181362 = eq(T_181275, UInt<1>(0))
    node T_181363 = eq(T_181362, UInt<1>(0))
    node T_181364 = eq(T_181276, UInt<1>(0))
    node T_181365 = eq(T_181364, UInt<1>(0))
    node T_181366 = eq(T_181277, UInt<1>(0))
    node T_181367 = eq(T_181366, UInt<1>(0))
    node T_181368 = eq(T_181278, UInt<1>(0))
    node T_181369 = eq(T_181368, UInt<1>(0))
    node T_181370 = eq(T_181279, UInt<1>(0))
    node T_181371 = eq(T_181370, UInt<1>(0))
    node T_181372 = eq(T_181280, UInt<1>(0))
    node T_181373 = eq(T_181372, UInt<1>(0))
    node T_181374 = eq(T_181281, UInt<1>(0))
    node T_181375 = eq(T_181374, UInt<1>(0))
    node T_181376 = eq(T_181282, UInt<1>(0))
    node T_181377 = eq(T_181376, UInt<1>(0))
    node T_181378 = eq(T_181283, UInt<1>(0))
    node T_181379 = eq(T_181378, UInt<1>(0))
    node T_181380 = eq(T_181284, UInt<1>(0))
    node T_181381 = eq(T_181380, UInt<1>(0))
    node T_181382 = eq(T_181285, UInt<1>(0))
    node T_181383 = eq(T_181382, UInt<1>(0))
    node T_181384 = eq(T_181286, UInt<1>(0))
    node T_181385 = eq(T_181384, UInt<1>(0))
    node T_181386 = eq(T_181287, UInt<1>(0))
    node T_181387 = eq(T_181386, UInt<1>(0))
    node T_181388 = eq(T_181288, UInt<1>(0))
    node T_181389 = eq(T_181388, UInt<1>(0))
    node T_181390 = eq(T_181289, UInt<1>(0))
    node T_181391 = eq(T_181390, UInt<1>(0))
    node T_181392 = eq(T_181290, UInt<1>(0))
    node T_181393 = eq(T_181392, UInt<1>(0))
    node T_181394 = eq(T_181291, UInt<1>(0))
    node T_181395 = eq(T_181394, UInt<1>(0))
    node T_181396 = eq(T_181292, UInt<1>(0))
    node T_181397 = eq(T_181396, UInt<1>(0))
    node T_181398 = eq(T_181293, UInt<1>(0))
    node T_181399 = eq(T_181398, UInt<1>(0))
    node T_181400 = eq(T_181294, UInt<1>(0))
    node T_181401 = eq(T_181400, UInt<1>(0))
    node T_181402 = eq(T_181295, UInt<1>(0))
    node T_181403 = eq(T_181402, UInt<1>(0))
    node T_181404 = eq(T_181296, UInt<1>(0))
    node T_181405 = eq(T_181404, UInt<1>(0))
    node T_181406 = eq(T_181297, UInt<1>(0))
    node T_181407 = eq(T_181406, UInt<1>(0))
    node T_181408 = eq(T_181298, UInt<1>(0))
    node T_181409 = eq(T_181408, UInt<1>(0))
    node T_181410 = eq(T_181299, UInt<1>(0))
    node T_181411 = eq(T_181410, UInt<1>(0))
    node T_181412 = eq(T_181300, UInt<1>(0))
    node T_181413 = eq(T_181412, UInt<1>(0))
    node T_181414 = eq(T_181301, UInt<1>(0))
    node T_181415 = eq(T_181414, UInt<1>(0))
    node T_181416 = eq(T_181302, UInt<1>(0))
    node T_181417 = eq(T_181416, UInt<1>(0))
    node T_181418 = eq(T_181303, UInt<1>(0))
    node T_181419 = eq(T_181418, UInt<1>(0))
    node T_181420 = eq(T_181304, UInt<1>(0))
    node T_181421 = eq(T_181420, UInt<1>(0))
    node T_181422 = eq(T_181305, UInt<1>(0))
    node T_181423 = eq(T_181422, UInt<1>(0))
    node T_181424 = eq(T_181306, UInt<1>(0))
    node T_181425 = eq(T_181424, UInt<1>(0))
    node T_181426 = eq(T_181307, UInt<1>(0))
    node T_181427 = eq(T_181426, UInt<1>(0))
    node T_181428 = eq(T_181308, UInt<1>(0))
    node T_181429 = eq(T_181428, UInt<1>(0))
    node T_181430 = eq(T_181309, UInt<1>(0))
    node T_181431 = eq(T_181430, UInt<1>(0))
    node T_181432 = eq(T_181310, UInt<1>(0))
    node T_181433 = eq(T_181432, UInt<1>(0))
    node T_181434 = eq(T_181311, UInt<1>(0))
    node T_181435 = eq(T_181434, UInt<1>(0))
    wire T_181436 : UInt<1>[62]
    T_181436[0] := T_181313
    T_181436[1] := T_181315
    T_181436[2] := T_181317
    T_181436[3] := T_181319
    T_181436[4] := T_181321
    T_181436[5] := T_181323
    T_181436[6] := T_181325
    T_181436[7] := T_181327
    T_181436[8] := T_181329
    T_181436[9] := T_181331
    T_181436[10] := T_181333
    T_181436[11] := T_181335
    T_181436[12] := T_181337
    T_181436[13] := T_181339
    T_181436[14] := T_181341
    T_181436[15] := T_181343
    T_181436[16] := T_181345
    T_181436[17] := T_181347
    T_181436[18] := T_181349
    T_181436[19] := T_181351
    T_181436[20] := T_181353
    T_181436[21] := T_181355
    T_181436[22] := T_181357
    T_181436[23] := T_181359
    T_181436[24] := T_181361
    T_181436[25] := T_181363
    T_181436[26] := T_181365
    T_181436[27] := T_181367
    T_181436[28] := T_181369
    T_181436[29] := T_181371
    T_181436[30] := T_181373
    T_181436[31] := T_181375
    T_181436[32] := T_181377
    T_181436[33] := T_181379
    T_181436[34] := T_181381
    T_181436[35] := T_181383
    T_181436[36] := T_181385
    T_181436[37] := T_181387
    T_181436[38] := T_181389
    T_181436[39] := T_181391
    T_181436[40] := T_181393
    T_181436[41] := T_181395
    T_181436[42] := T_181397
    T_181436[43] := T_181399
    T_181436[44] := T_181401
    T_181436[45] := T_181403
    T_181436[46] := T_181405
    T_181436[47] := T_181407
    T_181436[48] := T_181409
    T_181436[49] := T_181411
    T_181436[50] := T_181413
    T_181436[51] := T_181415
    T_181436[52] := T_181417
    T_181436[53] := T_181419
    T_181436[54] := T_181421
    T_181436[55] := T_181423
    T_181436[56] := T_181425
    T_181436[57] := T_181427
    T_181436[58] := T_181429
    T_181436[59] := T_181431
    T_181436[60] := T_181433
    T_181436[61] := T_181435
    node T_181437 = cat(T_181436[60], T_181436[59])
    node T_181438 = cat(T_181436[61], T_181437)
    node T_181439 = cat(T_181436[58], T_181436[57])
    node T_181440 = cat(T_181436[56], T_181436[55])
    node T_181441 = cat(T_181439, T_181440)
    node T_181442 = cat(T_181438, T_181441)
    node T_181443 = cat(T_181436[54], T_181436[53])
    node T_181444 = cat(T_181436[52], T_181436[51])
    node T_181445 = cat(T_181443, T_181444)
    node T_181446 = cat(T_181436[50], T_181436[49])
    node T_181447 = cat(T_181436[48], T_181436[47])
    node T_181448 = cat(T_181446, T_181447)
    node T_181449 = cat(T_181445, T_181448)
    node T_181450 = cat(T_181442, T_181449)
    node T_181451 = cat(T_181436[46], T_181436[45])
    node T_181452 = cat(T_181436[44], T_181436[43])
    node T_181453 = cat(T_181451, T_181452)
    node T_181454 = cat(T_181436[42], T_181436[41])
    node T_181455 = cat(T_181436[40], T_181436[39])
    node T_181456 = cat(T_181454, T_181455)
    node T_181457 = cat(T_181453, T_181456)
    node T_181458 = cat(T_181436[38], T_181436[37])
    node T_181459 = cat(T_181436[36], T_181436[35])
    node T_181460 = cat(T_181458, T_181459)
    node T_181461 = cat(T_181436[34], T_181436[33])
    node T_181462 = cat(T_181436[32], T_181436[31])
    node T_181463 = cat(T_181461, T_181462)
    node T_181464 = cat(T_181460, T_181463)
    node T_181465 = cat(T_181457, T_181464)
    node T_181466 = cat(T_181450, T_181465)
    node T_181467 = cat(T_181436[29], T_181436[28])
    node T_181468 = cat(T_181436[30], T_181467)
    node T_181469 = cat(T_181436[27], T_181436[26])
    node T_181470 = cat(T_181436[25], T_181436[24])
    node T_181471 = cat(T_181469, T_181470)
    node T_181472 = cat(T_181468, T_181471)
    node T_181473 = cat(T_181436[23], T_181436[22])
    node T_181474 = cat(T_181436[21], T_181436[20])
    node T_181475 = cat(T_181473, T_181474)
    node T_181476 = cat(T_181436[19], T_181436[18])
    node T_181477 = cat(T_181436[17], T_181436[16])
    node T_181478 = cat(T_181476, T_181477)
    node T_181479 = cat(T_181475, T_181478)
    node T_181480 = cat(T_181472, T_181479)
    node T_181481 = cat(T_181436[15], T_181436[14])
    node T_181482 = cat(T_181436[13], T_181436[12])
    node T_181483 = cat(T_181481, T_181482)
    node T_181484 = cat(T_181436[11], T_181436[10])
    node T_181485 = cat(T_181436[9], T_181436[8])
    node T_181486 = cat(T_181484, T_181485)
    node T_181487 = cat(T_181483, T_181486)
    node T_181488 = cat(T_181436[7], T_181436[6])
    node T_181489 = cat(T_181436[5], T_181436[4])
    node T_181490 = cat(T_181488, T_181489)
    node T_181491 = cat(T_181436[3], T_181436[2])
    node T_181492 = cat(T_181436[1], T_181436[0])
    node T_181493 = cat(T_181491, T_181492)
    node T_181494 = cat(T_181490, T_181493)
    node T_181495 = cat(T_181487, T_181494)
    node T_181496 = cat(T_181480, T_181495)
    node T_181497 = cat(T_181466, T_181496)
    node T_181498 = bit(T_181249, 0)
    node T_181499 = and(idxValid[0], T_181498)
    node T_181500 = bit(T_181497, 0)
    node T_181501 = and(T_181499, T_181500)
    node T_181502 = bit(T_181249, 1)
    node T_181503 = and(idxValid[1], T_181502)
    node T_181504 = bit(T_181497, 1)
    node T_181505 = and(T_181503, T_181504)
    node T_181506 = bit(T_181249, 2)
    node T_181507 = and(idxValid[2], T_181506)
    node T_181508 = bit(T_181497, 2)
    node T_181509 = and(T_181507, T_181508)
    node T_181510 = bit(T_181249, 3)
    node T_181511 = and(idxValid[3], T_181510)
    node T_181512 = bit(T_181497, 3)
    node T_181513 = and(T_181511, T_181512)
    node T_181514 = bit(T_181249, 4)
    node T_181515 = and(idxValid[4], T_181514)
    node T_181516 = bit(T_181497, 4)
    node T_181517 = and(T_181515, T_181516)
    node T_181518 = bit(T_181249, 5)
    node T_181519 = and(idxValid[5], T_181518)
    node T_181520 = bit(T_181497, 5)
    node T_181521 = and(T_181519, T_181520)
    node T_181522 = bit(T_181249, 6)
    node T_181523 = and(idxValid[6], T_181522)
    node T_181524 = bit(T_181497, 6)
    node T_181525 = and(T_181523, T_181524)
    node T_181526 = bit(T_181249, 7)
    node T_181527 = and(idxValid[7], T_181526)
    node T_181528 = bit(T_181497, 7)
    node T_181529 = and(T_181527, T_181528)
    node T_181530 = bit(T_181249, 8)
    node T_181531 = and(idxValid[8], T_181530)
    node T_181532 = bit(T_181497, 8)
    node T_181533 = and(T_181531, T_181532)
    node T_181534 = bit(T_181249, 9)
    node T_181535 = and(idxValid[9], T_181534)
    node T_181536 = bit(T_181497, 9)
    node T_181537 = and(T_181535, T_181536)
    node T_181538 = bit(T_181249, 10)
    node T_181539 = and(idxValid[10], T_181538)
    node T_181540 = bit(T_181497, 10)
    node T_181541 = and(T_181539, T_181540)
    node T_181542 = bit(T_181249, 11)
    node T_181543 = and(idxValid[11], T_181542)
    node T_181544 = bit(T_181497, 11)
    node T_181545 = and(T_181543, T_181544)
    node T_181546 = bit(T_181249, 12)
    node T_181547 = and(idxValid[12], T_181546)
    node T_181548 = bit(T_181497, 12)
    node T_181549 = and(T_181547, T_181548)
    node T_181550 = bit(T_181249, 13)
    node T_181551 = and(idxValid[13], T_181550)
    node T_181552 = bit(T_181497, 13)
    node T_181553 = and(T_181551, T_181552)
    node T_181554 = bit(T_181249, 14)
    node T_181555 = and(idxValid[14], T_181554)
    node T_181556 = bit(T_181497, 14)
    node T_181557 = and(T_181555, T_181556)
    node T_181558 = bit(T_181249, 15)
    node T_181559 = and(idxValid[15], T_181558)
    node T_181560 = bit(T_181497, 15)
    node T_181561 = and(T_181559, T_181560)
    node T_181562 = bit(T_181249, 16)
    node T_181563 = and(idxValid[16], T_181562)
    node T_181564 = bit(T_181497, 16)
    node T_181565 = and(T_181563, T_181564)
    node T_181566 = bit(T_181249, 17)
    node T_181567 = and(idxValid[17], T_181566)
    node T_181568 = bit(T_181497, 17)
    node T_181569 = and(T_181567, T_181568)
    node T_181570 = bit(T_181249, 18)
    node T_181571 = and(idxValid[18], T_181570)
    node T_181572 = bit(T_181497, 18)
    node T_181573 = and(T_181571, T_181572)
    node T_181574 = bit(T_181249, 19)
    node T_181575 = and(idxValid[19], T_181574)
    node T_181576 = bit(T_181497, 19)
    node T_181577 = and(T_181575, T_181576)
    node T_181578 = bit(T_181249, 20)
    node T_181579 = and(idxValid[20], T_181578)
    node T_181580 = bit(T_181497, 20)
    node T_181581 = and(T_181579, T_181580)
    node T_181582 = bit(T_181249, 21)
    node T_181583 = and(idxValid[21], T_181582)
    node T_181584 = bit(T_181497, 21)
    node T_181585 = and(T_181583, T_181584)
    node T_181586 = bit(T_181249, 22)
    node T_181587 = and(idxValid[22], T_181586)
    node T_181588 = bit(T_181497, 22)
    node T_181589 = and(T_181587, T_181588)
    node T_181590 = bit(T_181249, 23)
    node T_181591 = and(idxValid[23], T_181590)
    node T_181592 = bit(T_181497, 23)
    node T_181593 = and(T_181591, T_181592)
    node T_181594 = bit(T_181249, 24)
    node T_181595 = and(idxValid[24], T_181594)
    node T_181596 = bit(T_181497, 24)
    node T_181597 = and(T_181595, T_181596)
    node T_181598 = bit(T_181249, 25)
    node T_181599 = and(idxValid[25], T_181598)
    node T_181600 = bit(T_181497, 25)
    node T_181601 = and(T_181599, T_181600)
    node T_181602 = bit(T_181249, 26)
    node T_181603 = and(idxValid[26], T_181602)
    node T_181604 = bit(T_181497, 26)
    node T_181605 = and(T_181603, T_181604)
    node T_181606 = bit(T_181249, 27)
    node T_181607 = and(idxValid[27], T_181606)
    node T_181608 = bit(T_181497, 27)
    node T_181609 = and(T_181607, T_181608)
    node T_181610 = bit(T_181249, 28)
    node T_181611 = and(idxValid[28], T_181610)
    node T_181612 = bit(T_181497, 28)
    node T_181613 = and(T_181611, T_181612)
    node T_181614 = bit(T_181249, 29)
    node T_181615 = and(idxValid[29], T_181614)
    node T_181616 = bit(T_181497, 29)
    node T_181617 = and(T_181615, T_181616)
    node T_181618 = bit(T_181249, 30)
    node T_181619 = and(idxValid[30], T_181618)
    node T_181620 = bit(T_181497, 30)
    node T_181621 = and(T_181619, T_181620)
    node T_181622 = bit(T_181249, 31)
    node T_181623 = and(idxValid[31], T_181622)
    node T_181624 = bit(T_181497, 31)
    node T_181625 = and(T_181623, T_181624)
    node T_181626 = bit(T_181249, 32)
    node T_181627 = and(idxValid[32], T_181626)
    node T_181628 = bit(T_181497, 32)
    node T_181629 = and(T_181627, T_181628)
    node T_181630 = bit(T_181249, 33)
    node T_181631 = and(idxValid[33], T_181630)
    node T_181632 = bit(T_181497, 33)
    node T_181633 = and(T_181631, T_181632)
    node T_181634 = bit(T_181249, 34)
    node T_181635 = and(idxValid[34], T_181634)
    node T_181636 = bit(T_181497, 34)
    node T_181637 = and(T_181635, T_181636)
    node T_181638 = bit(T_181249, 35)
    node T_181639 = and(idxValid[35], T_181638)
    node T_181640 = bit(T_181497, 35)
    node T_181641 = and(T_181639, T_181640)
    node T_181642 = bit(T_181249, 36)
    node T_181643 = and(idxValid[36], T_181642)
    node T_181644 = bit(T_181497, 36)
    node T_181645 = and(T_181643, T_181644)
    node T_181646 = bit(T_181249, 37)
    node T_181647 = and(idxValid[37], T_181646)
    node T_181648 = bit(T_181497, 37)
    node T_181649 = and(T_181647, T_181648)
    node T_181650 = bit(T_181249, 38)
    node T_181651 = and(idxValid[38], T_181650)
    node T_181652 = bit(T_181497, 38)
    node T_181653 = and(T_181651, T_181652)
    node T_181654 = bit(T_181249, 39)
    node T_181655 = and(idxValid[39], T_181654)
    node T_181656 = bit(T_181497, 39)
    node T_181657 = and(T_181655, T_181656)
    node T_181658 = bit(T_181249, 40)
    node T_181659 = and(idxValid[40], T_181658)
    node T_181660 = bit(T_181497, 40)
    node T_181661 = and(T_181659, T_181660)
    node T_181662 = bit(T_181249, 41)
    node T_181663 = and(idxValid[41], T_181662)
    node T_181664 = bit(T_181497, 41)
    node T_181665 = and(T_181663, T_181664)
    node T_181666 = bit(T_181249, 42)
    node T_181667 = and(idxValid[42], T_181666)
    node T_181668 = bit(T_181497, 42)
    node T_181669 = and(T_181667, T_181668)
    node T_181670 = bit(T_181249, 43)
    node T_181671 = and(idxValid[43], T_181670)
    node T_181672 = bit(T_181497, 43)
    node T_181673 = and(T_181671, T_181672)
    node T_181674 = bit(T_181249, 44)
    node T_181675 = and(idxValid[44], T_181674)
    node T_181676 = bit(T_181497, 44)
    node T_181677 = and(T_181675, T_181676)
    node T_181678 = bit(T_181249, 45)
    node T_181679 = and(idxValid[45], T_181678)
    node T_181680 = bit(T_181497, 45)
    node T_181681 = and(T_181679, T_181680)
    node T_181682 = bit(T_181249, 46)
    node T_181683 = and(idxValid[46], T_181682)
    node T_181684 = bit(T_181497, 46)
    node T_181685 = and(T_181683, T_181684)
    node T_181686 = bit(T_181249, 47)
    node T_181687 = and(idxValid[47], T_181686)
    node T_181688 = bit(T_181497, 47)
    node T_181689 = and(T_181687, T_181688)
    node T_181690 = bit(T_181249, 48)
    node T_181691 = and(idxValid[48], T_181690)
    node T_181692 = bit(T_181497, 48)
    node T_181693 = and(T_181691, T_181692)
    node T_181694 = bit(T_181249, 49)
    node T_181695 = and(idxValid[49], T_181694)
    node T_181696 = bit(T_181497, 49)
    node T_181697 = and(T_181695, T_181696)
    node T_181698 = bit(T_181249, 50)
    node T_181699 = and(idxValid[50], T_181698)
    node T_181700 = bit(T_181497, 50)
    node T_181701 = and(T_181699, T_181700)
    node T_181702 = bit(T_181249, 51)
    node T_181703 = and(idxValid[51], T_181702)
    node T_181704 = bit(T_181497, 51)
    node T_181705 = and(T_181703, T_181704)
    node T_181706 = bit(T_181249, 52)
    node T_181707 = and(idxValid[52], T_181706)
    node T_181708 = bit(T_181497, 52)
    node T_181709 = and(T_181707, T_181708)
    node T_181710 = bit(T_181249, 53)
    node T_181711 = and(idxValid[53], T_181710)
    node T_181712 = bit(T_181497, 53)
    node T_181713 = and(T_181711, T_181712)
    node T_181714 = bit(T_181249, 54)
    node T_181715 = and(idxValid[54], T_181714)
    node T_181716 = bit(T_181497, 54)
    node T_181717 = and(T_181715, T_181716)
    node T_181718 = bit(T_181249, 55)
    node T_181719 = and(idxValid[55], T_181718)
    node T_181720 = bit(T_181497, 55)
    node T_181721 = and(T_181719, T_181720)
    node T_181722 = bit(T_181249, 56)
    node T_181723 = and(idxValid[56], T_181722)
    node T_181724 = bit(T_181497, 56)
    node T_181725 = and(T_181723, T_181724)
    node T_181726 = bit(T_181249, 57)
    node T_181727 = and(idxValid[57], T_181726)
    node T_181728 = bit(T_181497, 57)
    node T_181729 = and(T_181727, T_181728)
    node T_181730 = bit(T_181249, 58)
    node T_181731 = and(idxValid[58], T_181730)
    node T_181732 = bit(T_181497, 58)
    node T_181733 = and(T_181731, T_181732)
    node T_181734 = bit(T_181249, 59)
    node T_181735 = and(idxValid[59], T_181734)
    node T_181736 = bit(T_181497, 59)
    node T_181737 = and(T_181735, T_181736)
    node T_181738 = bit(T_181249, 60)
    node T_181739 = and(idxValid[60], T_181738)
    node T_181740 = bit(T_181497, 60)
    node T_181741 = and(T_181739, T_181740)
    node T_181742 = bit(T_181249, 61)
    node T_181743 = and(idxValid[61], T_181742)
    node T_181744 = bit(T_181497, 61)
    node T_181745 = and(T_181743, T_181744)
    wire hits : UInt<1>[62]
    hits[0] := T_181501
    hits[1] := T_181505
    hits[2] := T_181509
    hits[3] := T_181513
    hits[4] := T_181517
    hits[5] := T_181521
    hits[6] := T_181525
    hits[7] := T_181529
    hits[8] := T_181533
    hits[9] := T_181537
    hits[10] := T_181541
    hits[11] := T_181545
    hits[12] := T_181549
    hits[13] := T_181553
    hits[14] := T_181557
    hits[15] := T_181561
    hits[16] := T_181565
    hits[17] := T_181569
    hits[18] := T_181573
    hits[19] := T_181577
    hits[20] := T_181581
    hits[21] := T_181585
    hits[22] := T_181589
    hits[23] := T_181593
    hits[24] := T_181597
    hits[25] := T_181601
    hits[26] := T_181605
    hits[27] := T_181609
    hits[28] := T_181613
    hits[29] := T_181617
    hits[30] := T_181621
    hits[31] := T_181625
    hits[32] := T_181629
    hits[33] := T_181633
    hits[34] := T_181637
    hits[35] := T_181641
    hits[36] := T_181645
    hits[37] := T_181649
    hits[38] := T_181653
    hits[39] := T_181657
    hits[40] := T_181661
    hits[41] := T_181665
    hits[42] := T_181669
    hits[43] := T_181673
    hits[44] := T_181677
    hits[45] := T_181681
    hits[46] := T_181685
    hits[47] := T_181689
    hits[48] := T_181693
    hits[49] := T_181697
    hits[50] := T_181701
    hits[51] := T_181705
    hits[52] := T_181709
    hits[53] := T_181713
    hits[54] := T_181717
    hits[55] := T_181721
    hits[56] := T_181725
    hits[57] := T_181729
    hits[58] := T_181733
    hits[59] := T_181737
    hits[60] := T_181741
    hits[61] := T_181745
    node T_181746 = shr(r_btb_update.bits.pc, 12)
    accessor T_181747 = pages[UInt<1>(0)]
    node T_181748 = eq(T_181747, T_181746)
    accessor T_181749 = pages[UInt<1>(1)]
    node T_181750 = eq(T_181749, T_181746)
    accessor T_181751 = pages[UInt<2>(2)]
    node T_181752 = eq(T_181751, T_181746)
    accessor T_181753 = pages[UInt<2>(3)]
    node T_181754 = eq(T_181753, T_181746)
    accessor T_181755 = pages[UInt<3>(4)]
    node T_181756 = eq(T_181755, T_181746)
    accessor T_181757 = pages[UInt<3>(5)]
    node T_181758 = eq(T_181757, T_181746)
    wire T_181759 : UInt<1>[6]
    T_181759[0] := T_181748
    T_181759[1] := T_181750
    T_181759[2] := T_181752
    T_181759[3] := T_181754
    T_181759[4] := T_181756
    T_181759[5] := T_181758
    node T_181760 = cat(T_181759[4], T_181759[3])
    node T_181761 = cat(T_181759[5], T_181760)
    node T_181762 = cat(T_181759[1], T_181759[0])
    node T_181763 = cat(T_181759[2], T_181762)
    node T_181764 = cat(T_181761, T_181763)
    node updatePageHit = and(T_181764, pageValid)
    node T_181765 = bits(r_btb_update.bits.pc, 11, 0)
    accessor T_181766 = idxs[UInt<1>(0)]
    node T_181767 = eq(T_181766, T_181765)
    accessor T_181768 = idxs[UInt<1>(1)]
    node T_181769 = eq(T_181768, T_181765)
    accessor T_181770 = idxs[UInt<2>(2)]
    node T_181771 = eq(T_181770, T_181765)
    accessor T_181772 = idxs[UInt<2>(3)]
    node T_181773 = eq(T_181772, T_181765)
    accessor T_181774 = idxs[UInt<3>(4)]
    node T_181775 = eq(T_181774, T_181765)
    accessor T_181776 = idxs[UInt<3>(5)]
    node T_181777 = eq(T_181776, T_181765)
    accessor T_181778 = idxs[UInt<3>(6)]
    node T_181779 = eq(T_181778, T_181765)
    accessor T_181780 = idxs[UInt<3>(7)]
    node T_181781 = eq(T_181780, T_181765)
    accessor T_181782 = idxs[UInt<4>(8)]
    node T_181783 = eq(T_181782, T_181765)
    accessor T_181784 = idxs[UInt<4>(9)]
    node T_181785 = eq(T_181784, T_181765)
    accessor T_181786 = idxs[UInt<4>(10)]
    node T_181787 = eq(T_181786, T_181765)
    accessor T_181788 = idxs[UInt<4>(11)]
    node T_181789 = eq(T_181788, T_181765)
    accessor T_181790 = idxs[UInt<4>(12)]
    node T_181791 = eq(T_181790, T_181765)
    accessor T_181792 = idxs[UInt<4>(13)]
    node T_181793 = eq(T_181792, T_181765)
    accessor T_181794 = idxs[UInt<4>(14)]
    node T_181795 = eq(T_181794, T_181765)
    accessor T_181796 = idxs[UInt<4>(15)]
    node T_181797 = eq(T_181796, T_181765)
    accessor T_181798 = idxs[UInt<5>(16)]
    node T_181799 = eq(T_181798, T_181765)
    accessor T_181800 = idxs[UInt<5>(17)]
    node T_181801 = eq(T_181800, T_181765)
    accessor T_181802 = idxs[UInt<5>(18)]
    node T_181803 = eq(T_181802, T_181765)
    accessor T_181804 = idxs[UInt<5>(19)]
    node T_181805 = eq(T_181804, T_181765)
    accessor T_181806 = idxs[UInt<5>(20)]
    node T_181807 = eq(T_181806, T_181765)
    accessor T_181808 = idxs[UInt<5>(21)]
    node T_181809 = eq(T_181808, T_181765)
    accessor T_181810 = idxs[UInt<5>(22)]
    node T_181811 = eq(T_181810, T_181765)
    accessor T_181812 = idxs[UInt<5>(23)]
    node T_181813 = eq(T_181812, T_181765)
    accessor T_181814 = idxs[UInt<5>(24)]
    node T_181815 = eq(T_181814, T_181765)
    accessor T_181816 = idxs[UInt<5>(25)]
    node T_181817 = eq(T_181816, T_181765)
    accessor T_181818 = idxs[UInt<5>(26)]
    node T_181819 = eq(T_181818, T_181765)
    accessor T_181820 = idxs[UInt<5>(27)]
    node T_181821 = eq(T_181820, T_181765)
    accessor T_181822 = idxs[UInt<5>(28)]
    node T_181823 = eq(T_181822, T_181765)
    accessor T_181824 = idxs[UInt<5>(29)]
    node T_181825 = eq(T_181824, T_181765)
    accessor T_181826 = idxs[UInt<5>(30)]
    node T_181827 = eq(T_181826, T_181765)
    accessor T_181828 = idxs[UInt<5>(31)]
    node T_181829 = eq(T_181828, T_181765)
    accessor T_181830 = idxs[UInt<6>(32)]
    node T_181831 = eq(T_181830, T_181765)
    accessor T_181832 = idxs[UInt<6>(33)]
    node T_181833 = eq(T_181832, T_181765)
    accessor T_181834 = idxs[UInt<6>(34)]
    node T_181835 = eq(T_181834, T_181765)
    accessor T_181836 = idxs[UInt<6>(35)]
    node T_181837 = eq(T_181836, T_181765)
    accessor T_181838 = idxs[UInt<6>(36)]
    node T_181839 = eq(T_181838, T_181765)
    accessor T_181840 = idxs[UInt<6>(37)]
    node T_181841 = eq(T_181840, T_181765)
    accessor T_181842 = idxs[UInt<6>(38)]
    node T_181843 = eq(T_181842, T_181765)
    accessor T_181844 = idxs[UInt<6>(39)]
    node T_181845 = eq(T_181844, T_181765)
    accessor T_181846 = idxs[UInt<6>(40)]
    node T_181847 = eq(T_181846, T_181765)
    accessor T_181848 = idxs[UInt<6>(41)]
    node T_181849 = eq(T_181848, T_181765)
    accessor T_181850 = idxs[UInt<6>(42)]
    node T_181851 = eq(T_181850, T_181765)
    accessor T_181852 = idxs[UInt<6>(43)]
    node T_181853 = eq(T_181852, T_181765)
    accessor T_181854 = idxs[UInt<6>(44)]
    node T_181855 = eq(T_181854, T_181765)
    accessor T_181856 = idxs[UInt<6>(45)]
    node T_181857 = eq(T_181856, T_181765)
    accessor T_181858 = idxs[UInt<6>(46)]
    node T_181859 = eq(T_181858, T_181765)
    accessor T_181860 = idxs[UInt<6>(47)]
    node T_181861 = eq(T_181860, T_181765)
    accessor T_181862 = idxs[UInt<6>(48)]
    node T_181863 = eq(T_181862, T_181765)
    accessor T_181864 = idxs[UInt<6>(49)]
    node T_181865 = eq(T_181864, T_181765)
    accessor T_181866 = idxs[UInt<6>(50)]
    node T_181867 = eq(T_181866, T_181765)
    accessor T_181868 = idxs[UInt<6>(51)]
    node T_181869 = eq(T_181868, T_181765)
    accessor T_181870 = idxs[UInt<6>(52)]
    node T_181871 = eq(T_181870, T_181765)
    accessor T_181872 = idxs[UInt<6>(53)]
    node T_181873 = eq(T_181872, T_181765)
    accessor T_181874 = idxs[UInt<6>(54)]
    node T_181875 = eq(T_181874, T_181765)
    accessor T_181876 = idxs[UInt<6>(55)]
    node T_181877 = eq(T_181876, T_181765)
    accessor T_181878 = idxs[UInt<6>(56)]
    node T_181879 = eq(T_181878, T_181765)
    accessor T_181880 = idxs[UInt<6>(57)]
    node T_181881 = eq(T_181880, T_181765)
    accessor T_181882 = idxs[UInt<6>(58)]
    node T_181883 = eq(T_181882, T_181765)
    accessor T_181884 = idxs[UInt<6>(59)]
    node T_181885 = eq(T_181884, T_181765)
    accessor T_181886 = idxs[UInt<6>(60)]
    node T_181887 = eq(T_181886, T_181765)
    accessor T_181888 = idxs[UInt<6>(61)]
    node T_181889 = eq(T_181888, T_181765)
    wire T_181890 : UInt<1>[62]
    T_181890[0] := T_181767
    T_181890[1] := T_181769
    T_181890[2] := T_181771
    T_181890[3] := T_181773
    T_181890[4] := T_181775
    T_181890[5] := T_181777
    T_181890[6] := T_181779
    T_181890[7] := T_181781
    T_181890[8] := T_181783
    T_181890[9] := T_181785
    T_181890[10] := T_181787
    T_181890[11] := T_181789
    T_181890[12] := T_181791
    T_181890[13] := T_181793
    T_181890[14] := T_181795
    T_181890[15] := T_181797
    T_181890[16] := T_181799
    T_181890[17] := T_181801
    T_181890[18] := T_181803
    T_181890[19] := T_181805
    T_181890[20] := T_181807
    T_181890[21] := T_181809
    T_181890[22] := T_181811
    T_181890[23] := T_181813
    T_181890[24] := T_181815
    T_181890[25] := T_181817
    T_181890[26] := T_181819
    T_181890[27] := T_181821
    T_181890[28] := T_181823
    T_181890[29] := T_181825
    T_181890[30] := T_181827
    T_181890[31] := T_181829
    T_181890[32] := T_181831
    T_181890[33] := T_181833
    T_181890[34] := T_181835
    T_181890[35] := T_181837
    T_181890[36] := T_181839
    T_181890[37] := T_181841
    T_181890[38] := T_181843
    T_181890[39] := T_181845
    T_181890[40] := T_181847
    T_181890[41] := T_181849
    T_181890[42] := T_181851
    T_181890[43] := T_181853
    T_181890[44] := T_181855
    T_181890[45] := T_181857
    T_181890[46] := T_181859
    T_181890[47] := T_181861
    T_181890[48] := T_181863
    T_181890[49] := T_181865
    T_181890[50] := T_181867
    T_181890[51] := T_181869
    T_181890[52] := T_181871
    T_181890[53] := T_181873
    T_181890[54] := T_181875
    T_181890[55] := T_181877
    T_181890[56] := T_181879
    T_181890[57] := T_181881
    T_181890[58] := T_181883
    T_181890[59] := T_181885
    T_181890[60] := T_181887
    T_181890[61] := T_181889
    node T_181891 = cat(T_181890[60], T_181890[59])
    node T_181892 = cat(T_181890[61], T_181891)
    node T_181893 = cat(T_181890[58], T_181890[57])
    node T_181894 = cat(T_181890[56], T_181890[55])
    node T_181895 = cat(T_181893, T_181894)
    node T_181896 = cat(T_181892, T_181895)
    node T_181897 = cat(T_181890[54], T_181890[53])
    node T_181898 = cat(T_181890[52], T_181890[51])
    node T_181899 = cat(T_181897, T_181898)
    node T_181900 = cat(T_181890[50], T_181890[49])
    node T_181901 = cat(T_181890[48], T_181890[47])
    node T_181902 = cat(T_181900, T_181901)
    node T_181903 = cat(T_181899, T_181902)
    node T_181904 = cat(T_181896, T_181903)
    node T_181905 = cat(T_181890[46], T_181890[45])
    node T_181906 = cat(T_181890[44], T_181890[43])
    node T_181907 = cat(T_181905, T_181906)
    node T_181908 = cat(T_181890[42], T_181890[41])
    node T_181909 = cat(T_181890[40], T_181890[39])
    node T_181910 = cat(T_181908, T_181909)
    node T_181911 = cat(T_181907, T_181910)
    node T_181912 = cat(T_181890[38], T_181890[37])
    node T_181913 = cat(T_181890[36], T_181890[35])
    node T_181914 = cat(T_181912, T_181913)
    node T_181915 = cat(T_181890[34], T_181890[33])
    node T_181916 = cat(T_181890[32], T_181890[31])
    node T_181917 = cat(T_181915, T_181916)
    node T_181918 = cat(T_181914, T_181917)
    node T_181919 = cat(T_181911, T_181918)
    node T_181920 = cat(T_181904, T_181919)
    node T_181921 = cat(T_181890[29], T_181890[28])
    node T_181922 = cat(T_181890[30], T_181921)
    node T_181923 = cat(T_181890[27], T_181890[26])
    node T_181924 = cat(T_181890[25], T_181890[24])
    node T_181925 = cat(T_181923, T_181924)
    node T_181926 = cat(T_181922, T_181925)
    node T_181927 = cat(T_181890[23], T_181890[22])
    node T_181928 = cat(T_181890[21], T_181890[20])
    node T_181929 = cat(T_181927, T_181928)
    node T_181930 = cat(T_181890[19], T_181890[18])
    node T_181931 = cat(T_181890[17], T_181890[16])
    node T_181932 = cat(T_181930, T_181931)
    node T_181933 = cat(T_181929, T_181932)
    node T_181934 = cat(T_181926, T_181933)
    node T_181935 = cat(T_181890[15], T_181890[14])
    node T_181936 = cat(T_181890[13], T_181890[12])
    node T_181937 = cat(T_181935, T_181936)
    node T_181938 = cat(T_181890[11], T_181890[10])
    node T_181939 = cat(T_181890[9], T_181890[8])
    node T_181940 = cat(T_181938, T_181939)
    node T_181941 = cat(T_181937, T_181940)
    node T_181942 = cat(T_181890[7], T_181890[6])
    node T_181943 = cat(T_181890[5], T_181890[4])
    node T_181944 = cat(T_181942, T_181943)
    node T_181945 = cat(T_181890[3], T_181890[2])
    node T_181946 = cat(T_181890[1], T_181890[0])
    node T_181947 = cat(T_181945, T_181946)
    node T_181948 = cat(T_181944, T_181947)
    node T_181949 = cat(T_181941, T_181948)
    node T_181950 = cat(T_181934, T_181949)
    node T_181951 = cat(T_181920, T_181950)
    node T_181952 = and(T_180672, updatePageHit)
    node T_181953 = and(T_180675, updatePageHit)
    node T_181954 = and(T_180678, updatePageHit)
    node T_181955 = and(T_180681, updatePageHit)
    node T_181956 = and(T_180684, updatePageHit)
    node T_181957 = and(T_180687, updatePageHit)
    node T_181958 = and(T_180690, updatePageHit)
    node T_181959 = and(T_180693, updatePageHit)
    node T_181960 = and(T_180696, updatePageHit)
    node T_181961 = and(T_180699, updatePageHit)
    node T_181962 = and(T_180702, updatePageHit)
    node T_181963 = and(T_180705, updatePageHit)
    node T_181964 = and(T_180708, updatePageHit)
    node T_181965 = and(T_180711, updatePageHit)
    node T_181966 = and(T_180714, updatePageHit)
    node T_181967 = and(T_180717, updatePageHit)
    node T_181968 = and(T_180720, updatePageHit)
    node T_181969 = and(T_180723, updatePageHit)
    node T_181970 = and(T_180726, updatePageHit)
    node T_181971 = and(T_180729, updatePageHit)
    node T_181972 = and(T_180732, updatePageHit)
    node T_181973 = and(T_180735, updatePageHit)
    node T_181974 = and(T_180738, updatePageHit)
    node T_181975 = and(T_180741, updatePageHit)
    node T_181976 = and(T_180744, updatePageHit)
    node T_181977 = and(T_180747, updatePageHit)
    node T_181978 = and(T_180750, updatePageHit)
    node T_181979 = and(T_180753, updatePageHit)
    node T_181980 = and(T_180756, updatePageHit)
    node T_181981 = and(T_180759, updatePageHit)
    node T_181982 = and(T_180762, updatePageHit)
    node T_181983 = and(T_180765, updatePageHit)
    node T_181984 = and(T_180768, updatePageHit)
    node T_181985 = and(T_180771, updatePageHit)
    node T_181986 = and(T_180774, updatePageHit)
    node T_181987 = and(T_180777, updatePageHit)
    node T_181988 = and(T_180780, updatePageHit)
    node T_181989 = and(T_180783, updatePageHit)
    node T_181990 = and(T_180786, updatePageHit)
    node T_181991 = and(T_180789, updatePageHit)
    node T_181992 = and(T_180792, updatePageHit)
    node T_181993 = and(T_180795, updatePageHit)
    node T_181994 = and(T_180798, updatePageHit)
    node T_181995 = and(T_180801, updatePageHit)
    node T_181996 = and(T_180804, updatePageHit)
    node T_181997 = and(T_180807, updatePageHit)
    node T_181998 = and(T_180810, updatePageHit)
    node T_181999 = and(T_180813, updatePageHit)
    node T_182000 = and(T_180816, updatePageHit)
    node T_182001 = and(T_180819, updatePageHit)
    node T_182002 = and(T_180822, updatePageHit)
    node T_182003 = and(T_180825, updatePageHit)
    node T_182004 = and(T_180828, updatePageHit)
    node T_182005 = and(T_180831, updatePageHit)
    node T_182006 = and(T_180834, updatePageHit)
    node T_182007 = and(T_180837, updatePageHit)
    node T_182008 = and(T_180840, updatePageHit)
    node T_182009 = and(T_180843, updatePageHit)
    node T_182010 = and(T_180846, updatePageHit)
    node T_182011 = and(T_180849, updatePageHit)
    node T_182012 = and(T_180852, updatePageHit)
    node T_182013 = and(T_180855, updatePageHit)
    node T_182014 = eq(T_181952, UInt<1>(0))
    node T_182015 = eq(T_182014, UInt<1>(0))
    node T_182016 = eq(T_181953, UInt<1>(0))
    node T_182017 = eq(T_182016, UInt<1>(0))
    node T_182018 = eq(T_181954, UInt<1>(0))
    node T_182019 = eq(T_182018, UInt<1>(0))
    node T_182020 = eq(T_181955, UInt<1>(0))
    node T_182021 = eq(T_182020, UInt<1>(0))
    node T_182022 = eq(T_181956, UInt<1>(0))
    node T_182023 = eq(T_182022, UInt<1>(0))
    node T_182024 = eq(T_181957, UInt<1>(0))
    node T_182025 = eq(T_182024, UInt<1>(0))
    node T_182026 = eq(T_181958, UInt<1>(0))
    node T_182027 = eq(T_182026, UInt<1>(0))
    node T_182028 = eq(T_181959, UInt<1>(0))
    node T_182029 = eq(T_182028, UInt<1>(0))
    node T_182030 = eq(T_181960, UInt<1>(0))
    node T_182031 = eq(T_182030, UInt<1>(0))
    node T_182032 = eq(T_181961, UInt<1>(0))
    node T_182033 = eq(T_182032, UInt<1>(0))
    node T_182034 = eq(T_181962, UInt<1>(0))
    node T_182035 = eq(T_182034, UInt<1>(0))
    node T_182036 = eq(T_181963, UInt<1>(0))
    node T_182037 = eq(T_182036, UInt<1>(0))
    node T_182038 = eq(T_181964, UInt<1>(0))
    node T_182039 = eq(T_182038, UInt<1>(0))
    node T_182040 = eq(T_181965, UInt<1>(0))
    node T_182041 = eq(T_182040, UInt<1>(0))
    node T_182042 = eq(T_181966, UInt<1>(0))
    node T_182043 = eq(T_182042, UInt<1>(0))
    node T_182044 = eq(T_181967, UInt<1>(0))
    node T_182045 = eq(T_182044, UInt<1>(0))
    node T_182046 = eq(T_181968, UInt<1>(0))
    node T_182047 = eq(T_182046, UInt<1>(0))
    node T_182048 = eq(T_181969, UInt<1>(0))
    node T_182049 = eq(T_182048, UInt<1>(0))
    node T_182050 = eq(T_181970, UInt<1>(0))
    node T_182051 = eq(T_182050, UInt<1>(0))
    node T_182052 = eq(T_181971, UInt<1>(0))
    node T_182053 = eq(T_182052, UInt<1>(0))
    node T_182054 = eq(T_181972, UInt<1>(0))
    node T_182055 = eq(T_182054, UInt<1>(0))
    node T_182056 = eq(T_181973, UInt<1>(0))
    node T_182057 = eq(T_182056, UInt<1>(0))
    node T_182058 = eq(T_181974, UInt<1>(0))
    node T_182059 = eq(T_182058, UInt<1>(0))
    node T_182060 = eq(T_181975, UInt<1>(0))
    node T_182061 = eq(T_182060, UInt<1>(0))
    node T_182062 = eq(T_181976, UInt<1>(0))
    node T_182063 = eq(T_182062, UInt<1>(0))
    node T_182064 = eq(T_181977, UInt<1>(0))
    node T_182065 = eq(T_182064, UInt<1>(0))
    node T_182066 = eq(T_181978, UInt<1>(0))
    node T_182067 = eq(T_182066, UInt<1>(0))
    node T_182068 = eq(T_181979, UInt<1>(0))
    node T_182069 = eq(T_182068, UInt<1>(0))
    node T_182070 = eq(T_181980, UInt<1>(0))
    node T_182071 = eq(T_182070, UInt<1>(0))
    node T_182072 = eq(T_181981, UInt<1>(0))
    node T_182073 = eq(T_182072, UInt<1>(0))
    node T_182074 = eq(T_181982, UInt<1>(0))
    node T_182075 = eq(T_182074, UInt<1>(0))
    node T_182076 = eq(T_181983, UInt<1>(0))
    node T_182077 = eq(T_182076, UInt<1>(0))
    node T_182078 = eq(T_181984, UInt<1>(0))
    node T_182079 = eq(T_182078, UInt<1>(0))
    node T_182080 = eq(T_181985, UInt<1>(0))
    node T_182081 = eq(T_182080, UInt<1>(0))
    node T_182082 = eq(T_181986, UInt<1>(0))
    node T_182083 = eq(T_182082, UInt<1>(0))
    node T_182084 = eq(T_181987, UInt<1>(0))
    node T_182085 = eq(T_182084, UInt<1>(0))
    node T_182086 = eq(T_181988, UInt<1>(0))
    node T_182087 = eq(T_182086, UInt<1>(0))
    node T_182088 = eq(T_181989, UInt<1>(0))
    node T_182089 = eq(T_182088, UInt<1>(0))
    node T_182090 = eq(T_181990, UInt<1>(0))
    node T_182091 = eq(T_182090, UInt<1>(0))
    node T_182092 = eq(T_181991, UInt<1>(0))
    node T_182093 = eq(T_182092, UInt<1>(0))
    node T_182094 = eq(T_181992, UInt<1>(0))
    node T_182095 = eq(T_182094, UInt<1>(0))
    node T_182096 = eq(T_181993, UInt<1>(0))
    node T_182097 = eq(T_182096, UInt<1>(0))
    node T_182098 = eq(T_181994, UInt<1>(0))
    node T_182099 = eq(T_182098, UInt<1>(0))
    node T_182100 = eq(T_181995, UInt<1>(0))
    node T_182101 = eq(T_182100, UInt<1>(0))
    node T_182102 = eq(T_181996, UInt<1>(0))
    node T_182103 = eq(T_182102, UInt<1>(0))
    node T_182104 = eq(T_181997, UInt<1>(0))
    node T_182105 = eq(T_182104, UInt<1>(0))
    node T_182106 = eq(T_181998, UInt<1>(0))
    node T_182107 = eq(T_182106, UInt<1>(0))
    node T_182108 = eq(T_181999, UInt<1>(0))
    node T_182109 = eq(T_182108, UInt<1>(0))
    node T_182110 = eq(T_182000, UInt<1>(0))
    node T_182111 = eq(T_182110, UInt<1>(0))
    node T_182112 = eq(T_182001, UInt<1>(0))
    node T_182113 = eq(T_182112, UInt<1>(0))
    node T_182114 = eq(T_182002, UInt<1>(0))
    node T_182115 = eq(T_182114, UInt<1>(0))
    node T_182116 = eq(T_182003, UInt<1>(0))
    node T_182117 = eq(T_182116, UInt<1>(0))
    node T_182118 = eq(T_182004, UInt<1>(0))
    node T_182119 = eq(T_182118, UInt<1>(0))
    node T_182120 = eq(T_182005, UInt<1>(0))
    node T_182121 = eq(T_182120, UInt<1>(0))
    node T_182122 = eq(T_182006, UInt<1>(0))
    node T_182123 = eq(T_182122, UInt<1>(0))
    node T_182124 = eq(T_182007, UInt<1>(0))
    node T_182125 = eq(T_182124, UInt<1>(0))
    node T_182126 = eq(T_182008, UInt<1>(0))
    node T_182127 = eq(T_182126, UInt<1>(0))
    node T_182128 = eq(T_182009, UInt<1>(0))
    node T_182129 = eq(T_182128, UInt<1>(0))
    node T_182130 = eq(T_182010, UInt<1>(0))
    node T_182131 = eq(T_182130, UInt<1>(0))
    node T_182132 = eq(T_182011, UInt<1>(0))
    node T_182133 = eq(T_182132, UInt<1>(0))
    node T_182134 = eq(T_182012, UInt<1>(0))
    node T_182135 = eq(T_182134, UInt<1>(0))
    node T_182136 = eq(T_182013, UInt<1>(0))
    node T_182137 = eq(T_182136, UInt<1>(0))
    wire T_182138 : UInt<1>[62]
    T_182138[0] := T_182015
    T_182138[1] := T_182017
    T_182138[2] := T_182019
    T_182138[3] := T_182021
    T_182138[4] := T_182023
    T_182138[5] := T_182025
    T_182138[6] := T_182027
    T_182138[7] := T_182029
    T_182138[8] := T_182031
    T_182138[9] := T_182033
    T_182138[10] := T_182035
    T_182138[11] := T_182037
    T_182138[12] := T_182039
    T_182138[13] := T_182041
    T_182138[14] := T_182043
    T_182138[15] := T_182045
    T_182138[16] := T_182047
    T_182138[17] := T_182049
    T_182138[18] := T_182051
    T_182138[19] := T_182053
    T_182138[20] := T_182055
    T_182138[21] := T_182057
    T_182138[22] := T_182059
    T_182138[23] := T_182061
    T_182138[24] := T_182063
    T_182138[25] := T_182065
    T_182138[26] := T_182067
    T_182138[27] := T_182069
    T_182138[28] := T_182071
    T_182138[29] := T_182073
    T_182138[30] := T_182075
    T_182138[31] := T_182077
    T_182138[32] := T_182079
    T_182138[33] := T_182081
    T_182138[34] := T_182083
    T_182138[35] := T_182085
    T_182138[36] := T_182087
    T_182138[37] := T_182089
    T_182138[38] := T_182091
    T_182138[39] := T_182093
    T_182138[40] := T_182095
    T_182138[41] := T_182097
    T_182138[42] := T_182099
    T_182138[43] := T_182101
    T_182138[44] := T_182103
    T_182138[45] := T_182105
    T_182138[46] := T_182107
    T_182138[47] := T_182109
    T_182138[48] := T_182111
    T_182138[49] := T_182113
    T_182138[50] := T_182115
    T_182138[51] := T_182117
    T_182138[52] := T_182119
    T_182138[53] := T_182121
    T_182138[54] := T_182123
    T_182138[55] := T_182125
    T_182138[56] := T_182127
    T_182138[57] := T_182129
    T_182138[58] := T_182131
    T_182138[59] := T_182133
    T_182138[60] := T_182135
    T_182138[61] := T_182137
    node T_182139 = cat(T_182138[60], T_182138[59])
    node T_182140 = cat(T_182138[61], T_182139)
    node T_182141 = cat(T_182138[58], T_182138[57])
    node T_182142 = cat(T_182138[56], T_182138[55])
    node T_182143 = cat(T_182141, T_182142)
    node T_182144 = cat(T_182140, T_182143)
    node T_182145 = cat(T_182138[54], T_182138[53])
    node T_182146 = cat(T_182138[52], T_182138[51])
    node T_182147 = cat(T_182145, T_182146)
    node T_182148 = cat(T_182138[50], T_182138[49])
    node T_182149 = cat(T_182138[48], T_182138[47])
    node T_182150 = cat(T_182148, T_182149)
    node T_182151 = cat(T_182147, T_182150)
    node T_182152 = cat(T_182144, T_182151)
    node T_182153 = cat(T_182138[46], T_182138[45])
    node T_182154 = cat(T_182138[44], T_182138[43])
    node T_182155 = cat(T_182153, T_182154)
    node T_182156 = cat(T_182138[42], T_182138[41])
    node T_182157 = cat(T_182138[40], T_182138[39])
    node T_182158 = cat(T_182156, T_182157)
    node T_182159 = cat(T_182155, T_182158)
    node T_182160 = cat(T_182138[38], T_182138[37])
    node T_182161 = cat(T_182138[36], T_182138[35])
    node T_182162 = cat(T_182160, T_182161)
    node T_182163 = cat(T_182138[34], T_182138[33])
    node T_182164 = cat(T_182138[32], T_182138[31])
    node T_182165 = cat(T_182163, T_182164)
    node T_182166 = cat(T_182162, T_182165)
    node T_182167 = cat(T_182159, T_182166)
    node T_182168 = cat(T_182152, T_182167)
    node T_182169 = cat(T_182138[29], T_182138[28])
    node T_182170 = cat(T_182138[30], T_182169)
    node T_182171 = cat(T_182138[27], T_182138[26])
    node T_182172 = cat(T_182138[25], T_182138[24])
    node T_182173 = cat(T_182171, T_182172)
    node T_182174 = cat(T_182170, T_182173)
    node T_182175 = cat(T_182138[23], T_182138[22])
    node T_182176 = cat(T_182138[21], T_182138[20])
    node T_182177 = cat(T_182175, T_182176)
    node T_182178 = cat(T_182138[19], T_182138[18])
    node T_182179 = cat(T_182138[17], T_182138[16])
    node T_182180 = cat(T_182178, T_182179)
    node T_182181 = cat(T_182177, T_182180)
    node T_182182 = cat(T_182174, T_182181)
    node T_182183 = cat(T_182138[15], T_182138[14])
    node T_182184 = cat(T_182138[13], T_182138[12])
    node T_182185 = cat(T_182183, T_182184)
    node T_182186 = cat(T_182138[11], T_182138[10])
    node T_182187 = cat(T_182138[9], T_182138[8])
    node T_182188 = cat(T_182186, T_182187)
    node T_182189 = cat(T_182185, T_182188)
    node T_182190 = cat(T_182138[7], T_182138[6])
    node T_182191 = cat(T_182138[5], T_182138[4])
    node T_182192 = cat(T_182190, T_182191)
    node T_182193 = cat(T_182138[3], T_182138[2])
    node T_182194 = cat(T_182138[1], T_182138[0])
    node T_182195 = cat(T_182193, T_182194)
    node T_182196 = cat(T_182192, T_182195)
    node T_182197 = cat(T_182189, T_182196)
    node T_182198 = cat(T_182182, T_182197)
    node T_182199 = cat(T_182168, T_182198)
    node T_182200 = bit(T_181951, 0)
    node T_182201 = and(idxValid[0], T_182200)
    node T_182202 = bit(T_182199, 0)
    node T_182203 = and(T_182201, T_182202)
    node T_182204 = bit(T_181951, 1)
    node T_182205 = and(idxValid[1], T_182204)
    node T_182206 = bit(T_182199, 1)
    node T_182207 = and(T_182205, T_182206)
    node T_182208 = bit(T_181951, 2)
    node T_182209 = and(idxValid[2], T_182208)
    node T_182210 = bit(T_182199, 2)
    node T_182211 = and(T_182209, T_182210)
    node T_182212 = bit(T_181951, 3)
    node T_182213 = and(idxValid[3], T_182212)
    node T_182214 = bit(T_182199, 3)
    node T_182215 = and(T_182213, T_182214)
    node T_182216 = bit(T_181951, 4)
    node T_182217 = and(idxValid[4], T_182216)
    node T_182218 = bit(T_182199, 4)
    node T_182219 = and(T_182217, T_182218)
    node T_182220 = bit(T_181951, 5)
    node T_182221 = and(idxValid[5], T_182220)
    node T_182222 = bit(T_182199, 5)
    node T_182223 = and(T_182221, T_182222)
    node T_182224 = bit(T_181951, 6)
    node T_182225 = and(idxValid[6], T_182224)
    node T_182226 = bit(T_182199, 6)
    node T_182227 = and(T_182225, T_182226)
    node T_182228 = bit(T_181951, 7)
    node T_182229 = and(idxValid[7], T_182228)
    node T_182230 = bit(T_182199, 7)
    node T_182231 = and(T_182229, T_182230)
    node T_182232 = bit(T_181951, 8)
    node T_182233 = and(idxValid[8], T_182232)
    node T_182234 = bit(T_182199, 8)
    node T_182235 = and(T_182233, T_182234)
    node T_182236 = bit(T_181951, 9)
    node T_182237 = and(idxValid[9], T_182236)
    node T_182238 = bit(T_182199, 9)
    node T_182239 = and(T_182237, T_182238)
    node T_182240 = bit(T_181951, 10)
    node T_182241 = and(idxValid[10], T_182240)
    node T_182242 = bit(T_182199, 10)
    node T_182243 = and(T_182241, T_182242)
    node T_182244 = bit(T_181951, 11)
    node T_182245 = and(idxValid[11], T_182244)
    node T_182246 = bit(T_182199, 11)
    node T_182247 = and(T_182245, T_182246)
    node T_182248 = bit(T_181951, 12)
    node T_182249 = and(idxValid[12], T_182248)
    node T_182250 = bit(T_182199, 12)
    node T_182251 = and(T_182249, T_182250)
    node T_182252 = bit(T_181951, 13)
    node T_182253 = and(idxValid[13], T_182252)
    node T_182254 = bit(T_182199, 13)
    node T_182255 = and(T_182253, T_182254)
    node T_182256 = bit(T_181951, 14)
    node T_182257 = and(idxValid[14], T_182256)
    node T_182258 = bit(T_182199, 14)
    node T_182259 = and(T_182257, T_182258)
    node T_182260 = bit(T_181951, 15)
    node T_182261 = and(idxValid[15], T_182260)
    node T_182262 = bit(T_182199, 15)
    node T_182263 = and(T_182261, T_182262)
    node T_182264 = bit(T_181951, 16)
    node T_182265 = and(idxValid[16], T_182264)
    node T_182266 = bit(T_182199, 16)
    node T_182267 = and(T_182265, T_182266)
    node T_182268 = bit(T_181951, 17)
    node T_182269 = and(idxValid[17], T_182268)
    node T_182270 = bit(T_182199, 17)
    node T_182271 = and(T_182269, T_182270)
    node T_182272 = bit(T_181951, 18)
    node T_182273 = and(idxValid[18], T_182272)
    node T_182274 = bit(T_182199, 18)
    node T_182275 = and(T_182273, T_182274)
    node T_182276 = bit(T_181951, 19)
    node T_182277 = and(idxValid[19], T_182276)
    node T_182278 = bit(T_182199, 19)
    node T_182279 = and(T_182277, T_182278)
    node T_182280 = bit(T_181951, 20)
    node T_182281 = and(idxValid[20], T_182280)
    node T_182282 = bit(T_182199, 20)
    node T_182283 = and(T_182281, T_182282)
    node T_182284 = bit(T_181951, 21)
    node T_182285 = and(idxValid[21], T_182284)
    node T_182286 = bit(T_182199, 21)
    node T_182287 = and(T_182285, T_182286)
    node T_182288 = bit(T_181951, 22)
    node T_182289 = and(idxValid[22], T_182288)
    node T_182290 = bit(T_182199, 22)
    node T_182291 = and(T_182289, T_182290)
    node T_182292 = bit(T_181951, 23)
    node T_182293 = and(idxValid[23], T_182292)
    node T_182294 = bit(T_182199, 23)
    node T_182295 = and(T_182293, T_182294)
    node T_182296 = bit(T_181951, 24)
    node T_182297 = and(idxValid[24], T_182296)
    node T_182298 = bit(T_182199, 24)
    node T_182299 = and(T_182297, T_182298)
    node T_182300 = bit(T_181951, 25)
    node T_182301 = and(idxValid[25], T_182300)
    node T_182302 = bit(T_182199, 25)
    node T_182303 = and(T_182301, T_182302)
    node T_182304 = bit(T_181951, 26)
    node T_182305 = and(idxValid[26], T_182304)
    node T_182306 = bit(T_182199, 26)
    node T_182307 = and(T_182305, T_182306)
    node T_182308 = bit(T_181951, 27)
    node T_182309 = and(idxValid[27], T_182308)
    node T_182310 = bit(T_182199, 27)
    node T_182311 = and(T_182309, T_182310)
    node T_182312 = bit(T_181951, 28)
    node T_182313 = and(idxValid[28], T_182312)
    node T_182314 = bit(T_182199, 28)
    node T_182315 = and(T_182313, T_182314)
    node T_182316 = bit(T_181951, 29)
    node T_182317 = and(idxValid[29], T_182316)
    node T_182318 = bit(T_182199, 29)
    node T_182319 = and(T_182317, T_182318)
    node T_182320 = bit(T_181951, 30)
    node T_182321 = and(idxValid[30], T_182320)
    node T_182322 = bit(T_182199, 30)
    node T_182323 = and(T_182321, T_182322)
    node T_182324 = bit(T_181951, 31)
    node T_182325 = and(idxValid[31], T_182324)
    node T_182326 = bit(T_182199, 31)
    node T_182327 = and(T_182325, T_182326)
    node T_182328 = bit(T_181951, 32)
    node T_182329 = and(idxValid[32], T_182328)
    node T_182330 = bit(T_182199, 32)
    node T_182331 = and(T_182329, T_182330)
    node T_182332 = bit(T_181951, 33)
    node T_182333 = and(idxValid[33], T_182332)
    node T_182334 = bit(T_182199, 33)
    node T_182335 = and(T_182333, T_182334)
    node T_182336 = bit(T_181951, 34)
    node T_182337 = and(idxValid[34], T_182336)
    node T_182338 = bit(T_182199, 34)
    node T_182339 = and(T_182337, T_182338)
    node T_182340 = bit(T_181951, 35)
    node T_182341 = and(idxValid[35], T_182340)
    node T_182342 = bit(T_182199, 35)
    node T_182343 = and(T_182341, T_182342)
    node T_182344 = bit(T_181951, 36)
    node T_182345 = and(idxValid[36], T_182344)
    node T_182346 = bit(T_182199, 36)
    node T_182347 = and(T_182345, T_182346)
    node T_182348 = bit(T_181951, 37)
    node T_182349 = and(idxValid[37], T_182348)
    node T_182350 = bit(T_182199, 37)
    node T_182351 = and(T_182349, T_182350)
    node T_182352 = bit(T_181951, 38)
    node T_182353 = and(idxValid[38], T_182352)
    node T_182354 = bit(T_182199, 38)
    node T_182355 = and(T_182353, T_182354)
    node T_182356 = bit(T_181951, 39)
    node T_182357 = and(idxValid[39], T_182356)
    node T_182358 = bit(T_182199, 39)
    node T_182359 = and(T_182357, T_182358)
    node T_182360 = bit(T_181951, 40)
    node T_182361 = and(idxValid[40], T_182360)
    node T_182362 = bit(T_182199, 40)
    node T_182363 = and(T_182361, T_182362)
    node T_182364 = bit(T_181951, 41)
    node T_182365 = and(idxValid[41], T_182364)
    node T_182366 = bit(T_182199, 41)
    node T_182367 = and(T_182365, T_182366)
    node T_182368 = bit(T_181951, 42)
    node T_182369 = and(idxValid[42], T_182368)
    node T_182370 = bit(T_182199, 42)
    node T_182371 = and(T_182369, T_182370)
    node T_182372 = bit(T_181951, 43)
    node T_182373 = and(idxValid[43], T_182372)
    node T_182374 = bit(T_182199, 43)
    node T_182375 = and(T_182373, T_182374)
    node T_182376 = bit(T_181951, 44)
    node T_182377 = and(idxValid[44], T_182376)
    node T_182378 = bit(T_182199, 44)
    node T_182379 = and(T_182377, T_182378)
    node T_182380 = bit(T_181951, 45)
    node T_182381 = and(idxValid[45], T_182380)
    node T_182382 = bit(T_182199, 45)
    node T_182383 = and(T_182381, T_182382)
    node T_182384 = bit(T_181951, 46)
    node T_182385 = and(idxValid[46], T_182384)
    node T_182386 = bit(T_182199, 46)
    node T_182387 = and(T_182385, T_182386)
    node T_182388 = bit(T_181951, 47)
    node T_182389 = and(idxValid[47], T_182388)
    node T_182390 = bit(T_182199, 47)
    node T_182391 = and(T_182389, T_182390)
    node T_182392 = bit(T_181951, 48)
    node T_182393 = and(idxValid[48], T_182392)
    node T_182394 = bit(T_182199, 48)
    node T_182395 = and(T_182393, T_182394)
    node T_182396 = bit(T_181951, 49)
    node T_182397 = and(idxValid[49], T_182396)
    node T_182398 = bit(T_182199, 49)
    node T_182399 = and(T_182397, T_182398)
    node T_182400 = bit(T_181951, 50)
    node T_182401 = and(idxValid[50], T_182400)
    node T_182402 = bit(T_182199, 50)
    node T_182403 = and(T_182401, T_182402)
    node T_182404 = bit(T_181951, 51)
    node T_182405 = and(idxValid[51], T_182404)
    node T_182406 = bit(T_182199, 51)
    node T_182407 = and(T_182405, T_182406)
    node T_182408 = bit(T_181951, 52)
    node T_182409 = and(idxValid[52], T_182408)
    node T_182410 = bit(T_182199, 52)
    node T_182411 = and(T_182409, T_182410)
    node T_182412 = bit(T_181951, 53)
    node T_182413 = and(idxValid[53], T_182412)
    node T_182414 = bit(T_182199, 53)
    node T_182415 = and(T_182413, T_182414)
    node T_182416 = bit(T_181951, 54)
    node T_182417 = and(idxValid[54], T_182416)
    node T_182418 = bit(T_182199, 54)
    node T_182419 = and(T_182417, T_182418)
    node T_182420 = bit(T_181951, 55)
    node T_182421 = and(idxValid[55], T_182420)
    node T_182422 = bit(T_182199, 55)
    node T_182423 = and(T_182421, T_182422)
    node T_182424 = bit(T_181951, 56)
    node T_182425 = and(idxValid[56], T_182424)
    node T_182426 = bit(T_182199, 56)
    node T_182427 = and(T_182425, T_182426)
    node T_182428 = bit(T_181951, 57)
    node T_182429 = and(idxValid[57], T_182428)
    node T_182430 = bit(T_182199, 57)
    node T_182431 = and(T_182429, T_182430)
    node T_182432 = bit(T_181951, 58)
    node T_182433 = and(idxValid[58], T_182432)
    node T_182434 = bit(T_182199, 58)
    node T_182435 = and(T_182433, T_182434)
    node T_182436 = bit(T_181951, 59)
    node T_182437 = and(idxValid[59], T_182436)
    node T_182438 = bit(T_182199, 59)
    node T_182439 = and(T_182437, T_182438)
    node T_182440 = bit(T_181951, 60)
    node T_182441 = and(idxValid[60], T_182440)
    node T_182442 = bit(T_182199, 60)
    node T_182443 = and(T_182441, T_182442)
    node T_182444 = bit(T_181951, 61)
    node T_182445 = and(idxValid[61], T_182444)
    node T_182446 = bit(T_182199, 61)
    node T_182447 = and(T_182445, T_182446)
    wire updateHits : UInt<1>[62]
    updateHits[0] := T_182203
    updateHits[1] := T_182207
    updateHits[2] := T_182211
    updateHits[3] := T_182215
    updateHits[4] := T_182219
    updateHits[5] := T_182223
    updateHits[6] := T_182227
    updateHits[7] := T_182231
    updateHits[8] := T_182235
    updateHits[9] := T_182239
    updateHits[10] := T_182243
    updateHits[11] := T_182247
    updateHits[12] := T_182251
    updateHits[13] := T_182255
    updateHits[14] := T_182259
    updateHits[15] := T_182263
    updateHits[16] := T_182267
    updateHits[17] := T_182271
    updateHits[18] := T_182275
    updateHits[19] := T_182279
    updateHits[20] := T_182283
    updateHits[21] := T_182287
    updateHits[22] := T_182291
    updateHits[23] := T_182295
    updateHits[24] := T_182299
    updateHits[25] := T_182303
    updateHits[26] := T_182307
    updateHits[27] := T_182311
    updateHits[28] := T_182315
    updateHits[29] := T_182319
    updateHits[30] := T_182323
    updateHits[31] := T_182327
    updateHits[32] := T_182331
    updateHits[33] := T_182335
    updateHits[34] := T_182339
    updateHits[35] := T_182343
    updateHits[36] := T_182347
    updateHits[37] := T_182351
    updateHits[38] := T_182355
    updateHits[39] := T_182359
    updateHits[40] := T_182363
    updateHits[41] := T_182367
    updateHits[42] := T_182371
    updateHits[43] := T_182375
    updateHits[44] := T_182379
    updateHits[45] := T_182383
    updateHits[46] := T_182387
    updateHits[47] := T_182391
    updateHits[48] := T_182395
    updateHits[49] := T_182399
    updateHits[50] := T_182403
    updateHits[51] := T_182407
    updateHits[52] := T_182411
    updateHits[53] := T_182415
    updateHits[54] := T_182419
    updateHits[55] := T_182423
    updateHits[56] := T_182427
    updateHits[57] := T_182431
    updateHits[58] := T_182435
    updateHits[59] := T_182439
    updateHits[60] := T_182443
    updateHits[61] := T_182447
    reg T_182448 : UInt<16>
    onreset T_182448 := UInt<16>(1)
    when r_btb_update.valid : 
      node T_182449 = bit(T_182448, 0)
      node T_182450 = bit(T_182448, 2)
      node T_182451 = xor(T_182449, T_182450)
      node T_182452 = bit(T_182448, 3)
      node T_182453 = xor(T_182451, T_182452)
      node T_182454 = bit(T_182448, 5)
      node T_182455 = xor(T_182453, T_182454)
      node T_182456 = bits(T_182448, 15, 1)
      node T_182457 = cat(T_182455, T_182456)
      T_182448 := T_182457
    node T_182458 = eq(updatePageHit, UInt<1>(0))
    node useUpdatePageHit = eq(T_182458, UInt<1>(0))
    node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>(0))
    wire idxPageRepl : UInt
    wire idxPageUpdateOH : UInt
    idxPageUpdateOH := idxPageRepl
    when useUpdatePageHit : idxPageUpdateOH := updatePageHit
    wire idxPageReplEn : UInt<1>
    idxPageReplEn := UInt<1>(0)
    when doIdxPageRepl : idxPageReplEn := idxPageRepl
    node T_182459 = shr(r_btb_update.bits.pc, 12)
    node T_182460 = shr(req.bits.addr, 12)
    node samePage = eq(T_182459, T_182460)
    node T_182461 = not(idxPageReplEn)
    node T_182462 = and(pageHit, T_182461)
    node T_182463 = eq(T_182462, UInt<1>(0))
    node usePageHit = eq(T_182463, UInt<1>(0))
    node T_182464 = eq(samePage, UInt<1>(0))
    node T_182465 = eq(usePageHit, UInt<1>(0))
    node doTgtPageRepl = and(T_182464, T_182465)
    node T_182466 = bits(idxPageUpdateOH, 4, 0)
    node T_182467 = shl(T_182466, 1)
    node T_182468 = bit(idxPageUpdateOH, 5)
    node T_182469 = or(T_182467, T_182468)
    wire tgtPageRepl : UInt<6>
    tgtPageRepl := T_182469
    when samePage : tgtPageRepl := idxPageUpdateOH
    wire T_182470 : UInt<6>
    T_182470 := tgtPageRepl
    when usePageHit : T_182470 := pageHit
    node T_182471 = bits(T_182470, 5, 4)
    node T_182472 = bits(T_182470, 3, 0)
    node T_182473 = eq(T_182471, UInt<1>(0))
    node T_182474 = eq(T_182473, UInt<1>(0))
    node T_182475 = or(T_182471, T_182472)
    node T_182476 = bits(T_182475, 3, 2)
    node T_182477 = bits(T_182475, 1, 0)
    node T_182478 = eq(T_182476, UInt<1>(0))
    node T_182479 = eq(T_182478, UInt<1>(0))
    node T_182480 = or(T_182476, T_182477)
    node T_182481 = bit(T_182480, 1)
    node T_182482 = cat(T_182479, T_182481)
    node tgtPageUpdate = cat(T_182474, T_182482)
    wire tgtPageReplEn : UInt<1>
    tgtPageReplEn := UInt<1>(0)
    when doTgtPageRepl : tgtPageReplEn := tgtPageRepl
    node doPageRepl = or(doIdxPageRepl, doTgtPageRepl)
    node pageReplEn = or(idxPageReplEn, tgtPageReplEn)
    node T_182483 = and(r_btb_update.valid, doPageRepl)
    reg T_182484 : UInt<3>
    onreset T_182484 := UInt<3>(0)
    when T_182483 : 
      node T_182485 = eq(T_182484, UInt<3>(5))
      node T_182486 = and(UInt<1>(1), T_182485)
      node T_182487 = addw(T_182484, UInt<1>(1))
      wire T_182488 : UInt<3>
      T_182488 := T_182487
      when T_182486 : T_182488 := UInt<1>(0)
      T_182484 := T_182488
    node T_182489 = and(T_182483, T_182485)
    node T_182490 = dshl(UInt<1>(1), T_182484)
    idxPageRepl := T_182490
    when r_btb_update.valid : 
      node T_182491 = eq(req.bits.addr, r_btb_update.bits.target)
      node T_182492 = eq(r_btb_update.bits.prediction.valid, UInt<1>(0))
      reg T_182493 : UInt<6>
      onreset T_182493 := UInt<6>(0)
      when T_182492 : 
        node T_182494 = eq(T_182493, UInt<6>(61))
        node T_182495 = and(UInt<1>(1), T_182494)
        node T_182496 = addw(T_182493, UInt<1>(1))
        wire T_182497 : UInt<6>
        T_182497 := T_182496
        when T_182495 : T_182497 := UInt<1>(0)
        T_182493 := T_182497
      node T_182498 = and(T_182492, T_182494)
      wire T_182499 : UInt<6>
      T_182499 := T_182493
      when r_btb_update.bits.prediction.valid : T_182499 := r_btb_update.bits.prediction.bits.entry
      
      
      node T_182500 = or(T_180672, T_180858)
      node T_182501 = and(pageReplEn, T_182500)
      node T_182502 = eq(T_182501, UInt<1>(0))
      node T_182503 = eq(T_182502, UInt<1>(0))
      when T_182503 : idxValid[0] := UInt<1>(0)
      
      
      node T_182504 = or(T_180675, T_180861)
      node T_182505 = and(pageReplEn, T_182504)
      node T_182506 = eq(T_182505, UInt<1>(0))
      node T_182507 = eq(T_182506, UInt<1>(0))
      when T_182507 : idxValid[1] := UInt<1>(0)
      
      
      node T_182508 = or(T_180678, T_180864)
      node T_182509 = and(pageReplEn, T_182508)
      node T_182510 = eq(T_182509, UInt<1>(0))
      node T_182511 = eq(T_182510, UInt<1>(0))
      when T_182511 : idxValid[2] := UInt<1>(0)
      
      
      node T_182512 = or(T_180681, T_180867)
      node T_182513 = and(pageReplEn, T_182512)
      node T_182514 = eq(T_182513, UInt<1>(0))
      node T_182515 = eq(T_182514, UInt<1>(0))
      when T_182515 : idxValid[3] := UInt<1>(0)
      
      
      node T_182516 = or(T_180684, T_180870)
      node T_182517 = and(pageReplEn, T_182516)
      node T_182518 = eq(T_182517, UInt<1>(0))
      node T_182519 = eq(T_182518, UInt<1>(0))
      when T_182519 : idxValid[4] := UInt<1>(0)
      
      
      node T_182520 = or(T_180687, T_180873)
      node T_182521 = and(pageReplEn, T_182520)
      node T_182522 = eq(T_182521, UInt<1>(0))
      node T_182523 = eq(T_182522, UInt<1>(0))
      when T_182523 : idxValid[5] := UInt<1>(0)
      
      
      node T_182524 = or(T_180690, T_180876)
      node T_182525 = and(pageReplEn, T_182524)
      node T_182526 = eq(T_182525, UInt<1>(0))
      node T_182527 = eq(T_182526, UInt<1>(0))
      when T_182527 : idxValid[6] := UInt<1>(0)
      
      
      node T_182528 = or(T_180693, T_180879)
      node T_182529 = and(pageReplEn, T_182528)
      node T_182530 = eq(T_182529, UInt<1>(0))
      node T_182531 = eq(T_182530, UInt<1>(0))
      when T_182531 : idxValid[7] := UInt<1>(0)
      
      
      node T_182532 = or(T_180696, T_180882)
      node T_182533 = and(pageReplEn, T_182532)
      node T_182534 = eq(T_182533, UInt<1>(0))
      node T_182535 = eq(T_182534, UInt<1>(0))
      when T_182535 : idxValid[8] := UInt<1>(0)
      
      
      node T_182536 = or(T_180699, T_180885)
      node T_182537 = and(pageReplEn, T_182536)
      node T_182538 = eq(T_182537, UInt<1>(0))
      node T_182539 = eq(T_182538, UInt<1>(0))
      when T_182539 : idxValid[9] := UInt<1>(0)
      
      
      node T_182540 = or(T_180702, T_180888)
      node T_182541 = and(pageReplEn, T_182540)
      node T_182542 = eq(T_182541, UInt<1>(0))
      node T_182543 = eq(T_182542, UInt<1>(0))
      when T_182543 : idxValid[10] := UInt<1>(0)
      
      
      node T_182544 = or(T_180705, T_180891)
      node T_182545 = and(pageReplEn, T_182544)
      node T_182546 = eq(T_182545, UInt<1>(0))
      node T_182547 = eq(T_182546, UInt<1>(0))
      when T_182547 : idxValid[11] := UInt<1>(0)
      
      
      node T_182548 = or(T_180708, T_180894)
      node T_182549 = and(pageReplEn, T_182548)
      node T_182550 = eq(T_182549, UInt<1>(0))
      node T_182551 = eq(T_182550, UInt<1>(0))
      when T_182551 : idxValid[12] := UInt<1>(0)
      
      
      node T_182552 = or(T_180711, T_180897)
      node T_182553 = and(pageReplEn, T_182552)
      node T_182554 = eq(T_182553, UInt<1>(0))
      node T_182555 = eq(T_182554, UInt<1>(0))
      when T_182555 : idxValid[13] := UInt<1>(0)
      
      
      node T_182556 = or(T_180714, T_180900)
      node T_182557 = and(pageReplEn, T_182556)
      node T_182558 = eq(T_182557, UInt<1>(0))
      node T_182559 = eq(T_182558, UInt<1>(0))
      when T_182559 : idxValid[14] := UInt<1>(0)
      
      
      node T_182560 = or(T_180717, T_180903)
      node T_182561 = and(pageReplEn, T_182560)
      node T_182562 = eq(T_182561, UInt<1>(0))
      node T_182563 = eq(T_182562, UInt<1>(0))
      when T_182563 : idxValid[15] := UInt<1>(0)
      
      
      node T_182564 = or(T_180720, T_180906)
      node T_182565 = and(pageReplEn, T_182564)
      node T_182566 = eq(T_182565, UInt<1>(0))
      node T_182567 = eq(T_182566, UInt<1>(0))
      when T_182567 : idxValid[16] := UInt<1>(0)
      
      
      node T_182568 = or(T_180723, T_180909)
      node T_182569 = and(pageReplEn, T_182568)
      node T_182570 = eq(T_182569, UInt<1>(0))
      node T_182571 = eq(T_182570, UInt<1>(0))
      when T_182571 : idxValid[17] := UInt<1>(0)
      
      
      node T_182572 = or(T_180726, T_180912)
      node T_182573 = and(pageReplEn, T_182572)
      node T_182574 = eq(T_182573, UInt<1>(0))
      node T_182575 = eq(T_182574, UInt<1>(0))
      when T_182575 : idxValid[18] := UInt<1>(0)
      
      
      node T_182576 = or(T_180729, T_180915)
      node T_182577 = and(pageReplEn, T_182576)
      node T_182578 = eq(T_182577, UInt<1>(0))
      node T_182579 = eq(T_182578, UInt<1>(0))
      when T_182579 : idxValid[19] := UInt<1>(0)
      
      
      node T_182580 = or(T_180732, T_180918)
      node T_182581 = and(pageReplEn, T_182580)
      node T_182582 = eq(T_182581, UInt<1>(0))
      node T_182583 = eq(T_182582, UInt<1>(0))
      when T_182583 : idxValid[20] := UInt<1>(0)
      
      
      node T_182584 = or(T_180735, T_180921)
      node T_182585 = and(pageReplEn, T_182584)
      node T_182586 = eq(T_182585, UInt<1>(0))
      node T_182587 = eq(T_182586, UInt<1>(0))
      when T_182587 : idxValid[21] := UInt<1>(0)
      
      
      node T_182588 = or(T_180738, T_180924)
      node T_182589 = and(pageReplEn, T_182588)
      node T_182590 = eq(T_182589, UInt<1>(0))
      node T_182591 = eq(T_182590, UInt<1>(0))
      when T_182591 : idxValid[22] := UInt<1>(0)
      
      
      node T_182592 = or(T_180741, T_180927)
      node T_182593 = and(pageReplEn, T_182592)
      node T_182594 = eq(T_182593, UInt<1>(0))
      node T_182595 = eq(T_182594, UInt<1>(0))
      when T_182595 : idxValid[23] := UInt<1>(0)
      
      
      node T_182596 = or(T_180744, T_180930)
      node T_182597 = and(pageReplEn, T_182596)
      node T_182598 = eq(T_182597, UInt<1>(0))
      node T_182599 = eq(T_182598, UInt<1>(0))
      when T_182599 : idxValid[24] := UInt<1>(0)
      
      
      node T_182600 = or(T_180747, T_180933)
      node T_182601 = and(pageReplEn, T_182600)
      node T_182602 = eq(T_182601, UInt<1>(0))
      node T_182603 = eq(T_182602, UInt<1>(0))
      when T_182603 : idxValid[25] := UInt<1>(0)
      
      
      node T_182604 = or(T_180750, T_180936)
      node T_182605 = and(pageReplEn, T_182604)
      node T_182606 = eq(T_182605, UInt<1>(0))
      node T_182607 = eq(T_182606, UInt<1>(0))
      when T_182607 : idxValid[26] := UInt<1>(0)
      
      
      node T_182608 = or(T_180753, T_180939)
      node T_182609 = and(pageReplEn, T_182608)
      node T_182610 = eq(T_182609, UInt<1>(0))
      node T_182611 = eq(T_182610, UInt<1>(0))
      when T_182611 : idxValid[27] := UInt<1>(0)
      
      
      node T_182612 = or(T_180756, T_180942)
      node T_182613 = and(pageReplEn, T_182612)
      node T_182614 = eq(T_182613, UInt<1>(0))
      node T_182615 = eq(T_182614, UInt<1>(0))
      when T_182615 : idxValid[28] := UInt<1>(0)
      
      
      node T_182616 = or(T_180759, T_180945)
      node T_182617 = and(pageReplEn, T_182616)
      node T_182618 = eq(T_182617, UInt<1>(0))
      node T_182619 = eq(T_182618, UInt<1>(0))
      when T_182619 : idxValid[29] := UInt<1>(0)
      
      
      node T_182620 = or(T_180762, T_180948)
      node T_182621 = and(pageReplEn, T_182620)
      node T_182622 = eq(T_182621, UInt<1>(0))
      node T_182623 = eq(T_182622, UInt<1>(0))
      when T_182623 : idxValid[30] := UInt<1>(0)
      
      
      node T_182624 = or(T_180765, T_180951)
      node T_182625 = and(pageReplEn, T_182624)
      node T_182626 = eq(T_182625, UInt<1>(0))
      node T_182627 = eq(T_182626, UInt<1>(0))
      when T_182627 : idxValid[31] := UInt<1>(0)
      
      
      node T_182628 = or(T_180768, T_180954)
      node T_182629 = and(pageReplEn, T_182628)
      node T_182630 = eq(T_182629, UInt<1>(0))
      node T_182631 = eq(T_182630, UInt<1>(0))
      when T_182631 : idxValid[32] := UInt<1>(0)
      
      
      node T_182632 = or(T_180771, T_180957)
      node T_182633 = and(pageReplEn, T_182632)
      node T_182634 = eq(T_182633, UInt<1>(0))
      node T_182635 = eq(T_182634, UInt<1>(0))
      when T_182635 : idxValid[33] := UInt<1>(0)
      
      
      node T_182636 = or(T_180774, T_180960)
      node T_182637 = and(pageReplEn, T_182636)
      node T_182638 = eq(T_182637, UInt<1>(0))
      node T_182639 = eq(T_182638, UInt<1>(0))
      when T_182639 : idxValid[34] := UInt<1>(0)
      
      
      node T_182640 = or(T_180777, T_180963)
      node T_182641 = and(pageReplEn, T_182640)
      node T_182642 = eq(T_182641, UInt<1>(0))
      node T_182643 = eq(T_182642, UInt<1>(0))
      when T_182643 : idxValid[35] := UInt<1>(0)
      
      
      node T_182644 = or(T_180780, T_180966)
      node T_182645 = and(pageReplEn, T_182644)
      node T_182646 = eq(T_182645, UInt<1>(0))
      node T_182647 = eq(T_182646, UInt<1>(0))
      when T_182647 : idxValid[36] := UInt<1>(0)
      
      
      node T_182648 = or(T_180783, T_180969)
      node T_182649 = and(pageReplEn, T_182648)
      node T_182650 = eq(T_182649, UInt<1>(0))
      node T_182651 = eq(T_182650, UInt<1>(0))
      when T_182651 : idxValid[37] := UInt<1>(0)
      
      
      node T_182652 = or(T_180786, T_180972)
      node T_182653 = and(pageReplEn, T_182652)
      node T_182654 = eq(T_182653, UInt<1>(0))
      node T_182655 = eq(T_182654, UInt<1>(0))
      when T_182655 : idxValid[38] := UInt<1>(0)
      
      
      node T_182656 = or(T_180789, T_180975)
      node T_182657 = and(pageReplEn, T_182656)
      node T_182658 = eq(T_182657, UInt<1>(0))
      node T_182659 = eq(T_182658, UInt<1>(0))
      when T_182659 : idxValid[39] := UInt<1>(0)
      
      
      node T_182660 = or(T_180792, T_180978)
      node T_182661 = and(pageReplEn, T_182660)
      node T_182662 = eq(T_182661, UInt<1>(0))
      node T_182663 = eq(T_182662, UInt<1>(0))
      when T_182663 : idxValid[40] := UInt<1>(0)
      
      
      node T_182664 = or(T_180795, T_180981)
      node T_182665 = and(pageReplEn, T_182664)
      node T_182666 = eq(T_182665, UInt<1>(0))
      node T_182667 = eq(T_182666, UInt<1>(0))
      when T_182667 : idxValid[41] := UInt<1>(0)
      
      
      node T_182668 = or(T_180798, T_180984)
      node T_182669 = and(pageReplEn, T_182668)
      node T_182670 = eq(T_182669, UInt<1>(0))
      node T_182671 = eq(T_182670, UInt<1>(0))
      when T_182671 : idxValid[42] := UInt<1>(0)
      
      
      node T_182672 = or(T_180801, T_180987)
      node T_182673 = and(pageReplEn, T_182672)
      node T_182674 = eq(T_182673, UInt<1>(0))
      node T_182675 = eq(T_182674, UInt<1>(0))
      when T_182675 : idxValid[43] := UInt<1>(0)
      
      
      node T_182676 = or(T_180804, T_180990)
      node T_182677 = and(pageReplEn, T_182676)
      node T_182678 = eq(T_182677, UInt<1>(0))
      node T_182679 = eq(T_182678, UInt<1>(0))
      when T_182679 : idxValid[44] := UInt<1>(0)
      
      
      node T_182680 = or(T_180807, T_180993)
      node T_182681 = and(pageReplEn, T_182680)
      node T_182682 = eq(T_182681, UInt<1>(0))
      node T_182683 = eq(T_182682, UInt<1>(0))
      when T_182683 : idxValid[45] := UInt<1>(0)
      
      
      node T_182684 = or(T_180810, T_180996)
      node T_182685 = and(pageReplEn, T_182684)
      node T_182686 = eq(T_182685, UInt<1>(0))
      node T_182687 = eq(T_182686, UInt<1>(0))
      when T_182687 : idxValid[46] := UInt<1>(0)
      
      
      node T_182688 = or(T_180813, T_180999)
      node T_182689 = and(pageReplEn, T_182688)
      node T_182690 = eq(T_182689, UInt<1>(0))
      node T_182691 = eq(T_182690, UInt<1>(0))
      when T_182691 : idxValid[47] := UInt<1>(0)
      
      
      node T_182692 = or(T_180816, T_181002)
      node T_182693 = and(pageReplEn, T_182692)
      node T_182694 = eq(T_182693, UInt<1>(0))
      node T_182695 = eq(T_182694, UInt<1>(0))
      when T_182695 : idxValid[48] := UInt<1>(0)
      
      
      node T_182696 = or(T_180819, T_181005)
      node T_182697 = and(pageReplEn, T_182696)
      node T_182698 = eq(T_182697, UInt<1>(0))
      node T_182699 = eq(T_182698, UInt<1>(0))
      when T_182699 : idxValid[49] := UInt<1>(0)
      
      
      node T_182700 = or(T_180822, T_181008)
      node T_182701 = and(pageReplEn, T_182700)
      node T_182702 = eq(T_182701, UInt<1>(0))
      node T_182703 = eq(T_182702, UInt<1>(0))
      when T_182703 : idxValid[50] := UInt<1>(0)
      
      
      node T_182704 = or(T_180825, T_181011)
      node T_182705 = and(pageReplEn, T_182704)
      node T_182706 = eq(T_182705, UInt<1>(0))
      node T_182707 = eq(T_182706, UInt<1>(0))
      when T_182707 : idxValid[51] := UInt<1>(0)
      
      
      node T_182708 = or(T_180828, T_181014)
      node T_182709 = and(pageReplEn, T_182708)
      node T_182710 = eq(T_182709, UInt<1>(0))
      node T_182711 = eq(T_182710, UInt<1>(0))
      when T_182711 : idxValid[52] := UInt<1>(0)
      
      
      node T_182712 = or(T_180831, T_181017)
      node T_182713 = and(pageReplEn, T_182712)
      node T_182714 = eq(T_182713, UInt<1>(0))
      node T_182715 = eq(T_182714, UInt<1>(0))
      when T_182715 : idxValid[53] := UInt<1>(0)
      
      
      node T_182716 = or(T_180834, T_181020)
      node T_182717 = and(pageReplEn, T_182716)
      node T_182718 = eq(T_182717, UInt<1>(0))
      node T_182719 = eq(T_182718, UInt<1>(0))
      when T_182719 : idxValid[54] := UInt<1>(0)
      
      
      node T_182720 = or(T_180837, T_181023)
      node T_182721 = and(pageReplEn, T_182720)
      node T_182722 = eq(T_182721, UInt<1>(0))
      node T_182723 = eq(T_182722, UInt<1>(0))
      when T_182723 : idxValid[55] := UInt<1>(0)
      
      
      node T_182724 = or(T_180840, T_181026)
      node T_182725 = and(pageReplEn, T_182724)
      node T_182726 = eq(T_182725, UInt<1>(0))
      node T_182727 = eq(T_182726, UInt<1>(0))
      when T_182727 : idxValid[56] := UInt<1>(0)
      
      
      node T_182728 = or(T_180843, T_181029)
      node T_182729 = and(pageReplEn, T_182728)
      node T_182730 = eq(T_182729, UInt<1>(0))
      node T_182731 = eq(T_182730, UInt<1>(0))
      when T_182731 : idxValid[57] := UInt<1>(0)
      
      
      node T_182732 = or(T_180846, T_181032)
      node T_182733 = and(pageReplEn, T_182732)
      node T_182734 = eq(T_182733, UInt<1>(0))
      node T_182735 = eq(T_182734, UInt<1>(0))
      when T_182735 : idxValid[58] := UInt<1>(0)
      
      
      node T_182736 = or(T_180849, T_181035)
      node T_182737 = and(pageReplEn, T_182736)
      node T_182738 = eq(T_182737, UInt<1>(0))
      node T_182739 = eq(T_182738, UInt<1>(0))
      when T_182739 : idxValid[59] := UInt<1>(0)
      
      
      node T_182740 = or(T_180852, T_181038)
      node T_182741 = and(pageReplEn, T_182740)
      node T_182742 = eq(T_182741, UInt<1>(0))
      node T_182743 = eq(T_182742, UInt<1>(0))
      when T_182743 : idxValid[60] := UInt<1>(0)
      
      
      node T_182744 = or(T_180855, T_181041)
      node T_182745 = and(pageReplEn, T_182744)
      node T_182746 = eq(T_182745, UInt<1>(0))
      node T_182747 = eq(T_182746, UInt<1>(0))
      when T_182747 : idxValid[61] := UInt<1>(0)
      accessor T_182748 = idxValid[T_182499]
      T_182748 := UInt<1>(1)
      accessor T_182749 = idxs[T_182499]
      T_182749 := r_btb_update.bits.pc
      accessor T_182750 = tgts[T_182499]
      T_182750 := req.bits.addr
      accessor T_182751 = idxPages[T_182499]
      T_182751 := UInt<1>(0)
      accessor T_182752 = tgtPages[T_182499]
      T_182752 := tgtPageUpdate
      accessor T_182753 = useRAS[T_182499]
      T_182753 := r_btb_update.bits.isReturn
      accessor T_182754 = isJump[T_182499]
      T_182754 := r_btb_update.bits.isJump
      accessor T_182755 = brIdx[T_182499]
      T_182755 := UInt<1>(0)
      node T_182756 = and(idxPageUpdateOH, UInt<6>(21))
      node T_182757 = eq(T_182756, UInt<1>(0))
      node T_182758 = eq(T_182757, UInt<1>(0))
      wire T_182759 : UInt<1>
      T_182759 := doTgtPageRepl
      when T_182758 : T_182759 := doIdxPageRepl
      node T_182760 = shr(r_btb_update.bits.pc, 12)
      node T_182761 = shr(req.bits.addr, 12)
      wire T_182762 : UInt<27>
      T_182762 := T_182761
      when T_182758 : T_182762 := T_182760
      
      
      node T_182763 = bit(pageReplEn, 0)
      node T_182764 = and(T_182759, T_182763)
      when T_182764 : 
        accessor T_182765 = pages[UInt<1>(0)]
        T_182765 := T_182762
      
      
      node T_182766 = bit(pageReplEn, 2)
      node T_182767 = and(T_182759, T_182766)
      when T_182767 : 
        accessor T_182768 = pages[UInt<2>(2)]
        T_182768 := T_182762
      
      
      node T_182769 = bit(pageReplEn, 4)
      node T_182770 = and(T_182759, T_182769)
      when T_182770 : 
        accessor T_182771 = pages[UInt<3>(4)]
        T_182771 := T_182762
      wire T_182772 : UInt<1>
      T_182772 := doIdxPageRepl
      when T_182758 : T_182772 := doTgtPageRepl
      node T_182773 = shr(req.bits.addr, 12)
      node T_182774 = shr(r_btb_update.bits.pc, 12)
      wire T_182775 : UInt<27>
      T_182775 := T_182774
      when T_182758 : T_182775 := T_182773
      
      
      node T_182776 = bit(pageReplEn, 1)
      node T_182777 = and(T_182772, T_182776)
      when T_182777 : 
        accessor T_182778 = pages[UInt<1>(1)]
        T_182778 := T_182775
      
      
      node T_182779 = bit(pageReplEn, 3)
      node T_182780 = and(T_182772, T_182779)
      when T_182780 : 
        accessor T_182781 = pages[UInt<2>(3)]
        T_182781 := T_182775
      
      
      node T_182782 = bit(pageReplEn, 5)
      node T_182783 = and(T_182772, T_182782)
      when T_182783 : 
        accessor T_182784 = pages[UInt<3>(5)]
        T_182784 := T_182775
      when doPageRepl : 
        node T_182785 = or(pageValid, pageReplEn)
        pageValid := T_182785
    when invalidate : 
      idxValid := UInt<1>(0)
      pageValid := UInt<1>(0)
    node T_182786 = or(hits[0], hits[1])
    node T_182787 = or(T_182786, hits[2])
    node T_182788 = or(T_182787, hits[3])
    node T_182789 = or(T_182788, hits[4])
    node T_182790 = or(T_182789, hits[5])
    node T_182791 = or(T_182790, hits[6])
    node T_182792 = or(T_182791, hits[7])
    node T_182793 = or(T_182792, hits[8])
    node T_182794 = or(T_182793, hits[9])
    node T_182795 = or(T_182794, hits[10])
    node T_182796 = or(T_182795, hits[11])
    node T_182797 = or(T_182796, hits[12])
    node T_182798 = or(T_182797, hits[13])
    node T_182799 = or(T_182798, hits[14])
    node T_182800 = or(T_182799, hits[15])
    node T_182801 = or(T_182800, hits[16])
    node T_182802 = or(T_182801, hits[17])
    node T_182803 = or(T_182802, hits[18])
    node T_182804 = or(T_182803, hits[19])
    node T_182805 = or(T_182804, hits[20])
    node T_182806 = or(T_182805, hits[21])
    node T_182807 = or(T_182806, hits[22])
    node T_182808 = or(T_182807, hits[23])
    node T_182809 = or(T_182808, hits[24])
    node T_182810 = or(T_182809, hits[25])
    node T_182811 = or(T_182810, hits[26])
    node T_182812 = or(T_182811, hits[27])
    node T_182813 = or(T_182812, hits[28])
    node T_182814 = or(T_182813, hits[29])
    node T_182815 = or(T_182814, hits[30])
    node T_182816 = or(T_182815, hits[31])
    node T_182817 = or(T_182816, hits[32])
    node T_182818 = or(T_182817, hits[33])
    node T_182819 = or(T_182818, hits[34])
    node T_182820 = or(T_182819, hits[35])
    node T_182821 = or(T_182820, hits[36])
    node T_182822 = or(T_182821, hits[37])
    node T_182823 = or(T_182822, hits[38])
    node T_182824 = or(T_182823, hits[39])
    node T_182825 = or(T_182824, hits[40])
    node T_182826 = or(T_182825, hits[41])
    node T_182827 = or(T_182826, hits[42])
    node T_182828 = or(T_182827, hits[43])
    node T_182829 = or(T_182828, hits[44])
    node T_182830 = or(T_182829, hits[45])
    node T_182831 = or(T_182830, hits[46])
    node T_182832 = or(T_182831, hits[47])
    node T_182833 = or(T_182832, hits[48])
    node T_182834 = or(T_182833, hits[49])
    node T_182835 = or(T_182834, hits[50])
    node T_182836 = or(T_182835, hits[51])
    node T_182837 = or(T_182836, hits[52])
    node T_182838 = or(T_182837, hits[53])
    node T_182839 = or(T_182838, hits[54])
    node T_182840 = or(T_182839, hits[55])
    node T_182841 = or(T_182840, hits[56])
    node T_182842 = or(T_182841, hits[57])
    node T_182843 = or(T_182842, hits[58])
    node T_182844 = or(T_182843, hits[59])
    node T_182845 = or(T_182844, hits[60])
    node T_182846 = or(T_182845, hits[61])
    resp.valid := T_182846
    resp.bits.taken := resp.valid
    wire T_182847 : UInt<1>
    T_182847 := UInt<1>(0)
    when hits[0] : T_182847 := T_180858
    wire T_182848 : UInt<1>
    T_182848 := UInt<1>(0)
    when hits[1] : T_182848 := T_180861
    wire T_182849 : UInt<1>
    T_182849 := UInt<1>(0)
    when hits[2] : T_182849 := T_180864
    wire T_182850 : UInt<1>
    T_182850 := UInt<1>(0)
    when hits[3] : T_182850 := T_180867
    wire T_182851 : UInt<1>
    T_182851 := UInt<1>(0)
    when hits[4] : T_182851 := T_180870
    wire T_182852 : UInt<1>
    T_182852 := UInt<1>(0)
    when hits[5] : T_182852 := T_180873
    wire T_182853 : UInt<1>
    T_182853 := UInt<1>(0)
    when hits[6] : T_182853 := T_180876
    wire T_182854 : UInt<1>
    T_182854 := UInt<1>(0)
    when hits[7] : T_182854 := T_180879
    wire T_182855 : UInt<1>
    T_182855 := UInt<1>(0)
    when hits[8] : T_182855 := T_180882
    wire T_182856 : UInt<1>
    T_182856 := UInt<1>(0)
    when hits[9] : T_182856 := T_180885
    wire T_182857 : UInt<1>
    T_182857 := UInt<1>(0)
    when hits[10] : T_182857 := T_180888
    wire T_182858 : UInt<1>
    T_182858 := UInt<1>(0)
    when hits[11] : T_182858 := T_180891
    wire T_182859 : UInt<1>
    T_182859 := UInt<1>(0)
    when hits[12] : T_182859 := T_180894
    wire T_182860 : UInt<1>
    T_182860 := UInt<1>(0)
    when hits[13] : T_182860 := T_180897
    wire T_182861 : UInt<1>
    T_182861 := UInt<1>(0)
    when hits[14] : T_182861 := T_180900
    wire T_182862 : UInt<1>
    T_182862 := UInt<1>(0)
    when hits[15] : T_182862 := T_180903
    wire T_182863 : UInt<1>
    T_182863 := UInt<1>(0)
    when hits[16] : T_182863 := T_180906
    wire T_182864 : UInt<1>
    T_182864 := UInt<1>(0)
    when hits[17] : T_182864 := T_180909
    wire T_182865 : UInt<1>
    T_182865 := UInt<1>(0)
    when hits[18] : T_182865 := T_180912
    wire T_182866 : UInt<1>
    T_182866 := UInt<1>(0)
    when hits[19] : T_182866 := T_180915
    wire T_182867 : UInt<1>
    T_182867 := UInt<1>(0)
    when hits[20] : T_182867 := T_180918
    wire T_182868 : UInt<1>
    T_182868 := UInt<1>(0)
    when hits[21] : T_182868 := T_180921
    wire T_182869 : UInt<1>
    T_182869 := UInt<1>(0)
    when hits[22] : T_182869 := T_180924
    wire T_182870 : UInt<1>
    T_182870 := UInt<1>(0)
    when hits[23] : T_182870 := T_180927
    wire T_182871 : UInt<1>
    T_182871 := UInt<1>(0)
    when hits[24] : T_182871 := T_180930
    wire T_182872 : UInt<1>
    T_182872 := UInt<1>(0)
    when hits[25] : T_182872 := T_180933
    wire T_182873 : UInt<1>
    T_182873 := UInt<1>(0)
    when hits[26] : T_182873 := T_180936
    wire T_182874 : UInt<1>
    T_182874 := UInt<1>(0)
    when hits[27] : T_182874 := T_180939
    wire T_182875 : UInt<1>
    T_182875 := UInt<1>(0)
    when hits[28] : T_182875 := T_180942
    wire T_182876 : UInt<1>
    T_182876 := UInt<1>(0)
    when hits[29] : T_182876 := T_180945
    wire T_182877 : UInt<1>
    T_182877 := UInt<1>(0)
    when hits[30] : T_182877 := T_180948
    wire T_182878 : UInt<1>
    T_182878 := UInt<1>(0)
    when hits[31] : T_182878 := T_180951
    wire T_182879 : UInt<1>
    T_182879 := UInt<1>(0)
    when hits[32] : T_182879 := T_180954
    wire T_182880 : UInt<1>
    T_182880 := UInt<1>(0)
    when hits[33] : T_182880 := T_180957
    wire T_182881 : UInt<1>
    T_182881 := UInt<1>(0)
    when hits[34] : T_182881 := T_180960
    wire T_182882 : UInt<1>
    T_182882 := UInt<1>(0)
    when hits[35] : T_182882 := T_180963
    wire T_182883 : UInt<1>
    T_182883 := UInt<1>(0)
    when hits[36] : T_182883 := T_180966
    wire T_182884 : UInt<1>
    T_182884 := UInt<1>(0)
    when hits[37] : T_182884 := T_180969
    wire T_182885 : UInt<1>
    T_182885 := UInt<1>(0)
    when hits[38] : T_182885 := T_180972
    wire T_182886 : UInt<1>
    T_182886 := UInt<1>(0)
    when hits[39] : T_182886 := T_180975
    wire T_182887 : UInt<1>
    T_182887 := UInt<1>(0)
    when hits[40] : T_182887 := T_180978
    wire T_182888 : UInt<1>
    T_182888 := UInt<1>(0)
    when hits[41] : T_182888 := T_180981
    wire T_182889 : UInt<1>
    T_182889 := UInt<1>(0)
    when hits[42] : T_182889 := T_180984
    wire T_182890 : UInt<1>
    T_182890 := UInt<1>(0)
    when hits[43] : T_182890 := T_180987
    wire T_182891 : UInt<1>
    T_182891 := UInt<1>(0)
    when hits[44] : T_182891 := T_180990
    wire T_182892 : UInt<1>
    T_182892 := UInt<1>(0)
    when hits[45] : T_182892 := T_180993
    wire T_182893 : UInt<1>
    T_182893 := UInt<1>(0)
    when hits[46] : T_182893 := T_180996
    wire T_182894 : UInt<1>
    T_182894 := UInt<1>(0)
    when hits[47] : T_182894 := T_180999
    wire T_182895 : UInt<1>
    T_182895 := UInt<1>(0)
    when hits[48] : T_182895 := T_181002
    wire T_182896 : UInt<1>
    T_182896 := UInt<1>(0)
    when hits[49] : T_182896 := T_181005
    wire T_182897 : UInt<1>
    T_182897 := UInt<1>(0)
    when hits[50] : T_182897 := T_181008
    wire T_182898 : UInt<1>
    T_182898 := UInt<1>(0)
    when hits[51] : T_182898 := T_181011
    wire T_182899 : UInt<1>
    T_182899 := UInt<1>(0)
    when hits[52] : T_182899 := T_181014
    wire T_182900 : UInt<1>
    T_182900 := UInt<1>(0)
    when hits[53] : T_182900 := T_181017
    wire T_182901 : UInt<1>
    T_182901 := UInt<1>(0)
    when hits[54] : T_182901 := T_181020
    wire T_182902 : UInt<1>
    T_182902 := UInt<1>(0)
    when hits[55] : T_182902 := T_181023
    wire T_182903 : UInt<1>
    T_182903 := UInt<1>(0)
    when hits[56] : T_182903 := T_181026
    wire T_182904 : UInt<1>
    T_182904 := UInt<1>(0)
    when hits[57] : T_182904 := T_181029
    wire T_182905 : UInt<1>
    T_182905 := UInt<1>(0)
    when hits[58] : T_182905 := T_181032
    wire T_182906 : UInt<1>
    T_182906 := UInt<1>(0)
    when hits[59] : T_182906 := T_181035
    wire T_182907 : UInt<1>
    T_182907 := UInt<1>(0)
    when hits[60] : T_182907 := T_181038
    wire T_182908 : UInt<1>
    T_182908 := UInt<1>(0)
    when hits[61] : T_182908 := T_181041
    node T_182909 = or(T_182847, T_182848)
    node T_182910 = or(T_182909, T_182849)
    node T_182911 = or(T_182910, T_182850)
    node T_182912 = or(T_182911, T_182851)
    node T_182913 = or(T_182912, T_182852)
    node T_182914 = or(T_182913, T_182853)
    node T_182915 = or(T_182914, T_182854)
    node T_182916 = or(T_182915, T_182855)
    node T_182917 = or(T_182916, T_182856)
    node T_182918 = or(T_182917, T_182857)
    node T_182919 = or(T_182918, T_182858)
    node T_182920 = or(T_182919, T_182859)
    node T_182921 = or(T_182920, T_182860)
    node T_182922 = or(T_182921, T_182861)
    node T_182923 = or(T_182922, T_182862)
    node T_182924 = or(T_182923, T_182863)
    node T_182925 = or(T_182924, T_182864)
    node T_182926 = or(T_182925, T_182865)
    node T_182927 = or(T_182926, T_182866)
    node T_182928 = or(T_182927, T_182867)
    node T_182929 = or(T_182928, T_182868)
    node T_182930 = or(T_182929, T_182869)
    node T_182931 = or(T_182930, T_182870)
    node T_182932 = or(T_182931, T_182871)
    node T_182933 = or(T_182932, T_182872)
    node T_182934 = or(T_182933, T_182873)
    node T_182935 = or(T_182934, T_182874)
    node T_182936 = or(T_182935, T_182875)
    node T_182937 = or(T_182936, T_182876)
    node T_182938 = or(T_182937, T_182877)
    node T_182939 = or(T_182938, T_182878)
    node T_182940 = or(T_182939, T_182879)
    node T_182941 = or(T_182940, T_182880)
    node T_182942 = or(T_182941, T_182881)
    node T_182943 = or(T_182942, T_182882)
    node T_182944 = or(T_182943, T_182883)
    node T_182945 = or(T_182944, T_182884)
    node T_182946 = or(T_182945, T_182885)
    node T_182947 = or(T_182946, T_182886)
    node T_182948 = or(T_182947, T_182887)
    node T_182949 = or(T_182948, T_182888)
    node T_182950 = or(T_182949, T_182889)
    node T_182951 = or(T_182950, T_182890)
    node T_182952 = or(T_182951, T_182891)
    node T_182953 = or(T_182952, T_182892)
    node T_182954 = or(T_182953, T_182893)
    node T_182955 = or(T_182954, T_182894)
    node T_182956 = or(T_182955, T_182895)
    node T_182957 = or(T_182956, T_182896)
    node T_182958 = or(T_182957, T_182897)
    node T_182959 = or(T_182958, T_182898)
    node T_182960 = or(T_182959, T_182899)
    node T_182961 = or(T_182960, T_182900)
    node T_182962 = or(T_182961, T_182901)
    node T_182963 = or(T_182962, T_182902)
    node T_182964 = or(T_182963, T_182903)
    node T_182965 = or(T_182964, T_182904)
    node T_182966 = or(T_182965, T_182905)
    node T_182967 = or(T_182966, T_182906)
    node T_182968 = or(T_182967, T_182907)
    node T_182969 = or(T_182968, T_182908)
    wire T_182970 : UInt<6>
    node T_182971 = bits(T_182969, 5, 0)
    T_182970 := T_182971
    node T_182972 = bit(T_182970, 0)
    node T_182973 = bit(T_182970, 1)
    node T_182974 = bit(T_182970, 2)
    node T_182975 = bit(T_182970, 3)
    node T_182976 = bit(T_182970, 4)
    node T_182977 = bit(T_182970, 5)
    accessor T_182978 = pages[UInt<1>(0)]
    accessor T_182979 = pages[UInt<1>(1)]
    accessor T_182980 = pages[UInt<2>(2)]
    accessor T_182981 = pages[UInt<2>(3)]
    accessor T_182982 = pages[UInt<3>(4)]
    accessor T_182983 = pages[UInt<3>(5)]
    wire T_182984 : UInt<1>
    T_182984 := UInt<1>(0)
    when T_182972 : T_182984 := T_182978
    wire T_182985 : UInt<1>
    T_182985 := UInt<1>(0)
    when T_182973 : T_182985 := T_182979
    wire T_182986 : UInt<1>
    T_182986 := UInt<1>(0)
    when T_182974 : T_182986 := T_182980
    wire T_182987 : UInt<1>
    T_182987 := UInt<1>(0)
    when T_182975 : T_182987 := T_182981
    wire T_182988 : UInt<1>
    T_182988 := UInt<1>(0)
    when T_182976 : T_182988 := T_182982
    wire T_182989 : UInt<1>
    T_182989 := UInt<1>(0)
    when T_182977 : T_182989 := T_182983
    node T_182990 = or(T_182984, T_182985)
    node T_182991 = or(T_182990, T_182986)
    node T_182992 = or(T_182991, T_182987)
    node T_182993 = or(T_182992, T_182988)
    node T_182994 = or(T_182993, T_182989)
    wire T_182995 : UInt<27>
    node T_182996 = bits(T_182994, 26, 0)
    T_182995 := T_182996
    accessor T_182997 = tgts[UInt<1>(0)]
    accessor T_182998 = tgts[UInt<1>(1)]
    accessor T_182999 = tgts[UInt<2>(2)]
    accessor T_183000 = tgts[UInt<2>(3)]
    accessor T_183001 = tgts[UInt<3>(4)]
    accessor T_183002 = tgts[UInt<3>(5)]
    accessor T_183003 = tgts[UInt<3>(6)]
    accessor T_183004 = tgts[UInt<3>(7)]
    accessor T_183005 = tgts[UInt<4>(8)]
    accessor T_183006 = tgts[UInt<4>(9)]
    accessor T_183007 = tgts[UInt<4>(10)]
    accessor T_183008 = tgts[UInt<4>(11)]
    accessor T_183009 = tgts[UInt<4>(12)]
    accessor T_183010 = tgts[UInt<4>(13)]
    accessor T_183011 = tgts[UInt<4>(14)]
    accessor T_183012 = tgts[UInt<4>(15)]
    accessor T_183013 = tgts[UInt<5>(16)]
    accessor T_183014 = tgts[UInt<5>(17)]
    accessor T_183015 = tgts[UInt<5>(18)]
    accessor T_183016 = tgts[UInt<5>(19)]
    accessor T_183017 = tgts[UInt<5>(20)]
    accessor T_183018 = tgts[UInt<5>(21)]
    accessor T_183019 = tgts[UInt<5>(22)]
    accessor T_183020 = tgts[UInt<5>(23)]
    accessor T_183021 = tgts[UInt<5>(24)]
    accessor T_183022 = tgts[UInt<5>(25)]
    accessor T_183023 = tgts[UInt<5>(26)]
    accessor T_183024 = tgts[UInt<5>(27)]
    accessor T_183025 = tgts[UInt<5>(28)]
    accessor T_183026 = tgts[UInt<5>(29)]
    accessor T_183027 = tgts[UInt<5>(30)]
    accessor T_183028 = tgts[UInt<5>(31)]
    accessor T_183029 = tgts[UInt<6>(32)]
    accessor T_183030 = tgts[UInt<6>(33)]
    accessor T_183031 = tgts[UInt<6>(34)]
    accessor T_183032 = tgts[UInt<6>(35)]
    accessor T_183033 = tgts[UInt<6>(36)]
    accessor T_183034 = tgts[UInt<6>(37)]
    accessor T_183035 = tgts[UInt<6>(38)]
    accessor T_183036 = tgts[UInt<6>(39)]
    accessor T_183037 = tgts[UInt<6>(40)]
    accessor T_183038 = tgts[UInt<6>(41)]
    accessor T_183039 = tgts[UInt<6>(42)]
    accessor T_183040 = tgts[UInt<6>(43)]
    accessor T_183041 = tgts[UInt<6>(44)]
    accessor T_183042 = tgts[UInt<6>(45)]
    accessor T_183043 = tgts[UInt<6>(46)]
    accessor T_183044 = tgts[UInt<6>(47)]
    accessor T_183045 = tgts[UInt<6>(48)]
    accessor T_183046 = tgts[UInt<6>(49)]
    accessor T_183047 = tgts[UInt<6>(50)]
    accessor T_183048 = tgts[UInt<6>(51)]
    accessor T_183049 = tgts[UInt<6>(52)]
    accessor T_183050 = tgts[UInt<6>(53)]
    accessor T_183051 = tgts[UInt<6>(54)]
    accessor T_183052 = tgts[UInt<6>(55)]
    accessor T_183053 = tgts[UInt<6>(56)]
    accessor T_183054 = tgts[UInt<6>(57)]
    accessor T_183055 = tgts[UInt<6>(58)]
    accessor T_183056 = tgts[UInt<6>(59)]
    accessor T_183057 = tgts[UInt<6>(60)]
    accessor T_183058 = tgts[UInt<6>(61)]
    wire T_183059 : UInt<1>
    T_183059 := UInt<1>(0)
    when hits[0] : T_183059 := T_182997
    wire T_183060 : UInt<1>
    T_183060 := UInt<1>(0)
    when hits[1] : T_183060 := T_182998
    wire T_183061 : UInt<1>
    T_183061 := UInt<1>(0)
    when hits[2] : T_183061 := T_182999
    wire T_183062 : UInt<1>
    T_183062 := UInt<1>(0)
    when hits[3] : T_183062 := T_183000
    wire T_183063 : UInt<1>
    T_183063 := UInt<1>(0)
    when hits[4] : T_183063 := T_183001
    wire T_183064 : UInt<1>
    T_183064 := UInt<1>(0)
    when hits[5] : T_183064 := T_183002
    wire T_183065 : UInt<1>
    T_183065 := UInt<1>(0)
    when hits[6] : T_183065 := T_183003
    wire T_183066 : UInt<1>
    T_183066 := UInt<1>(0)
    when hits[7] : T_183066 := T_183004
    wire T_183067 : UInt<1>
    T_183067 := UInt<1>(0)
    when hits[8] : T_183067 := T_183005
    wire T_183068 : UInt<1>
    T_183068 := UInt<1>(0)
    when hits[9] : T_183068 := T_183006
    wire T_183069 : UInt<1>
    T_183069 := UInt<1>(0)
    when hits[10] : T_183069 := T_183007
    wire T_183070 : UInt<1>
    T_183070 := UInt<1>(0)
    when hits[11] : T_183070 := T_183008
    wire T_183071 : UInt<1>
    T_183071 := UInt<1>(0)
    when hits[12] : T_183071 := T_183009
    wire T_183072 : UInt<1>
    T_183072 := UInt<1>(0)
    when hits[13] : T_183072 := T_183010
    wire T_183073 : UInt<1>
    T_183073 := UInt<1>(0)
    when hits[14] : T_183073 := T_183011
    wire T_183074 : UInt<1>
    T_183074 := UInt<1>(0)
    when hits[15] : T_183074 := T_183012
    wire T_183075 : UInt<1>
    T_183075 := UInt<1>(0)
    when hits[16] : T_183075 := T_183013
    wire T_183076 : UInt<1>
    T_183076 := UInt<1>(0)
    when hits[17] : T_183076 := T_183014
    wire T_183077 : UInt<1>
    T_183077 := UInt<1>(0)
    when hits[18] : T_183077 := T_183015
    wire T_183078 : UInt<1>
    T_183078 := UInt<1>(0)
    when hits[19] : T_183078 := T_183016
    wire T_183079 : UInt<1>
    T_183079 := UInt<1>(0)
    when hits[20] : T_183079 := T_183017
    wire T_183080 : UInt<1>
    T_183080 := UInt<1>(0)
    when hits[21] : T_183080 := T_183018
    wire T_183081 : UInt<1>
    T_183081 := UInt<1>(0)
    when hits[22] : T_183081 := T_183019
    wire T_183082 : UInt<1>
    T_183082 := UInt<1>(0)
    when hits[23] : T_183082 := T_183020
    wire T_183083 : UInt<1>
    T_183083 := UInt<1>(0)
    when hits[24] : T_183083 := T_183021
    wire T_183084 : UInt<1>
    T_183084 := UInt<1>(0)
    when hits[25] : T_183084 := T_183022
    wire T_183085 : UInt<1>
    T_183085 := UInt<1>(0)
    when hits[26] : T_183085 := T_183023
    wire T_183086 : UInt<1>
    T_183086 := UInt<1>(0)
    when hits[27] : T_183086 := T_183024
    wire T_183087 : UInt<1>
    T_183087 := UInt<1>(0)
    when hits[28] : T_183087 := T_183025
    wire T_183088 : UInt<1>
    T_183088 := UInt<1>(0)
    when hits[29] : T_183088 := T_183026
    wire T_183089 : UInt<1>
    T_183089 := UInt<1>(0)
    when hits[30] : T_183089 := T_183027
    wire T_183090 : UInt<1>
    T_183090 := UInt<1>(0)
    when hits[31] : T_183090 := T_183028
    wire T_183091 : UInt<1>
    T_183091 := UInt<1>(0)
    when hits[32] : T_183091 := T_183029
    wire T_183092 : UInt<1>
    T_183092 := UInt<1>(0)
    when hits[33] : T_183092 := T_183030
    wire T_183093 : UInt<1>
    T_183093 := UInt<1>(0)
    when hits[34] : T_183093 := T_183031
    wire T_183094 : UInt<1>
    T_183094 := UInt<1>(0)
    when hits[35] : T_183094 := T_183032
    wire T_183095 : UInt<1>
    T_183095 := UInt<1>(0)
    when hits[36] : T_183095 := T_183033
    wire T_183096 : UInt<1>
    T_183096 := UInt<1>(0)
    when hits[37] : T_183096 := T_183034
    wire T_183097 : UInt<1>
    T_183097 := UInt<1>(0)
    when hits[38] : T_183097 := T_183035
    wire T_183098 : UInt<1>
    T_183098 := UInt<1>(0)
    when hits[39] : T_183098 := T_183036
    wire T_183099 : UInt<1>
    T_183099 := UInt<1>(0)
    when hits[40] : T_183099 := T_183037
    wire T_183100 : UInt<1>
    T_183100 := UInt<1>(0)
    when hits[41] : T_183100 := T_183038
    wire T_183101 : UInt<1>
    T_183101 := UInt<1>(0)
    when hits[42] : T_183101 := T_183039
    wire T_183102 : UInt<1>
    T_183102 := UInt<1>(0)
    when hits[43] : T_183102 := T_183040
    wire T_183103 : UInt<1>
    T_183103 := UInt<1>(0)
    when hits[44] : T_183103 := T_183041
    wire T_183104 : UInt<1>
    T_183104 := UInt<1>(0)
    when hits[45] : T_183104 := T_183042
    wire T_183105 : UInt<1>
    T_183105 := UInt<1>(0)
    when hits[46] : T_183105 := T_183043
    wire T_183106 : UInt<1>
    T_183106 := UInt<1>(0)
    when hits[47] : T_183106 := T_183044
    wire T_183107 : UInt<1>
    T_183107 := UInt<1>(0)
    when hits[48] : T_183107 := T_183045
    wire T_183108 : UInt<1>
    T_183108 := UInt<1>(0)
    when hits[49] : T_183108 := T_183046
    wire T_183109 : UInt<1>
    T_183109 := UInt<1>(0)
    when hits[50] : T_183109 := T_183047
    wire T_183110 : UInt<1>
    T_183110 := UInt<1>(0)
    when hits[51] : T_183110 := T_183048
    wire T_183111 : UInt<1>
    T_183111 := UInt<1>(0)
    when hits[52] : T_183111 := T_183049
    wire T_183112 : UInt<1>
    T_183112 := UInt<1>(0)
    when hits[53] : T_183112 := T_183050
    wire T_183113 : UInt<1>
    T_183113 := UInt<1>(0)
    when hits[54] : T_183113 := T_183051
    wire T_183114 : UInt<1>
    T_183114 := UInt<1>(0)
    when hits[55] : T_183114 := T_183052
    wire T_183115 : UInt<1>
    T_183115 := UInt<1>(0)
    when hits[56] : T_183115 := T_183053
    wire T_183116 : UInt<1>
    T_183116 := UInt<1>(0)
    when hits[57] : T_183116 := T_183054
    wire T_183117 : UInt<1>
    T_183117 := UInt<1>(0)
    when hits[58] : T_183117 := T_183055
    wire T_183118 : UInt<1>
    T_183118 := UInt<1>(0)
    when hits[59] : T_183118 := T_183056
    wire T_183119 : UInt<1>
    T_183119 := UInt<1>(0)
    when hits[60] : T_183119 := T_183057
    wire T_183120 : UInt<1>
    T_183120 := UInt<1>(0)
    when hits[61] : T_183120 := T_183058
    node T_183121 = or(T_183059, T_183060)
    node T_183122 = or(T_183121, T_183061)
    node T_183123 = or(T_183122, T_183062)
    node T_183124 = or(T_183123, T_183063)
    node T_183125 = or(T_183124, T_183064)
    node T_183126 = or(T_183125, T_183065)
    node T_183127 = or(T_183126, T_183066)
    node T_183128 = or(T_183127, T_183067)
    node T_183129 = or(T_183128, T_183068)
    node T_183130 = or(T_183129, T_183069)
    node T_183131 = or(T_183130, T_183070)
    node T_183132 = or(T_183131, T_183071)
    node T_183133 = or(T_183132, T_183072)
    node T_183134 = or(T_183133, T_183073)
    node T_183135 = or(T_183134, T_183074)
    node T_183136 = or(T_183135, T_183075)
    node T_183137 = or(T_183136, T_183076)
    node T_183138 = or(T_183137, T_183077)
    node T_183139 = or(T_183138, T_183078)
    node T_183140 = or(T_183139, T_183079)
    node T_183141 = or(T_183140, T_183080)
    node T_183142 = or(T_183141, T_183081)
    node T_183143 = or(T_183142, T_183082)
    node T_183144 = or(T_183143, T_183083)
    node T_183145 = or(T_183144, T_183084)
    node T_183146 = or(T_183145, T_183085)
    node T_183147 = or(T_183146, T_183086)
    node T_183148 = or(T_183147, T_183087)
    node T_183149 = or(T_183148, T_183088)
    node T_183150 = or(T_183149, T_183089)
    node T_183151 = or(T_183150, T_183090)
    node T_183152 = or(T_183151, T_183091)
    node T_183153 = or(T_183152, T_183092)
    node T_183154 = or(T_183153, T_183093)
    node T_183155 = or(T_183154, T_183094)
    node T_183156 = or(T_183155, T_183095)
    node T_183157 = or(T_183156, T_183096)
    node T_183158 = or(T_183157, T_183097)
    node T_183159 = or(T_183158, T_183098)
    node T_183160 = or(T_183159, T_183099)
    node T_183161 = or(T_183160, T_183100)
    node T_183162 = or(T_183161, T_183101)
    node T_183163 = or(T_183162, T_183102)
    node T_183164 = or(T_183163, T_183103)
    node T_183165 = or(T_183164, T_183104)
    node T_183166 = or(T_183165, T_183105)
    node T_183167 = or(T_183166, T_183106)
    node T_183168 = or(T_183167, T_183107)
    node T_183169 = or(T_183168, T_183108)
    node T_183170 = or(T_183169, T_183109)
    node T_183171 = or(T_183170, T_183110)
    node T_183172 = or(T_183171, T_183111)
    node T_183173 = or(T_183172, T_183112)
    node T_183174 = or(T_183173, T_183113)
    node T_183175 = or(T_183174, T_183114)
    node T_183176 = or(T_183175, T_183115)
    node T_183177 = or(T_183176, T_183116)
    node T_183178 = or(T_183177, T_183117)
    node T_183179 = or(T_183178, T_183118)
    node T_183180 = or(T_183179, T_183119)
    node T_183181 = or(T_183180, T_183120)
    wire T_183182 : UInt<12>
    node T_183183 = bits(T_183181, 11, 0)
    T_183182 := T_183183
    node T_183184 = cat(T_182995, T_183182)
    resp.bits.target := T_183184
    node T_183185 = cat(hits[60], hits[59])
    node T_183186 = cat(hits[61], T_183185)
    node T_183187 = cat(hits[58], hits[57])
    node T_183188 = cat(hits[56], hits[55])
    node T_183189 = cat(T_183187, T_183188)
    node T_183190 = cat(T_183186, T_183189)
    node T_183191 = cat(hits[54], hits[53])
    node T_183192 = cat(hits[52], hits[51])
    node T_183193 = cat(T_183191, T_183192)
    node T_183194 = cat(hits[50], hits[49])
    node T_183195 = cat(hits[48], hits[47])
    node T_183196 = cat(T_183194, T_183195)
    node T_183197 = cat(T_183193, T_183196)
    node T_183198 = cat(T_183190, T_183197)
    node T_183199 = cat(hits[46], hits[45])
    node T_183200 = cat(hits[44], hits[43])
    node T_183201 = cat(T_183199, T_183200)
    node T_183202 = cat(hits[42], hits[41])
    node T_183203 = cat(hits[40], hits[39])
    node T_183204 = cat(T_183202, T_183203)
    node T_183205 = cat(T_183201, T_183204)
    node T_183206 = cat(hits[38], hits[37])
    node T_183207 = cat(hits[36], hits[35])
    node T_183208 = cat(T_183206, T_183207)
    node T_183209 = cat(hits[34], hits[33])
    node T_183210 = cat(hits[32], hits[31])
    node T_183211 = cat(T_183209, T_183210)
    node T_183212 = cat(T_183208, T_183211)
    node T_183213 = cat(T_183205, T_183212)
    node T_183214 = cat(T_183198, T_183213)
    node T_183215 = cat(hits[29], hits[28])
    node T_183216 = cat(hits[30], T_183215)
    node T_183217 = cat(hits[27], hits[26])
    node T_183218 = cat(hits[25], hits[24])
    node T_183219 = cat(T_183217, T_183218)
    node T_183220 = cat(T_183216, T_183219)
    node T_183221 = cat(hits[23], hits[22])
    node T_183222 = cat(hits[21], hits[20])
    node T_183223 = cat(T_183221, T_183222)
    node T_183224 = cat(hits[19], hits[18])
    node T_183225 = cat(hits[17], hits[16])
    node T_183226 = cat(T_183224, T_183225)
    node T_183227 = cat(T_183223, T_183226)
    node T_183228 = cat(T_183220, T_183227)
    node T_183229 = cat(hits[15], hits[14])
    node T_183230 = cat(hits[13], hits[12])
    node T_183231 = cat(T_183229, T_183230)
    node T_183232 = cat(hits[11], hits[10])
    node T_183233 = cat(hits[9], hits[8])
    node T_183234 = cat(T_183232, T_183233)
    node T_183235 = cat(T_183231, T_183234)
    node T_183236 = cat(hits[7], hits[6])
    node T_183237 = cat(hits[5], hits[4])
    node T_183238 = cat(T_183236, T_183237)
    node T_183239 = cat(hits[3], hits[2])
    node T_183240 = cat(hits[1], hits[0])
    node T_183241 = cat(T_183239, T_183240)
    node T_183242 = cat(T_183238, T_183241)
    node T_183243 = cat(T_183235, T_183242)
    node T_183244 = cat(T_183228, T_183243)
    node T_183245 = cat(T_183214, T_183244)
    node T_183246 = bits(T_183245, 61, 32)
    node T_183247 = bits(T_183245, 31, 0)
    node T_183248 = eq(T_183246, UInt<1>(0))
    node T_183249 = eq(T_183248, UInt<1>(0))
    node T_183250 = or(T_183246, T_183247)
    node T_183251 = bits(T_183250, 31, 16)
    node T_183252 = bits(T_183250, 15, 0)
    node T_183253 = eq(T_183251, UInt<1>(0))
    node T_183254 = eq(T_183253, UInt<1>(0))
    node T_183255 = or(T_183251, T_183252)
    node T_183256 = bits(T_183255, 15, 8)
    node T_183257 = bits(T_183255, 7, 0)
    node T_183258 = eq(T_183256, UInt<1>(0))
    node T_183259 = eq(T_183258, UInt<1>(0))
    node T_183260 = or(T_183256, T_183257)
    node T_183261 = bits(T_183260, 7, 4)
    node T_183262 = bits(T_183260, 3, 0)
    node T_183263 = eq(T_183261, UInt<1>(0))
    node T_183264 = eq(T_183263, UInt<1>(0))
    node T_183265 = or(T_183261, T_183262)
    node T_183266 = bits(T_183265, 3, 2)
    node T_183267 = bits(T_183265, 1, 0)
    node T_183268 = eq(T_183266, UInt<1>(0))
    node T_183269 = eq(T_183268, UInt<1>(0))
    node T_183270 = or(T_183266, T_183267)
    node T_183271 = bit(T_183270, 1)
    node T_183272 = cat(T_183269, T_183271)
    node T_183273 = cat(T_183264, T_183272)
    node T_183274 = cat(T_183259, T_183273)
    node T_183275 = cat(T_183254, T_183274)
    node T_183276 = cat(T_183249, T_183275)
    resp.bits.entry := T_183276
    accessor T_183277 = brIdx[resp.bits.entry]
    resp.bits.bridx := T_183277
    resp.bits.mask := UInt<1>(1)
    cmem T_183278 : UInt<2>[128]
    reg T_183279 : UInt<7>
    wire T_183280 : UInt<1>
    T_183280 := UInt<1>(0)
    when hits[0] : T_183280 := isJump[0]
    wire T_183281 : UInt<1>
    T_183281 := UInt<1>(0)
    when hits[1] : T_183281 := isJump[1]
    wire T_183282 : UInt<1>
    T_183282 := UInt<1>(0)
    when hits[2] : T_183282 := isJump[2]
    wire T_183283 : UInt<1>
    T_183283 := UInt<1>(0)
    when hits[3] : T_183283 := isJump[3]
    wire T_183284 : UInt<1>
    T_183284 := UInt<1>(0)
    when hits[4] : T_183284 := isJump[4]
    wire T_183285 : UInt<1>
    T_183285 := UInt<1>(0)
    when hits[5] : T_183285 := isJump[5]
    wire T_183286 : UInt<1>
    T_183286 := UInt<1>(0)
    when hits[6] : T_183286 := isJump[6]
    wire T_183287 : UInt<1>
    T_183287 := UInt<1>(0)
    when hits[7] : T_183287 := isJump[7]
    wire T_183288 : UInt<1>
    T_183288 := UInt<1>(0)
    when hits[8] : T_183288 := isJump[8]
    wire T_183289 : UInt<1>
    T_183289 := UInt<1>(0)
    when hits[9] : T_183289 := isJump[9]
    wire T_183290 : UInt<1>
    T_183290 := UInt<1>(0)
    when hits[10] : T_183290 := isJump[10]
    wire T_183291 : UInt<1>
    T_183291 := UInt<1>(0)
    when hits[11] : T_183291 := isJump[11]
    wire T_183292 : UInt<1>
    T_183292 := UInt<1>(0)
    when hits[12] : T_183292 := isJump[12]
    wire T_183293 : UInt<1>
    T_183293 := UInt<1>(0)
    when hits[13] : T_183293 := isJump[13]
    wire T_183294 : UInt<1>
    T_183294 := UInt<1>(0)
    when hits[14] : T_183294 := isJump[14]
    wire T_183295 : UInt<1>
    T_183295 := UInt<1>(0)
    when hits[15] : T_183295 := isJump[15]
    wire T_183296 : UInt<1>
    T_183296 := UInt<1>(0)
    when hits[16] : T_183296 := isJump[16]
    wire T_183297 : UInt<1>
    T_183297 := UInt<1>(0)
    when hits[17] : T_183297 := isJump[17]
    wire T_183298 : UInt<1>
    T_183298 := UInt<1>(0)
    when hits[18] : T_183298 := isJump[18]
    wire T_183299 : UInt<1>
    T_183299 := UInt<1>(0)
    when hits[19] : T_183299 := isJump[19]
    wire T_183300 : UInt<1>
    T_183300 := UInt<1>(0)
    when hits[20] : T_183300 := isJump[20]
    wire T_183301 : UInt<1>
    T_183301 := UInt<1>(0)
    when hits[21] : T_183301 := isJump[21]
    wire T_183302 : UInt<1>
    T_183302 := UInt<1>(0)
    when hits[22] : T_183302 := isJump[22]
    wire T_183303 : UInt<1>
    T_183303 := UInt<1>(0)
    when hits[23] : T_183303 := isJump[23]
    wire T_183304 : UInt<1>
    T_183304 := UInt<1>(0)
    when hits[24] : T_183304 := isJump[24]
    wire T_183305 : UInt<1>
    T_183305 := UInt<1>(0)
    when hits[25] : T_183305 := isJump[25]
    wire T_183306 : UInt<1>
    T_183306 := UInt<1>(0)
    when hits[26] : T_183306 := isJump[26]
    wire T_183307 : UInt<1>
    T_183307 := UInt<1>(0)
    when hits[27] : T_183307 := isJump[27]
    wire T_183308 : UInt<1>
    T_183308 := UInt<1>(0)
    when hits[28] : T_183308 := isJump[28]
    wire T_183309 : UInt<1>
    T_183309 := UInt<1>(0)
    when hits[29] : T_183309 := isJump[29]
    wire T_183310 : UInt<1>
    T_183310 := UInt<1>(0)
    when hits[30] : T_183310 := isJump[30]
    wire T_183311 : UInt<1>
    T_183311 := UInt<1>(0)
    when hits[31] : T_183311 := isJump[31]
    wire T_183312 : UInt<1>
    T_183312 := UInt<1>(0)
    when hits[32] : T_183312 := isJump[32]
    wire T_183313 : UInt<1>
    T_183313 := UInt<1>(0)
    when hits[33] : T_183313 := isJump[33]
    wire T_183314 : UInt<1>
    T_183314 := UInt<1>(0)
    when hits[34] : T_183314 := isJump[34]
    wire T_183315 : UInt<1>
    T_183315 := UInt<1>(0)
    when hits[35] : T_183315 := isJump[35]
    wire T_183316 : UInt<1>
    T_183316 := UInt<1>(0)
    when hits[36] : T_183316 := isJump[36]
    wire T_183317 : UInt<1>
    T_183317 := UInt<1>(0)
    when hits[37] : T_183317 := isJump[37]
    wire T_183318 : UInt<1>
    T_183318 := UInt<1>(0)
    when hits[38] : T_183318 := isJump[38]
    wire T_183319 : UInt<1>
    T_183319 := UInt<1>(0)
    when hits[39] : T_183319 := isJump[39]
    wire T_183320 : UInt<1>
    T_183320 := UInt<1>(0)
    when hits[40] : T_183320 := isJump[40]
    wire T_183321 : UInt<1>
    T_183321 := UInt<1>(0)
    when hits[41] : T_183321 := isJump[41]
    wire T_183322 : UInt<1>
    T_183322 := UInt<1>(0)
    when hits[42] : T_183322 := isJump[42]
    wire T_183323 : UInt<1>
    T_183323 := UInt<1>(0)
    when hits[43] : T_183323 := isJump[43]
    wire T_183324 : UInt<1>
    T_183324 := UInt<1>(0)
    when hits[44] : T_183324 := isJump[44]
    wire T_183325 : UInt<1>
    T_183325 := UInt<1>(0)
    when hits[45] : T_183325 := isJump[45]
    wire T_183326 : UInt<1>
    T_183326 := UInt<1>(0)
    when hits[46] : T_183326 := isJump[46]
    wire T_183327 : UInt<1>
    T_183327 := UInt<1>(0)
    when hits[47] : T_183327 := isJump[47]
    wire T_183328 : UInt<1>
    T_183328 := UInt<1>(0)
    when hits[48] : T_183328 := isJump[48]
    wire T_183329 : UInt<1>
    T_183329 := UInt<1>(0)
    when hits[49] : T_183329 := isJump[49]
    wire T_183330 : UInt<1>
    T_183330 := UInt<1>(0)
    when hits[50] : T_183330 := isJump[50]
    wire T_183331 : UInt<1>
    T_183331 := UInt<1>(0)
    when hits[51] : T_183331 := isJump[51]
    wire T_183332 : UInt<1>
    T_183332 := UInt<1>(0)
    when hits[52] : T_183332 := isJump[52]
    wire T_183333 : UInt<1>
    T_183333 := UInt<1>(0)
    when hits[53] : T_183333 := isJump[53]
    wire T_183334 : UInt<1>
    T_183334 := UInt<1>(0)
    when hits[54] : T_183334 := isJump[54]
    wire T_183335 : UInt<1>
    T_183335 := UInt<1>(0)
    when hits[55] : T_183335 := isJump[55]
    wire T_183336 : UInt<1>
    T_183336 := UInt<1>(0)
    when hits[56] : T_183336 := isJump[56]
    wire T_183337 : UInt<1>
    T_183337 := UInt<1>(0)
    when hits[57] : T_183337 := isJump[57]
    wire T_183338 : UInt<1>
    T_183338 := UInt<1>(0)
    when hits[58] : T_183338 := isJump[58]
    wire T_183339 : UInt<1>
    T_183339 := UInt<1>(0)
    when hits[59] : T_183339 := isJump[59]
    wire T_183340 : UInt<1>
    T_183340 := UInt<1>(0)
    when hits[60] : T_183340 := isJump[60]
    wire T_183341 : UInt<1>
    T_183341 := UInt<1>(0)
    when hits[61] : T_183341 := isJump[61]
    node T_183342 = or(T_183280, T_183281)
    node T_183343 = or(T_183342, T_183282)
    node T_183344 = or(T_183343, T_183283)
    node T_183345 = or(T_183344, T_183284)
    node T_183346 = or(T_183345, T_183285)
    node T_183347 = or(T_183346, T_183286)
    node T_183348 = or(T_183347, T_183287)
    node T_183349 = or(T_183348, T_183288)
    node T_183350 = or(T_183349, T_183289)
    node T_183351 = or(T_183350, T_183290)
    node T_183352 = or(T_183351, T_183291)
    node T_183353 = or(T_183352, T_183292)
    node T_183354 = or(T_183353, T_183293)
    node T_183355 = or(T_183354, T_183294)
    node T_183356 = or(T_183355, T_183295)
    node T_183357 = or(T_183356, T_183296)
    node T_183358 = or(T_183357, T_183297)
    node T_183359 = or(T_183358, T_183298)
    node T_183360 = or(T_183359, T_183299)
    node T_183361 = or(T_183360, T_183300)
    node T_183362 = or(T_183361, T_183301)
    node T_183363 = or(T_183362, T_183302)
    node T_183364 = or(T_183363, T_183303)
    node T_183365 = or(T_183364, T_183304)
    node T_183366 = or(T_183365, T_183305)
    node T_183367 = or(T_183366, T_183306)
    node T_183368 = or(T_183367, T_183307)
    node T_183369 = or(T_183368, T_183308)
    node T_183370 = or(T_183369, T_183309)
    node T_183371 = or(T_183370, T_183310)
    node T_183372 = or(T_183371, T_183311)
    node T_183373 = or(T_183372, T_183312)
    node T_183374 = or(T_183373, T_183313)
    node T_183375 = or(T_183374, T_183314)
    node T_183376 = or(T_183375, T_183315)
    node T_183377 = or(T_183376, T_183316)
    node T_183378 = or(T_183377, T_183317)
    node T_183379 = or(T_183378, T_183318)
    node T_183380 = or(T_183379, T_183319)
    node T_183381 = or(T_183380, T_183320)
    node T_183382 = or(T_183381, T_183321)
    node T_183383 = or(T_183382, T_183322)
    node T_183384 = or(T_183383, T_183323)
    node T_183385 = or(T_183384, T_183324)
    node T_183386 = or(T_183385, T_183325)
    node T_183387 = or(T_183386, T_183326)
    node T_183388 = or(T_183387, T_183327)
    node T_183389 = or(T_183388, T_183328)
    node T_183390 = or(T_183389, T_183329)
    node T_183391 = or(T_183390, T_183330)
    node T_183392 = or(T_183391, T_183331)
    node T_183393 = or(T_183392, T_183332)
    node T_183394 = or(T_183393, T_183333)
    node T_183395 = or(T_183394, T_183334)
    node T_183396 = or(T_183395, T_183335)
    node T_183397 = or(T_183396, T_183336)
    node T_183398 = or(T_183397, T_183337)
    node T_183399 = or(T_183398, T_183338)
    node T_183400 = or(T_183399, T_183339)
    node T_183401 = or(T_183400, T_183340)
    node T_183402 = or(T_183401, T_183341)
    wire T_183403 : UInt<1>
    node T_183404 = bits(T_183402, 0, 0)
    T_183403 := T_183404
    node T_183405 = eq(T_183403, UInt<1>(0))
    node T_183406 = and(req.valid, resp.valid)
    node T_183407 = and(T_183406, T_183405)
    wire T_183408 : {history : UInt<7>, value : UInt<2>}
    node T_183409 = bits(req.bits.addr, 8, 2)
    node T_183410 = xor(T_183409, T_183279)
    accessor T_183411 = T_183278[T_183410]
    T_183408.value := T_183411
    T_183408.history := T_183279
    node T_183412 = bit(T_183408.value, 0)
    when T_183407 : 
      node T_183413 = bits(T_183279, 6, 1)
      node T_183414 = cat(T_183412, T_183413)
      T_183279 := T_183414
    
    node T_183415 = and(bht_update.valid, bht_update.bits.prediction.valid)
    when T_183415 : 
      node T_183416 = bits(bht_update.bits.pc, 8, 2)
      node T_183417 = xor(T_183416, bht_update.bits.prediction.bits.bht.history)
      accessor T_183418 = T_183278[T_183417]
      node T_183419 = bit(bht_update.bits.prediction.bits.bht.value, 1)
      node T_183420 = bit(bht_update.bits.prediction.bits.bht.value, 0)
      node T_183421 = and(T_183419, T_183420)
      node T_183422 = bit(bht_update.bits.prediction.bits.bht.value, 1)
      node T_183423 = bit(bht_update.bits.prediction.bits.bht.value, 0)
      node T_183424 = or(T_183422, T_183423)
      node T_183425 = and(T_183424, bht_update.bits.taken)
      node T_183426 = or(T_183421, T_183425)
      node T_183427 = cat(bht_update.bits.taken, T_183426)
      T_183418 := T_183427
      when bht_update.bits.mispredict : 
        node T_183428 = bits(bht_update.bits.prediction.bits.bht.history, 6, 1)
        node T_183429 = cat(bht_update.bits.taken, T_183428)
        T_183279 := T_183429
    
    
    node T_183430 = bit(T_183408.value, 0)
    node T_183431 = eq(T_183430, UInt<1>(0))
    node T_183432 = and(T_183431, T_183405)
    when T_183432 : resp.bits.taken := UInt<1>(0)
    resp.bits.bht := T_183408
    reg T_183433 : UInt<2>
    onreset T_183433 := UInt<2>(0)
    reg T_183434 : UInt<1>
    onreset T_183434 := UInt<1>(0)
    wire T_183435 : UInt[2]
    T_183435[0] := T_183436
    T_183435[1] := T_183437
    reg T_183438 : UInt[2]
    wire T_183439 : UInt<1>
    T_183439 := UInt<1>(0)
    when hits[0] : T_183439 := useRAS[0]
    wire T_183440 : UInt<1>
    T_183440 := UInt<1>(0)
    when hits[1] : T_183440 := useRAS[1]
    wire T_183441 : UInt<1>
    T_183441 := UInt<1>(0)
    when hits[2] : T_183441 := useRAS[2]
    wire T_183442 : UInt<1>
    T_183442 := UInt<1>(0)
    when hits[3] : T_183442 := useRAS[3]
    wire T_183443 : UInt<1>
    T_183443 := UInt<1>(0)
    when hits[4] : T_183443 := useRAS[4]
    wire T_183444 : UInt<1>
    T_183444 := UInt<1>(0)
    when hits[5] : T_183444 := useRAS[5]
    wire T_183445 : UInt<1>
    T_183445 := UInt<1>(0)
    when hits[6] : T_183445 := useRAS[6]
    wire T_183446 : UInt<1>
    T_183446 := UInt<1>(0)
    when hits[7] : T_183446 := useRAS[7]
    wire T_183447 : UInt<1>
    T_183447 := UInt<1>(0)
    when hits[8] : T_183447 := useRAS[8]
    wire T_183448 : UInt<1>
    T_183448 := UInt<1>(0)
    when hits[9] : T_183448 := useRAS[9]
    wire T_183449 : UInt<1>
    T_183449 := UInt<1>(0)
    when hits[10] : T_183449 := useRAS[10]
    wire T_183450 : UInt<1>
    T_183450 := UInt<1>(0)
    when hits[11] : T_183450 := useRAS[11]
    wire T_183451 : UInt<1>
    T_183451 := UInt<1>(0)
    when hits[12] : T_183451 := useRAS[12]
    wire T_183452 : UInt<1>
    T_183452 := UInt<1>(0)
    when hits[13] : T_183452 := useRAS[13]
    wire T_183453 : UInt<1>
    T_183453 := UInt<1>(0)
    when hits[14] : T_183453 := useRAS[14]
    wire T_183454 : UInt<1>
    T_183454 := UInt<1>(0)
    when hits[15] : T_183454 := useRAS[15]
    wire T_183455 : UInt<1>
    T_183455 := UInt<1>(0)
    when hits[16] : T_183455 := useRAS[16]
    wire T_183456 : UInt<1>
    T_183456 := UInt<1>(0)
    when hits[17] : T_183456 := useRAS[17]
    wire T_183457 : UInt<1>
    T_183457 := UInt<1>(0)
    when hits[18] : T_183457 := useRAS[18]
    wire T_183458 : UInt<1>
    T_183458 := UInt<1>(0)
    when hits[19] : T_183458 := useRAS[19]
    wire T_183459 : UInt<1>
    T_183459 := UInt<1>(0)
    when hits[20] : T_183459 := useRAS[20]
    wire T_183460 : UInt<1>
    T_183460 := UInt<1>(0)
    when hits[21] : T_183460 := useRAS[21]
    wire T_183461 : UInt<1>
    T_183461 := UInt<1>(0)
    when hits[22] : T_183461 := useRAS[22]
    wire T_183462 : UInt<1>
    T_183462 := UInt<1>(0)
    when hits[23] : T_183462 := useRAS[23]
    wire T_183463 : UInt<1>
    T_183463 := UInt<1>(0)
    when hits[24] : T_183463 := useRAS[24]
    wire T_183464 : UInt<1>
    T_183464 := UInt<1>(0)
    when hits[25] : T_183464 := useRAS[25]
    wire T_183465 : UInt<1>
    T_183465 := UInt<1>(0)
    when hits[26] : T_183465 := useRAS[26]
    wire T_183466 : UInt<1>
    T_183466 := UInt<1>(0)
    when hits[27] : T_183466 := useRAS[27]
    wire T_183467 : UInt<1>
    T_183467 := UInt<1>(0)
    when hits[28] : T_183467 := useRAS[28]
    wire T_183468 : UInt<1>
    T_183468 := UInt<1>(0)
    when hits[29] : T_183468 := useRAS[29]
    wire T_183469 : UInt<1>
    T_183469 := UInt<1>(0)
    when hits[30] : T_183469 := useRAS[30]
    wire T_183470 : UInt<1>
    T_183470 := UInt<1>(0)
    when hits[31] : T_183470 := useRAS[31]
    wire T_183471 : UInt<1>
    T_183471 := UInt<1>(0)
    when hits[32] : T_183471 := useRAS[32]
    wire T_183472 : UInt<1>
    T_183472 := UInt<1>(0)
    when hits[33] : T_183472 := useRAS[33]
    wire T_183473 : UInt<1>
    T_183473 := UInt<1>(0)
    when hits[34] : T_183473 := useRAS[34]
    wire T_183474 : UInt<1>
    T_183474 := UInt<1>(0)
    when hits[35] : T_183474 := useRAS[35]
    wire T_183475 : UInt<1>
    T_183475 := UInt<1>(0)
    when hits[36] : T_183475 := useRAS[36]
    wire T_183476 : UInt<1>
    T_183476 := UInt<1>(0)
    when hits[37] : T_183476 := useRAS[37]
    wire T_183477 : UInt<1>
    T_183477 := UInt<1>(0)
    when hits[38] : T_183477 := useRAS[38]
    wire T_183478 : UInt<1>
    T_183478 := UInt<1>(0)
    when hits[39] : T_183478 := useRAS[39]
    wire T_183479 : UInt<1>
    T_183479 := UInt<1>(0)
    when hits[40] : T_183479 := useRAS[40]
    wire T_183480 : UInt<1>
    T_183480 := UInt<1>(0)
    when hits[41] : T_183480 := useRAS[41]
    wire T_183481 : UInt<1>
    T_183481 := UInt<1>(0)
    when hits[42] : T_183481 := useRAS[42]
    wire T_183482 : UInt<1>
    T_183482 := UInt<1>(0)
    when hits[43] : T_183482 := useRAS[43]
    wire T_183483 : UInt<1>
    T_183483 := UInt<1>(0)
    when hits[44] : T_183483 := useRAS[44]
    wire T_183484 : UInt<1>
    T_183484 := UInt<1>(0)
    when hits[45] : T_183484 := useRAS[45]
    wire T_183485 : UInt<1>
    T_183485 := UInt<1>(0)
    when hits[46] : T_183485 := useRAS[46]
    wire T_183486 : UInt<1>
    T_183486 := UInt<1>(0)
    when hits[47] : T_183486 := useRAS[47]
    wire T_183487 : UInt<1>
    T_183487 := UInt<1>(0)
    when hits[48] : T_183487 := useRAS[48]
    wire T_183488 : UInt<1>
    T_183488 := UInt<1>(0)
    when hits[49] : T_183488 := useRAS[49]
    wire T_183489 : UInt<1>
    T_183489 := UInt<1>(0)
    when hits[50] : T_183489 := useRAS[50]
    wire T_183490 : UInt<1>
    T_183490 := UInt<1>(0)
    when hits[51] : T_183490 := useRAS[51]
    wire T_183491 : UInt<1>
    T_183491 := UInt<1>(0)
    when hits[52] : T_183491 := useRAS[52]
    wire T_183492 : UInt<1>
    T_183492 := UInt<1>(0)
    when hits[53] : T_183492 := useRAS[53]
    wire T_183493 : UInt<1>
    T_183493 := UInt<1>(0)
    when hits[54] : T_183493 := useRAS[54]
    wire T_183494 : UInt<1>
    T_183494 := UInt<1>(0)
    when hits[55] : T_183494 := useRAS[55]
    wire T_183495 : UInt<1>
    T_183495 := UInt<1>(0)
    when hits[56] : T_183495 := useRAS[56]
    wire T_183496 : UInt<1>
    T_183496 := UInt<1>(0)
    when hits[57] : T_183496 := useRAS[57]
    wire T_183497 : UInt<1>
    T_183497 := UInt<1>(0)
    when hits[58] : T_183497 := useRAS[58]
    wire T_183498 : UInt<1>
    T_183498 := UInt<1>(0)
    when hits[59] : T_183498 := useRAS[59]
    wire T_183499 : UInt<1>
    T_183499 := UInt<1>(0)
    when hits[60] : T_183499 := useRAS[60]
    wire T_183500 : UInt<1>
    T_183500 := UInt<1>(0)
    when hits[61] : T_183500 := useRAS[61]
    node T_183501 = or(T_183439, T_183440)
    node T_183502 = or(T_183501, T_183441)
    node T_183503 = or(T_183502, T_183442)
    node T_183504 = or(T_183503, T_183443)
    node T_183505 = or(T_183504, T_183444)
    node T_183506 = or(T_183505, T_183445)
    node T_183507 = or(T_183506, T_183446)
    node T_183508 = or(T_183507, T_183447)
    node T_183509 = or(T_183508, T_183448)
    node T_183510 = or(T_183509, T_183449)
    node T_183511 = or(T_183510, T_183450)
    node T_183512 = or(T_183511, T_183451)
    node T_183513 = or(T_183512, T_183452)
    node T_183514 = or(T_183513, T_183453)
    node T_183515 = or(T_183514, T_183454)
    node T_183516 = or(T_183515, T_183455)
    node T_183517 = or(T_183516, T_183456)
    node T_183518 = or(T_183517, T_183457)
    node T_183519 = or(T_183518, T_183458)
    node T_183520 = or(T_183519, T_183459)
    node T_183521 = or(T_183520, T_183460)
    node T_183522 = or(T_183521, T_183461)
    node T_183523 = or(T_183522, T_183462)
    node T_183524 = or(T_183523, T_183463)
    node T_183525 = or(T_183524, T_183464)
    node T_183526 = or(T_183525, T_183465)
    node T_183527 = or(T_183526, T_183466)
    node T_183528 = or(T_183527, T_183467)
    node T_183529 = or(T_183528, T_183468)
    node T_183530 = or(T_183529, T_183469)
    node T_183531 = or(T_183530, T_183470)
    node T_183532 = or(T_183531, T_183471)
    node T_183533 = or(T_183532, T_183472)
    node T_183534 = or(T_183533, T_183473)
    node T_183535 = or(T_183534, T_183474)
    node T_183536 = or(T_183535, T_183475)
    node T_183537 = or(T_183536, T_183476)
    node T_183538 = or(T_183537, T_183477)
    node T_183539 = or(T_183538, T_183478)
    node T_183540 = or(T_183539, T_183479)
    node T_183541 = or(T_183540, T_183480)
    node T_183542 = or(T_183541, T_183481)
    node T_183543 = or(T_183542, T_183482)
    node T_183544 = or(T_183543, T_183483)
    node T_183545 = or(T_183544, T_183484)
    node T_183546 = or(T_183545, T_183485)
    node T_183547 = or(T_183546, T_183486)
    node T_183548 = or(T_183547, T_183487)
    node T_183549 = or(T_183548, T_183488)
    node T_183550 = or(T_183549, T_183489)
    node T_183551 = or(T_183550, T_183490)
    node T_183552 = or(T_183551, T_183491)
    node T_183553 = or(T_183552, T_183492)
    node T_183554 = or(T_183553, T_183493)
    node T_183555 = or(T_183554, T_183494)
    node T_183556 = or(T_183555, T_183495)
    node T_183557 = or(T_183556, T_183496)
    node T_183558 = or(T_183557, T_183497)
    node T_183559 = or(T_183558, T_183498)
    node T_183560 = or(T_183559, T_183499)
    node T_183561 = or(T_183560, T_183500)
    wire T_183562 : UInt<1>
    node T_183563 = bits(T_183561, 0, 0)
    T_183562 := T_183563
    
    
    node T_183564 = eq(T_183433, UInt<1>(0))
    node T_183565 = eq(T_183564, UInt<1>(0))
    node T_183566 = and(T_183565, T_183562)
    when T_183566 : 
      accessor T_183567 = T_183438[T_183434]
      resp.bits.target := T_183567
    when ras_update.valid : when ras_update.bits.isCall : 
        
        node T_183576 = lt(T_183433, UInt<2>(2))
        when T_183576 : 
          node T_183577 = addw(T_183433, UInt<1>(1))
          T_183433 := T_183577
        node T_183578 = lt(T_183434, UInt<1>(1))
        node T_183579 = or(UInt<1>(1), T_183578)
        node T_183580 = addw(T_183434, UInt<1>(1))
        wire T_183581 : UInt<1>
        T_183581 := UInt<1>(0)
        when T_183579 : T_183581 := T_183580
        accessor T_183582 = T_183438[T_183581]
        T_183582 := ras_update.bits.returnAddr
        T_183434 := T_183581
        when T_183562 : resp.bits.target := ras_update.bits.returnAddr
      else : 
        
        node T_183568 = and(ras_update.bits.isReturn, ras_update.bits.prediction.valid)
        when T_183568 : 
          
          node T_183569 = eq(T_183433, UInt<1>(0))
          node T_183570 = eq(T_183569, UInt<1>(0))
          when T_183570 : 
            node T_183571 = subw(T_183433, UInt<1>(1))
            T_183433 := T_183571
            node T_183572 = gt(T_183434, UInt<1>(0))
            node T_183573 = or(UInt<1>(1), T_183572)
            node T_183574 = subw(T_183434, UInt<1>(1))
            wire T_183575 : UInt<1>
            T_183575 := UInt<1>(1)
            when T_183573 : T_183575 := T_183574
            T_183434 := T_183575
    when invalidate : T_183433 := UInt<1>(0)
  module FlowThroughSerializer : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output cnt : UInt<1>
    output done : UInt<1>
    
    wire T_183583 : UInt<3>[3]
    T_183583[0] := UInt<3>(0)
    T_183583[1] := UInt<3>(1)
    T_183583[2] := UInt<3>(2)
    wire T_183584 : UInt<2>[2]
    T_183584[0] := UInt<2>(0)
    T_183584[1] := UInt<2>(1)
    wire T_183585 : UInt<2>[3]
    T_183585[0] := UInt<2>(1)
    T_183585[1] := UInt<2>(2)
    T_183585[2] := UInt<2>(3)
    wire T_183586 : UInt<2>[2]
    T_183586[0] := UInt<2>(2)
    T_183586[1] := UInt<2>(3)
    wire T_183587 : UInt<2>[1]
    T_183587[0] := UInt<2>(3)
    wire T_183588 : UInt<3>[3]
    T_183588[0] := UInt<3>(0)
    T_183588[1] := UInt<3>(1)
    T_183588[2] := UInt<3>(2)
    wire T_183589 : UInt<2>[2]
    T_183589[0] := UInt<2>(0)
    T_183589[1] := UInt<2>(1)
    wire T_183590 : UInt<2>[3]
    T_183590[0] := UInt<2>(1)
    T_183590[1] := UInt<2>(2)
    T_183590[2] := UInt<2>(3)
    wire T_183591 : UInt<2>[2]
    T_183591[0] := UInt<2>(2)
    T_183591[1] := UInt<2>(3)
    wire T_183592 : UInt<2>[1]
    T_183592[0] := UInt<2>(3)
    in <> out
    cnt := T_183593
    done := UInt<1>(1)
  module ICache : 
    input req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}
    output resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}
    input invalidate : UInt<1>
    output mem__ : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    
    wire T_183594 : UInt<3>[3]
    T_183594[0] := UInt<3>(0)
    T_183594[1] := UInt<3>(1)
    T_183594[2] := UInt<3>(2)
    wire T_183595 : UInt<2>[2]
    T_183595[0] := UInt<2>(0)
    T_183595[1] := UInt<2>(1)
    wire T_183596 : UInt<2>[3]
    T_183596[0] := UInt<2>(1)
    T_183596[1] := UInt<2>(2)
    T_183596[2] := UInt<2>(3)
    wire T_183597 : UInt<2>[2]
    T_183597[0] := UInt<2>(2)
    T_183597[1] := UInt<2>(3)
    wire T_183598 : UInt<2>[1]
    T_183598[0] := UInt<2>(3)
    wire T_183599 : UInt<3>[3]
    T_183599[0] := UInt<3>(0)
    T_183599[1] := UInt<3>(1)
    T_183599[2] := UInt<3>(2)
    wire T_183600 : UInt<2>[2]
    T_183600[0] := UInt<2>(0)
    T_183600[1] := UInt<2>(1)
    wire T_183601 : UInt<2>[3]
    T_183601[0] := UInt<2>(1)
    T_183601[1] := UInt<2>(2)
    T_183601[2] := UInt<2>(3)
    wire T_183602 : UInt<2>[2]
    T_183602[0] := UInt<2>(2)
    T_183602[1] := UInt<2>(3)
    wire T_183603 : UInt<2>[1]
    T_183603[0] := UInt<2>(3)
    wire T_183604 : UInt<3>[3]
    T_183604[0] := UInt<3>(0)
    T_183604[1] := UInt<3>(1)
    T_183604[2] := UInt<3>(2)
    wire T_183605 : UInt<2>[2]
    T_183605[0] := UInt<2>(0)
    T_183605[1] := UInt<2>(1)
    wire T_183606 : UInt<2>[3]
    T_183606[0] := UInt<2>(1)
    T_183606[1] := UInt<2>(2)
    T_183606[2] := UInt<2>(3)
    wire T_183607 : UInt<2>[2]
    T_183607[0] := UInt<2>(2)
    T_183607[1] := UInt<2>(3)
    wire T_183608 : UInt<2>[1]
    T_183608[0] := UInt<2>(3)
    wire T_183609 : UInt<3>[3]
    T_183609[0] := UInt<3>(0)
    T_183609[1] := UInt<3>(1)
    T_183609[2] := UInt<3>(2)
    wire T_183610 : UInt<2>[2]
    T_183610[0] := UInt<2>(0)
    T_183610[1] := UInt<2>(1)
    wire T_183611 : UInt<2>[3]
    T_183611[0] := UInt<2>(1)
    T_183611[1] := UInt<2>(2)
    T_183611[2] := UInt<2>(3)
    wire T_183612 : UInt<2>[2]
    T_183612[0] := UInt<2>(2)
    T_183612[1] := UInt<2>(3)
    wire T_183613 : UInt<2>[1]
    T_183613[0] := UInt<2>(3)
    wire T_183614 : UInt<3>[3]
    T_183614[0] := UInt<3>(0)
    T_183614[1] := UInt<3>(1)
    T_183614[2] := UInt<3>(2)
    wire T_183615 : UInt<2>[2]
    T_183615[0] := UInt<2>(0)
    T_183615[1] := UInt<2>(1)
    wire T_183616 : UInt<2>[3]
    T_183616[0] := UInt<2>(1)
    T_183616[1] := UInt<2>(2)
    T_183616[2] := UInt<2>(3)
    wire T_183617 : UInt<2>[2]
    T_183617[0] := UInt<2>(2)
    T_183617[1] := UInt<2>(3)
    wire T_183618 : UInt<2>[1]
    T_183618[0] := UInt<2>(3)
    reg state : UInt<2>
    onreset state := UInt<2>(0)
    reg invalidated : UInt<1>
    node stall = eq(resp.ready, UInt<1>(0))
    wire rdy : UInt<1>
    reg s2_valid : UInt<1>
    onreset s2_valid := UInt<1>(0)
    reg s2_addr : UInt<32>
    wire s2_any_tag_hit : UInt<1>
    reg s1_valid : UInt<1>
    onreset s1_valid := UInt<1>(0)
    reg s1_pgoff : UInt<12>
    node s1_addr = cat(req.bits.ppn, s1_pgoff)
    node s1_tag = bits(s1_addr, 31, 12)
    node T_183619 = and(s1_valid, stall)
    node s0_valid = or(req.valid, T_183619)
    node T_183620 = and(s1_valid, stall)
    wire s0_pgoff : UInt<12>
    s0_pgoff := req.bits.idx
    when T_183620 : s0_pgoff := s1_pgoff
    node T_183621 = and(req.valid, rdy)
    node T_183622 = and(s1_valid, stall)
    node T_183623 = eq(req.bits.kill, UInt<1>(0))
    node T_183624 = and(T_183622, T_183623)
    node T_183625 = or(T_183621, T_183624)
    s1_valid := T_183625
    
    node T_183626 = and(req.valid, rdy)
    when T_183626 : s1_pgoff := req.bits.idx
    node T_183627 = and(s1_valid, rdy)
    node T_183628 = eq(req.bits.kill, UInt<1>(0))
    node T_183629 = and(T_183627, T_183628)
    node T_183630 = and(resp.valid, stall)
    node T_183631 = or(T_183629, T_183630)
    s2_valid := T_183631
    
    
    node T_183632 = and(s1_valid, rdy)
    node T_183633 = eq(stall, UInt<1>(0))
    node T_183634 = and(T_183632, T_183633)
    when T_183634 : s2_addr := s1_addr
    node s2_tag = bits(s2_addr, 31, 12)
    node s2_idx = bits(s2_addr, 11, 6)
    node s2_offset = bits(s2_addr, 5, 0)
    node s2_hit = and(s2_valid, s2_any_tag_hit)
    node T_183635 = eq(s2_any_tag_hit, UInt<1>(0))
    node s2_miss = and(s2_valid, T_183635)
    node T_183636 = eq(state, UInt<2>(0))
    node T_183637 = eq(s2_miss, UInt<1>(0))
    node T_183638 = and(T_183636, T_183637)
    rdy := T_183638
    inst T_183639 of FlowThroughSerializer
    T_183639.in.valid := mem__.grant.valid
    T_183639.in.bits := mem__.grant.bits
    mem__.grant.ready := T_183639.in.ready
    node T_183640 = and(T_183639.out.ready, T_183639.out.valid)
    reg refill_cnt : UInt<2>
    onreset refill_cnt := UInt<2>(0)
    when T_183640 : 
      node T_183641 = eq(refill_cnt, UInt<2>(3))
      node T_183642 = and(UInt<1>(0), T_183641)
      node T_183643 = addw(refill_cnt, UInt<1>(1))
      wire T_183644 : UInt<2>
      T_183644 := T_183643
      when T_183642 : T_183644 := UInt<1>(0)
      refill_cnt := T_183644
    node refill_wrap = and(T_183640, T_183641)
    node T_183645 = eq(state, UInt<2>(3))
    node refill_done = and(T_183645, refill_wrap)
    T_183639.out.ready := UInt<1>(1)
    reg T_183646 : UInt<16>
    onreset T_183646 := UInt<16>(1)
    when s2_miss : 
      node T_183647 = bit(T_183646, 0)
      node T_183648 = bit(T_183646, 2)
      node T_183649 = xor(T_183647, T_183648)
      node T_183650 = bit(T_183646, 3)
      node T_183651 = xor(T_183649, T_183650)
      node T_183652 = bit(T_183646, 5)
      node T_183653 = xor(T_183651, T_183652)
      node T_183654 = bits(T_183646, 15, 1)
      node T_183655 = cat(T_183653, T_183654)
      T_183646 := T_183655
    node repl_way = bits(T_183646, 1, 0)
    cmem T_183656 : UInt<80>[64]
    node T_183657 = bits(s0_pgoff, 11, 6)
    node T_183658 = eq(refill_done, UInt<1>(0))
    node T_183659 = and(T_183658, s0_valid)
    reg T_183660 : UInt<6>
    when T_183659 : T_183660 := T_183657
    accessor tag_rdata = T_183656[T_183660]
    when refill_done : 
      node T_183661 = dshl(UInt<1>(1), repl_way)
      node T_183662 = bit(T_183661, 0)
      node T_183663 = bit(T_183661, 1)
      node T_183664 = bit(T_183661, 2)
      node T_183665 = bit(T_183661, 3)
      node T_183666 = bit(T_183661, 4)
      wire T_183667 : UInt<1>[5]
      T_183667[0] := T_183662
      T_183667[1] := T_183663
      T_183667[2] := T_183664
      T_183667[3] := T_183665
      T_183667[4] := T_183666
      node T_183668 = subw(UInt<20>(0), UInt<5>(20))
      node T_183669 = subw(UInt<20>(0), UInt<5>(20))
      node T_183670 = subw(UInt<20>(0), UInt<5>(20))
      node T_183671 = subw(UInt<20>(0), UInt<5>(20))
      node T_183672 = subw(UInt<20>(0), UInt<5>(20))
      wire T_183673 : UInt<20>[5]
      T_183673[0] := T_183668
      T_183673[1] := T_183669
      T_183673[2] := T_183670
      T_183673[3] := T_183671
      T_183673[4] := T_183672
      node T_183674 = cat(T_183673[4], T_183673[3])
      node T_183675 = cat(T_183673[1], T_183673[0])
      node T_183676 = cat(T_183673[2], T_183675)
      node T_183677 = cat(T_183674, T_183676)
      node T_183678 = cat(s2_tag, s2_tag)
      node T_183679 = cat(T_183678, T_183678)
      accessor T_183680 = T_183656[s2_idx]
      node T_183681 = not(T_183677)
      node T_183682 = and(T_183680, T_183681)
      node T_183683 = and(T_183679, T_183677)
      node T_183684 = or(T_183682, T_183683)
      wire T_183685 : UInt<80>
      node T_183686 = bits(T_183684, 79, 0)
      T_183685 := T_183686
      accessor T_183687 = T_183656[s2_idx]
      T_183687 := T_183685
    reg vb_array : UInt<256>
    onreset vb_array := UInt<256>(0)
    
    
    node T_183688 = eq(invalidated, UInt<1>(0))
    node T_183689 = and(refill_done, T_183688)
    when T_183689 : 
      node T_183690 = cat(repl_way, s2_idx)
      node T_183691 = dshl(UInt<1>(1), T_183690)
      node T_183692 = or(vb_array, T_183691)
      node T_183693 = not(vb_array)
      node T_183694 = or(T_183693, T_183691)
      node T_183695 = not(T_183694)
      wire T_183696 : UInt<257>
      T_183696 := T_183695
      when UInt<1>(1) : T_183696 := T_183692
      vb_array := T_183696
    when invalidate : 
      vb_array := UInt<1>(0)
      invalidated := UInt<1>(1)
    wire s2_disparity : UInt<1>[4]
    
    node T_183697 = and(s2_valid, s2_disparity[0])
    when T_183697 : 
      node T_183698 = cat(UInt<1>(0), s2_idx)
      node T_183699 = dshl(UInt<1>(1), T_183698)
      node T_183700 = or(vb_array, T_183699)
      node T_183701 = not(vb_array)
      node T_183702 = or(T_183701, T_183699)
      node T_183703 = not(T_183702)
      wire T_183704 : UInt<256>
      T_183704 := T_183703
      when UInt<1>(0) : T_183704 := T_183700
      vb_array := T_183704
    
    node T_183705 = and(s2_valid, s2_disparity[1])
    when T_183705 : 
      node T_183706 = cat(UInt<1>(1), s2_idx)
      node T_183707 = dshl(UInt<1>(1), T_183706)
      node T_183708 = or(vb_array, T_183707)
      node T_183709 = not(vb_array)
      node T_183710 = or(T_183709, T_183707)
      node T_183711 = not(T_183710)
      wire T_183712 : UInt<256>
      T_183712 := T_183711
      when UInt<1>(0) : T_183712 := T_183708
      vb_array := T_183712
    
    node T_183713 = and(s2_valid, s2_disparity[2])
    when T_183713 : 
      node T_183714 = cat(UInt<2>(2), s2_idx)
      node T_183715 = dshl(UInt<1>(1), T_183714)
      node T_183716 = or(vb_array, T_183715)
      node T_183717 = not(vb_array)
      node T_183718 = or(T_183717, T_183715)
      node T_183719 = not(T_183718)
      wire T_183720 : UInt<257>
      T_183720 := T_183719
      when UInt<1>(0) : T_183720 := T_183716
      vb_array := T_183720
    
    node T_183721 = and(s2_valid, s2_disparity[3])
    when T_183721 : 
      node T_183722 = cat(UInt<2>(3), s2_idx)
      node T_183723 = dshl(UInt<1>(1), T_183722)
      node T_183724 = or(vb_array, T_183723)
      node T_183725 = not(vb_array)
      node T_183726 = or(T_183725, T_183723)
      node T_183727 = not(T_183726)
      wire T_183728 : UInt<257>
      T_183728 := T_183727
      when UInt<1>(0) : T_183728 := T_183724
      vb_array := T_183728
    wire s1_tag_match : UInt<1>[4]
    wire s2_tag_hit : UInt<1>[4]
    reg s2_dout : UInt[4]
    node T_183729 = eq(invalidate, UInt<1>(0))
    node T_183730 = bits(s1_pgoff, 11, 6)
    node T_183731 = cat(UInt<1>(0), T_183730)
    node T_183732 = dshr(vb_array, T_183731)
    node T_183733 = bit(T_183732, 0)
    node T_183734 = bit(T_183733, 0)
    node T_183735 = and(T_183729, T_183734)
    reg T_183736 : UInt<1>
    reg T_183737 : UInt<1>
    reg T_183738 : UInt<1>
    node T_183739 = bits(tag_rdata, 19, 0)
    
    
    node T_183740 = and(s1_valid, rdy)
    node T_183741 = eq(stall, UInt<1>(0))
    node T_183742 = and(T_183740, T_183741)
    when T_183742 : 
      T_183736 := T_183735
      node T_183743 = or(UInt<1>(0), UInt<1>(0))
      T_183737 := T_183743
      T_183738 := s1_tag_match[0]
    node T_183744 = bits(T_183739, 19, 0)
    node T_183745 = eq(T_183744, s1_tag)
    s1_tag_match[0] := T_183745
    node T_183746 = and(T_183736, T_183738)
    s2_tag_hit[0] := T_183746
    node T_183747 = or(UInt<1>(0), UInt<1>(0))
    node T_183748 = or(T_183737, T_183747)
    node T_183749 = and(T_183736, T_183748)
    s2_disparity[0] := T_183749
    node T_183750 = eq(invalidate, UInt<1>(0))
    node T_183751 = bits(s1_pgoff, 11, 6)
    node T_183752 = cat(UInt<1>(1), T_183751)
    node T_183753 = dshr(vb_array, T_183752)
    node T_183754 = bit(T_183753, 0)
    node T_183755 = bit(T_183754, 0)
    node T_183756 = and(T_183750, T_183755)
    reg T_183757 : UInt<1>
    reg T_183758 : UInt<1>
    reg T_183759 : UInt<1>
    node T_183760 = bits(tag_rdata, 39, 20)
    
    
    node T_183761 = and(s1_valid, rdy)
    node T_183762 = eq(stall, UInt<1>(0))
    node T_183763 = and(T_183761, T_183762)
    when T_183763 : 
      T_183757 := T_183756
      node T_183764 = or(UInt<1>(0), UInt<1>(0))
      T_183758 := T_183764
      T_183759 := s1_tag_match[1]
    node T_183765 = bits(T_183760, 19, 0)
    node T_183766 = eq(T_183765, s1_tag)
    s1_tag_match[1] := T_183766
    node T_183767 = and(T_183757, T_183759)
    s2_tag_hit[1] := T_183767
    node T_183768 = or(UInt<1>(0), UInt<1>(0))
    node T_183769 = or(T_183758, T_183768)
    node T_183770 = and(T_183757, T_183769)
    s2_disparity[1] := T_183770
    node T_183771 = eq(invalidate, UInt<1>(0))
    node T_183772 = bits(s1_pgoff, 11, 6)
    node T_183773 = cat(UInt<2>(2), T_183772)
    node T_183774 = dshr(vb_array, T_183773)
    node T_183775 = bit(T_183774, 0)
    node T_183776 = bit(T_183775, 0)
    node T_183777 = and(T_183771, T_183776)
    reg T_183778 : UInt<1>
    reg T_183779 : UInt<1>
    reg T_183780 : UInt<1>
    node T_183781 = bits(tag_rdata, 59, 40)
    
    
    node T_183782 = and(s1_valid, rdy)
    node T_183783 = eq(stall, UInt<1>(0))
    node T_183784 = and(T_183782, T_183783)
    when T_183784 : 
      T_183778 := T_183777
      node T_183785 = or(UInt<1>(0), UInt<1>(0))
      T_183779 := T_183785
      T_183780 := s1_tag_match[2]
    node T_183786 = bits(T_183781, 19, 0)
    node T_183787 = eq(T_183786, s1_tag)
    s1_tag_match[2] := T_183787
    node T_183788 = and(T_183778, T_183780)
    s2_tag_hit[2] := T_183788
    node T_183789 = or(UInt<1>(0), UInt<1>(0))
    node T_183790 = or(T_183779, T_183789)
    node T_183791 = and(T_183778, T_183790)
    s2_disparity[2] := T_183791
    node T_183792 = eq(invalidate, UInt<1>(0))
    node T_183793 = bits(s1_pgoff, 11, 6)
    node T_183794 = cat(UInt<2>(3), T_183793)
    node T_183795 = dshr(vb_array, T_183794)
    node T_183796 = bit(T_183795, 0)
    node T_183797 = bit(T_183796, 0)
    node T_183798 = and(T_183792, T_183797)
    reg T_183799 : UInt<1>
    reg T_183800 : UInt<1>
    reg T_183801 : UInt<1>
    node T_183802 = bits(tag_rdata, 79, 60)
    
    
    node T_183803 = and(s1_valid, rdy)
    node T_183804 = eq(stall, UInt<1>(0))
    node T_183805 = and(T_183803, T_183804)
    when T_183805 : 
      T_183799 := T_183798
      node T_183806 = or(UInt<1>(0), UInt<1>(0))
      T_183800 := T_183806
      T_183801 := s1_tag_match[3]
    node T_183807 = bits(T_183802, 19, 0)
    node T_183808 = eq(T_183807, s1_tag)
    s1_tag_match[3] := T_183808
    node T_183809 = and(T_183799, T_183801)
    s2_tag_hit[3] := T_183809
    node T_183810 = or(UInt<1>(0), UInt<1>(0))
    node T_183811 = or(T_183800, T_183810)
    node T_183812 = and(T_183799, T_183811)
    s2_disparity[3] := T_183812
    node T_183813 = or(s2_tag_hit[0], s2_tag_hit[1])
    node T_183814 = or(T_183813, s2_tag_hit[2])
    node T_183815 = or(T_183814, s2_tag_hit[3])
    node T_183816 = or(s2_disparity[0], s2_disparity[1])
    node T_183817 = or(T_183816, s2_disparity[2])
    node T_183818 = or(T_183817, s2_disparity[3])
    node T_183819 = eq(T_183818, UInt<1>(0))
    node T_183820 = and(T_183815, T_183819)
    s2_any_tag_hit := T_183820
    cmem T_183821 : UInt<128>[256]
    node T_183822 = eq(repl_way, UInt<1>(0))
    node T_183823 = and(T_183639.out.valid, T_183822)
    when T_183823 : 
      node T_183824 = cat(s2_idx, refill_cnt)
      accessor T_183825 = T_183821[T_183824]
      T_183825 := T_183639.out.bits.data
    node T_183826 = bits(s0_pgoff, 11, 4)
    node T_183827 = eq(T_183823, UInt<1>(0))
    node T_183828 = and(T_183827, s0_valid)
    reg T_183829 : UInt<8>
    when T_183828 : T_183829 := T_183826
    accessor T_183830 = T_183821[T_183829]
    
    
    node T_183831 = and(s1_valid, rdy)
    node T_183832 = eq(stall, UInt<1>(0))
    node T_183833 = and(T_183831, T_183832)
    node T_183834 = or(UInt<1>(0), s1_tag_match[0])
    node T_183835 = and(T_183833, T_183834)
    when T_183835 : s2_dout[0] := T_183830
    cmem T_183836 : UInt<128>[256]
    node T_183837 = eq(repl_way, UInt<1>(1))
    node T_183838 = and(T_183639.out.valid, T_183837)
    when T_183838 : 
      node T_183839 = cat(s2_idx, refill_cnt)
      accessor T_183840 = T_183836[T_183839]
      T_183840 := T_183639.out.bits.data
    node T_183841 = bits(s0_pgoff, 11, 4)
    node T_183842 = eq(T_183838, UInt<1>(0))
    node T_183843 = and(T_183842, s0_valid)
    reg T_183844 : UInt<8>
    when T_183843 : T_183844 := T_183841
    accessor T_183845 = T_183836[T_183844]
    
    
    node T_183846 = and(s1_valid, rdy)
    node T_183847 = eq(stall, UInt<1>(0))
    node T_183848 = and(T_183846, T_183847)
    node T_183849 = or(UInt<1>(0), s1_tag_match[1])
    node T_183850 = and(T_183848, T_183849)
    when T_183850 : s2_dout[1] := T_183845
    cmem T_183851 : UInt<128>[256]
    node T_183852 = eq(repl_way, UInt<2>(2))
    node T_183853 = and(T_183639.out.valid, T_183852)
    when T_183853 : 
      node T_183854 = cat(s2_idx, refill_cnt)
      accessor T_183855 = T_183851[T_183854]
      T_183855 := T_183639.out.bits.data
    node T_183856 = bits(s0_pgoff, 11, 4)
    node T_183857 = eq(T_183853, UInt<1>(0))
    node T_183858 = and(T_183857, s0_valid)
    reg T_183859 : UInt<8>
    when T_183858 : T_183859 := T_183856
    accessor T_183860 = T_183851[T_183859]
    
    
    node T_183861 = and(s1_valid, rdy)
    node T_183862 = eq(stall, UInt<1>(0))
    node T_183863 = and(T_183861, T_183862)
    node T_183864 = or(UInt<1>(0), s1_tag_match[2])
    node T_183865 = and(T_183863, T_183864)
    when T_183865 : s2_dout[2] := T_183860
    cmem T_183866 : UInt<128>[256]
    node T_183867 = eq(repl_way, UInt<2>(3))
    node T_183868 = and(T_183639.out.valid, T_183867)
    when T_183868 : 
      node T_183869 = cat(s2_idx, refill_cnt)
      accessor T_183870 = T_183866[T_183869]
      T_183870 := T_183639.out.bits.data
    node T_183871 = bits(s0_pgoff, 11, 4)
    node T_183872 = eq(T_183868, UInt<1>(0))
    node T_183873 = and(T_183872, s0_valid)
    reg T_183874 : UInt<8>
    when T_183873 : T_183874 := T_183871
    accessor T_183875 = T_183866[T_183874]
    
    
    node T_183876 = and(s1_valid, rdy)
    node T_183877 = eq(stall, UInt<1>(0))
    node T_183878 = and(T_183876, T_183877)
    node T_183879 = or(UInt<1>(0), s1_tag_match[3])
    node T_183880 = and(T_183878, T_183879)
    when T_183880 : s2_dout[3] := T_183875
    node T_183881 = bits(s2_offset, 3, 2)
    node T_183882 = shl(T_183881, 5)
    node T_183883 = dshr(s2_dout[0], T_183882)
    node T_183884 = bits(T_183883, 31, 0)
    node T_183885 = bits(s2_offset, 3, 2)
    node T_183886 = shl(T_183885, 5)
    node T_183887 = dshr(s2_dout[1], T_183886)
    node T_183888 = bits(T_183887, 31, 0)
    node T_183889 = bits(s2_offset, 3, 2)
    node T_183890 = shl(T_183889, 5)
    node T_183891 = dshr(s2_dout[2], T_183890)
    node T_183892 = bits(T_183891, 31, 0)
    node T_183893 = bits(s2_offset, 3, 2)
    node T_183894 = shl(T_183893, 5)
    node T_183895 = dshr(s2_dout[3], T_183894)
    node T_183896 = bits(T_183895, 31, 0)
    wire T_183897 : UInt<1>
    T_183897 := UInt<1>(0)
    when s2_tag_hit[0] : T_183897 := T_183884
    wire T_183898 : UInt<1>
    T_183898 := UInt<1>(0)
    when s2_tag_hit[1] : T_183898 := T_183888
    wire T_183899 : UInt<1>
    T_183899 := UInt<1>(0)
    when s2_tag_hit[2] : T_183899 := T_183892
    wire T_183900 : UInt<1>
    T_183900 := UInt<1>(0)
    when s2_tag_hit[3] : T_183900 := T_183896
    node T_183901 = or(T_183897, T_183898)
    node T_183902 = or(T_183901, T_183899)
    node T_183903 = or(T_183902, T_183900)
    wire T_183904 : UInt<32>
    node T_183905 = bits(T_183903, 31, 0)
    T_183904 := T_183905
    resp.bits.data := T_183904
    wire T_183906 : UInt<1>
    T_183906 := UInt<1>(0)
    when s2_tag_hit[0] : T_183906 := s2_dout[0]
    wire T_183907 : UInt<1>
    T_183907 := UInt<1>(0)
    when s2_tag_hit[1] : T_183907 := s2_dout[1]
    wire T_183908 : UInt<1>
    T_183908 := UInt<1>(0)
    when s2_tag_hit[2] : T_183908 := s2_dout[2]
    wire T_183909 : UInt<1>
    T_183909 := UInt<1>(0)
    when s2_tag_hit[3] : T_183909 := s2_dout[3]
    node T_183910 = or(T_183906, T_183907)
    node T_183911 = or(T_183910, T_183908)
    node T_183912 = or(T_183911, T_183909)
    wire T_183913 : UInt
    node T_183914 = bits(T_183912, -2, 0)
    T_183913 := T_183914
    resp.bits.datablock := T_183913
    resp.valid := s2_hit
    node T_183915 = eq(state, UInt<2>(1))
    mem__.acquire.valid := T_183915
    node T_183916 = dshr(s2_addr, UInt<3>(6))
    wire T_183917 : UInt<3>[3]
    T_183917[0] := UInt<3>(0)
    T_183917[1] := UInt<3>(1)
    T_183917[2] := UInt<3>(2)
    wire T_183918 : UInt<2>[2]
    T_183918[0] := UInt<2>(0)
    T_183918[1] := UInt<2>(1)
    wire T_183919 : UInt<2>[3]
    T_183919[0] := UInt<2>(1)
    T_183919[1] := UInt<2>(2)
    T_183919[2] := UInt<2>(3)
    wire T_183920 : UInt<2>[2]
    T_183920[0] := UInt<2>(2)
    T_183920[1] := UInt<2>(3)
    wire T_183921 : UInt<2>[1]
    T_183921[0] := UInt<2>(3)
    wire T_183922 : UInt<3>[3]
    T_183922[0] := UInt<3>(0)
    T_183922[1] := UInt<3>(1)
    T_183922[2] := UInt<3>(2)
    wire T_183923 : UInt<2>[2]
    T_183923[0] := UInt<2>(0)
    T_183923[1] := UInt<2>(1)
    wire T_183924 : UInt<2>[3]
    T_183924[0] := UInt<2>(1)
    T_183924[1] := UInt<2>(2)
    T_183924[2] := UInt<2>(3)
    wire T_183925 : UInt<2>[2]
    T_183925[0] := UInt<2>(2)
    T_183925[1] := UInt<2>(3)
    wire T_183926 : UInt<2>[1]
    T_183926[0] := UInt<2>(3)
    wire T_183927 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_183927.is_builtin_type := UInt<1>(1)
    T_183927.a_type := UInt<3>(1)
    T_183927.client_xact_id := UInt<1>(0)
    T_183927.addr_block := T_183916
    T_183927.addr_beat := UInt<1>(0)
    T_183927.data := UInt<1>(0)
    T_183927.union := UInt<9>(449)
    mem__.acquire.bits := T_183927
    
    node T_183928 = eq(UInt<2>(0), state)
    when T_183928 : 
      when s2_miss : state := UInt<2>(1)
      invalidated := UInt<1>(0)
    
    node T_183929 = eq(UInt<2>(1), state)
    when T_183929 : when mem__.acquire.ready : state := UInt<2>(2)
    
    node T_183930 = eq(UInt<2>(2), state)
    when T_183930 : when mem__.grant.valid : state := UInt<2>(3)
    
    node T_183931 = eq(UInt<2>(3), state)
    when T_183931 : when refill_done : state := UInt<2>(0)
  module RocketCAM : 
    input clear : UInt<1>
    input clear_mask : UInt<8>
    input tag : UInt<34>
    output hit : UInt<1>
    output hits : UInt<8>
    output valid_bits : UInt<8>
    input write : UInt<1>
    input write_tag : UInt<34>
    input write_addr : UInt<3>
    
    cmem cam_tags : UInt<34>[8]
    reg vb_array : UInt<8>
    onreset vb_array := UInt<8>(0)
    when write : 
      node T_183932 = dshl(UInt<1>(1), write_addr)
      node T_183933 = or(vb_array, T_183932)
      node T_183934 = not(vb_array)
      node T_183935 = or(T_183934, T_183932)
      node T_183936 = not(T_183935)
      wire T_183937 : UInt<9>
      T_183937 := T_183936
      when UInt<1>(1) : T_183937 := T_183933
      vb_array := T_183937
      accessor T_183938 = cam_tags[write_addr]
      T_183938 := write_tag
    when clear : 
      node T_183939 = not(clear_mask)
      node T_183940 = and(vb_array, T_183939)
      vb_array := T_183940
    node T_183941 = bit(vb_array, 0)
    accessor T_183942 = cam_tags[UInt<1>(0)]
    node T_183943 = eq(T_183942, tag)
    node T_183944 = and(T_183941, T_183943)
    node T_183945 = bit(vb_array, 1)
    accessor T_183946 = cam_tags[UInt<1>(1)]
    node T_183947 = eq(T_183946, tag)
    node T_183948 = and(T_183945, T_183947)
    node T_183949 = bit(vb_array, 2)
    accessor T_183950 = cam_tags[UInt<2>(2)]
    node T_183951 = eq(T_183950, tag)
    node T_183952 = and(T_183949, T_183951)
    node T_183953 = bit(vb_array, 3)
    accessor T_183954 = cam_tags[UInt<2>(3)]
    node T_183955 = eq(T_183954, tag)
    node T_183956 = and(T_183953, T_183955)
    node T_183957 = bit(vb_array, 4)
    accessor T_183958 = cam_tags[UInt<3>(4)]
    node T_183959 = eq(T_183958, tag)
    node T_183960 = and(T_183957, T_183959)
    node T_183961 = bit(vb_array, 5)
    accessor T_183962 = cam_tags[UInt<3>(5)]
    node T_183963 = eq(T_183962, tag)
    node T_183964 = and(T_183961, T_183963)
    node T_183965 = bit(vb_array, 6)
    accessor T_183966 = cam_tags[UInt<3>(6)]
    node T_183967 = eq(T_183966, tag)
    node T_183968 = and(T_183965, T_183967)
    node T_183969 = bit(vb_array, 7)
    accessor T_183970 = cam_tags[UInt<3>(7)]
    node T_183971 = eq(T_183970, tag)
    node T_183972 = and(T_183969, T_183971)
    valid_bits := vb_array
    wire T_183973 : UInt<1>[8]
    T_183973[0] := T_183944
    T_183973[1] := T_183948
    T_183973[2] := T_183952
    T_183973[3] := T_183956
    T_183973[4] := T_183960
    T_183973[5] := T_183964
    T_183973[6] := T_183968
    T_183973[7] := T_183972
    node T_183974 = cat(T_183973[7], T_183973[6])
    node T_183975 = cat(T_183973[5], T_183973[4])
    node T_183976 = cat(T_183974, T_183975)
    node T_183977 = cat(T_183973[3], T_183973[2])
    node T_183978 = cat(T_183973[1], T_183973[0])
    node T_183979 = cat(T_183977, T_183978)
    node T_183980 = cat(T_183976, T_183979)
    hits := T_183980
    node T_183981 = eq(hits, UInt<1>(0))
    node T_183982 = eq(T_183981, UInt<1>(0))
    hit := T_183982
  module TLB : 
    input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}
    output resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}
    output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}
    
    reg state : UInt<2>
    onreset state := UInt<2>(0)
    reg r_refill_tag : UInt
    reg r_refill_waddr : UInt
    reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}
    inst tag_cam of RocketCAM
    cmem tag_ram : UInt<20>[8]
    node lookup_tag = cat(req.bits.asid, req.bits.vpn)
    tag_cam.tag := lookup_tag
    node T_183983 = eq(state, UInt<2>(2))
    node T_183984 = and(T_183983, ptw.resp.valid)
    tag_cam.write := T_183984
    tag_cam.write_tag := r_refill_tag
    tag_cam.write_addr := r_refill_waddr
    node T_183985 = bits(tag_cam.hits, 7, 4)
    node T_183986 = bits(tag_cam.hits, 3, 0)
    node T_183987 = eq(T_183985, UInt<1>(0))
    node T_183988 = eq(T_183987, UInt<1>(0))
    node T_183989 = or(T_183985, T_183986)
    node T_183990 = bits(T_183989, 3, 2)
    node T_183991 = bits(T_183989, 1, 0)
    node T_183992 = eq(T_183990, UInt<1>(0))
    node T_183993 = eq(T_183992, UInt<1>(0))
    node T_183994 = or(T_183990, T_183991)
    node T_183995 = bit(T_183994, 1)
    node T_183996 = cat(T_183993, T_183995)
    node tag_hit_addr = cat(T_183988, T_183996)
    reg valid_array : UInt<1>[8]
    reg ur_array : UInt<1>[8]
    reg uw_array : UInt<1>[8]
    reg ux_array : UInt<1>[8]
    reg sr_array : UInt<1>[8]
    reg sw_array : UInt<1>[8]
    reg sx_array : UInt<1>[8]
    reg dirty_array : UInt<1>[8]
    when ptw.resp.valid : 
      accessor T_183997 = tag_ram[r_refill_waddr]
      T_183997 := ptw.resp.bits.pte.ppn
      accessor T_183998 = valid_array[r_refill_waddr]
      node T_183999 = eq(ptw.resp.bits.error, UInt<1>(0))
      T_183998 := T_183999
      accessor T_184000 = ur_array[r_refill_waddr]
      node T_184001 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_184002 = and(ptw.resp.bits.pte.v, T_184001)
      node T_184003 = lt(ptw.resp.bits.pte.typ, UInt<4>(8))
      node T_184004 = and(T_184002, T_184003)
      node T_184005 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_184006 = and(T_184004, T_184005)
      T_184000 := T_184006
      accessor T_184007 = uw_array[r_refill_waddr]
      node T_184008 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_184009 = and(ptw.resp.bits.pte.v, T_184008)
      node T_184010 = lt(ptw.resp.bits.pte.typ, UInt<4>(8))
      node T_184011 = and(T_184009, T_184010)
      node T_184012 = bit(ptw.resp.bits.pte.typ, 0)
      node T_184013 = and(T_184011, T_184012)
      node T_184014 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_184015 = and(T_184013, T_184014)
      T_184007 := T_184015
      accessor T_184016 = ux_array[r_refill_waddr]
      node T_184017 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_184018 = and(ptw.resp.bits.pte.v, T_184017)
      node T_184019 = lt(ptw.resp.bits.pte.typ, UInt<4>(8))
      node T_184020 = and(T_184018, T_184019)
      node T_184021 = bit(ptw.resp.bits.pte.typ, 1)
      node T_184022 = and(T_184020, T_184021)
      node T_184023 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_184024 = and(T_184022, T_184023)
      T_184016 := T_184024
      accessor T_184025 = sr_array[r_refill_waddr]
      node T_184026 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_184027 = and(ptw.resp.bits.pte.v, T_184026)
      node T_184028 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_184029 = and(T_184027, T_184028)
      T_184025 := T_184029
      accessor T_184030 = sw_array[r_refill_waddr]
      node T_184031 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_184032 = and(ptw.resp.bits.pte.v, T_184031)
      node T_184033 = bit(ptw.resp.bits.pte.typ, 0)
      node T_184034 = and(T_184032, T_184033)
      node T_184035 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_184036 = and(T_184034, T_184035)
      T_184030 := T_184036
      accessor T_184037 = sx_array[r_refill_waddr]
      node T_184038 = geq(ptw.resp.bits.pte.typ, UInt<3>(4))
      node T_184039 = and(ptw.resp.bits.pte.v, T_184038)
      node T_184040 = bit(ptw.resp.bits.pte.typ, 1)
      node T_184041 = and(T_184039, T_184040)
      node T_184042 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_184043 = and(T_184041, T_184042)
      T_184037 := T_184043
      accessor T_184044 = dirty_array[r_refill_waddr]
      T_184044 := ptw.resp.bits.pte.d
    node T_184045 = eq(tag_cam.valid_bits, UInt<1>(-1))
    node has_invalid_entry = eq(T_184045, UInt<1>(0))
    node T_184046 = not(tag_cam.valid_bits)
    node T_184047 = bit(T_184046, 0)
    node T_184048 = bit(T_184046, 1)
    node T_184049 = bit(T_184046, 2)
    node T_184050 = bit(T_184046, 3)
    node T_184051 = bit(T_184046, 4)
    node T_184052 = bit(T_184046, 5)
    node T_184053 = bit(T_184046, 6)
    node T_184054 = bit(T_184046, 7)
    wire T_184055 : UInt<1>[8]
    T_184055[0] := T_184047
    T_184055[1] := T_184048
    T_184055[2] := T_184049
    T_184055[3] := T_184050
    T_184055[4] := T_184051
    T_184055[5] := T_184052
    T_184055[6] := T_184053
    T_184055[7] := T_184054
    wire T_184056 : UInt<3>
    T_184056 := UInt<3>(7)
    when T_184055[6] : T_184056 := UInt<3>(6)
    wire T_184057 : UInt<3>
    T_184057 := T_184056
    when T_184055[5] : T_184057 := UInt<3>(5)
    wire T_184058 : UInt<3>
    T_184058 := T_184057
    when T_184055[4] : T_184058 := UInt<3>(4)
    wire T_184059 : UInt<3>
    T_184059 := T_184058
    when T_184055[3] : T_184059 := UInt<2>(3)
    wire T_184060 : UInt<3>
    T_184060 := T_184059
    when T_184055[2] : T_184060 := UInt<2>(2)
    wire T_184061 : UInt<3>
    T_184061 := T_184060
    when T_184055[1] : T_184061 := UInt<1>(1)
    wire invalid_entry : UInt<3>
    invalid_entry := T_184061
    when T_184055[0] : invalid_entry := UInt<1>(0)
    reg T_184062 : UInt<8>
    node T_184063 = dshr(T_184062, UInt<1>(1))
    node T_184064 = bit(T_184063, 0)
    node T_184065 = cat(UInt<1>(1), T_184064)
    node T_184066 = dshr(T_184062, T_184065)
    node T_184067 = bit(T_184066, 0)
    node T_184068 = cat(T_184065, T_184067)
    node T_184069 = dshr(T_184062, T_184068)
    node T_184070 = bit(T_184069, 0)
    node T_184071 = cat(T_184068, T_184070)
    node T_184072 = bits(T_184071, 2, 0)
    wire repl_waddr : UInt<3>
    repl_waddr := T_184072
    when has_invalid_entry : repl_waddr := invalid_entry
    node T_184073 = eq(req.bits.instruction, UInt<1>(0))
    node T_184074 = and(ptw.status.mprv, T_184073)
    wire priv : UInt<2>
    priv := ptw.status.prv
    when T_184074 : priv := ptw.status.prv1
    node priv_s = eq(priv, UInt<1>(1))
    node priv_uses_vm = leq(priv, UInt<1>(1))
    node T_184075 = eq(r_req.store, UInt<1>(0))
    node T_184076 = or(r_req.instruction, r_req.store)
    node T_184077 = eq(T_184076, UInt<1>(0))
    node T_184078 = cat(r_req.store, T_184077)
    node req_xwr = cat(T_184075, T_184078)
    node T_184079 = cat(sr_array[7], sr_array[6])
    node T_184080 = cat(sr_array[5], sr_array[4])
    node T_184081 = cat(T_184079, T_184080)
    node T_184082 = cat(sr_array[3], sr_array[2])
    node T_184083 = cat(sr_array[1], sr_array[0])
    node T_184084 = cat(T_184082, T_184083)
    node T_184085 = cat(T_184081, T_184084)
    node T_184086 = cat(ur_array[7], ur_array[6])
    node T_184087 = cat(ur_array[5], ur_array[4])
    node T_184088 = cat(T_184086, T_184087)
    node T_184089 = cat(ur_array[3], ur_array[2])
    node T_184090 = cat(ur_array[1], ur_array[0])
    node T_184091 = cat(T_184089, T_184090)
    node T_184092 = cat(T_184088, T_184091)
    wire r_array : UInt<8>
    r_array := T_184092
    when priv_s : r_array := T_184085
    node T_184093 = cat(sw_array[7], sw_array[6])
    node T_184094 = cat(sw_array[5], sw_array[4])
    node T_184095 = cat(T_184093, T_184094)
    node T_184096 = cat(sw_array[3], sw_array[2])
    node T_184097 = cat(sw_array[1], sw_array[0])
    node T_184098 = cat(T_184096, T_184097)
    node T_184099 = cat(T_184095, T_184098)
    node T_184100 = cat(uw_array[7], uw_array[6])
    node T_184101 = cat(uw_array[5], uw_array[4])
    node T_184102 = cat(T_184100, T_184101)
    node T_184103 = cat(uw_array[3], uw_array[2])
    node T_184104 = cat(uw_array[1], uw_array[0])
    node T_184105 = cat(T_184103, T_184104)
    node T_184106 = cat(T_184102, T_184105)
    wire w_array : UInt<8>
    w_array := T_184106
    when priv_s : w_array := T_184099
    node T_184107 = cat(sx_array[7], sx_array[6])
    node T_184108 = cat(sx_array[5], sx_array[4])
    node T_184109 = cat(T_184107, T_184108)
    node T_184110 = cat(sx_array[3], sx_array[2])
    node T_184111 = cat(sx_array[1], sx_array[0])
    node T_184112 = cat(T_184110, T_184111)
    node T_184113 = cat(T_184109, T_184112)
    node T_184114 = cat(ux_array[7], ux_array[6])
    node T_184115 = cat(ux_array[5], ux_array[4])
    node T_184116 = cat(T_184114, T_184115)
    node T_184117 = cat(ux_array[3], ux_array[2])
    node T_184118 = cat(ux_array[1], ux_array[0])
    node T_184119 = cat(T_184117, T_184118)
    node T_184120 = cat(T_184116, T_184119)
    wire x_array : UInt<8>
    x_array := T_184120
    when priv_s : x_array := T_184113
    node T_184121 = bit(ptw.status.vm, 3)
    node vm_enabled = and(T_184121, priv_uses_vm)
    node T_184122 = bit(req.bits.vpn, 27)
    node T_184123 = bit(req.bits.vpn, 26)
    node bad_va = neq(T_184122, T_184123)
    node T_184124 = cat(dirty_array[7], dirty_array[6])
    node T_184125 = cat(dirty_array[5], dirty_array[4])
    node T_184126 = cat(T_184124, T_184125)
    node T_184127 = cat(dirty_array[3], dirty_array[2])
    node T_184128 = cat(dirty_array[1], dirty_array[0])
    node T_184129 = cat(T_184127, T_184128)
    node T_184130 = cat(T_184126, T_184129)
    wire T_184131 : UInt<1>
    T_184131 := UInt<1>(0)
    when req.bits.store : T_184131 := w_array
    node T_184132 = not(T_184131)
    node T_184133 = or(T_184130, T_184132)
    node tag_hits = and(tag_cam.hits, T_184133)
    node T_184134 = eq(tag_hits, UInt<1>(0))
    node tag_hit = eq(T_184134, UInt<1>(0))
    node tlb_hit = and(vm_enabled, tag_hit)
    node T_184135 = eq(tag_hit, UInt<1>(0))
    node T_184136 = and(vm_enabled, T_184135)
    node T_184137 = eq(bad_va, UInt<1>(0))
    node tlb_miss = and(T_184136, T_184137)
    
    node T_184138 = and(req.valid, tlb_hit)
    when T_184138 : 
      node T_184139 = bits(tag_cam.hits, 7, 4)
      node T_184140 = bits(tag_cam.hits, 3, 0)
      node T_184141 = eq(T_184139, UInt<1>(0))
      node T_184142 = eq(T_184141, UInt<1>(0))
      node T_184143 = or(T_184139, T_184140)
      node T_184144 = bits(T_184143, 3, 2)
      node T_184145 = bits(T_184143, 1, 0)
      node T_184146 = eq(T_184144, UInt<1>(0))
      node T_184147 = eq(T_184146, UInt<1>(0))
      node T_184148 = or(T_184144, T_184145)
      node T_184149 = bit(T_184148, 1)
      node T_184150 = cat(T_184147, T_184149)
      node T_184151 = cat(T_184142, T_184150)
      node T_184152 = bit(T_184151, 2)
      node T_184153 = dshl(UInt<8>(1), UInt<1>(1))
      node T_184154 = bits(T_184153, 7, 0)
      node T_184155 = not(T_184154)
      node T_184156 = and(T_184062, T_184155)
      wire T_184157 : UInt<8>
      T_184157 := T_184154
      when T_184152 : T_184157 := UInt<1>(0)
      node T_184158 = or(T_184156, T_184157)
      node T_184159 = cat(UInt<1>(1), T_184152)
      node T_184160 = bit(T_184151, 1)
      node T_184161 = dshl(UInt<8>(1), T_184159)
      node T_184162 = bits(T_184161, 7, 0)
      node T_184163 = not(T_184162)
      node T_184164 = and(T_184158, T_184163)
      wire T_184165 : UInt<8>
      T_184165 := T_184162
      when T_184160 : T_184165 := UInt<1>(0)
      node T_184166 = or(T_184164, T_184165)
      node T_184167 = cat(T_184159, T_184160)
      node T_184168 = bit(T_184151, 0)
      node T_184169 = dshl(UInt<8>(1), T_184167)
      node T_184170 = bits(T_184169, 7, 0)
      node T_184171 = not(T_184170)
      node T_184172 = and(T_184166, T_184171)
      wire T_184173 : UInt<8>
      T_184173 := T_184170
      when T_184168 : T_184173 := UInt<1>(0)
      node T_184174 = or(T_184172, T_184173)
      node T_184175 = cat(T_184167, T_184168)
      T_184062 := T_184174
    node T_184176 = eq(state, UInt<2>(0))
    req.ready := T_184176
    node T_184177 = and(r_array, tag_cam.hits)
    node T_184178 = eq(T_184177, UInt<1>(0))
    node T_184179 = eq(T_184178, UInt<1>(0))
    node T_184180 = eq(T_184179, UInt<1>(0))
    node T_184181 = and(tlb_hit, T_184180)
    node T_184182 = or(bad_va, T_184181)
    resp.xcpt_ld := T_184182
    node T_184183 = and(w_array, tag_cam.hits)
    node T_184184 = eq(T_184183, UInt<1>(0))
    node T_184185 = eq(T_184184, UInt<1>(0))
    node T_184186 = eq(T_184185, UInt<1>(0))
    node T_184187 = and(tlb_hit, T_184186)
    node T_184188 = or(bad_va, T_184187)
    resp.xcpt_st := T_184188
    node T_184189 = and(x_array, tag_cam.hits)
    node T_184190 = eq(T_184189, UInt<1>(0))
    node T_184191 = eq(T_184190, UInt<1>(0))
    node T_184192 = eq(T_184191, UInt<1>(0))
    node T_184193 = and(tlb_hit, T_184192)
    node T_184194 = or(bad_va, T_184193)
    resp.xcpt_if := T_184194
    resp.miss := tlb_miss
    node T_184195 = eq(req.bits.passthrough, UInt<1>(0))
    node T_184196 = and(vm_enabled, T_184195)
    node T_184197 = bit(tag_cam.hits, 0)
    node T_184198 = bit(tag_cam.hits, 1)
    node T_184199 = bit(tag_cam.hits, 2)
    node T_184200 = bit(tag_cam.hits, 3)
    node T_184201 = bit(tag_cam.hits, 4)
    node T_184202 = bit(tag_cam.hits, 5)
    node T_184203 = bit(tag_cam.hits, 6)
    node T_184204 = bit(tag_cam.hits, 7)
    accessor T_184205 = tag_ram[UInt<1>(0)]
    accessor T_184206 = tag_ram[UInt<1>(1)]
    accessor T_184207 = tag_ram[UInt<2>(2)]
    accessor T_184208 = tag_ram[UInt<2>(3)]
    accessor T_184209 = tag_ram[UInt<3>(4)]
    accessor T_184210 = tag_ram[UInt<3>(5)]
    accessor T_184211 = tag_ram[UInt<3>(6)]
    accessor T_184212 = tag_ram[UInt<3>(7)]
    wire T_184213 : UInt<1>
    T_184213 := UInt<1>(0)
    when T_184197 : T_184213 := T_184205
    wire T_184214 : UInt<1>
    T_184214 := UInt<1>(0)
    when T_184198 : T_184214 := T_184206
    wire T_184215 : UInt<1>
    T_184215 := UInt<1>(0)
    when T_184199 : T_184215 := T_184207
    wire T_184216 : UInt<1>
    T_184216 := UInt<1>(0)
    when T_184200 : T_184216 := T_184208
    wire T_184217 : UInt<1>
    T_184217 := UInt<1>(0)
    when T_184201 : T_184217 := T_184209
    wire T_184218 : UInt<1>
    T_184218 := UInt<1>(0)
    when T_184202 : T_184218 := T_184210
    wire T_184219 : UInt<1>
    T_184219 := UInt<1>(0)
    when T_184203 : T_184219 := T_184211
    wire T_184220 : UInt<1>
    T_184220 := UInt<1>(0)
    when T_184204 : T_184220 := T_184212
    node T_184221 = or(T_184213, T_184214)
    node T_184222 = or(T_184221, T_184215)
    node T_184223 = or(T_184222, T_184216)
    node T_184224 = or(T_184223, T_184217)
    node T_184225 = or(T_184224, T_184218)
    node T_184226 = or(T_184225, T_184219)
    node T_184227 = or(T_184226, T_184220)
    wire T_184228 : UInt<20>
    node T_184229 = bits(T_184227, 19, 0)
    T_184228 := T_184229
    node T_184230 = bits(req.bits.vpn, 19, 0)
    wire T_184231 : UInt<20>
    T_184231 := T_184230
    when T_184196 : T_184231 := T_184228
    resp.ppn := T_184231
    resp.hit_idx := tag_cam.hits
    node T_184232 = and(req.ready, req.valid)
    node T_184233 = or(ptw.invalidate, T_184232)
    tag_cam.clear := T_184233
    node T_184234 = cat(valid_array[7], valid_array[6])
    node T_184235 = cat(valid_array[5], valid_array[4])
    node T_184236 = cat(T_184234, T_184235)
    node T_184237 = cat(valid_array[3], valid_array[2])
    node T_184238 = cat(valid_array[1], valid_array[0])
    node T_184239 = cat(T_184237, T_184238)
    node T_184240 = cat(T_184236, T_184239)
    node T_184241 = not(T_184240)
    node T_184242 = not(tag_hits)
    node T_184243 = and(tag_cam.hits, T_184242)
    node T_184244 = or(T_184241, T_184243)
    tag_cam.clear_mask := T_184244
    when ptw.invalidate : tag_cam.clear_mask := SInt<1>(-1)
    node T_184245 = eq(state, UInt<2>(1))
    ptw.req.valid := T_184245
    ptw.req.bits.addr := r_refill_tag
    ptw.req.bits.prv := ptw.status.prv
    ptw.req.bits.store := r_req.store
    ptw.req.bits.fetch := r_req.instruction
    
    
    node T_184246 = and(req.ready, req.valid)
    node T_184247 = and(T_184246, tlb_miss)
    when T_184247 : 
      state := UInt<2>(1)
      r_refill_tag := lookup_tag
      r_refill_waddr := repl_waddr
      r_req := req.bits
    
    node T_184248 = eq(state, UInt<2>(1))
    when T_184248 : 
      when ptw.invalidate : state := UInt<2>(0)
      when ptw.req.ready : 
        state := UInt<2>(2)
        when ptw.invalidate : state := UInt<2>(3)
    
    
    node T_184249 = eq(state, UInt<2>(2))
    node T_184250 = and(T_184249, ptw.invalidate)
    when T_184250 : state := UInt<2>(3)
    when ptw.resp.valid : state := UInt<2>(0)
  module Frontend : 
    input cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}
    output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}
    output mem__ : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    
    wire data : UInt<32>[1]
    T_184251.data[0] := T_184252
    wire data : UInt<32>[1]
    cpu.resp.bits.data[0] := T_184253
    wire T_184254 : UInt<3>[3]
    T_184254[0] := UInt<3>(0)
    T_184254[1] := UInt<3>(1)
    T_184254[2] := UInt<3>(2)
    wire T_184255 : UInt<2>[2]
    T_184255[0] := UInt<2>(0)
    T_184255[1] := UInt<2>(1)
    wire T_184256 : UInt<2>[3]
    T_184256[0] := UInt<2>(1)
    T_184256[1] := UInt<2>(2)
    T_184256[2] := UInt<2>(3)
    wire T_184257 : UInt<2>[2]
    T_184257[0] := UInt<2>(2)
    T_184257[1] := UInt<2>(3)
    wire T_184258 : UInt<2>[1]
    T_184258[0] := UInt<2>(3)
    wire T_184259 : UInt<3>[3]
    T_184259[0] := UInt<3>(0)
    T_184259[1] := UInt<3>(1)
    T_184259[2] := UInt<3>(2)
    wire T_184260 : UInt<2>[2]
    T_184260[0] := UInt<2>(0)
    T_184260[1] := UInt<2>(1)
    wire T_184261 : UInt<2>[3]
    T_184261[0] := UInt<2>(1)
    T_184261[1] := UInt<2>(2)
    T_184261[2] := UInt<2>(3)
    wire T_184262 : UInt<2>[2]
    T_184262[0] := UInt<2>(2)
    T_184262[1] := UInt<2>(3)
    wire T_184263 : UInt<2>[1]
    T_184263[0] := UInt<2>(3)
    wire T_184264 : UInt<3>[3]
    T_184264[0] := UInt<3>(0)
    T_184264[1] := UInt<3>(1)
    T_184264[2] := UInt<3>(2)
    wire T_184265 : UInt<2>[2]
    T_184265[0] := UInt<2>(0)
    T_184265[1] := UInt<2>(1)
    wire T_184266 : UInt<2>[3]
    T_184266[0] := UInt<2>(1)
    T_184266[1] := UInt<2>(2)
    T_184266[2] := UInt<2>(3)
    wire T_184267 : UInt<2>[2]
    T_184267[0] := UInt<2>(2)
    T_184267[1] := UInt<2>(3)
    wire T_184268 : UInt<2>[1]
    T_184268[0] := UInt<2>(3)
    wire T_184269 : UInt<3>[3]
    T_184269[0] := UInt<3>(0)
    T_184269[1] := UInt<3>(1)
    T_184269[2] := UInt<3>(2)
    wire T_184270 : UInt<2>[2]
    T_184270[0] := UInt<2>(0)
    T_184270[1] := UInt<2>(1)
    wire T_184271 : UInt<2>[3]
    T_184271[0] := UInt<2>(1)
    T_184271[1] := UInt<2>(2)
    T_184271[2] := UInt<2>(3)
    wire T_184272 : UInt<2>[2]
    T_184272[0] := UInt<2>(2)
    T_184272[1] := UInt<2>(3)
    wire T_184273 : UInt<2>[1]
    T_184273[0] := UInt<2>(3)
    wire T_184274 : UInt<3>[3]
    T_184274[0] := UInt<3>(0)
    T_184274[1] := UInt<3>(1)
    T_184274[2] := UInt<3>(2)
    wire T_184275 : UInt<2>[2]
    T_184275[0] := UInt<2>(0)
    T_184275[1] := UInt<2>(1)
    wire T_184276 : UInt<2>[3]
    T_184276[0] := UInt<2>(1)
    T_184276[1] := UInt<2>(2)
    T_184276[2] := UInt<2>(3)
    wire T_184277 : UInt<2>[2]
    T_184277[0] := UInt<2>(2)
    T_184277[1] := UInt<2>(3)
    wire T_184278 : UInt<2>[1]
    T_184278[0] := UInt<2>(3)
    inst btb of BTB
    inst icache of ICache
    inst tlb of TLB
    reg s1_pc_ : UInt
    node T_184279 = not(s1_pc_)
    node T_184280 = or(T_184279, UInt<2>(3))
    node s1_pc = not(T_184280)
    reg s1_same_block : UInt<1>
    reg s2_valid : UInt<1>
    onreset s2_valid := UInt<1>(1)
    reg s2_pc : UInt<10>
    onreset s2_pc := UInt<10>(512)
    reg s2_btb_resp_valid : UInt<1>
    onreset s2_btb_resp_valid := UInt<1>(0)
    reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}
    reg s2_xcpt_if : UInt<1>
    onreset s2_xcpt_if := UInt<1>(0)
    node T_184281 = bit(btb.resp.bits.target, 38)
    node btbTarget = cat(T_184281, btb.resp.bits.target)
    node ntpc_0 = addw(s1_pc, UInt<3>(4))
    node T_184282 = bit(s1_pc, 38)
    node T_184283 = bit(ntpc_0, 38)
    node T_184284 = and(T_184282, T_184283)
    node T_184285 = bits(ntpc_0, 38, 2)
    node T_184286 = cat(T_184285, UInt<2>(0))
    node ntpc = cat(T_184284, T_184286)
    node T_184287 = eq(icache.resp.valid, UInt<1>(0))
    node icmiss = and(s2_valid, T_184287)
    wire predicted_npc : UInt<40>
    predicted_npc := ntpc
    when btb.resp.bits.taken : predicted_npc := btbTarget
    wire npc : UInt<40>
    npc := predicted_npc
    when icmiss : npc := s2_pc
    node T_184288 = eq(icmiss, UInt<1>(0))
    node T_184289 = eq(cpu.req.valid, UInt<1>(0))
    node T_184290 = and(T_184288, T_184289)
    node T_184291 = eq(btb.resp.bits.taken, UInt<1>(0))
    node T_184292 = and(T_184290, T_184291)
    node T_184293 = and(ntpc, UInt<5>(16))
    node T_184294 = and(s1_pc, UInt<5>(16))
    node T_184295 = eq(T_184293, T_184294)
    node s0_same_block = and(T_184292, T_184295)
    node T_184296 = eq(cpu.resp.ready, UInt<1>(0))
    node stall = and(cpu.resp.valid, T_184296)
    
    node T_184297 = eq(stall, UInt<1>(0))
    when T_184297 : 
      node T_184298 = eq(tlb.resp.miss, UInt<1>(0))
      node T_184299 = and(s0_same_block, T_184298)
      s1_same_block := T_184299
      s1_pc_ := npc
      node T_184300 = eq(icmiss, UInt<1>(0))
      s2_valid := T_184300
      
      node T_184301 = eq(icmiss, UInt<1>(0))
      when T_184301 : 
        s2_pc := s1_pc
        s2_btb_resp_valid := btb.resp.valid
        when btb.resp.valid : s2_btb_resp_bits := btb.resp.bits
        s2_xcpt_if := tlb.resp.xcpt_if
    when cpu.req.valid : 
      s1_same_block := UInt<1>(0)
      s1_pc_ := cpu.req.bits.pc
      s2_valid := UInt<1>(0)
    node T_184302 = eq(stall, UInt<1>(0))
    node T_184303 = eq(icmiss, UInt<1>(0))
    node T_184304 = and(T_184302, T_184303)
    btb.req.valid := T_184304
    btb.req.bits.addr := s1_pc
    btb.btb_update := cpu.btb_update
    btb.bht_update := cpu.bht_update
    btb.ras_update := cpu.ras_update
    node T_184305 = or(cpu.invalidate, ptw.invalidate)
    btb.invalidate := T_184305
    tlb.ptw <> ptw
    node T_184306 = eq(stall, UInt<1>(0))
    node T_184307 = eq(icmiss, UInt<1>(0))
    node T_184308 = and(T_184306, T_184307)
    tlb.req.valid := T_184308
    node T_184309 = dshr(s1_pc, UInt<4>(12))
    tlb.req.bits.vpn := T_184309
    tlb.req.bits.asid := UInt<1>(0)
    tlb.req.bits.passthrough := UInt<1>(0)
    tlb.req.bits.instruction := UInt<1>(1)
    tlb.req.bits.store := UInt<1>(0)
    icache.mem__ <> mem__
    node T_184310 = eq(stall, UInt<1>(0))
    node T_184311 = eq(s0_same_block, UInt<1>(0))
    node T_184312 = and(T_184310, T_184311)
    icache.req.valid := T_184312
    icache.req.bits.idx := cpu.npc
    icache.invalidate := cpu.invalidate
    icache.req.bits.ppn := tlb.resp.ppn
    node T_184313 = or(cpu.req.valid, tlb.resp.miss)
    node T_184314 = or(T_184313, icmiss)
    node T_184315 = or(T_184314, ptw.invalidate)
    icache.req.bits.kill := T_184315
    node T_184316 = eq(stall, UInt<1>(0))
    node T_184317 = eq(s1_same_block, UInt<1>(0))
    node T_184318 = and(T_184316, T_184317)
    icache.resp.ready := T_184318
    node T_184319 = or(s2_xcpt_if, icache.resp.valid)
    node T_184320 = and(s2_valid, T_184319)
    cpu.resp.valid := T_184320
    cpu.resp.bits.pc := s2_pc
    wire T_184321 : UInt<40>
    T_184321 := npc
    when cpu.req.valid : T_184321 := cpu.req.bits.pc
    cpu.npc := T_184321
    node T_184322 = bits(s2_pc, 3, 2)
    node T_184323 = shl(T_184322, 5)
    node fetch_data = dshr(icache.resp.bits.datablock, T_184323)
    node T_184324 = bits(fetch_data, 31, 0)
    cpu.resp.bits.data[0] := T_184324
    node T_184325 = and(UInt<2>(3), s2_btb_resp_bits.mask)
    wire T_184326 : UInt<2>
    T_184326 := UInt<2>(3)
    when s2_btb_resp_valid : T_184326 := T_184325
    cpu.resp.bits.mask := T_184326
    cpu.resp.bits.xcpt_if := s2_xcpt_if
    cpu.btb_resp.valid := s2_btb_resp_valid
    cpu.btb_resp.bits := s2_btb_resp_bits
  module WritebackUnit : 
    input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}
    output data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}
    input data_resp : UInt<128>
    output release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    
    wire T_184327 : UInt<3>[3]
    T_184327[0] := UInt<3>(0)
    T_184327[1] := UInt<3>(1)
    T_184327[2] := UInt<3>(2)
    wire T_184328 : UInt<2>[2]
    T_184328[0] := UInt<2>(0)
    T_184328[1] := UInt<2>(1)
    wire T_184329 : UInt<2>[3]
    T_184329[0] := UInt<2>(1)
    T_184329[1] := UInt<2>(2)
    T_184329[2] := UInt<2>(3)
    wire T_184330 : UInt<2>[2]
    T_184330[0] := UInt<2>(2)
    T_184330[1] := UInt<2>(3)
    wire T_184331 : UInt<2>[1]
    T_184331[0] := UInt<2>(3)
    wire T_184332 : UInt<3>[3]
    T_184332[0] := UInt<3>(0)
    T_184332[1] := UInt<3>(1)
    T_184332[2] := UInt<3>(2)
    wire T_184333 : UInt<2>[2]
    T_184333[0] := UInt<2>(0)
    T_184333[1] := UInt<2>(1)
    wire T_184334 : UInt<2>[3]
    T_184334[0] := UInt<2>(1)
    T_184334[1] := UInt<2>(2)
    T_184334[2] := UInt<2>(3)
    wire T_184335 : UInt<2>[2]
    T_184335[0] := UInt<2>(2)
    T_184335[1] := UInt<2>(3)
    wire T_184336 : UInt<2>[1]
    T_184336[0] := UInt<2>(3)
    wire T_184337 : UInt<3>[3]
    T_184337[0] := UInt<3>(0)
    T_184337[1] := UInt<3>(1)
    T_184337[2] := UInt<3>(2)
    wire T_184338 : UInt<2>[2]
    T_184338[0] := UInt<2>(0)
    T_184338[1] := UInt<2>(1)
    wire T_184339 : UInt<2>[3]
    T_184339[0] := UInt<2>(1)
    T_184339[1] := UInt<2>(2)
    T_184339[2] := UInt<2>(3)
    wire T_184340 : UInt<2>[2]
    T_184340[0] := UInt<2>(2)
    T_184340[1] := UInt<2>(3)
    wire T_184341 : UInt<2>[1]
    T_184341[0] := UInt<2>(3)
    wire T_184342 : UInt<3>[3]
    T_184342[0] := UInt<3>(0)
    T_184342[1] := UInt<3>(1)
    T_184342[2] := UInt<3>(2)
    wire T_184343 : UInt<2>[2]
    T_184343[0] := UInt<2>(0)
    T_184343[1] := UInt<2>(1)
    wire T_184344 : UInt<2>[3]
    T_184344[0] := UInt<2>(1)
    T_184344[1] := UInt<2>(2)
    T_184344[2] := UInt<2>(3)
    wire T_184345 : UInt<2>[2]
    T_184345[0] := UInt<2>(2)
    T_184345[1] := UInt<2>(3)
    wire T_184346 : UInt<2>[1]
    T_184346[0] := UInt<2>(3)
    reg active : UInt<1>
    onreset active := UInt<1>(0)
    reg r1_data_req_fired : UInt<1>
    onreset r1_data_req_fired := UInt<1>(0)
    reg r2_data_req_fired : UInt<1>
    onreset r2_data_req_fired := UInt<1>(0)
    reg data_req_cnt : UInt<3>
    onreset data_req_cnt := UInt<3>(0)
    node beat_done = eq(UInt<1>(1), UInt<1>(-1))
    node T_184347 = and(release.ready, release.valid)
    reg beat_cnt : UInt<2>
    onreset beat_cnt := UInt<2>(0)
    when T_184347 : 
      node T_184348 = eq(beat_cnt, UInt<2>(3))
      node T_184349 = and(UInt<1>(0), T_184348)
      node T_184350 = addw(beat_cnt, UInt<1>(1))
      wire T_184351 : UInt<2>
      T_184351 := T_184350
      when T_184349 : T_184351 := UInt<1>(0)
      beat_cnt := T_184351
    node all_beats_done = and(T_184347, T_184348)
    wire T_184352 : UInt<3>[3]
    T_184352[0] := UInt<3>(0)
    T_184352[1] := UInt<3>(1)
    T_184352[2] := UInt<3>(2)
    wire T_184353 : UInt<2>[2]
    T_184353[0] := UInt<2>(0)
    T_184353[1] := UInt<2>(1)
    wire T_184354 : UInt<2>[3]
    T_184354[0] := UInt<2>(1)
    T_184354[1] := UInt<2>(2)
    T_184354[2] := UInt<2>(3)
    wire T_184355 : UInt<2>[2]
    T_184355[0] := UInt<2>(2)
    T_184355[1] := UInt<2>(3)
    wire T_184356 : UInt<2>[1]
    T_184356[0] := UInt<2>(3)
    wire T_184357 : UInt<3>[3]
    T_184357[0] := UInt<3>(0)
    T_184357[1] := UInt<3>(1)
    T_184357[2] := UInt<3>(2)
    wire T_184358 : UInt<2>[2]
    T_184358[0] := UInt<2>(0)
    T_184358[1] := UInt<2>(1)
    wire T_184359 : UInt<2>[3]
    T_184359[0] := UInt<2>(1)
    T_184359[1] := UInt<2>(2)
    T_184359[2] := UInt<2>(3)
    wire T_184360 : UInt<2>[2]
    T_184360[0] := UInt<2>(2)
    T_184360[1] := UInt<2>(3)
    wire T_184361 : UInt<2>[1]
    T_184361[0] := UInt<2>(3)
    reg req : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}
    release.valid := UInt<1>(0)
    when active : 
      r1_data_req_fired := UInt<1>(0)
      r2_data_req_fired := r1_data_req_fired
      
      
      node T_184362 = and(data_req.ready, data_req.valid)
      node T_184363 = and(meta_read.ready, meta_read.valid)
      node T_184364 = and(T_184362, T_184363)
      when T_184364 : 
        r1_data_req_fired := UInt<1>(1)
        node T_184365 = addw(data_req_cnt, UInt<1>(1))
        data_req_cnt := T_184365
      when r2_data_req_fired : 
        release.valid := beat_done
        when beat_done : 
          node T_184366 = eq(release.ready, UInt<1>(0))
          when T_184366 : 
            r1_data_req_fired := UInt<1>(0)
            r2_data_req_fired := UInt<1>(0)
            node T_184367 = and(UInt<1>(1), r1_data_req_fired)
            wire T_184368 : UInt<1>
            T_184368 := UInt<1>(1)
            when T_184367 : T_184368 := UInt<2>(2)
            node T_184369 = subw(data_req_cnt, T_184368)
            data_req_cnt := T_184369
        
        node T_184370 = eq(r1_data_req_fired, UInt<1>(0))
        when T_184370 : 
          node T_184371 = lt(data_req_cnt, UInt<3>(4))
          node T_184372 = eq(release.ready, UInt<1>(0))
          node T_184373 = or(T_184371, T_184372)
          active := T_184373
    
    node T_184374 = and(req.ready, req.valid)
    when T_184374 : 
      active := UInt<1>(1)
      data_req_cnt := UInt<1>(0)
      req := req.bits
    node T_184375 = eq(active, UInt<1>(0))
    req.ready := T_184375
    node req_idx = bits(req.addr_block, 5, 0)
    node T_184376 = lt(data_req_cnt, UInt<3>(4))
    node fire = and(active, T_184376)
    meta_read.valid := fire
    meta_read.bits.idx := req_idx
    node T_184377 = dshr(req.addr_block, UInt<3>(6))
    meta_read.bits.tag := T_184377
    data_req.valid := fire
    data_req.bits.way_en := req.way_en
    node T_184378 = bits(data_req_cnt, 1, 0)
    node T_184379 = cat(req_idx, T_184378)
    node T_184380 = shl(T_184379, 4)
    data_req.bits.addr := T_184380
    release.bits := req
    release.bits.addr_beat := beat_cnt
    release.bits.data := data_resp
  module ProbeUnit : 
    input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<1>}}
    output rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}
    output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    input way_en : UInt<4>
    input mshr_rdy : UInt<1>
    input block_state : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    
    wire T_184381 : UInt<3>[3]
    T_184381[0] := UInt<3>(0)
    T_184381[1] := UInt<3>(1)
    T_184381[2] := UInt<3>(2)
    wire T_184382 : UInt<2>[2]
    T_184382[0] := UInt<2>(0)
    T_184382[1] := UInt<2>(1)
    wire T_184383 : UInt<2>[3]
    T_184383[0] := UInt<2>(1)
    T_184383[1] := UInt<2>(2)
    T_184383[2] := UInt<2>(3)
    wire T_184384 : UInt<2>[2]
    T_184384[0] := UInt<2>(2)
    T_184384[1] := UInt<2>(3)
    wire T_184385 : UInt<2>[1]
    T_184385[0] := UInt<2>(3)
    wire T_184386 : UInt<3>[3]
    T_184386[0] := UInt<3>(0)
    T_184386[1] := UInt<3>(1)
    T_184386[2] := UInt<3>(2)
    wire T_184387 : UInt<2>[2]
    T_184387[0] := UInt<2>(0)
    T_184387[1] := UInt<2>(1)
    wire T_184388 : UInt<2>[3]
    T_184388[0] := UInt<2>(1)
    T_184388[1] := UInt<2>(2)
    T_184388[2] := UInt<2>(3)
    wire T_184389 : UInt<2>[2]
    T_184389[0] := UInt<2>(2)
    T_184389[1] := UInt<2>(3)
    wire T_184390 : UInt<2>[1]
    T_184390[0] := UInt<2>(3)
    wire T_184391 : UInt<3>[3]
    T_184391[0] := UInt<3>(0)
    T_184391[1] := UInt<3>(1)
    T_184391[2] := UInt<3>(2)
    wire T_184392 : UInt<2>[2]
    T_184392[0] := UInt<2>(0)
    T_184392[1] := UInt<2>(1)
    wire T_184393 : UInt<2>[3]
    T_184393[0] := UInt<2>(1)
    T_184393[1] := UInt<2>(2)
    T_184393[2] := UInt<2>(3)
    wire T_184394 : UInt<2>[2]
    T_184394[0] := UInt<2>(2)
    T_184394[1] := UInt<2>(3)
    wire T_184395 : UInt<2>[1]
    T_184395[0] := UInt<2>(3)
    wire T_184396 : UInt<3>[3]
    T_184396[0] := UInt<3>(0)
    T_184396[1] := UInt<3>(1)
    T_184396[2] := UInt<3>(2)
    wire T_184397 : UInt<2>[2]
    T_184397[0] := UInt<2>(0)
    T_184397[1] := UInt<2>(1)
    wire T_184398 : UInt<2>[3]
    T_184398[0] := UInt<2>(1)
    T_184398[1] := UInt<2>(2)
    T_184398[2] := UInt<2>(3)
    wire T_184399 : UInt<2>[2]
    T_184399[0] := UInt<2>(2)
    T_184399[1] := UInt<2>(3)
    wire T_184400 : UInt<2>[1]
    T_184400[0] := UInt<2>(3)
    wire T_184401 : UInt<3>[3]
    T_184401[0] := UInt<3>(0)
    T_184401[1] := UInt<3>(1)
    T_184401[2] := UInt<3>(2)
    wire T_184402 : UInt<2>[2]
    T_184402[0] := UInt<2>(0)
    T_184402[1] := UInt<2>(1)
    wire T_184403 : UInt<2>[3]
    T_184403[0] := UInt<2>(1)
    T_184403[1] := UInt<2>(2)
    T_184403[2] := UInt<2>(3)
    wire T_184404 : UInt<2>[2]
    T_184404[0] := UInt<2>(2)
    T_184404[1] := UInt<2>(3)
    wire T_184405 : UInt<2>[1]
    T_184405[0] := UInt<2>(3)
    wire T_184406 : UInt<3>[3]
    T_184406[0] := UInt<3>(0)
    T_184406[1] := UInt<3>(1)
    T_184406[2] := UInt<3>(2)
    wire T_184407 : UInt<2>[2]
    T_184407[0] := UInt<2>(0)
    T_184407[1] := UInt<2>(1)
    wire T_184408 : UInt<2>[3]
    T_184408[0] := UInt<2>(1)
    T_184408[1] := UInt<2>(2)
    T_184408[2] := UInt<2>(3)
    wire T_184409 : UInt<2>[2]
    T_184409[0] := UInt<2>(2)
    T_184409[1] := UInt<2>(3)
    wire T_184410 : UInt<2>[1]
    T_184410[0] := UInt<2>(3)
    wire T_184411 : UInt<3>[3]
    T_184411[0] := UInt<3>(0)
    T_184411[1] := UInt<3>(1)
    T_184411[2] := UInt<3>(2)
    wire T_184412 : UInt<2>[2]
    T_184412[0] := UInt<2>(0)
    T_184412[1] := UInt<2>(1)
    wire T_184413 : UInt<2>[3]
    T_184413[0] := UInt<2>(1)
    T_184413[1] := UInt<2>(2)
    T_184413[2] := UInt<2>(3)
    wire T_184414 : UInt<2>[2]
    T_184414[0] := UInt<2>(2)
    T_184414[1] := UInt<2>(3)
    wire T_184415 : UInt<2>[1]
    T_184415[0] := UInt<2>(3)
    wire T_184416 : UInt<3>[3]
    T_184416[0] := UInt<3>(0)
    T_184416[1] := UInt<3>(1)
    T_184416[2] := UInt<3>(2)
    wire T_184417 : UInt<2>[2]
    T_184417[0] := UInt<2>(0)
    T_184417[1] := UInt<2>(1)
    wire T_184418 : UInt<2>[3]
    T_184418[0] := UInt<2>(1)
    T_184418[1] := UInt<2>(2)
    T_184418[2] := UInt<2>(3)
    wire T_184419 : UInt<2>[2]
    T_184419[0] := UInt<2>(2)
    T_184419[1] := UInt<2>(3)
    wire T_184420 : UInt<2>[1]
    T_184420[0] := UInt<2>(3)
    wire T_184421 : UInt<3>[3]
    T_184421[0] := UInt<3>(0)
    T_184421[1] := UInt<3>(1)
    T_184421[2] := UInt<3>(2)
    wire T_184422 : UInt<2>[2]
    T_184422[0] := UInt<2>(0)
    T_184422[1] := UInt<2>(1)
    wire T_184423 : UInt<2>[3]
    T_184423[0] := UInt<2>(1)
    T_184423[1] := UInt<2>(2)
    T_184423[2] := UInt<2>(3)
    wire T_184424 : UInt<2>[2]
    T_184424[0] := UInt<2>(2)
    T_184424[1] := UInt<2>(3)
    wire T_184425 : UInt<2>[1]
    T_184425[0] := UInt<2>(3)
    wire T_184426 : UInt<3>[3]
    T_184426[0] := UInt<3>(0)
    T_184426[1] := UInt<3>(1)
    T_184426[2] := UInt<3>(2)
    wire T_184427 : UInt<2>[2]
    T_184427[0] := UInt<2>(0)
    T_184427[1] := UInt<2>(1)
    wire T_184428 : UInt<2>[3]
    T_184428[0] := UInt<2>(1)
    T_184428[1] := UInt<2>(2)
    T_184428[2] := UInt<2>(3)
    wire T_184429 : UInt<2>[2]
    T_184429[0] := UInt<2>(2)
    T_184429[1] := UInt<2>(3)
    wire T_184430 : UInt<2>[1]
    T_184430[0] := UInt<2>(3)
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    wire T_184431 : UInt<3>[3]
    T_184431[0] := UInt<3>(0)
    T_184431[1] := UInt<3>(1)
    T_184431[2] := UInt<3>(2)
    wire T_184432 : UInt<2>[2]
    T_184432[0] := UInt<2>(0)
    T_184432[1] := UInt<2>(1)
    wire T_184433 : UInt<2>[3]
    T_184433[0] := UInt<2>(1)
    T_184433[1] := UInt<2>(2)
    T_184433[2] := UInt<2>(3)
    wire T_184434 : UInt<2>[2]
    T_184434[0] := UInt<2>(2)
    T_184434[1] := UInt<2>(3)
    wire T_184435 : UInt<2>[1]
    T_184435[0] := UInt<2>(3)
    wire T_184436 : UInt<3>[3]
    T_184436[0] := UInt<3>(0)
    T_184436[1] := UInt<3>(1)
    T_184436[2] := UInt<3>(2)
    wire T_184437 : UInt<2>[2]
    T_184437[0] := UInt<2>(0)
    T_184437[1] := UInt<2>(1)
    wire T_184438 : UInt<2>[3]
    T_184438[0] := UInt<2>(1)
    T_184438[1] := UInt<2>(2)
    T_184438[2] := UInt<2>(3)
    wire T_184439 : UInt<2>[2]
    T_184439[0] := UInt<2>(2)
    T_184439[1] := UInt<2>(3)
    wire T_184440 : UInt<2>[1]
    T_184440[0] := UInt<2>(3)
    reg old_coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    reg way_en : UInt
    wire T_184441 : UInt<3>[3]
    T_184441[0] := UInt<3>(0)
    T_184441[1] := UInt<3>(1)
    T_184441[2] := UInt<3>(2)
    wire T_184442 : UInt<2>[2]
    T_184442[0] := UInt<2>(0)
    T_184442[1] := UInt<2>(1)
    wire T_184443 : UInt<2>[3]
    T_184443[0] := UInt<2>(1)
    T_184443[1] := UInt<2>(2)
    T_184443[2] := UInt<2>(3)
    wire T_184444 : UInt<2>[2]
    T_184444[0] := UInt<2>(2)
    T_184444[1] := UInt<2>(3)
    wire T_184445 : UInt<2>[1]
    T_184445[0] := UInt<2>(3)
    wire T_184446 : UInt<3>[3]
    T_184446[0] := UInt<3>(0)
    T_184446[1] := UInt<3>(1)
    T_184446[2] := UInt<3>(2)
    wire T_184447 : UInt<2>[2]
    T_184447[0] := UInt<2>(0)
    T_184447[1] := UInt<2>(1)
    wire T_184448 : UInt<2>[3]
    T_184448[0] := UInt<2>(1)
    T_184448[1] := UInt<2>(2)
    T_184448[2] := UInt<2>(3)
    wire T_184449 : UInt<2>[2]
    T_184449[0] := UInt<2>(2)
    T_184449[1] := UInt<2>(3)
    wire T_184450 : UInt<2>[1]
    T_184450[0] := UInt<2>(3)
    reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<1>}
    node T_184451 = eq(way_en, UInt<1>(0))
    node tag_matches = eq(T_184451, UInt<1>(0))
    
    
    node T_184452 = eq(state, UInt<3>(7))
    node T_184453 = and(T_184452, meta_write.ready)
    when T_184453 : state := UInt<3>(0)
    
    
    node T_184454 = eq(state, UInt<3>(6))
    node T_184455 = and(T_184454, wb_req.ready)
    when T_184455 : state := UInt<3>(7)
    
    
    node T_184456 = eq(state, UInt<3>(5))
    node T_184457 = and(T_184456, wb_req.ready)
    when T_184457 : state := UInt<3>(6)
    
    
    node T_184458 = eq(state, UInt<3>(4))
    node T_184459 = and(T_184458, rep.ready)
    when T_184459 : 
      state := UInt<3>(0)
      when tag_matches : 
        node T_184460 = eq(T_184440[0], old_coh.state)
        node T_184461 = or(UInt<1>(0), T_184460)
        wire T_184462 : UInt<3>
        T_184462 := UInt<3>(7)
        when T_184461 : T_184462 := UInt<3>(5)
        state := T_184462
    
    node T_184463 = eq(state, UInt<3>(3))
    when T_184463 : 
      state := UInt<3>(4)
      old_coh := block_state
      way_en := way_en
      
      node T_184464 = eq(mshr_rdy, UInt<1>(0))
      when T_184464 : state := UInt<3>(1)
    
    node T_184465 = eq(state, UInt<3>(2))
    when T_184465 : state := UInt<3>(3)
    
    
    node T_184466 = eq(state, UInt<3>(1))
    node T_184467 = and(T_184466, meta_read.ready)
    when T_184467 : state := UInt<3>(2)
    
    
    node T_184468 = eq(state, UInt<3>(0))
    node T_184469 = and(T_184468, req.valid)
    when T_184469 : 
      state := UInt<3>(1)
      req := req.bits
    node T_184470 = eq(T_184440[0], old_coh.state)
    node T_184471 = or(UInt<1>(0), T_184470)
    wire T_184472 : UInt<3>
    T_184472 := UInt<3>(3)
    when T_184471 : T_184472 := UInt<3>(0)
    wire T_184473 : UInt<3>
    T_184473 := UInt<3>(4)
    when T_184471 : T_184473 := UInt<3>(1)
    wire T_184474 : UInt<3>
    T_184474 := UInt<3>(5)
    when T_184471 : T_184474 := UInt<3>(2)
    node T_184475 = eq(UInt<5>(19), UInt<5>(16))
    wire T_184476 : UInt<3>
    T_184476 := UInt<3>(5)
    when T_184475 : T_184476 := T_184474
    node T_184477 = eq(UInt<5>(17), UInt<5>(16))
    wire T_184478 : UInt<3>
    T_184478 := T_184476
    when T_184477 : T_184478 := T_184473
    node T_184479 = eq(UInt<5>(16), UInt<5>(16))
    wire T_184480 : UInt<3>
    T_184480 := T_184478
    when T_184479 : T_184480 := T_184472
    node T_184481 = eq(T_184440[0], old_coh.state)
    node T_184482 = or(UInt<1>(0), T_184481)
    wire T_184483 : UInt<3>
    T_184483 := UInt<3>(3)
    when T_184482 : T_184483 := UInt<3>(0)
    wire T_184484 : UInt<3>
    T_184484 := UInt<3>(4)
    when T_184482 : T_184484 := UInt<3>(1)
    wire T_184485 : UInt<3>
    T_184485 := UInt<3>(5)
    when T_184482 : T_184485 := UInt<3>(2)
    node T_184486 = eq(UInt<5>(19), UInt<5>(17))
    wire T_184487 : UInt<3>
    T_184487 := UInt<3>(5)
    when T_184486 : T_184487 := T_184485
    node T_184488 = eq(UInt<5>(17), UInt<5>(17))
    wire T_184489 : UInt<3>
    T_184489 := T_184487
    when T_184488 : T_184489 := T_184484
    node T_184490 = eq(UInt<5>(16), UInt<5>(17))
    wire T_184491 : UInt<3>
    T_184491 := T_184489
    when T_184490 : T_184491 := T_184483
    node T_184492 = eq(T_184440[0], old_coh.state)
    node T_184493 = or(UInt<1>(0), T_184492)
    wire T_184494 : UInt<3>
    T_184494 := UInt<3>(3)
    when T_184493 : T_184494 := UInt<3>(0)
    wire T_184495 : UInt<3>
    T_184495 := UInt<3>(4)
    when T_184493 : T_184495 := UInt<3>(1)
    wire T_184496 : UInt<3>
    T_184496 := UInt<3>(5)
    when T_184493 : T_184496 := UInt<3>(2)
    node T_184497 = eq(UInt<5>(19), UInt<5>(19))
    wire T_184498 : UInt<3>
    T_184498 := UInt<3>(5)
    when T_184497 : T_184498 := T_184496
    node T_184499 = eq(UInt<5>(17), UInt<5>(19))
    wire T_184500 : UInt<3>
    T_184500 := T_184498
    when T_184499 : T_184500 := T_184495
    node T_184501 = eq(UInt<5>(16), UInt<5>(19))
    wire T_184502 : UInt<3>
    T_184502 := T_184500
    when T_184501 : T_184502 := T_184494
    node T_184503 = eq(UInt<2>(2), req.p_type)
    wire T_184504 : UInt<3>
    T_184504 := UInt<3>(3)
    when T_184503 : T_184504 := T_184502
    node T_184505 = eq(UInt<2>(1), req.p_type)
    wire T_184506 : UInt<3>
    T_184506 := T_184504
    when T_184505 : T_184506 := T_184491
    node T_184507 = eq(UInt<2>(0), req.p_type)
    wire T_184508 : UInt<3>
    T_184508 := T_184506
    when T_184507 : T_184508 := T_184480
    wire T_184509 : UInt<3>[3]
    T_184509[0] := UInt<3>(0)
    T_184509[1] := UInt<3>(1)
    T_184509[2] := UInt<3>(2)
    wire T_184510 : UInt<2>[2]
    T_184510[0] := UInt<2>(0)
    T_184510[1] := UInt<2>(1)
    wire T_184511 : UInt<2>[3]
    T_184511[0] := UInt<2>(1)
    T_184511[1] := UInt<2>(2)
    T_184511[2] := UInt<2>(3)
    wire T_184512 : UInt<2>[2]
    T_184512[0] := UInt<2>(2)
    T_184512[1] := UInt<2>(3)
    wire T_184513 : UInt<2>[1]
    T_184513[0] := UInt<2>(3)
    wire T_184514 : UInt<3>[3]
    T_184514[0] := UInt<3>(0)
    T_184514[1] := UInt<3>(1)
    T_184514[2] := UInt<3>(2)
    wire T_184515 : UInt<2>[2]
    T_184515[0] := UInt<2>(0)
    T_184515[1] := UInt<2>(1)
    wire T_184516 : UInt<2>[3]
    T_184516[0] := UInt<2>(1)
    T_184516[1] := UInt<2>(2)
    T_184516[2] := UInt<2>(3)
    wire T_184517 : UInt<2>[2]
    T_184517[0] := UInt<2>(2)
    T_184517[1] := UInt<2>(3)
    wire T_184518 : UInt<2>[1]
    T_184518[0] := UInt<2>(3)
    wire reply : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}
    reply.r_type := T_184508
    reply.client_xact_id := UInt<1>(0)
    reply.addr_block := req.addr_block
    reply.addr_beat := UInt<1>(0)
    reply.data := UInt<1>(0)
    reply.voluntary := UInt<1>(0)
    node T_184519 = eq(state, UInt<3>(0))
    req.ready := T_184519
    node T_184520 = eq(state, UInt<3>(4))
    node T_184521 = eq(T_184440[0], old_coh.state)
    node T_184522 = or(UInt<1>(0), T_184521)
    node T_184523 = and(tag_matches, T_184522)
    node T_184524 = eq(T_184523, UInt<1>(0))
    node T_184525 = and(T_184520, T_184524)
    rep.valid := T_184525
    rep.bits := reply
    node T_184526 = eq(state, UInt<3>(1))
    meta_read.valid := T_184526
    meta_read.bits.idx := req.addr_block
    node T_184527 = shr(req.addr_block, 6)
    meta_read.bits.tag := T_184527
    node T_184528 = eq(state, UInt<3>(7))
    meta_write.valid := T_184528
    meta_write.bits.way_en := way_en
    meta_write.bits.idx := req.addr_block
    node T_184529 = shr(req.addr_block, 6)
    meta_write.bits.data.tag := T_184529
    node T_184530 = eq(UInt<2>(2), req.p_type)
    wire T_184531 : UInt<2>
    T_184531 := old_coh.state
    when T_184530 : T_184531 := old_coh.state
    node T_184532 = eq(UInt<2>(1), req.p_type)
    wire T_184533 : UInt<2>
    T_184533 := T_184531
    when T_184532 : T_184533 := UInt<2>(1)
    node T_184534 = eq(UInt<2>(0), req.p_type)
    wire T_184535 : UInt<2>
    T_184535 := T_184533
    when T_184534 : T_184535 := UInt<2>(0)
    wire T_184536 : UInt<3>[3]
    T_184536[0] := UInt<3>(0)
    T_184536[1] := UInt<3>(1)
    T_184536[2] := UInt<3>(2)
    wire T_184537 : UInt<2>[2]
    T_184537[0] := UInt<2>(0)
    T_184537[1] := UInt<2>(1)
    wire T_184538 : UInt<2>[3]
    T_184538[0] := UInt<2>(1)
    T_184538[1] := UInt<2>(2)
    T_184538[2] := UInt<2>(3)
    wire T_184539 : UInt<2>[2]
    T_184539[0] := UInt<2>(2)
    T_184539[1] := UInt<2>(3)
    wire T_184540 : UInt<2>[1]
    T_184540[0] := UInt<2>(3)
    wire T_184541 : UInt<3>[3]
    T_184541[0] := UInt<3>(0)
    T_184541[1] := UInt<3>(1)
    T_184541[2] := UInt<3>(2)
    wire T_184542 : UInt<2>[2]
    T_184542[0] := UInt<2>(0)
    T_184542[1] := UInt<2>(1)
    wire T_184543 : UInt<2>[3]
    T_184543[0] := UInt<2>(1)
    T_184543[1] := UInt<2>(2)
    T_184543[2] := UInt<2>(3)
    wire T_184544 : UInt<2>[2]
    T_184544[0] := UInt<2>(2)
    T_184544[1] := UInt<2>(3)
    wire T_184545 : UInt<2>[1]
    T_184545[0] := UInt<2>(3)
    wire T_184546 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_184546.state := T_184535
    meta_write.bits.data.coh := T_184546
    node T_184547 = eq(state, UInt<3>(5))
    wb_req.valid := T_184547
    wb_req.bits := reply
    wb_req.bits.way_en := way_en
  module Arbiter_135527 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}
    output chosen : UInt<1>
    
    wire T_184548 : UInt<1>
    node T_184549 = or(UInt<1>(0), in[0].valid)
    node T_184550 = eq(T_184549, UInt<1>(0))
    node T_184551 = eq(UInt<1>(1), UInt<1>(0))
    wire T_184552 : UInt<1>
    T_184552 := UInt<1>(1)
    when UInt<1>(0) : T_184552 := T_184551
    node T_184553 = and(T_184552, out.ready)
    in[0].ready := T_184553
    node T_184554 = eq(UInt<1>(1), UInt<1>(1))
    wire T_184555 : UInt<1>
    T_184555 := T_184550
    when UInt<1>(0) : T_184555 := T_184554
    node T_184556 = and(T_184555, out.ready)
    in[1].ready := T_184556
    accessor T_184557 = in[T_184548]
    out.valid := T_184557.valid
    accessor T_184558 = in[T_184548]
    out.bits := T_184558.bits
    chosen := T_184548
    wire T_184559 : UInt<1>
    T_184559 := UInt<1>(1)
    when in[0].valid : T_184559 := UInt<1>(0)
    wire T_184560 : UInt<1>
    T_184560 := T_184559
    when UInt<1>(0) : T_184560 := UInt<1>(1)
    T_184548 := T_184560
  module Arbiter_136117 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output chosen : UInt<1>
    
    wire T_184561 : UInt<3>[3]
    T_184561[0] := UInt<3>(0)
    T_184561[1] := UInt<3>(1)
    T_184561[2] := UInt<3>(2)
    wire T_184562 : UInt<2>[2]
    T_184562[0] := UInt<2>(0)
    T_184562[1] := UInt<2>(1)
    wire T_184563 : UInt<2>[3]
    T_184563[0] := UInt<2>(1)
    T_184563[1] := UInt<2>(2)
    T_184563[2] := UInt<2>(3)
    wire T_184564 : UInt<2>[2]
    T_184564[0] := UInt<2>(2)
    T_184564[1] := UInt<2>(3)
    wire T_184565 : UInt<2>[1]
    T_184565[0] := UInt<2>(3)
    wire T_184566 : UInt<3>[3]
    T_184566[0] := UInt<3>(0)
    T_184566[1] := UInt<3>(1)
    T_184566[2] := UInt<3>(2)
    wire T_184567 : UInt<2>[2]
    T_184567[0] := UInt<2>(0)
    T_184567[1] := UInt<2>(1)
    wire T_184568 : UInt<2>[3]
    T_184568[0] := UInt<2>(1)
    T_184568[1] := UInt<2>(2)
    T_184568[2] := UInt<2>(3)
    wire T_184569 : UInt<2>[2]
    T_184569[0] := UInt<2>(2)
    T_184569[1] := UInt<2>(3)
    wire T_184570 : UInt<2>[1]
    T_184570[0] := UInt<2>(3)
    wire T_184571 : UInt<3>[3]
    T_184571[0] := UInt<3>(0)
    T_184571[1] := UInt<3>(1)
    T_184571[2] := UInt<3>(2)
    wire T_184572 : UInt<2>[2]
    T_184572[0] := UInt<2>(0)
    T_184572[1] := UInt<2>(1)
    wire T_184573 : UInt<2>[3]
    T_184573[0] := UInt<2>(1)
    T_184573[1] := UInt<2>(2)
    T_184573[2] := UInt<2>(3)
    wire T_184574 : UInt<2>[2]
    T_184574[0] := UInt<2>(2)
    T_184574[1] := UInt<2>(3)
    wire T_184575 : UInt<2>[1]
    T_184575[0] := UInt<2>(3)
    wire T_184576 : UInt<3>[3]
    T_184576[0] := UInt<3>(0)
    T_184576[1] := UInt<3>(1)
    T_184576[2] := UInt<3>(2)
    wire T_184577 : UInt<2>[2]
    T_184577[0] := UInt<2>(0)
    T_184577[1] := UInt<2>(1)
    wire T_184578 : UInt<2>[3]
    T_184578[0] := UInt<2>(1)
    T_184578[1] := UInt<2>(2)
    T_184578[2] := UInt<2>(3)
    wire T_184579 : UInt<2>[2]
    T_184579[0] := UInt<2>(2)
    T_184579[1] := UInt<2>(3)
    wire T_184580 : UInt<2>[1]
    T_184580[0] := UInt<2>(3)
    wire T_184581 : UInt<1>
    node T_184582 = or(UInt<1>(0), in[0].valid)
    node T_184583 = eq(T_184582, UInt<1>(0))
    node T_184584 = eq(UInt<1>(1), UInt<1>(0))
    wire T_184585 : UInt<1>
    T_184585 := UInt<1>(1)
    when UInt<1>(0) : T_184585 := T_184584
    node T_184586 = and(T_184585, out.ready)
    in[0].ready := T_184586
    node T_184587 = eq(UInt<1>(1), UInt<1>(1))
    wire T_184588 : UInt<1>
    T_184588 := T_184583
    when UInt<1>(0) : T_184588 := T_184587
    node T_184589 = and(T_184588, out.ready)
    in[1].ready := T_184589
    wire T_184590 : UInt<3>[3]
    T_184590[0] := UInt<3>(0)
    T_184590[1] := UInt<3>(1)
    T_184590[2] := UInt<3>(2)
    wire T_184591 : UInt<2>[2]
    T_184591[0] := UInt<2>(0)
    T_184591[1] := UInt<2>(1)
    wire T_184592 : UInt<2>[3]
    T_184592[0] := UInt<2>(1)
    T_184592[1] := UInt<2>(2)
    T_184592[2] := UInt<2>(3)
    wire T_184593 : UInt<2>[2]
    T_184593[0] := UInt<2>(2)
    T_184593[1] := UInt<2>(3)
    wire T_184594 : UInt<2>[1]
    T_184594[0] := UInt<2>(3)
    accessor T_184595 = in[T_184581]
    out.valid := T_184595.valid
    wire T_184596 : UInt<3>[3]
    T_184596[0] := UInt<3>(0)
    T_184596[1] := UInt<3>(1)
    T_184596[2] := UInt<3>(2)
    wire T_184597 : UInt<2>[2]
    T_184597[0] := UInt<2>(0)
    T_184597[1] := UInt<2>(1)
    wire T_184598 : UInt<2>[3]
    T_184598[0] := UInt<2>(1)
    T_184598[1] := UInt<2>(2)
    T_184598[2] := UInt<2>(3)
    wire T_184599 : UInt<2>[2]
    T_184599[0] := UInt<2>(2)
    T_184599[1] := UInt<2>(3)
    wire T_184600 : UInt<2>[1]
    T_184600[0] := UInt<2>(3)
    accessor T_184601 = in[T_184581]
    out.bits := T_184601.bits
    chosen := T_184581
    wire T_184602 : UInt<1>
    T_184602 := UInt<1>(1)
    when in[0].valid : T_184602 := UInt<1>(0)
    wire T_184603 : UInt<1>
    T_184603 := T_184602
    when UInt<1>(0) : T_184603 := UInt<1>(1)
    T_184581 := T_184603
  module LockingArbiter : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    output chosen : UInt<1>
    
    wire T_184604 : UInt<3>[3]
    T_184604[0] := UInt<3>(0)
    T_184604[1] := UInt<3>(1)
    T_184604[2] := UInt<3>(2)
    wire T_184605 : UInt<2>[2]
    T_184605[0] := UInt<2>(0)
    T_184605[1] := UInt<2>(1)
    wire T_184606 : UInt<2>[3]
    T_184606[0] := UInt<2>(1)
    T_184606[1] := UInt<2>(2)
    T_184606[2] := UInt<2>(3)
    wire T_184607 : UInt<2>[2]
    T_184607[0] := UInt<2>(2)
    T_184607[1] := UInt<2>(3)
    wire T_184608 : UInt<2>[1]
    T_184608[0] := UInt<2>(3)
    wire T_184609 : UInt<3>[3]
    T_184609[0] := UInt<3>(0)
    T_184609[1] := UInt<3>(1)
    T_184609[2] := UInt<3>(2)
    wire T_184610 : UInt<2>[2]
    T_184610[0] := UInt<2>(0)
    T_184610[1] := UInt<2>(1)
    wire T_184611 : UInt<2>[3]
    T_184611[0] := UInt<2>(1)
    T_184611[1] := UInt<2>(2)
    T_184611[2] := UInt<2>(3)
    wire T_184612 : UInt<2>[2]
    T_184612[0] := UInt<2>(2)
    T_184612[1] := UInt<2>(3)
    wire T_184613 : UInt<2>[1]
    T_184613[0] := UInt<2>(3)
    wire T_184614 : UInt<3>[3]
    T_184614[0] := UInt<3>(0)
    T_184614[1] := UInt<3>(1)
    T_184614[2] := UInt<3>(2)
    wire T_184615 : UInt<2>[2]
    T_184615[0] := UInt<2>(0)
    T_184615[1] := UInt<2>(1)
    wire T_184616 : UInt<2>[3]
    T_184616[0] := UInt<2>(1)
    T_184616[1] := UInt<2>(2)
    T_184616[2] := UInt<2>(3)
    wire T_184617 : UInt<2>[2]
    T_184617[0] := UInt<2>(2)
    T_184617[1] := UInt<2>(3)
    wire T_184618 : UInt<2>[1]
    T_184618[0] := UInt<2>(3)
    wire T_184619 : UInt<3>[3]
    T_184619[0] := UInt<3>(0)
    T_184619[1] := UInt<3>(1)
    T_184619[2] := UInt<3>(2)
    wire T_184620 : UInt<2>[2]
    T_184620[0] := UInt<2>(0)
    T_184620[1] := UInt<2>(1)
    wire T_184621 : UInt<2>[3]
    T_184621[0] := UInt<2>(1)
    T_184621[1] := UInt<2>(2)
    T_184621[2] := UInt<2>(3)
    wire T_184622 : UInt<2>[2]
    T_184622[0] := UInt<2>(2)
    T_184622[1] := UInt<2>(3)
    wire T_184623 : UInt<2>[1]
    T_184623[0] := UInt<2>(3)
    reg T_184624 : UInt<1>
    onreset T_184624 := UInt<1>(0)
    reg T_184625 : UInt<1>
    onreset T_184625 := UInt<1>(1)
    wire T_184626 : UInt<1>
    node T_184627 = or(UInt<1>(0), in[0].valid)
    node T_184628 = eq(T_184627, UInt<1>(0))
    node T_184629 = eq(T_184625, UInt<1>(0))
    wire T_184630 : UInt<1>
    T_184630 := UInt<1>(1)
    when T_184624 : T_184630 := T_184629
    node T_184631 = and(T_184630, out.ready)
    in[0].ready := T_184631
    node T_184632 = eq(T_184625, UInt<1>(1))
    wire T_184633 : UInt<1>
    T_184633 := T_184628
    when T_184624 : T_184633 := T_184632
    node T_184634 = and(T_184633, out.ready)
    in[1].ready := T_184634
    wire T_184635 : UInt<3>[3]
    T_184635[0] := UInt<3>(0)
    T_184635[1] := UInt<3>(1)
    T_184635[2] := UInt<3>(2)
    wire T_184636 : UInt<2>[2]
    T_184636[0] := UInt<2>(0)
    T_184636[1] := UInt<2>(1)
    wire T_184637 : UInt<2>[3]
    T_184637[0] := UInt<2>(1)
    T_184637[1] := UInt<2>(2)
    T_184637[2] := UInt<2>(3)
    wire T_184638 : UInt<2>[2]
    T_184638[0] := UInt<2>(2)
    T_184638[1] := UInt<2>(3)
    wire T_184639 : UInt<2>[1]
    T_184639[0] := UInt<2>(3)
    accessor T_184640 = in[T_184626]
    out.valid := T_184640.valid
    wire T_184641 : UInt<3>[3]
    T_184641[0] := UInt<3>(0)
    T_184641[1] := UInt<3>(1)
    T_184641[2] := UInt<3>(2)
    wire T_184642 : UInt<2>[2]
    T_184642[0] := UInt<2>(0)
    T_184642[1] := UInt<2>(1)
    wire T_184643 : UInt<2>[3]
    T_184643[0] := UInt<2>(1)
    T_184643[1] := UInt<2>(2)
    T_184643[2] := UInt<2>(3)
    wire T_184644 : UInt<2>[2]
    T_184644[0] := UInt<2>(2)
    T_184644[1] := UInt<2>(3)
    wire T_184645 : UInt<2>[1]
    T_184645[0] := UInt<2>(3)
    accessor T_184646 = in[T_184626]
    out.bits := T_184646.bits
    chosen := T_184626
    reg T_184647 : UInt<2>
    onreset T_184647 := UInt<2>(0)
    node T_184648 = addw(T_184647, UInt<1>(1))
    
    node T_184649 = and(out.ready, out.valid)
    when T_184649 : 
      
      
      node T_184650 = and(UInt<1>(1), out.bits.is_builtin_type)
      wire T_184651 : UInt<3>[1]
      T_184651[0] := UInt<3>(3)
      node T_184652 = eq(T_184651[0], out.bits.a_type)
      node T_184653 = or(UInt<1>(0), T_184652)
      node T_184654 = and(T_184650, T_184653)
      when T_184654 : 
        T_184647 := T_184648
        
        node T_184655 = eq(T_184624, UInt<1>(0))
        when T_184655 : 
          T_184624 := UInt<1>(1)
          node T_184656 = and(in[0].ready, in[0].valid)
          node T_184657 = and(in[1].ready, in[1].valid)
          wire T_184658 : UInt<1>[2]
          T_184658[0] := T_184656
          T_184658[1] := T_184657
          wire T_184659 : UInt<1>
          T_184659 := UInt<1>(1)
          when T_184658[0] : T_184659 := UInt<1>(0)
          T_184625 := T_184659
      
      node T_184660 = eq(T_184648, UInt<1>(0))
      when T_184660 : T_184624 := UInt<1>(0)
    wire choose : UInt<1>
    choose := UInt<1>(1)
    when in[0].valid : choose := UInt<1>(0)
    wire T_184661 : UInt<1>
    T_184661 := choose
    when T_184624 : T_184661 := T_184625
    T_184626 := T_184661
  module Arbiter_137146 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    output chosen : UInt<1>
    
    wire T_184662 : UInt<3>[3]
    T_184662[0] := UInt<3>(0)
    T_184662[1] := UInt<3>(1)
    T_184662[2] := UInt<3>(2)
    wire T_184663 : UInt<2>[2]
    T_184663[0] := UInt<2>(0)
    T_184663[1] := UInt<2>(1)
    wire T_184664 : UInt<2>[3]
    T_184664[0] := UInt<2>(1)
    T_184664[1] := UInt<2>(2)
    T_184664[2] := UInt<2>(3)
    wire T_184665 : UInt<2>[2]
    T_184665[0] := UInt<2>(2)
    T_184665[1] := UInt<2>(3)
    wire T_184666 : UInt<2>[1]
    T_184666[0] := UInt<2>(3)
    wire T_184667 : UInt<3>[3]
    T_184667[0] := UInt<3>(0)
    T_184667[1] := UInt<3>(1)
    T_184667[2] := UInt<3>(2)
    wire T_184668 : UInt<2>[2]
    T_184668[0] := UInt<2>(0)
    T_184668[1] := UInt<2>(1)
    wire T_184669 : UInt<2>[3]
    T_184669[0] := UInt<2>(1)
    T_184669[1] := UInt<2>(2)
    T_184669[2] := UInt<2>(3)
    wire T_184670 : UInt<2>[2]
    T_184670[0] := UInt<2>(2)
    T_184670[1] := UInt<2>(3)
    wire T_184671 : UInt<2>[1]
    T_184671[0] := UInt<2>(3)
    wire T_184672 : UInt<3>[3]
    T_184672[0] := UInt<3>(0)
    T_184672[1] := UInt<3>(1)
    T_184672[2] := UInt<3>(2)
    wire T_184673 : UInt<2>[2]
    T_184673[0] := UInt<2>(0)
    T_184673[1] := UInt<2>(1)
    wire T_184674 : UInt<2>[3]
    T_184674[0] := UInt<2>(1)
    T_184674[1] := UInt<2>(2)
    T_184674[2] := UInt<2>(3)
    wire T_184675 : UInt<2>[2]
    T_184675[0] := UInt<2>(2)
    T_184675[1] := UInt<2>(3)
    wire T_184676 : UInt<2>[1]
    T_184676[0] := UInt<2>(3)
    wire T_184677 : UInt<3>[3]
    T_184677[0] := UInt<3>(0)
    T_184677[1] := UInt<3>(1)
    T_184677[2] := UInt<3>(2)
    wire T_184678 : UInt<2>[2]
    T_184678[0] := UInt<2>(0)
    T_184678[1] := UInt<2>(1)
    wire T_184679 : UInt<2>[3]
    T_184679[0] := UInt<2>(1)
    T_184679[1] := UInt<2>(2)
    T_184679[2] := UInt<2>(3)
    wire T_184680 : UInt<2>[2]
    T_184680[0] := UInt<2>(2)
    T_184680[1] := UInt<2>(3)
    wire T_184681 : UInt<2>[1]
    T_184681[0] := UInt<2>(3)
    wire T_184682 : UInt<1>
    node T_184683 = or(UInt<1>(0), in[0].valid)
    node T_184684 = eq(T_184683, UInt<1>(0))
    node T_184685 = eq(UInt<1>(1), UInt<1>(0))
    wire T_184686 : UInt<1>
    T_184686 := UInt<1>(1)
    when UInt<1>(0) : T_184686 := T_184685
    node T_184687 = and(T_184686, out.ready)
    in[0].ready := T_184687
    node T_184688 = eq(UInt<1>(1), UInt<1>(1))
    wire T_184689 : UInt<1>
    T_184689 := T_184684
    when UInt<1>(0) : T_184689 := T_184688
    node T_184690 = and(T_184689, out.ready)
    in[1].ready := T_184690
    wire T_184691 : UInt<3>[3]
    T_184691[0] := UInt<3>(0)
    T_184691[1] := UInt<3>(1)
    T_184691[2] := UInt<3>(2)
    wire T_184692 : UInt<2>[2]
    T_184692[0] := UInt<2>(0)
    T_184692[1] := UInt<2>(1)
    wire T_184693 : UInt<2>[3]
    T_184693[0] := UInt<2>(1)
    T_184693[1] := UInt<2>(2)
    T_184693[2] := UInt<2>(3)
    wire T_184694 : UInt<2>[2]
    T_184694[0] := UInt<2>(2)
    T_184694[1] := UInt<2>(3)
    wire T_184695 : UInt<2>[1]
    T_184695[0] := UInt<2>(3)
    accessor T_184696 = in[T_184682]
    out.valid := T_184696.valid
    wire T_184697 : UInt<3>[3]
    T_184697[0] := UInt<3>(0)
    T_184697[1] := UInt<3>(1)
    T_184697[2] := UInt<3>(2)
    wire T_184698 : UInt<2>[2]
    T_184698[0] := UInt<2>(0)
    T_184698[1] := UInt<2>(1)
    wire T_184699 : UInt<2>[3]
    T_184699[0] := UInt<2>(1)
    T_184699[1] := UInt<2>(2)
    T_184699[2] := UInt<2>(3)
    wire T_184700 : UInt<2>[2]
    T_184700[0] := UInt<2>(2)
    T_184700[1] := UInt<2>(3)
    wire T_184701 : UInt<2>[1]
    T_184701[0] := UInt<2>(3)
    accessor T_184702 = in[T_184682]
    out.bits := T_184702.bits
    chosen := T_184682
    wire T_184703 : UInt<1>
    T_184703 := UInt<1>(1)
    when in[0].valid : T_184703 := UInt<1>(0)
    wire T_184704 : UInt<1>
    T_184704 := T_184703
    when UInt<1>(0) : T_184704 := UInt<1>(1)
    T_184682 := T_184704
  module Arbiter_137247 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    output chosen : UInt<1>
    
    wire T_184705 : UInt<1>
    node T_184706 = or(UInt<1>(0), in[0].valid)
    node T_184707 = eq(T_184706, UInt<1>(0))
    node T_184708 = eq(UInt<1>(1), UInt<1>(0))
    wire T_184709 : UInt<1>
    T_184709 := UInt<1>(1)
    when UInt<1>(0) : T_184709 := T_184708
    node T_184710 = and(T_184709, out.ready)
    in[0].ready := T_184710
    node T_184711 = eq(UInt<1>(1), UInt<1>(1))
    wire T_184712 : UInt<1>
    T_184712 := T_184707
    when UInt<1>(0) : T_184712 := T_184711
    node T_184713 = and(T_184712, out.ready)
    in[1].ready := T_184713
    accessor T_184714 = in[T_184705]
    out.valid := T_184714.valid
    accessor T_184715 = in[T_184705]
    out.bits := T_184715.bits
    chosen := T_184705
    wire T_184716 : UInt<1>
    T_184716 := UInt<1>(1)
    when in[0].valid : T_184716 := UInt<1>(0)
    wire T_184717 : UInt<1>
    T_184717 := T_184716
    when UInt<1>(0) : T_184717 := UInt<1>(1)
    T_184705 := T_184717
  module Arbiter_137299 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
    output chosen : UInt<1>
    
    wire T_184718 : UInt<1>
    node T_184719 = or(UInt<1>(0), in[0].valid)
    node T_184720 = eq(T_184719, UInt<1>(0))
    node T_184721 = eq(UInt<1>(1), UInt<1>(0))
    wire T_184722 : UInt<1>
    T_184722 := UInt<1>(1)
    when UInt<1>(0) : T_184722 := T_184721
    node T_184723 = and(T_184722, out.ready)
    in[0].ready := T_184723
    node T_184724 = eq(UInt<1>(1), UInt<1>(1))
    wire T_184725 : UInt<1>
    T_184725 := T_184720
    when UInt<1>(0) : T_184725 := T_184724
    node T_184726 = and(T_184725, out.ready)
    in[1].ready := T_184726
    accessor T_184727 = in[T_184718]
    out.valid := T_184727.valid
    accessor T_184728 = in[T_184718]
    out.bits := T_184728.bits
    chosen := T_184718
    wire T_184729 : UInt<1>
    T_184729 := UInt<1>(1)
    when in[0].valid : T_184729 := UInt<1>(0)
    wire T_184730 : UInt<1>
    T_184730 := T_184729
    when UInt<1>(0) : T_184730 := UInt<1>(1)
    T_184718 := T_184730
  module Queue_138637 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    output count : UInt<5>
    
    cmem ram : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16]
    reg T_184731 : UInt<4>
    onreset T_184731 := UInt<4>(0)
    reg T_184732 : UInt<4>
    onreset T_184732 := UInt<4>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_184731, T_184732)
    node T_184733 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_184733)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_184734 = and(enq.ready, enq.valid)
    node T_184735 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_184734, T_184735)
    node T_184736 = and(deq.ready, deq.valid)
    node T_184737 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_184736, T_184737)
    when do_enq : 
      accessor T_184738 = ram[T_184731]
      T_184738 := enq.bits
      node T_184739 = eq(T_184731, UInt<4>(15))
      node T_184740 = and(UInt<1>(0), T_184739)
      node T_184741 = addw(T_184731, UInt<1>(1))
      wire T_184742 : UInt<4>
      T_184742 := T_184741
      when T_184740 : T_184742 := UInt<1>(0)
      T_184731 := T_184742
    when do_deq : 
      node T_184743 = eq(T_184732, UInt<4>(15))
      node T_184744 = and(UInt<1>(0), T_184743)
      node T_184745 = addw(T_184732, UInt<1>(1))
      wire T_184746 : UInt<4>
      T_184746 := T_184745
      when T_184744 : T_184746 := UInt<1>(0)
      T_184732 := T_184746
    
    node T_184747 = neq(do_enq, do_deq)
    when T_184747 : maybe_full := do_enq
    node T_184748 = eq(empty, UInt<1>(0))
    node T_184749 = and(UInt<1>(0), enq.valid)
    node T_184750 = or(T_184748, T_184749)
    deq.valid := T_184750
    node T_184751 = eq(full, UInt<1>(0))
    node T_184752 = and(UInt<1>(0), deq.ready)
    node T_184753 = or(T_184751, T_184752)
    enq.ready := T_184753
    accessor T_184754 = ram[T_184732]
    wire T_184755 : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}
    T_184755 := T_184754
    when maybe_flow : T_184755 := enq.bits
    deq.bits := T_184755
    node ptr_diff = subw(T_184731, T_184732)
    node T_184756 = and(maybe_full, ptr_match)
    node T_184757 = cat(T_184756, ptr_diff)
    count := T_184757
  module MSHR : 
    input req_pri_val : UInt<1>
    output req_pri_rdy : UInt<1>
    input req_sec_val : UInt<1>
    output req_sec_rdy : UInt<1>
    input req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, way_en : UInt<4>}
    output idx_match : UInt<1>
    output tag : UInt<20>
    output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    output refill : {way_en : UInt<4>, addr : UInt<12>}
    output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}
    output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    output probe_rdy : UInt<1>
    
    wire T_184758 : UInt<3>[3]
    T_184758[0] := UInt<3>(0)
    T_184758[1] := UInt<3>(1)
    T_184758[2] := UInt<3>(2)
    wire T_184759 : UInt<2>[2]
    T_184759[0] := UInt<2>(0)
    T_184759[1] := UInt<2>(1)
    wire T_184760 : UInt<2>[3]
    T_184760[0] := UInt<2>(1)
    T_184760[1] := UInt<2>(2)
    T_184760[2] := UInt<2>(3)
    wire T_184761 : UInt<2>[2]
    T_184761[0] := UInt<2>(2)
    T_184761[1] := UInt<2>(3)
    wire T_184762 : UInt<2>[1]
    T_184762[0] := UInt<2>(3)
    wire T_184763 : UInt<3>[3]
    T_184763[0] := UInt<3>(0)
    T_184763[1] := UInt<3>(1)
    T_184763[2] := UInt<3>(2)
    wire T_184764 : UInt<2>[2]
    T_184764[0] := UInt<2>(0)
    T_184764[1] := UInt<2>(1)
    wire T_184765 : UInt<2>[3]
    T_184765[0] := UInt<2>(1)
    T_184765[1] := UInt<2>(2)
    T_184765[2] := UInt<2>(3)
    wire T_184766 : UInt<2>[2]
    T_184766[0] := UInt<2>(2)
    T_184766[1] := UInt<2>(3)
    wire T_184767 : UInt<2>[1]
    T_184767[0] := UInt<2>(3)
    wire T_184768 : UInt<3>[3]
    T_184768[0] := UInt<3>(0)
    T_184768[1] := UInt<3>(1)
    T_184768[2] := UInt<3>(2)
    wire T_184769 : UInt<2>[2]
    T_184769[0] := UInt<2>(0)
    T_184769[1] := UInt<2>(1)
    wire T_184770 : UInt<2>[3]
    T_184770[0] := UInt<2>(1)
    T_184770[1] := UInt<2>(2)
    T_184770[2] := UInt<2>(3)
    wire T_184771 : UInt<2>[2]
    T_184771[0] := UInt<2>(2)
    T_184771[1] := UInt<2>(3)
    wire T_184772 : UInt<2>[1]
    T_184772[0] := UInt<2>(3)
    wire T_184773 : UInt<3>[3]
    T_184773[0] := UInt<3>(0)
    T_184773[1] := UInt<3>(1)
    T_184773[2] := UInt<3>(2)
    wire T_184774 : UInt<2>[2]
    T_184774[0] := UInt<2>(0)
    T_184774[1] := UInt<2>(1)
    wire T_184775 : UInt<2>[3]
    T_184775[0] := UInt<2>(1)
    T_184775[1] := UInt<2>(2)
    T_184775[2] := UInt<2>(3)
    wire T_184776 : UInt<2>[2]
    T_184776[0] := UInt<2>(2)
    T_184776[1] := UInt<2>(3)
    wire T_184777 : UInt<2>[1]
    T_184777[0] := UInt<2>(3)
    wire T_184778 : UInt<3>[3]
    T_184778[0] := UInt<3>(0)
    T_184778[1] := UInt<3>(1)
    T_184778[2] := UInt<3>(2)
    wire T_184779 : UInt<2>[2]
    T_184779[0] := UInt<2>(0)
    T_184779[1] := UInt<2>(1)
    wire T_184780 : UInt<2>[3]
    T_184780[0] := UInt<2>(1)
    T_184780[1] := UInt<2>(2)
    T_184780[2] := UInt<2>(3)
    wire T_184781 : UInt<2>[2]
    T_184781[0] := UInt<2>(2)
    T_184781[1] := UInt<2>(3)
    wire T_184782 : UInt<2>[1]
    T_184782[0] := UInt<2>(3)
    wire T_184783 : UInt<3>[3]
    T_184783[0] := UInt<3>(0)
    T_184783[1] := UInt<3>(1)
    T_184783[2] := UInt<3>(2)
    wire T_184784 : UInt<2>[2]
    T_184784[0] := UInt<2>(0)
    T_184784[1] := UInt<2>(1)
    wire T_184785 : UInt<2>[3]
    T_184785[0] := UInt<2>(1)
    T_184785[1] := UInt<2>(2)
    T_184785[2] := UInt<2>(3)
    wire T_184786 : UInt<2>[2]
    T_184786[0] := UInt<2>(2)
    T_184786[1] := UInt<2>(3)
    wire T_184787 : UInt<2>[1]
    T_184787[0] := UInt<2>(3)
    wire T_184788 : UInt<3>[3]
    T_184788[0] := UInt<3>(0)
    T_184788[1] := UInt<3>(1)
    T_184788[2] := UInt<3>(2)
    wire T_184789 : UInt<2>[2]
    T_184789[0] := UInt<2>(0)
    T_184789[1] := UInt<2>(1)
    wire T_184790 : UInt<2>[3]
    T_184790[0] := UInt<2>(1)
    T_184790[1] := UInt<2>(2)
    T_184790[2] := UInt<2>(3)
    wire T_184791 : UInt<2>[2]
    T_184791[0] := UInt<2>(2)
    T_184791[1] := UInt<2>(3)
    wire T_184792 : UInt<2>[1]
    T_184792[0] := UInt<2>(3)
    wire T_184793 : UInt<3>[3]
    T_184793[0] := UInt<3>(0)
    T_184793[1] := UInt<3>(1)
    T_184793[2] := UInt<3>(2)
    wire T_184794 : UInt<2>[2]
    T_184794[0] := UInt<2>(0)
    T_184794[1] := UInt<2>(1)
    wire T_184795 : UInt<2>[3]
    T_184795[0] := UInt<2>(1)
    T_184795[1] := UInt<2>(2)
    T_184795[2] := UInt<2>(3)
    wire T_184796 : UInt<2>[2]
    T_184796[0] := UInt<2>(2)
    T_184796[1] := UInt<2>(3)
    wire T_184797 : UInt<2>[1]
    T_184797[0] := UInt<2>(3)
    wire T_184798 : UInt<3>[3]
    T_184798[0] := UInt<3>(0)
    T_184798[1] := UInt<3>(1)
    T_184798[2] := UInt<3>(2)
    wire T_184799 : UInt<2>[2]
    T_184799[0] := UInt<2>(0)
    T_184799[1] := UInt<2>(1)
    wire T_184800 : UInt<2>[3]
    T_184800[0] := UInt<2>(1)
    T_184800[1] := UInt<2>(2)
    T_184800[2] := UInt<2>(3)
    wire T_184801 : UInt<2>[2]
    T_184801[0] := UInt<2>(2)
    T_184801[1] := UInt<2>(3)
    wire T_184802 : UInt<2>[1]
    T_184802[0] := UInt<2>(3)
    wire T_184803 : UInt<3>[3]
    T_184803[0] := UInt<3>(0)
    T_184803[1] := UInt<3>(1)
    T_184803[2] := UInt<3>(2)
    wire T_184804 : UInt<2>[2]
    T_184804[0] := UInt<2>(0)
    T_184804[1] := UInt<2>(1)
    wire T_184805 : UInt<2>[3]
    T_184805[0] := UInt<2>(1)
    T_184805[1] := UInt<2>(2)
    T_184805[2] := UInt<2>(3)
    wire T_184806 : UInt<2>[2]
    T_184806[0] := UInt<2>(2)
    T_184806[1] := UInt<2>(3)
    wire T_184807 : UInt<2>[1]
    T_184807[0] := UInt<2>(3)
    reg state : UInt<4>
    onreset state := UInt<4>(0)
    wire T_184808 : UInt<3>[3]
    T_184808[0] := UInt<3>(0)
    T_184808[1] := UInt<3>(1)
    T_184808[2] := UInt<3>(2)
    wire T_184809 : UInt<2>[2]
    T_184809[0] := UInt<2>(0)
    T_184809[1] := UInt<2>(1)
    wire T_184810 : UInt<2>[3]
    T_184810[0] := UInt<2>(1)
    T_184810[1] := UInt<2>(2)
    T_184810[2] := UInt<2>(3)
    wire T_184811 : UInt<2>[2]
    T_184811[0] := UInt<2>(2)
    T_184811[1] := UInt<2>(3)
    wire T_184812 : UInt<2>[1]
    T_184812[0] := UInt<2>(3)
    wire T_184813 : UInt<3>[3]
    T_184813[0] := UInt<3>(0)
    T_184813[1] := UInt<3>(1)
    T_184813[2] := UInt<3>(2)
    wire T_184814 : UInt<2>[2]
    T_184814[0] := UInt<2>(0)
    T_184814[1] := UInt<2>(1)
    wire T_184815 : UInt<2>[3]
    T_184815[0] := UInt<2>(1)
    T_184815[1] := UInt<2>(2)
    T_184815[2] := UInt<2>(3)
    wire T_184816 : UInt<2>[2]
    T_184816[0] := UInt<2>(2)
    T_184816[1] := UInt<2>(3)
    wire T_184817 : UInt<2>[1]
    T_184817[0] := UInt<2>(3)
    wire T_184818 : UInt<3>[3]
    T_184818[0] := UInt<3>(0)
    T_184818[1] := UInt<3>(1)
    T_184818[2] := UInt<3>(2)
    wire T_184819 : UInt<2>[2]
    T_184819[0] := UInt<2>(0)
    T_184819[1] := UInt<2>(1)
    wire T_184820 : UInt<2>[3]
    T_184820[0] := UInt<2>(1)
    T_184820[1] := UInt<2>(2)
    T_184820[2] := UInt<2>(3)
    wire T_184821 : UInt<2>[2]
    T_184821[0] := UInt<2>(2)
    T_184821[1] := UInt<2>(3)
    wire T_184822 : UInt<2>[1]
    T_184822[0] := UInt<2>(3)
    wire T_184823 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_184823.state := UInt<2>(0)
    wire T_184824 : UInt<3>[3]
    T_184824[0] := UInt<3>(0)
    T_184824[1] := UInt<3>(1)
    T_184824[2] := UInt<3>(2)
    wire T_184825 : UInt<2>[2]
    T_184825[0] := UInt<2>(0)
    T_184825[1] := UInt<2>(1)
    wire T_184826 : UInt<2>[3]
    T_184826[0] := UInt<2>(1)
    T_184826[1] := UInt<2>(2)
    T_184826[2] := UInt<2>(3)
    wire T_184827 : UInt<2>[2]
    T_184827[0] := UInt<2>(2)
    T_184827[1] := UInt<2>(3)
    wire T_184828 : UInt<2>[1]
    T_184828[0] := UInt<2>(3)
    reg new_coh_state : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    onreset new_coh_state := T_184823
    wire T_184829 : UInt<3>[3]
    T_184829[0] := UInt<3>(0)
    T_184829[1] := UInt<3>(1)
    T_184829[2] := UInt<3>(2)
    wire T_184830 : UInt<2>[2]
    T_184830[0] := UInt<2>(0)
    T_184830[1] := UInt<2>(1)
    wire T_184831 : UInt<2>[3]
    T_184831[0] := UInt<2>(1)
    T_184831[1] := UInt<2>(2)
    T_184831[2] := UInt<2>(3)
    wire T_184832 : UInt<2>[2]
    T_184832[0] := UInt<2>(2)
    T_184832[1] := UInt<2>(3)
    wire T_184833 : UInt<2>[1]
    T_184833[0] := UInt<2>(3)
    wire T_184834 : UInt<3>[3]
    T_184834[0] := UInt<3>(0)
    T_184834[1] := UInt<3>(1)
    T_184834[2] := UInt<3>(2)
    wire T_184835 : UInt<2>[2]
    T_184835[0] := UInt<2>(0)
    T_184835[1] := UInt<2>(1)
    wire T_184836 : UInt<2>[3]
    T_184836[0] := UInt<2>(1)
    T_184836[1] := UInt<2>(2)
    T_184836[2] := UInt<2>(3)
    wire T_184837 : UInt<2>[2]
    T_184837[0] := UInt<2>(2)
    T_184837[1] := UInt<2>(3)
    wire T_184838 : UInt<2>[1]
    T_184838[0] := UInt<2>(3)
    reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, way_en : UInt<4>}
    node req_idx = bits(req.addr, 11, 6)
    node T_184839 = bits(req_bits.addr, 11, 6)
    node idx_match = eq(req_idx, T_184839)
    node T_184840 = eq(req_bits.cmd, UInt<5>(1))
    node T_184841 = eq(req_bits.cmd, UInt<5>(7))
    node T_184842 = or(T_184840, T_184841)
    node T_184843 = bit(req_bits.cmd, 3)
    node T_184844 = eq(req_bits.cmd, UInt<5>(4))
    node T_184845 = or(T_184843, T_184844)
    node T_184846 = or(T_184842, T_184845)
    node T_184847 = eq(req_bits.cmd, UInt<5>(3))
    node T_184848 = or(T_184846, T_184847)
    node T_184849 = eq(req_bits.cmd, UInt<5>(6))
    node T_184850 = or(T_184848, T_184849)
    node T_184851 = eq(req.cmd, UInt<5>(1))
    node T_184852 = eq(req.cmd, UInt<5>(7))
    node T_184853 = or(T_184851, T_184852)
    node T_184854 = bit(req.cmd, 3)
    node T_184855 = eq(req.cmd, UInt<5>(4))
    node T_184856 = or(T_184854, T_184855)
    node T_184857 = or(T_184853, T_184856)
    node T_184858 = eq(req.cmd, UInt<5>(3))
    node T_184859 = or(T_184857, T_184858)
    node T_184860 = eq(req.cmd, UInt<5>(6))
    node T_184861 = or(T_184859, T_184860)
    node T_184862 = eq(T_184861, UInt<1>(0))
    node cmd_requires_second_acquire = and(T_184850, T_184862)
    wire states_before_refill : UInt<4>[3]
    states_before_refill[0] := UInt<4>(1)
    states_before_refill[1] := UInt<4>(2)
    states_before_refill[2] := UInt<4>(3)
    node T_184863 = eq(states_before_refill[0], state)
    node T_184864 = eq(states_before_refill[1], state)
    node T_184865 = eq(states_before_refill[2], state)
    node T_184866 = or(UInt<1>(0), T_184863)
    node T_184867 = or(T_184866, T_184864)
    node T_184868 = or(T_184867, T_184865)
    wire T_184869 : UInt<4>[2]
    T_184869[0] := UInt<4>(4)
    T_184869[1] := UInt<4>(5)
    node T_184870 = eq(T_184869[0], state)
    node T_184871 = eq(T_184869[1], state)
    node T_184872 = or(UInt<1>(0), T_184870)
    node T_184873 = or(T_184872, T_184871)
    node T_184874 = eq(cmd_requires_second_acquire, UInt<1>(0))
    node T_184875 = and(T_184873, T_184874)
    node T_184876 = or(T_184868, T_184875)
    node sec_rdy = and(idx_match, T_184876)
    wire T_184877 : UInt<3>[1]
    T_184877[0] := UInt<3>(5)
    node T_184878 = eq(T_184877[0], mem_grant.bits.g_type)
    node T_184879 = or(UInt<1>(0), T_184878)
    node T_184880 = eq(T_184794[0], mem_grant.bits.g_type)
    node T_184881 = eq(T_184794[1], mem_grant.bits.g_type)
    node T_184882 = or(UInt<1>(0), T_184880)
    node T_184883 = or(T_184882, T_184881)
    wire T_184884 : UInt<1>
    T_184884 := T_184883
    when mem_grant.bits.is_builtin_type : T_184884 := T_184879
    node gnt_multi_data = and(UInt<1>(1), T_184884)
    node T_184885 = and(mem_grant.valid, gnt_multi_data)
    reg refill_cnt : UInt<2>
    onreset refill_cnt := UInt<2>(0)
    when T_184885 : 
      node T_184886 = eq(refill_cnt, UInt<2>(3))
      node T_184887 = and(UInt<1>(0), T_184886)
      node T_184888 = addw(refill_cnt, UInt<1>(1))
      wire T_184889 : UInt<2>
      T_184889 := T_184888
      when T_184887 : T_184889 := UInt<1>(0)
      refill_cnt := T_184889
    node refill_count_done = and(T_184885, T_184886)
    node T_184890 = eq(gnt_multi_data, UInt<1>(0))
    node T_184891 = or(T_184890, refill_count_done)
    node refill_done = and(mem_grant.valid, T_184891)
    inst rpq of Queue_138637
    node T_184892 = and(req_pri_val, req_pri_rdy)
    node T_184893 = and(req_sec_val, sec_rdy)
    node T_184894 = or(T_184892, T_184893)
    node T_184895 = eq(req_bits.cmd, UInt<5>(2))
    node T_184896 = eq(req_bits.cmd, UInt<5>(3))
    node T_184897 = or(T_184895, T_184896)
    node T_184898 = eq(T_184897, UInt<1>(0))
    node T_184899 = and(T_184894, T_184898)
    rpq.enq.valid := T_184899
    rpq.enq.bits := req_bits
    node T_184900 = eq(state, UInt<4>(8))
    node T_184901 = and(replay.ready, T_184900)
    node T_184902 = eq(state, UInt<4>(0))
    node T_184903 = or(T_184901, T_184902)
    rpq.deq.ready := T_184903
    node T_184904 = eq(req.cmd, UInt<5>(1))
    node T_184905 = eq(req.cmd, UInt<5>(7))
    node T_184906 = or(T_184904, T_184905)
    node T_184907 = bit(req.cmd, 3)
    node T_184908 = eq(req.cmd, UInt<5>(4))
    node T_184909 = or(T_184907, T_184908)
    node T_184910 = or(T_184906, T_184909)
    wire T_184911 : UInt<2>
    T_184911 := UInt<2>(2)
    when T_184910 : T_184911 := UInt<2>(3)
    node T_184912 = eq(UInt<2>(2), mem_grant.bits.g_type)
    wire T_184913 : UInt<2>
    T_184913 := UInt<2>(0)
    when T_184912 : T_184913 := UInt<2>(3)
    node T_184914 = eq(UInt<2>(1), mem_grant.bits.g_type)
    wire T_184915 : UInt<2>
    T_184915 := T_184913
    when T_184914 : T_184915 := T_184911
    node T_184916 = eq(UInt<2>(0), mem_grant.bits.g_type)
    wire T_184917 : UInt<2>
    T_184917 := T_184915
    when T_184916 : T_184917 := UInt<2>(1)
    wire T_184918 : UInt<2>
    T_184918 := T_184917
    when mem_grant.bits.is_builtin_type : T_184918 := UInt<2>(0)
    wire T_184919 : UInt<3>[3]
    T_184919[0] := UInt<3>(0)
    T_184919[1] := UInt<3>(1)
    T_184919[2] := UInt<3>(2)
    wire T_184920 : UInt<2>[2]
    T_184920[0] := UInt<2>(0)
    T_184920[1] := UInt<2>(1)
    wire T_184921 : UInt<2>[3]
    T_184921[0] := UInt<2>(1)
    T_184921[1] := UInt<2>(2)
    T_184921[2] := UInt<2>(3)
    wire T_184922 : UInt<2>[2]
    T_184922[0] := UInt<2>(2)
    T_184922[1] := UInt<2>(3)
    wire T_184923 : UInt<2>[1]
    T_184923[0] := UInt<2>(3)
    wire T_184924 : UInt<3>[3]
    T_184924[0] := UInt<3>(0)
    T_184924[1] := UInt<3>(1)
    T_184924[2] := UInt<3>(2)
    wire T_184925 : UInt<2>[2]
    T_184925[0] := UInt<2>(0)
    T_184925[1] := UInt<2>(1)
    wire T_184926 : UInt<2>[3]
    T_184926[0] := UInt<2>(1)
    T_184926[1] := UInt<2>(2)
    T_184926[2] := UInt<2>(3)
    wire T_184927 : UInt<2>[2]
    T_184927[0] := UInt<2>(2)
    T_184927[1] := UInt<2>(3)
    wire T_184928 : UInt<2>[1]
    T_184928[0] := UInt<2>(3)
    wire coh_on_grant : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    coh_on_grant.state := T_184918
    node T_184929 = eq(req_bits.cmd, UInt<5>(1))
    node T_184930 = eq(req_bits.cmd, UInt<5>(7))
    node T_184931 = or(T_184929, T_184930)
    node T_184932 = bit(req_bits.cmd, 3)
    node T_184933 = eq(req_bits.cmd, UInt<5>(4))
    node T_184934 = or(T_184932, T_184933)
    node T_184935 = or(T_184931, T_184934)
    wire T_184936 : UInt<2>
    T_184936 := req_bits.old_meta.coh.state
    when T_184935 : T_184936 := UInt<2>(3)
    wire T_184937 : UInt<3>[3]
    T_184937[0] := UInt<3>(0)
    T_184937[1] := UInt<3>(1)
    T_184937[2] := UInt<3>(2)
    wire T_184938 : UInt<2>[2]
    T_184938[0] := UInt<2>(0)
    T_184938[1] := UInt<2>(1)
    wire T_184939 : UInt<2>[3]
    T_184939[0] := UInt<2>(1)
    T_184939[1] := UInt<2>(2)
    T_184939[2] := UInt<2>(3)
    wire T_184940 : UInt<2>[2]
    T_184940[0] := UInt<2>(2)
    T_184940[1] := UInt<2>(3)
    wire T_184941 : UInt<2>[1]
    T_184941[0] := UInt<2>(3)
    wire T_184942 : UInt<3>[3]
    T_184942[0] := UInt<3>(0)
    T_184942[1] := UInt<3>(1)
    T_184942[2] := UInt<3>(2)
    wire T_184943 : UInt<2>[2]
    T_184943[0] := UInt<2>(0)
    T_184943[1] := UInt<2>(1)
    wire T_184944 : UInt<2>[3]
    T_184944[0] := UInt<2>(1)
    T_184944[1] := UInt<2>(2)
    T_184944[2] := UInt<2>(3)
    wire T_184945 : UInt<2>[2]
    T_184945[0] := UInt<2>(2)
    T_184945[1] := UInt<2>(3)
    wire T_184946 : UInt<2>[1]
    T_184946[0] := UInt<2>(3)
    wire coh_on_hit : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    coh_on_hit.state := T_184936
    
    
    node T_184947 = eq(state, UInt<4>(8))
    node T_184948 = eq(rpq.deq.valid, UInt<1>(0))
    node T_184949 = and(T_184947, T_184948)
    when T_184949 : state := UInt<4>(0)
    
    node T_184950 = eq(state, UInt<4>(7))
    when T_184950 : state := UInt<4>(8)
    
    
    node T_184951 = eq(state, UInt<4>(6))
    node T_184952 = and(T_184951, meta_write.ready)
    when T_184952 : state := UInt<4>(7)
    
    node T_184953 = eq(state, UInt<4>(5))
    when T_184953 : 
      when mem_grant.valid : new_coh_state := coh_on_grant
      when refill_done : state := UInt<4>(6)
    
    node T_184954 = and(mem_req.ready, mem_req.valid)
    when T_184954 : state := UInt<4>(5)
    
    
    node T_184955 = eq(state, UInt<4>(3))
    node T_184956 = and(T_184955, meta_write.ready)
    when T_184956 : state := UInt<4>(4)
    
    
    node T_184957 = eq(state, UInt<4>(2))
    node T_184958 = and(T_184957, mem_grant.valid)
    when T_184958 : state := UInt<4>(3)
    
    node T_184959 = and(wb_req.ready, wb_req.valid)
    when T_184959 : 
      node T_184960 = eq(UInt<1>(0), UInt<1>(0))
      wire T_184961 : UInt<4>
      T_184961 := UInt<4>(3)
      when T_184960 : T_184961 := UInt<4>(2)
      state := T_184961
    
    node T_184962 = and(req_sec_val, req_sec_rdy)
    when T_184962 : when cmd_requires_second_acquire : req.cmd := req_bits.cmd
    
    node T_184963 = and(req_pri_val, req_pri_rdy)
    when T_184963 : 
      req := req_bits
      when req_bits.tag_match : 
        
        node T_184967 = eq(req_bits.cmd, UInt<5>(1))
        node T_184968 = eq(req_bits.cmd, UInt<5>(7))
        node T_184969 = or(T_184967, T_184968)
        node T_184970 = bit(req_bits.cmd, 3)
        node T_184971 = eq(req_bits.cmd, UInt<5>(4))
        node T_184972 = or(T_184970, T_184971)
        node T_184973 = or(T_184969, T_184972)
        node T_184974 = eq(req_bits.cmd, UInt<5>(3))
        node T_184975 = or(T_184973, T_184974)
        node T_184976 = eq(req_bits.cmd, UInt<5>(6))
        node T_184977 = or(T_184975, T_184976)
        node T_184978 = eq(T_184761[0], req_bits.old_meta.coh.state)
        node T_184979 = eq(T_184761[1], req_bits.old_meta.coh.state)
        node T_184980 = or(UInt<1>(0), T_184978)
        node T_184981 = or(T_184980, T_184979)
        node T_184982 = eq(T_184760[0], req_bits.old_meta.coh.state)
        node T_184983 = eq(T_184760[1], req_bits.old_meta.coh.state)
        node T_184984 = eq(T_184760[2], req_bits.old_meta.coh.state)
        node T_184985 = or(UInt<1>(0), T_184982)
        node T_184986 = or(T_184985, T_184983)
        node T_184987 = or(T_184986, T_184984)
        wire T_184988 : UInt<1>
        T_184988 := T_184987
        when T_184977 : T_184988 := T_184981
        when T_184988 : 
          state := UInt<4>(6)
          new_coh_state := coh_on_hit
        else : 
          state := UInt<4>(4)
      else : 
        
        node T_184964 = eq(T_184762[0], req_bits.old_meta.coh.state)
        node T_184965 = or(UInt<1>(0), T_184964)
        wire T_184966 : UInt<4>
        T_184966 := UInt<4>(3)
        when T_184965 : T_184966 := UInt<4>(1)
        state := T_184966
    node T_184989 = neq(state, UInt<4>(0))
    node T_184990 = and(T_184989, idx_match)
    idx_match := T_184990
    refill.way_en := req.way_en
    node T_184991 = cat(req_idx, refill_cnt)
    node T_184992 = shl(T_184991, 4)
    refill.addr := T_184992
    node T_184993 = shr(req.addr, 12)
    tag := T_184993
    node T_184994 = eq(state, UInt<4>(0))
    req_pri_rdy := T_184994
    node T_184995 = and(sec_rdy, rpq.enq.ready)
    req_sec_rdy := T_184995
    reg meta_hazard : UInt<2>
    onreset meta_hazard := UInt<2>(0)
    
    node T_184996 = neq(meta_hazard, UInt<1>(0))
    when T_184996 : 
      node T_184997 = addw(meta_hazard, UInt<1>(1))
      meta_hazard := T_184997
    
    node T_184998 = and(meta_write.ready, meta_write.valid)
    when T_184998 : meta_hazard := UInt<1>(1)
    node T_184999 = eq(idx_match, UInt<1>(0))
    node T_185000 = eq(states_before_refill[0], state)
    node T_185001 = eq(states_before_refill[1], state)
    node T_185002 = eq(states_before_refill[2], state)
    node T_185003 = or(UInt<1>(0), T_185000)
    node T_185004 = or(T_185003, T_185001)
    node T_185005 = or(T_185004, T_185002)
    node T_185006 = eq(T_185005, UInt<1>(0))
    node T_185007 = eq(meta_hazard, UInt<1>(0))
    node T_185008 = and(T_185006, T_185007)
    node T_185009 = or(T_184999, T_185008)
    probe_rdy := T_185009
    node T_185010 = eq(state, UInt<4>(6))
    node T_185011 = eq(state, UInt<4>(3))
    node T_185012 = or(T_185010, T_185011)
    meta_write.valid := T_185012
    meta_write.bits.idx := req_idx
    node T_185013 = eq(state, UInt<4>(3))
    node T_185014 = eq(T_184837[0], req.old_meta.coh.state)
    node T_185015 = eq(T_184837[1], req.old_meta.coh.state)
    node T_185016 = or(UInt<1>(0), T_185014)
    node T_185017 = or(T_185016, T_185015)
    wire T_185018 : UInt<2>
    T_185018 := req.old_meta.coh.state
    when T_185017 : T_185018 := UInt<2>(1)
    node T_185019 = eq(req.old_meta.coh.state, UInt<2>(3))
    wire T_185020 : UInt<2>
    T_185020 := req.old_meta.coh.state
    when T_185019 : T_185020 := UInt<2>(2)
    node T_185021 = eq(UInt<5>(19), UInt<5>(16))
    wire T_185022 : UInt<2>
    T_185022 := req.old_meta.coh.state
    when T_185021 : T_185022 := T_185020
    node T_185023 = eq(UInt<5>(17), UInt<5>(16))
    wire T_185024 : UInt<2>
    T_185024 := T_185022
    when T_185023 : T_185024 := T_185018
    node T_185025 = eq(UInt<5>(16), UInt<5>(16))
    wire T_185026 : UInt<2>
    T_185026 := T_185024
    when T_185025 : T_185026 := UInt<2>(0)
    wire T_185027 : UInt<3>[3]
    T_185027[0] := UInt<3>(0)
    T_185027[1] := UInt<3>(1)
    T_185027[2] := UInt<3>(2)
    wire T_185028 : UInt<2>[2]
    T_185028[0] := UInt<2>(0)
    T_185028[1] := UInt<2>(1)
    wire T_185029 : UInt<2>[3]
    T_185029[0] := UInt<2>(1)
    T_185029[1] := UInt<2>(2)
    T_185029[2] := UInt<2>(3)
    wire T_185030 : UInt<2>[2]
    T_185030[0] := UInt<2>(2)
    T_185030[1] := UInt<2>(3)
    wire T_185031 : UInt<2>[1]
    T_185031[0] := UInt<2>(3)
    wire T_185032 : UInt<3>[3]
    T_185032[0] := UInt<3>(0)
    T_185032[1] := UInt<3>(1)
    T_185032[2] := UInt<3>(2)
    wire T_185033 : UInt<2>[2]
    T_185033[0] := UInt<2>(0)
    T_185033[1] := UInt<2>(1)
    wire T_185034 : UInt<2>[3]
    T_185034[0] := UInt<2>(1)
    T_185034[1] := UInt<2>(2)
    T_185034[2] := UInt<2>(3)
    wire T_185035 : UInt<2>[2]
    T_185035[0] := UInt<2>(2)
    T_185035[1] := UInt<2>(3)
    wire T_185036 : UInt<2>[1]
    T_185036[0] := UInt<2>(3)
    wire T_185037 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_185037.state := T_185026
    wire T_185038 : UInt<3>[3]
    T_185038[0] := UInt<3>(0)
    T_185038[1] := UInt<3>(1)
    T_185038[2] := UInt<3>(2)
    wire T_185039 : UInt<2>[2]
    T_185039[0] := UInt<2>(0)
    T_185039[1] := UInt<2>(1)
    wire T_185040 : UInt<2>[3]
    T_185040[0] := UInt<2>(1)
    T_185040[1] := UInt<2>(2)
    T_185040[2] := UInt<2>(3)
    wire T_185041 : UInt<2>[2]
    T_185041[0] := UInt<2>(2)
    T_185041[1] := UInt<2>(3)
    wire T_185042 : UInt<2>[1]
    T_185042[0] := UInt<2>(3)
    wire T_185043 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_185043 := new_coh_state
    when T_185013 : T_185043 := T_185037
    meta_write.bits.data.coh := T_185043
    meta_write.bits.data.tag := tag
    meta_write.bits.way_en := req.way_en
    node T_185044 = eq(state, UInt<4>(1))
    wb_req.valid := T_185044
    node T_185045 = cat(req.old_meta.tag, req_idx)
    node T_185046 = eq(T_184838[0], req.old_meta.coh.state)
    node T_185047 = or(UInt<1>(0), T_185046)
    wire T_185048 : UInt<3>
    T_185048 := UInt<3>(3)
    when T_185047 : T_185048 := UInt<3>(0)
    wire T_185049 : UInt<3>
    T_185049 := UInt<3>(4)
    when T_185047 : T_185049 := UInt<3>(1)
    wire T_185050 : UInt<3>
    T_185050 := UInt<3>(5)
    when T_185047 : T_185050 := UInt<3>(2)
    node T_185051 = eq(UInt<5>(19), UInt<5>(16))
    wire T_185052 : UInt<3>
    T_185052 := UInt<3>(5)
    when T_185051 : T_185052 := T_185050
    node T_185053 = eq(UInt<5>(17), UInt<5>(16))
    wire T_185054 : UInt<3>
    T_185054 := T_185052
    when T_185053 : T_185054 := T_185049
    node T_185055 = eq(UInt<5>(16), UInt<5>(16))
    wire T_185056 : UInt<3>
    T_185056 := T_185054
    when T_185055 : T_185056 := T_185048
    wire T_185057 : UInt<3>[3]
    T_185057[0] := UInt<3>(0)
    T_185057[1] := UInt<3>(1)
    T_185057[2] := UInt<3>(2)
    wire T_185058 : UInt<2>[2]
    T_185058[0] := UInt<2>(0)
    T_185058[1] := UInt<2>(1)
    wire T_185059 : UInt<2>[3]
    T_185059[0] := UInt<2>(1)
    T_185059[1] := UInt<2>(2)
    T_185059[2] := UInt<2>(3)
    wire T_185060 : UInt<2>[2]
    T_185060[0] := UInt<2>(2)
    T_185060[1] := UInt<2>(3)
    wire T_185061 : UInt<2>[1]
    T_185061[0] := UInt<2>(3)
    wire T_185062 : UInt<3>[3]
    T_185062[0] := UInt<3>(0)
    T_185062[1] := UInt<3>(1)
    T_185062[2] := UInt<3>(2)
    wire T_185063 : UInt<2>[2]
    T_185063[0] := UInt<2>(0)
    T_185063[1] := UInt<2>(1)
    wire T_185064 : UInt<2>[3]
    T_185064[0] := UInt<2>(1)
    T_185064[1] := UInt<2>(2)
    T_185064[2] := UInt<2>(3)
    wire T_185065 : UInt<2>[2]
    T_185065[0] := UInt<2>(2)
    T_185065[1] := UInt<2>(3)
    wire T_185066 : UInt<2>[1]
    T_185066[0] := UInt<2>(3)
    wire T_185067 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}
    T_185067.r_type := T_185056
    T_185067.client_xact_id := UInt<1>(0)
    T_185067.addr_block := T_185045
    T_185067.addr_beat := UInt<1>(0)
    T_185067.data := UInt<1>(0)
    T_185067.voluntary := UInt<1>(1)
    wb_req.bits := T_185067
    wb_req.bits.way_en := req.way_en
    node T_185068 = eq(state, UInt<4>(4))
    mem_req.valid := T_185068
    node T_185069 = cat(tag, req_idx)
    node T_185070 = eq(req.cmd, UInt<5>(1))
    node T_185071 = eq(req.cmd, UInt<5>(7))
    node T_185072 = or(T_185070, T_185071)
    node T_185073 = bit(req.cmd, 3)
    node T_185074 = eq(req.cmd, UInt<5>(4))
    node T_185075 = or(T_185073, T_185074)
    node T_185076 = or(T_185072, T_185075)
    node T_185077 = eq(req.cmd, UInt<5>(3))
    node T_185078 = or(T_185076, T_185077)
    node T_185079 = eq(req.cmd, UInt<5>(6))
    node T_185080 = or(T_185078, T_185079)
    wire T_185081 : UInt<1>
    T_185081 := UInt<1>(0)
    when T_185080 : T_185081 := UInt<1>(1)
    node T_185082 = cat(req.cmd, UInt<1>(1))
    wire T_185083 : UInt<3>[3]
    T_185083[0] := UInt<3>(0)
    T_185083[1] := UInt<3>(1)
    T_185083[2] := UInt<3>(2)
    wire T_185084 : UInt<2>[2]
    T_185084[0] := UInt<2>(0)
    T_185084[1] := UInt<2>(1)
    wire T_185085 : UInt<2>[3]
    T_185085[0] := UInt<2>(1)
    T_185085[1] := UInt<2>(2)
    T_185085[2] := UInt<2>(3)
    wire T_185086 : UInt<2>[2]
    T_185086[0] := UInt<2>(2)
    T_185086[1] := UInt<2>(3)
    wire T_185087 : UInt<2>[1]
    T_185087[0] := UInt<2>(3)
    wire T_185088 : UInt<3>[3]
    T_185088[0] := UInt<3>(0)
    T_185088[1] := UInt<3>(1)
    T_185088[2] := UInt<3>(2)
    wire T_185089 : UInt<2>[2]
    T_185089[0] := UInt<2>(0)
    T_185089[1] := UInt<2>(1)
    wire T_185090 : UInt<2>[3]
    T_185090[0] := UInt<2>(1)
    T_185090[1] := UInt<2>(2)
    T_185090[2] := UInt<2>(3)
    wire T_185091 : UInt<2>[2]
    T_185091[0] := UInt<2>(2)
    T_185091[1] := UInt<2>(3)
    wire T_185092 : UInt<2>[1]
    T_185092[0] := UInt<2>(3)
    wire T_185093 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_185093.is_builtin_type := UInt<1>(0)
    T_185093.a_type := T_185081
    T_185093.client_xact_id := UInt<1>(0)
    T_185093.addr_block := T_185069
    T_185093.addr_beat := UInt<1>(0)
    T_185093.data := UInt<1>(0)
    T_185093.union := T_185082
    mem_req.bits := T_185093
    node T_185094 = eq(state, UInt<4>(8))
    meta_read.valid := T_185094
    meta_read.bits.idx := req_idx
    meta_read.bits.tag := tag
    node T_185095 = eq(state, UInt<4>(8))
    node T_185096 = and(T_185095, rpq.deq.valid)
    replay.valid := T_185096
    replay.bits := rpq.deq.bits
    replay.bits.phys := UInt<1>(1)
    node T_185097 = bits(rpq.deq.bits.addr, 5, 0)
    node T_185098 = cat(req_idx, T_185097)
    node T_185099 = cat(tag, T_185098)
    replay.bits.addr := T_185099
    
    node T_185100 = eq(meta_read.ready, UInt<1>(0))
    when T_185100 : 
      rpq.deq.ready := UInt<1>(0)
      replay.bits.cmd := UInt<5>(5)
  module Queue_140921 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    output count : UInt<5>
    
    cmem ram : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16]
    reg T_185101 : UInt<4>
    onreset T_185101 := UInt<4>(0)
    reg T_185102 : UInt<4>
    onreset T_185102 := UInt<4>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_185101, T_185102)
    node T_185103 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_185103)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_185104 = and(enq.ready, enq.valid)
    node T_185105 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_185104, T_185105)
    node T_185106 = and(deq.ready, deq.valid)
    node T_185107 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_185106, T_185107)
    when do_enq : 
      accessor T_185108 = ram[T_185101]
      T_185108 := enq.bits
      node T_185109 = eq(T_185101, UInt<4>(15))
      node T_185110 = and(UInt<1>(0), T_185109)
      node T_185111 = addw(T_185101, UInt<1>(1))
      wire T_185112 : UInt<4>
      T_185112 := T_185111
      when T_185110 : T_185112 := UInt<1>(0)
      T_185101 := T_185112
    when do_deq : 
      node T_185113 = eq(T_185102, UInt<4>(15))
      node T_185114 = and(UInt<1>(0), T_185113)
      node T_185115 = addw(T_185102, UInt<1>(1))
      wire T_185116 : UInt<4>
      T_185116 := T_185115
      when T_185114 : T_185116 := UInt<1>(0)
      T_185102 := T_185116
    
    node T_185117 = neq(do_enq, do_deq)
    when T_185117 : maybe_full := do_enq
    node T_185118 = eq(empty, UInt<1>(0))
    node T_185119 = and(UInt<1>(0), enq.valid)
    node T_185120 = or(T_185118, T_185119)
    deq.valid := T_185120
    node T_185121 = eq(full, UInt<1>(0))
    node T_185122 = and(UInt<1>(0), deq.ready)
    node T_185123 = or(T_185121, T_185122)
    enq.ready := T_185123
    accessor T_185124 = ram[T_185102]
    wire T_185125 : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}
    T_185125 := T_185124
    when maybe_flow : T_185125 := enq.bits
    deq.bits := T_185125
    node ptr_diff = subw(T_185101, T_185102)
    node T_185126 = and(maybe_full, ptr_match)
    node T_185127 = cat(T_185126, ptr_diff)
    count := T_185127
  module MSHR_141857 : 
    input req_pri_val : UInt<1>
    output req_pri_rdy : UInt<1>
    input req_sec_val : UInt<1>
    output req_sec_rdy : UInt<1>
    input req_bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, way_en : UInt<4>}
    output idx_match : UInt<1>
    output tag : UInt<20>
    output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    output refill : {way_en : UInt<4>, addr : UInt<12>}
    output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}
    output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}
    input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    output probe_rdy : UInt<1>
    
    wire T_185128 : UInt<3>[3]
    T_185128[0] := UInt<3>(0)
    T_185128[1] := UInt<3>(1)
    T_185128[2] := UInt<3>(2)
    wire T_185129 : UInt<2>[2]
    T_185129[0] := UInt<2>(0)
    T_185129[1] := UInt<2>(1)
    wire T_185130 : UInt<2>[3]
    T_185130[0] := UInt<2>(1)
    T_185130[1] := UInt<2>(2)
    T_185130[2] := UInt<2>(3)
    wire T_185131 : UInt<2>[2]
    T_185131[0] := UInt<2>(2)
    T_185131[1] := UInt<2>(3)
    wire T_185132 : UInt<2>[1]
    T_185132[0] := UInt<2>(3)
    wire T_185133 : UInt<3>[3]
    T_185133[0] := UInt<3>(0)
    T_185133[1] := UInt<3>(1)
    T_185133[2] := UInt<3>(2)
    wire T_185134 : UInt<2>[2]
    T_185134[0] := UInt<2>(0)
    T_185134[1] := UInt<2>(1)
    wire T_185135 : UInt<2>[3]
    T_185135[0] := UInt<2>(1)
    T_185135[1] := UInt<2>(2)
    T_185135[2] := UInt<2>(3)
    wire T_185136 : UInt<2>[2]
    T_185136[0] := UInt<2>(2)
    T_185136[1] := UInt<2>(3)
    wire T_185137 : UInt<2>[1]
    T_185137[0] := UInt<2>(3)
    wire T_185138 : UInt<3>[3]
    T_185138[0] := UInt<3>(0)
    T_185138[1] := UInt<3>(1)
    T_185138[2] := UInt<3>(2)
    wire T_185139 : UInt<2>[2]
    T_185139[0] := UInt<2>(0)
    T_185139[1] := UInt<2>(1)
    wire T_185140 : UInt<2>[3]
    T_185140[0] := UInt<2>(1)
    T_185140[1] := UInt<2>(2)
    T_185140[2] := UInt<2>(3)
    wire T_185141 : UInt<2>[2]
    T_185141[0] := UInt<2>(2)
    T_185141[1] := UInt<2>(3)
    wire T_185142 : UInt<2>[1]
    T_185142[0] := UInt<2>(3)
    wire T_185143 : UInt<3>[3]
    T_185143[0] := UInt<3>(0)
    T_185143[1] := UInt<3>(1)
    T_185143[2] := UInt<3>(2)
    wire T_185144 : UInt<2>[2]
    T_185144[0] := UInt<2>(0)
    T_185144[1] := UInt<2>(1)
    wire T_185145 : UInt<2>[3]
    T_185145[0] := UInt<2>(1)
    T_185145[1] := UInt<2>(2)
    T_185145[2] := UInt<2>(3)
    wire T_185146 : UInt<2>[2]
    T_185146[0] := UInt<2>(2)
    T_185146[1] := UInt<2>(3)
    wire T_185147 : UInt<2>[1]
    T_185147[0] := UInt<2>(3)
    wire T_185148 : UInt<3>[3]
    T_185148[0] := UInt<3>(0)
    T_185148[1] := UInt<3>(1)
    T_185148[2] := UInt<3>(2)
    wire T_185149 : UInt<2>[2]
    T_185149[0] := UInt<2>(0)
    T_185149[1] := UInt<2>(1)
    wire T_185150 : UInt<2>[3]
    T_185150[0] := UInt<2>(1)
    T_185150[1] := UInt<2>(2)
    T_185150[2] := UInt<2>(3)
    wire T_185151 : UInt<2>[2]
    T_185151[0] := UInt<2>(2)
    T_185151[1] := UInt<2>(3)
    wire T_185152 : UInt<2>[1]
    T_185152[0] := UInt<2>(3)
    wire T_185153 : UInt<3>[3]
    T_185153[0] := UInt<3>(0)
    T_185153[1] := UInt<3>(1)
    T_185153[2] := UInt<3>(2)
    wire T_185154 : UInt<2>[2]
    T_185154[0] := UInt<2>(0)
    T_185154[1] := UInt<2>(1)
    wire T_185155 : UInt<2>[3]
    T_185155[0] := UInt<2>(1)
    T_185155[1] := UInt<2>(2)
    T_185155[2] := UInt<2>(3)
    wire T_185156 : UInt<2>[2]
    T_185156[0] := UInt<2>(2)
    T_185156[1] := UInt<2>(3)
    wire T_185157 : UInt<2>[1]
    T_185157[0] := UInt<2>(3)
    wire T_185158 : UInt<3>[3]
    T_185158[0] := UInt<3>(0)
    T_185158[1] := UInt<3>(1)
    T_185158[2] := UInt<3>(2)
    wire T_185159 : UInt<2>[2]
    T_185159[0] := UInt<2>(0)
    T_185159[1] := UInt<2>(1)
    wire T_185160 : UInt<2>[3]
    T_185160[0] := UInt<2>(1)
    T_185160[1] := UInt<2>(2)
    T_185160[2] := UInt<2>(3)
    wire T_185161 : UInt<2>[2]
    T_185161[0] := UInt<2>(2)
    T_185161[1] := UInt<2>(3)
    wire T_185162 : UInt<2>[1]
    T_185162[0] := UInt<2>(3)
    wire T_185163 : UInt<3>[3]
    T_185163[0] := UInt<3>(0)
    T_185163[1] := UInt<3>(1)
    T_185163[2] := UInt<3>(2)
    wire T_185164 : UInt<2>[2]
    T_185164[0] := UInt<2>(0)
    T_185164[1] := UInt<2>(1)
    wire T_185165 : UInt<2>[3]
    T_185165[0] := UInt<2>(1)
    T_185165[1] := UInt<2>(2)
    T_185165[2] := UInt<2>(3)
    wire T_185166 : UInt<2>[2]
    T_185166[0] := UInt<2>(2)
    T_185166[1] := UInt<2>(3)
    wire T_185167 : UInt<2>[1]
    T_185167[0] := UInt<2>(3)
    wire T_185168 : UInt<3>[3]
    T_185168[0] := UInt<3>(0)
    T_185168[1] := UInt<3>(1)
    T_185168[2] := UInt<3>(2)
    wire T_185169 : UInt<2>[2]
    T_185169[0] := UInt<2>(0)
    T_185169[1] := UInt<2>(1)
    wire T_185170 : UInt<2>[3]
    T_185170[0] := UInt<2>(1)
    T_185170[1] := UInt<2>(2)
    T_185170[2] := UInt<2>(3)
    wire T_185171 : UInt<2>[2]
    T_185171[0] := UInt<2>(2)
    T_185171[1] := UInt<2>(3)
    wire T_185172 : UInt<2>[1]
    T_185172[0] := UInt<2>(3)
    wire T_185173 : UInt<3>[3]
    T_185173[0] := UInt<3>(0)
    T_185173[1] := UInt<3>(1)
    T_185173[2] := UInt<3>(2)
    wire T_185174 : UInt<2>[2]
    T_185174[0] := UInt<2>(0)
    T_185174[1] := UInt<2>(1)
    wire T_185175 : UInt<2>[3]
    T_185175[0] := UInt<2>(1)
    T_185175[1] := UInt<2>(2)
    T_185175[2] := UInt<2>(3)
    wire T_185176 : UInt<2>[2]
    T_185176[0] := UInt<2>(2)
    T_185176[1] := UInt<2>(3)
    wire T_185177 : UInt<2>[1]
    T_185177[0] := UInt<2>(3)
    reg state : UInt<4>
    onreset state := UInt<4>(0)
    wire T_185178 : UInt<3>[3]
    T_185178[0] := UInt<3>(0)
    T_185178[1] := UInt<3>(1)
    T_185178[2] := UInt<3>(2)
    wire T_185179 : UInt<2>[2]
    T_185179[0] := UInt<2>(0)
    T_185179[1] := UInt<2>(1)
    wire T_185180 : UInt<2>[3]
    T_185180[0] := UInt<2>(1)
    T_185180[1] := UInt<2>(2)
    T_185180[2] := UInt<2>(3)
    wire T_185181 : UInt<2>[2]
    T_185181[0] := UInt<2>(2)
    T_185181[1] := UInt<2>(3)
    wire T_185182 : UInt<2>[1]
    T_185182[0] := UInt<2>(3)
    wire T_185183 : UInt<3>[3]
    T_185183[0] := UInt<3>(0)
    T_185183[1] := UInt<3>(1)
    T_185183[2] := UInt<3>(2)
    wire T_185184 : UInt<2>[2]
    T_185184[0] := UInt<2>(0)
    T_185184[1] := UInt<2>(1)
    wire T_185185 : UInt<2>[3]
    T_185185[0] := UInt<2>(1)
    T_185185[1] := UInt<2>(2)
    T_185185[2] := UInt<2>(3)
    wire T_185186 : UInt<2>[2]
    T_185186[0] := UInt<2>(2)
    T_185186[1] := UInt<2>(3)
    wire T_185187 : UInt<2>[1]
    T_185187[0] := UInt<2>(3)
    wire T_185188 : UInt<3>[3]
    T_185188[0] := UInt<3>(0)
    T_185188[1] := UInt<3>(1)
    T_185188[2] := UInt<3>(2)
    wire T_185189 : UInt<2>[2]
    T_185189[0] := UInt<2>(0)
    T_185189[1] := UInt<2>(1)
    wire T_185190 : UInt<2>[3]
    T_185190[0] := UInt<2>(1)
    T_185190[1] := UInt<2>(2)
    T_185190[2] := UInt<2>(3)
    wire T_185191 : UInt<2>[2]
    T_185191[0] := UInt<2>(2)
    T_185191[1] := UInt<2>(3)
    wire T_185192 : UInt<2>[1]
    T_185192[0] := UInt<2>(3)
    wire T_185193 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_185193.state := UInt<2>(0)
    wire T_185194 : UInt<3>[3]
    T_185194[0] := UInt<3>(0)
    T_185194[1] := UInt<3>(1)
    T_185194[2] := UInt<3>(2)
    wire T_185195 : UInt<2>[2]
    T_185195[0] := UInt<2>(0)
    T_185195[1] := UInt<2>(1)
    wire T_185196 : UInt<2>[3]
    T_185196[0] := UInt<2>(1)
    T_185196[1] := UInt<2>(2)
    T_185196[2] := UInt<2>(3)
    wire T_185197 : UInt<2>[2]
    T_185197[0] := UInt<2>(2)
    T_185197[1] := UInt<2>(3)
    wire T_185198 : UInt<2>[1]
    T_185198[0] := UInt<2>(3)
    reg new_coh_state : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    onreset new_coh_state := T_185193
    wire T_185199 : UInt<3>[3]
    T_185199[0] := UInt<3>(0)
    T_185199[1] := UInt<3>(1)
    T_185199[2] := UInt<3>(2)
    wire T_185200 : UInt<2>[2]
    T_185200[0] := UInt<2>(0)
    T_185200[1] := UInt<2>(1)
    wire T_185201 : UInt<2>[3]
    T_185201[0] := UInt<2>(1)
    T_185201[1] := UInt<2>(2)
    T_185201[2] := UInt<2>(3)
    wire T_185202 : UInt<2>[2]
    T_185202[0] := UInt<2>(2)
    T_185202[1] := UInt<2>(3)
    wire T_185203 : UInt<2>[1]
    T_185203[0] := UInt<2>(3)
    wire T_185204 : UInt<3>[3]
    T_185204[0] := UInt<3>(0)
    T_185204[1] := UInt<3>(1)
    T_185204[2] := UInt<3>(2)
    wire T_185205 : UInt<2>[2]
    T_185205[0] := UInt<2>(0)
    T_185205[1] := UInt<2>(1)
    wire T_185206 : UInt<2>[3]
    T_185206[0] := UInt<2>(1)
    T_185206[1] := UInt<2>(2)
    T_185206[2] := UInt<2>(3)
    wire T_185207 : UInt<2>[2]
    T_185207[0] := UInt<2>(2)
    T_185207[1] := UInt<2>(3)
    wire T_185208 : UInt<2>[1]
    T_185208[0] := UInt<2>(3)
    reg req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, way_en : UInt<4>}
    node req_idx = bits(req.addr, 11, 6)
    node T_185209 = bits(req_bits.addr, 11, 6)
    node idx_match = eq(req_idx, T_185209)
    node T_185210 = eq(req_bits.cmd, UInt<5>(1))
    node T_185211 = eq(req_bits.cmd, UInt<5>(7))
    node T_185212 = or(T_185210, T_185211)
    node T_185213 = bit(req_bits.cmd, 3)
    node T_185214 = eq(req_bits.cmd, UInt<5>(4))
    node T_185215 = or(T_185213, T_185214)
    node T_185216 = or(T_185212, T_185215)
    node T_185217 = eq(req_bits.cmd, UInt<5>(3))
    node T_185218 = or(T_185216, T_185217)
    node T_185219 = eq(req_bits.cmd, UInt<5>(6))
    node T_185220 = or(T_185218, T_185219)
    node T_185221 = eq(req.cmd, UInt<5>(1))
    node T_185222 = eq(req.cmd, UInt<5>(7))
    node T_185223 = or(T_185221, T_185222)
    node T_185224 = bit(req.cmd, 3)
    node T_185225 = eq(req.cmd, UInt<5>(4))
    node T_185226 = or(T_185224, T_185225)
    node T_185227 = or(T_185223, T_185226)
    node T_185228 = eq(req.cmd, UInt<5>(3))
    node T_185229 = or(T_185227, T_185228)
    node T_185230 = eq(req.cmd, UInt<5>(6))
    node T_185231 = or(T_185229, T_185230)
    node T_185232 = eq(T_185231, UInt<1>(0))
    node cmd_requires_second_acquire = and(T_185220, T_185232)
    wire states_before_refill : UInt<4>[3]
    states_before_refill[0] := UInt<4>(1)
    states_before_refill[1] := UInt<4>(2)
    states_before_refill[2] := UInt<4>(3)
    node T_185233 = eq(states_before_refill[0], state)
    node T_185234 = eq(states_before_refill[1], state)
    node T_185235 = eq(states_before_refill[2], state)
    node T_185236 = or(UInt<1>(0), T_185233)
    node T_185237 = or(T_185236, T_185234)
    node T_185238 = or(T_185237, T_185235)
    wire T_185239 : UInt<4>[2]
    T_185239[0] := UInt<4>(4)
    T_185239[1] := UInt<4>(5)
    node T_185240 = eq(T_185239[0], state)
    node T_185241 = eq(T_185239[1], state)
    node T_185242 = or(UInt<1>(0), T_185240)
    node T_185243 = or(T_185242, T_185241)
    node T_185244 = eq(cmd_requires_second_acquire, UInt<1>(0))
    node T_185245 = and(T_185243, T_185244)
    node T_185246 = or(T_185238, T_185245)
    node sec_rdy = and(idx_match, T_185246)
    wire T_185247 : UInt<3>[1]
    T_185247[0] := UInt<3>(5)
    node T_185248 = eq(T_185247[0], mem_grant.bits.g_type)
    node T_185249 = or(UInt<1>(0), T_185248)
    node T_185250 = eq(T_185164[0], mem_grant.bits.g_type)
    node T_185251 = eq(T_185164[1], mem_grant.bits.g_type)
    node T_185252 = or(UInt<1>(0), T_185250)
    node T_185253 = or(T_185252, T_185251)
    wire T_185254 : UInt<1>
    T_185254 := T_185253
    when mem_grant.bits.is_builtin_type : T_185254 := T_185249
    node gnt_multi_data = and(UInt<1>(1), T_185254)
    node T_185255 = and(mem_grant.valid, gnt_multi_data)
    reg refill_cnt : UInt<2>
    onreset refill_cnt := UInt<2>(0)
    when T_185255 : 
      node T_185256 = eq(refill_cnt, UInt<2>(3))
      node T_185257 = and(UInt<1>(0), T_185256)
      node T_185258 = addw(refill_cnt, UInt<1>(1))
      wire T_185259 : UInt<2>
      T_185259 := T_185258
      when T_185257 : T_185259 := UInt<1>(0)
      refill_cnt := T_185259
    node refill_count_done = and(T_185255, T_185256)
    node T_185260 = eq(gnt_multi_data, UInt<1>(0))
    node T_185261 = or(T_185260, refill_count_done)
    node refill_done = and(mem_grant.valid, T_185261)
    inst rpq of Queue_140921
    node T_185262 = and(req_pri_val, req_pri_rdy)
    node T_185263 = and(req_sec_val, sec_rdy)
    node T_185264 = or(T_185262, T_185263)
    node T_185265 = eq(req_bits.cmd, UInt<5>(2))
    node T_185266 = eq(req_bits.cmd, UInt<5>(3))
    node T_185267 = or(T_185265, T_185266)
    node T_185268 = eq(T_185267, UInt<1>(0))
    node T_185269 = and(T_185264, T_185268)
    rpq.enq.valid := T_185269
    rpq.enq.bits := req_bits
    node T_185270 = eq(state, UInt<4>(8))
    node T_185271 = and(replay.ready, T_185270)
    node T_185272 = eq(state, UInt<4>(0))
    node T_185273 = or(T_185271, T_185272)
    rpq.deq.ready := T_185273
    node T_185274 = eq(req.cmd, UInt<5>(1))
    node T_185275 = eq(req.cmd, UInt<5>(7))
    node T_185276 = or(T_185274, T_185275)
    node T_185277 = bit(req.cmd, 3)
    node T_185278 = eq(req.cmd, UInt<5>(4))
    node T_185279 = or(T_185277, T_185278)
    node T_185280 = or(T_185276, T_185279)
    wire T_185281 : UInt<2>
    T_185281 := UInt<2>(2)
    when T_185280 : T_185281 := UInt<2>(3)
    node T_185282 = eq(UInt<2>(2), mem_grant.bits.g_type)
    wire T_185283 : UInt<2>
    T_185283 := UInt<2>(0)
    when T_185282 : T_185283 := UInt<2>(3)
    node T_185284 = eq(UInt<2>(1), mem_grant.bits.g_type)
    wire T_185285 : UInt<2>
    T_185285 := T_185283
    when T_185284 : T_185285 := T_185281
    node T_185286 = eq(UInt<2>(0), mem_grant.bits.g_type)
    wire T_185287 : UInt<2>
    T_185287 := T_185285
    when T_185286 : T_185287 := UInt<2>(1)
    wire T_185288 : UInt<2>
    T_185288 := T_185287
    when mem_grant.bits.is_builtin_type : T_185288 := UInt<2>(0)
    wire T_185289 : UInt<3>[3]
    T_185289[0] := UInt<3>(0)
    T_185289[1] := UInt<3>(1)
    T_185289[2] := UInt<3>(2)
    wire T_185290 : UInt<2>[2]
    T_185290[0] := UInt<2>(0)
    T_185290[1] := UInt<2>(1)
    wire T_185291 : UInt<2>[3]
    T_185291[0] := UInt<2>(1)
    T_185291[1] := UInt<2>(2)
    T_185291[2] := UInt<2>(3)
    wire T_185292 : UInt<2>[2]
    T_185292[0] := UInt<2>(2)
    T_185292[1] := UInt<2>(3)
    wire T_185293 : UInt<2>[1]
    T_185293[0] := UInt<2>(3)
    wire T_185294 : UInt<3>[3]
    T_185294[0] := UInt<3>(0)
    T_185294[1] := UInt<3>(1)
    T_185294[2] := UInt<3>(2)
    wire T_185295 : UInt<2>[2]
    T_185295[0] := UInt<2>(0)
    T_185295[1] := UInt<2>(1)
    wire T_185296 : UInt<2>[3]
    T_185296[0] := UInt<2>(1)
    T_185296[1] := UInt<2>(2)
    T_185296[2] := UInt<2>(3)
    wire T_185297 : UInt<2>[2]
    T_185297[0] := UInt<2>(2)
    T_185297[1] := UInt<2>(3)
    wire T_185298 : UInt<2>[1]
    T_185298[0] := UInt<2>(3)
    wire coh_on_grant : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    coh_on_grant.state := T_185288
    node T_185299 = eq(req_bits.cmd, UInt<5>(1))
    node T_185300 = eq(req_bits.cmd, UInt<5>(7))
    node T_185301 = or(T_185299, T_185300)
    node T_185302 = bit(req_bits.cmd, 3)
    node T_185303 = eq(req_bits.cmd, UInt<5>(4))
    node T_185304 = or(T_185302, T_185303)
    node T_185305 = or(T_185301, T_185304)
    wire T_185306 : UInt<2>
    T_185306 := req_bits.old_meta.coh.state
    when T_185305 : T_185306 := UInt<2>(3)
    wire T_185307 : UInt<3>[3]
    T_185307[0] := UInt<3>(0)
    T_185307[1] := UInt<3>(1)
    T_185307[2] := UInt<3>(2)
    wire T_185308 : UInt<2>[2]
    T_185308[0] := UInt<2>(0)
    T_185308[1] := UInt<2>(1)
    wire T_185309 : UInt<2>[3]
    T_185309[0] := UInt<2>(1)
    T_185309[1] := UInt<2>(2)
    T_185309[2] := UInt<2>(3)
    wire T_185310 : UInt<2>[2]
    T_185310[0] := UInt<2>(2)
    T_185310[1] := UInt<2>(3)
    wire T_185311 : UInt<2>[1]
    T_185311[0] := UInt<2>(3)
    wire T_185312 : UInt<3>[3]
    T_185312[0] := UInt<3>(0)
    T_185312[1] := UInt<3>(1)
    T_185312[2] := UInt<3>(2)
    wire T_185313 : UInt<2>[2]
    T_185313[0] := UInt<2>(0)
    T_185313[1] := UInt<2>(1)
    wire T_185314 : UInt<2>[3]
    T_185314[0] := UInt<2>(1)
    T_185314[1] := UInt<2>(2)
    T_185314[2] := UInt<2>(3)
    wire T_185315 : UInt<2>[2]
    T_185315[0] := UInt<2>(2)
    T_185315[1] := UInt<2>(3)
    wire T_185316 : UInt<2>[1]
    T_185316[0] := UInt<2>(3)
    wire coh_on_hit : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    coh_on_hit.state := T_185306
    
    
    node T_185317 = eq(state, UInt<4>(8))
    node T_185318 = eq(rpq.deq.valid, UInt<1>(0))
    node T_185319 = and(T_185317, T_185318)
    when T_185319 : state := UInt<4>(0)
    
    node T_185320 = eq(state, UInt<4>(7))
    when T_185320 : state := UInt<4>(8)
    
    
    node T_185321 = eq(state, UInt<4>(6))
    node T_185322 = and(T_185321, meta_write.ready)
    when T_185322 : state := UInt<4>(7)
    
    node T_185323 = eq(state, UInt<4>(5))
    when T_185323 : 
      when mem_grant.valid : new_coh_state := coh_on_grant
      when refill_done : state := UInt<4>(6)
    
    node T_185324 = and(mem_req.ready, mem_req.valid)
    when T_185324 : state := UInt<4>(5)
    
    
    node T_185325 = eq(state, UInt<4>(3))
    node T_185326 = and(T_185325, meta_write.ready)
    when T_185326 : state := UInt<4>(4)
    
    
    node T_185327 = eq(state, UInt<4>(2))
    node T_185328 = and(T_185327, mem_grant.valid)
    when T_185328 : state := UInt<4>(3)
    
    node T_185329 = and(wb_req.ready, wb_req.valid)
    when T_185329 : 
      node T_185330 = eq(UInt<1>(0), UInt<1>(0))
      wire T_185331 : UInt<4>
      T_185331 := UInt<4>(3)
      when T_185330 : T_185331 := UInt<4>(2)
      state := T_185331
    
    node T_185332 = and(req_sec_val, req_sec_rdy)
    when T_185332 : when cmd_requires_second_acquire : req.cmd := req_bits.cmd
    
    node T_185333 = and(req_pri_val, req_pri_rdy)
    when T_185333 : 
      req := req_bits
      when req_bits.tag_match : 
        
        node T_185337 = eq(req_bits.cmd, UInt<5>(1))
        node T_185338 = eq(req_bits.cmd, UInt<5>(7))
        node T_185339 = or(T_185337, T_185338)
        node T_185340 = bit(req_bits.cmd, 3)
        node T_185341 = eq(req_bits.cmd, UInt<5>(4))
        node T_185342 = or(T_185340, T_185341)
        node T_185343 = or(T_185339, T_185342)
        node T_185344 = eq(req_bits.cmd, UInt<5>(3))
        node T_185345 = or(T_185343, T_185344)
        node T_185346 = eq(req_bits.cmd, UInt<5>(6))
        node T_185347 = or(T_185345, T_185346)
        node T_185348 = eq(T_185131[0], req_bits.old_meta.coh.state)
        node T_185349 = eq(T_185131[1], req_bits.old_meta.coh.state)
        node T_185350 = or(UInt<1>(0), T_185348)
        node T_185351 = or(T_185350, T_185349)
        node T_185352 = eq(T_185130[0], req_bits.old_meta.coh.state)
        node T_185353 = eq(T_185130[1], req_bits.old_meta.coh.state)
        node T_185354 = eq(T_185130[2], req_bits.old_meta.coh.state)
        node T_185355 = or(UInt<1>(0), T_185352)
        node T_185356 = or(T_185355, T_185353)
        node T_185357 = or(T_185356, T_185354)
        wire T_185358 : UInt<1>
        T_185358 := T_185357
        when T_185347 : T_185358 := T_185351
        when T_185358 : 
          state := UInt<4>(6)
          new_coh_state := coh_on_hit
        else : 
          state := UInt<4>(4)
      else : 
        
        node T_185334 = eq(T_185132[0], req_bits.old_meta.coh.state)
        node T_185335 = or(UInt<1>(0), T_185334)
        wire T_185336 : UInt<4>
        T_185336 := UInt<4>(3)
        when T_185335 : T_185336 := UInt<4>(1)
        state := T_185336
    node T_185359 = neq(state, UInt<4>(0))
    node T_185360 = and(T_185359, idx_match)
    idx_match := T_185360
    refill.way_en := req.way_en
    node T_185361 = cat(req_idx, refill_cnt)
    node T_185362 = shl(T_185361, 4)
    refill.addr := T_185362
    node T_185363 = shr(req.addr, 12)
    tag := T_185363
    node T_185364 = eq(state, UInt<4>(0))
    req_pri_rdy := T_185364
    node T_185365 = and(sec_rdy, rpq.enq.ready)
    req_sec_rdy := T_185365
    reg meta_hazard : UInt<2>
    onreset meta_hazard := UInt<2>(0)
    
    node T_185366 = neq(meta_hazard, UInt<1>(0))
    when T_185366 : 
      node T_185367 = addw(meta_hazard, UInt<1>(1))
      meta_hazard := T_185367
    
    node T_185368 = and(meta_write.ready, meta_write.valid)
    when T_185368 : meta_hazard := UInt<1>(1)
    node T_185369 = eq(idx_match, UInt<1>(0))
    node T_185370 = eq(states_before_refill[0], state)
    node T_185371 = eq(states_before_refill[1], state)
    node T_185372 = eq(states_before_refill[2], state)
    node T_185373 = or(UInt<1>(0), T_185370)
    node T_185374 = or(T_185373, T_185371)
    node T_185375 = or(T_185374, T_185372)
    node T_185376 = eq(T_185375, UInt<1>(0))
    node T_185377 = eq(meta_hazard, UInt<1>(0))
    node T_185378 = and(T_185376, T_185377)
    node T_185379 = or(T_185369, T_185378)
    probe_rdy := T_185379
    node T_185380 = eq(state, UInt<4>(6))
    node T_185381 = eq(state, UInt<4>(3))
    node T_185382 = or(T_185380, T_185381)
    meta_write.valid := T_185382
    meta_write.bits.idx := req_idx
    node T_185383 = eq(state, UInt<4>(3))
    node T_185384 = eq(T_185207[0], req.old_meta.coh.state)
    node T_185385 = eq(T_185207[1], req.old_meta.coh.state)
    node T_185386 = or(UInt<1>(0), T_185384)
    node T_185387 = or(T_185386, T_185385)
    wire T_185388 : UInt<2>
    T_185388 := req.old_meta.coh.state
    when T_185387 : T_185388 := UInt<2>(1)
    node T_185389 = eq(req.old_meta.coh.state, UInt<2>(3))
    wire T_185390 : UInt<2>
    T_185390 := req.old_meta.coh.state
    when T_185389 : T_185390 := UInt<2>(2)
    node T_185391 = eq(UInt<5>(19), UInt<5>(16))
    wire T_185392 : UInt<2>
    T_185392 := req.old_meta.coh.state
    when T_185391 : T_185392 := T_185390
    node T_185393 = eq(UInt<5>(17), UInt<5>(16))
    wire T_185394 : UInt<2>
    T_185394 := T_185392
    when T_185393 : T_185394 := T_185388
    node T_185395 = eq(UInt<5>(16), UInt<5>(16))
    wire T_185396 : UInt<2>
    T_185396 := T_185394
    when T_185395 : T_185396 := UInt<2>(0)
    wire T_185397 : UInt<3>[3]
    T_185397[0] := UInt<3>(0)
    T_185397[1] := UInt<3>(1)
    T_185397[2] := UInt<3>(2)
    wire T_185398 : UInt<2>[2]
    T_185398[0] := UInt<2>(0)
    T_185398[1] := UInt<2>(1)
    wire T_185399 : UInt<2>[3]
    T_185399[0] := UInt<2>(1)
    T_185399[1] := UInt<2>(2)
    T_185399[2] := UInt<2>(3)
    wire T_185400 : UInt<2>[2]
    T_185400[0] := UInt<2>(2)
    T_185400[1] := UInt<2>(3)
    wire T_185401 : UInt<2>[1]
    T_185401[0] := UInt<2>(3)
    wire T_185402 : UInt<3>[3]
    T_185402[0] := UInt<3>(0)
    T_185402[1] := UInt<3>(1)
    T_185402[2] := UInt<3>(2)
    wire T_185403 : UInt<2>[2]
    T_185403[0] := UInt<2>(0)
    T_185403[1] := UInt<2>(1)
    wire T_185404 : UInt<2>[3]
    T_185404[0] := UInt<2>(1)
    T_185404[1] := UInt<2>(2)
    T_185404[2] := UInt<2>(3)
    wire T_185405 : UInt<2>[2]
    T_185405[0] := UInt<2>(2)
    T_185405[1] := UInt<2>(3)
    wire T_185406 : UInt<2>[1]
    T_185406[0] := UInt<2>(3)
    wire T_185407 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_185407.state := T_185396
    wire T_185408 : UInt<3>[3]
    T_185408[0] := UInt<3>(0)
    T_185408[1] := UInt<3>(1)
    T_185408[2] := UInt<3>(2)
    wire T_185409 : UInt<2>[2]
    T_185409[0] := UInt<2>(0)
    T_185409[1] := UInt<2>(1)
    wire T_185410 : UInt<2>[3]
    T_185410[0] := UInt<2>(1)
    T_185410[1] := UInt<2>(2)
    T_185410[2] := UInt<2>(3)
    wire T_185411 : UInt<2>[2]
    T_185411[0] := UInt<2>(2)
    T_185411[1] := UInt<2>(3)
    wire T_185412 : UInt<2>[1]
    T_185412[0] := UInt<2>(3)
    wire T_185413 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_185413 := new_coh_state
    when T_185383 : T_185413 := T_185407
    meta_write.bits.data.coh := T_185413
    meta_write.bits.data.tag := tag
    meta_write.bits.way_en := req.way_en
    node T_185414 = eq(state, UInt<4>(1))
    wb_req.valid := T_185414
    node T_185415 = cat(req.old_meta.tag, req_idx)
    node T_185416 = eq(T_185208[0], req.old_meta.coh.state)
    node T_185417 = or(UInt<1>(0), T_185416)
    wire T_185418 : UInt<3>
    T_185418 := UInt<3>(3)
    when T_185417 : T_185418 := UInt<3>(0)
    wire T_185419 : UInt<3>
    T_185419 := UInt<3>(4)
    when T_185417 : T_185419 := UInt<3>(1)
    wire T_185420 : UInt<3>
    T_185420 := UInt<3>(5)
    when T_185417 : T_185420 := UInt<3>(2)
    node T_185421 = eq(UInt<5>(19), UInt<5>(16))
    wire T_185422 : UInt<3>
    T_185422 := UInt<3>(5)
    when T_185421 : T_185422 := T_185420
    node T_185423 = eq(UInt<5>(17), UInt<5>(16))
    wire T_185424 : UInt<3>
    T_185424 := T_185422
    when T_185423 : T_185424 := T_185419
    node T_185425 = eq(UInt<5>(16), UInt<5>(16))
    wire T_185426 : UInt<3>
    T_185426 := T_185424
    when T_185425 : T_185426 := T_185418
    wire T_185427 : UInt<3>[3]
    T_185427[0] := UInt<3>(0)
    T_185427[1] := UInt<3>(1)
    T_185427[2] := UInt<3>(2)
    wire T_185428 : UInt<2>[2]
    T_185428[0] := UInt<2>(0)
    T_185428[1] := UInt<2>(1)
    wire T_185429 : UInt<2>[3]
    T_185429[0] := UInt<2>(1)
    T_185429[1] := UInt<2>(2)
    T_185429[2] := UInt<2>(3)
    wire T_185430 : UInt<2>[2]
    T_185430[0] := UInt<2>(2)
    T_185430[1] := UInt<2>(3)
    wire T_185431 : UInt<2>[1]
    T_185431[0] := UInt<2>(3)
    wire T_185432 : UInt<3>[3]
    T_185432[0] := UInt<3>(0)
    T_185432[1] := UInt<3>(1)
    T_185432[2] := UInt<3>(2)
    wire T_185433 : UInt<2>[2]
    T_185433[0] := UInt<2>(0)
    T_185433[1] := UInt<2>(1)
    wire T_185434 : UInt<2>[3]
    T_185434[0] := UInt<2>(1)
    T_185434[1] := UInt<2>(2)
    T_185434[2] := UInt<2>(3)
    wire T_185435 : UInt<2>[2]
    T_185435[0] := UInt<2>(2)
    T_185435[1] := UInt<2>(3)
    wire T_185436 : UInt<2>[1]
    T_185436[0] := UInt<2>(3)
    wire T_185437 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}
    T_185437.r_type := T_185426
    T_185437.client_xact_id := UInt<1>(1)
    T_185437.addr_block := T_185415
    T_185437.addr_beat := UInt<1>(0)
    T_185437.data := UInt<1>(0)
    T_185437.voluntary := UInt<1>(1)
    wb_req.bits := T_185437
    wb_req.bits.way_en := req.way_en
    node T_185438 = eq(state, UInt<4>(4))
    mem_req.valid := T_185438
    node T_185439 = cat(tag, req_idx)
    node T_185440 = eq(req.cmd, UInt<5>(1))
    node T_185441 = eq(req.cmd, UInt<5>(7))
    node T_185442 = or(T_185440, T_185441)
    node T_185443 = bit(req.cmd, 3)
    node T_185444 = eq(req.cmd, UInt<5>(4))
    node T_185445 = or(T_185443, T_185444)
    node T_185446 = or(T_185442, T_185445)
    node T_185447 = eq(req.cmd, UInt<5>(3))
    node T_185448 = or(T_185446, T_185447)
    node T_185449 = eq(req.cmd, UInt<5>(6))
    node T_185450 = or(T_185448, T_185449)
    wire T_185451 : UInt<1>
    T_185451 := UInt<1>(0)
    when T_185450 : T_185451 := UInt<1>(1)
    node T_185452 = cat(req.cmd, UInt<1>(1))
    wire T_185453 : UInt<3>[3]
    T_185453[0] := UInt<3>(0)
    T_185453[1] := UInt<3>(1)
    T_185453[2] := UInt<3>(2)
    wire T_185454 : UInt<2>[2]
    T_185454[0] := UInt<2>(0)
    T_185454[1] := UInt<2>(1)
    wire T_185455 : UInt<2>[3]
    T_185455[0] := UInt<2>(1)
    T_185455[1] := UInt<2>(2)
    T_185455[2] := UInt<2>(3)
    wire T_185456 : UInt<2>[2]
    T_185456[0] := UInt<2>(2)
    T_185456[1] := UInt<2>(3)
    wire T_185457 : UInt<2>[1]
    T_185457[0] := UInt<2>(3)
    wire T_185458 : UInt<3>[3]
    T_185458[0] := UInt<3>(0)
    T_185458[1] := UInt<3>(1)
    T_185458[2] := UInt<3>(2)
    wire T_185459 : UInt<2>[2]
    T_185459[0] := UInt<2>(0)
    T_185459[1] := UInt<2>(1)
    wire T_185460 : UInt<2>[3]
    T_185460[0] := UInt<2>(1)
    T_185460[1] := UInt<2>(2)
    T_185460[2] := UInt<2>(3)
    wire T_185461 : UInt<2>[2]
    T_185461[0] := UInt<2>(2)
    T_185461[1] := UInt<2>(3)
    wire T_185462 : UInt<2>[1]
    T_185462[0] := UInt<2>(3)
    wire T_185463 : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}
    T_185463.is_builtin_type := UInt<1>(0)
    T_185463.a_type := T_185451
    T_185463.client_xact_id := UInt<1>(1)
    T_185463.addr_block := T_185439
    T_185463.addr_beat := UInt<1>(0)
    T_185463.data := UInt<1>(0)
    T_185463.union := T_185452
    mem_req.bits := T_185463
    node T_185464 = eq(state, UInt<4>(8))
    meta_read.valid := T_185464
    meta_read.bits.idx := req_idx
    meta_read.bits.tag := tag
    node T_185465 = eq(state, UInt<4>(8))
    node T_185466 = and(T_185465, rpq.deq.valid)
    replay.valid := T_185466
    replay.bits := rpq.deq.bits
    replay.bits.phys := UInt<1>(1)
    node T_185467 = bits(rpq.deq.bits.addr, 5, 0)
    node T_185468 = cat(req_idx, T_185467)
    node T_185469 = cat(tag, T_185468)
    replay.bits.addr := T_185469
    
    node T_185470 = eq(meta_read.ready, UInt<1>(0))
    when T_185470 : 
      rpq.deq.ready := UInt<1>(0)
      replay.bits.cmd := UInt<5>(5)
  module MSHRFile : 
    input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}, way_en : UInt<4>}}
    output secondary_miss : UInt<1>
    output mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}
    output refill : {way_en : UInt<4>, addr : UInt<12>}
    output meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}
    output meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}
    input mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    output probe_rdy : UInt<1>
    output fence_rdy : UInt<1>
    
    wire T_185471 : UInt<3>[3]
    T_185471[0] := UInt<3>(0)
    T_185471[1] := UInt<3>(1)
    T_185471[2] := UInt<3>(2)
    wire T_185472 : UInt<2>[2]
    T_185472[0] := UInt<2>(0)
    T_185472[1] := UInt<2>(1)
    wire T_185473 : UInt<2>[3]
    T_185473[0] := UInt<2>(1)
    T_185473[1] := UInt<2>(2)
    T_185473[2] := UInt<2>(3)
    wire T_185474 : UInt<2>[2]
    T_185474[0] := UInt<2>(2)
    T_185474[1] := UInt<2>(3)
    wire T_185475 : UInt<2>[1]
    T_185475[0] := UInt<2>(3)
    wire T_185476 : UInt<3>[3]
    T_185476[0] := UInt<3>(0)
    T_185476[1] := UInt<3>(1)
    T_185476[2] := UInt<3>(2)
    wire T_185477 : UInt<2>[2]
    T_185477[0] := UInt<2>(0)
    T_185477[1] := UInt<2>(1)
    wire T_185478 : UInt<2>[3]
    T_185478[0] := UInt<2>(1)
    T_185478[1] := UInt<2>(2)
    T_185478[2] := UInt<2>(3)
    wire T_185479 : UInt<2>[2]
    T_185479[0] := UInt<2>(2)
    T_185479[1] := UInt<2>(3)
    wire T_185480 : UInt<2>[1]
    T_185480[0] := UInt<2>(3)
    wire T_185481 : UInt<3>[3]
    T_185481[0] := UInt<3>(0)
    T_185481[1] := UInt<3>(1)
    T_185481[2] := UInt<3>(2)
    wire T_185482 : UInt<2>[2]
    T_185482[0] := UInt<2>(0)
    T_185482[1] := UInt<2>(1)
    wire T_185483 : UInt<2>[3]
    T_185483[0] := UInt<2>(1)
    T_185483[1] := UInt<2>(2)
    T_185483[2] := UInt<2>(3)
    wire T_185484 : UInt<2>[2]
    T_185484[0] := UInt<2>(2)
    T_185484[1] := UInt<2>(3)
    wire T_185485 : UInt<2>[1]
    T_185485[0] := UInt<2>(3)
    wire T_185486 : UInt<3>[3]
    T_185486[0] := UInt<3>(0)
    T_185486[1] := UInt<3>(1)
    T_185486[2] := UInt<3>(2)
    wire T_185487 : UInt<2>[2]
    T_185487[0] := UInt<2>(0)
    T_185487[1] := UInt<2>(1)
    wire T_185488 : UInt<2>[3]
    T_185488[0] := UInt<2>(1)
    T_185488[1] := UInt<2>(2)
    T_185488[2] := UInt<2>(3)
    wire T_185489 : UInt<2>[2]
    T_185489[0] := UInt<2>(2)
    T_185489[1] := UInt<2>(3)
    wire T_185490 : UInt<2>[1]
    T_185490[0] := UInt<2>(3)
    wire T_185491 : UInt<3>[3]
    T_185491[0] := UInt<3>(0)
    T_185491[1] := UInt<3>(1)
    T_185491[2] := UInt<3>(2)
    wire T_185492 : UInt<2>[2]
    T_185492[0] := UInt<2>(0)
    T_185492[1] := UInt<2>(1)
    wire T_185493 : UInt<2>[3]
    T_185493[0] := UInt<2>(1)
    T_185493[1] := UInt<2>(2)
    T_185493[2] := UInt<2>(3)
    wire T_185494 : UInt<2>[2]
    T_185494[0] := UInt<2>(2)
    T_185494[1] := UInt<2>(3)
    wire T_185495 : UInt<2>[1]
    T_185495[0] := UInt<2>(3)
    wire T_185496 : UInt<3>[3]
    T_185496[0] := UInt<3>(0)
    T_185496[1] := UInt<3>(1)
    T_185496[2] := UInt<3>(2)
    wire T_185497 : UInt<2>[2]
    T_185497[0] := UInt<2>(0)
    T_185497[1] := UInt<2>(1)
    wire T_185498 : UInt<2>[3]
    T_185498[0] := UInt<2>(1)
    T_185498[1] := UInt<2>(2)
    T_185498[2] := UInt<2>(3)
    wire T_185499 : UInt<2>[2]
    T_185499[0] := UInt<2>(2)
    T_185499[1] := UInt<2>(3)
    wire T_185500 : UInt<2>[1]
    T_185500[0] := UInt<2>(3)
    wire T_185501 : UInt<3>[3]
    T_185501[0] := UInt<3>(0)
    T_185501[1] := UInt<3>(1)
    T_185501[2] := UInt<3>(2)
    wire T_185502 : UInt<2>[2]
    T_185502[0] := UInt<2>(0)
    T_185502[1] := UInt<2>(1)
    wire T_185503 : UInt<2>[3]
    T_185503[0] := UInt<2>(1)
    T_185503[1] := UInt<2>(2)
    T_185503[2] := UInt<2>(3)
    wire T_185504 : UInt<2>[2]
    T_185504[0] := UInt<2>(2)
    T_185504[1] := UInt<2>(3)
    wire T_185505 : UInt<2>[1]
    T_185505[0] := UInt<2>(3)
    wire T_185506 : UInt<3>[3]
    T_185506[0] := UInt<3>(0)
    T_185506[1] := UInt<3>(1)
    T_185506[2] := UInt<3>(2)
    wire T_185507 : UInt<2>[2]
    T_185507[0] := UInt<2>(0)
    T_185507[1] := UInt<2>(1)
    wire T_185508 : UInt<2>[3]
    T_185508[0] := UInt<2>(1)
    T_185508[1] := UInt<2>(2)
    T_185508[2] := UInt<2>(3)
    wire T_185509 : UInt<2>[2]
    T_185509[0] := UInt<2>(2)
    T_185509[1] := UInt<2>(3)
    wire T_185510 : UInt<2>[1]
    T_185510[0] := UInt<2>(3)
    wire T_185511 : UInt<3>[3]
    T_185511[0] := UInt<3>(0)
    T_185511[1] := UInt<3>(1)
    T_185511[2] := UInt<3>(2)
    wire T_185512 : UInt<2>[2]
    T_185512[0] := UInt<2>(0)
    T_185512[1] := UInt<2>(1)
    wire T_185513 : UInt<2>[3]
    T_185513[0] := UInt<2>(1)
    T_185513[1] := UInt<2>(2)
    T_185513[2] := UInt<2>(3)
    wire T_185514 : UInt<2>[2]
    T_185514[0] := UInt<2>(2)
    T_185514[1] := UInt<2>(3)
    wire T_185515 : UInt<2>[1]
    T_185515[0] := UInt<2>(3)
    wire T_185516 : UInt<3>[3]
    T_185516[0] := UInt<3>(0)
    T_185516[1] := UInt<3>(1)
    T_185516[2] := UInt<3>(2)
    wire T_185517 : UInt<2>[2]
    T_185517[0] := UInt<2>(0)
    T_185517[1] := UInt<2>(1)
    wire T_185518 : UInt<2>[3]
    T_185518[0] := UInt<2>(1)
    T_185518[1] := UInt<2>(2)
    T_185518[2] := UInt<2>(3)
    wire T_185519 : UInt<2>[2]
    T_185519[0] := UInt<2>(2)
    T_185519[1] := UInt<2>(3)
    wire T_185520 : UInt<2>[1]
    T_185520[0] := UInt<2>(3)
    wire T_185521 : UInt<3>[3]
    T_185521[0] := UInt<3>(0)
    T_185521[1] := UInt<3>(1)
    T_185521[2] := UInt<3>(2)
    wire T_185522 : UInt<2>[2]
    T_185522[0] := UInt<2>(0)
    T_185522[1] := UInt<2>(1)
    wire T_185523 : UInt<2>[3]
    T_185523[0] := UInt<2>(1)
    T_185523[1] := UInt<2>(2)
    T_185523[2] := UInt<2>(3)
    wire T_185524 : UInt<2>[2]
    T_185524[0] := UInt<2>(2)
    T_185524[1] := UInt<2>(3)
    wire T_185525 : UInt<2>[1]
    T_185525[0] := UInt<2>(3)
    reg sdq_val : UInt<17>
    onreset sdq_val := UInt<17>(0)
    node T_185526 = bits(sdq_val, 16, 0)
    node T_185527 = not(T_185526)
    node T_185528 = bit(T_185527, 0)
    node T_185529 = bit(T_185527, 1)
    node T_185530 = bit(T_185527, 2)
    node T_185531 = bit(T_185527, 3)
    node T_185532 = bit(T_185527, 4)
    node T_185533 = bit(T_185527, 5)
    node T_185534 = bit(T_185527, 6)
    node T_185535 = bit(T_185527, 7)
    node T_185536 = bit(T_185527, 8)
    node T_185537 = bit(T_185527, 9)
    node T_185538 = bit(T_185527, 10)
    node T_185539 = bit(T_185527, 11)
    node T_185540 = bit(T_185527, 12)
    node T_185541 = bit(T_185527, 13)
    node T_185542 = bit(T_185527, 14)
    node T_185543 = bit(T_185527, 15)
    node T_185544 = bit(T_185527, 16)
    wire T_185545 : UInt<1>[17]
    T_185545[0] := T_185528
    T_185545[1] := T_185529
    T_185545[2] := T_185530
    T_185545[3] := T_185531
    T_185545[4] := T_185532
    T_185545[5] := T_185533
    T_185545[6] := T_185534
    T_185545[7] := T_185535
    T_185545[8] := T_185536
    T_185545[9] := T_185537
    T_185545[10] := T_185538
    T_185545[11] := T_185539
    T_185545[12] := T_185540
    T_185545[13] := T_185541
    T_185545[14] := T_185542
    T_185545[15] := T_185543
    T_185545[16] := T_185544
    wire T_185546 : UInt<5>
    T_185546 := UInt<5>(16)
    when T_185545[15] : T_185546 := UInt<4>(15)
    wire T_185547 : UInt<5>
    T_185547 := T_185546
    when T_185545[14] : T_185547 := UInt<4>(14)
    wire T_185548 : UInt<5>
    T_185548 := T_185547
    when T_185545[13] : T_185548 := UInt<4>(13)
    wire T_185549 : UInt<5>
    T_185549 := T_185548
    when T_185545[12] : T_185549 := UInt<4>(12)
    wire T_185550 : UInt<5>
    T_185550 := T_185549
    when T_185545[11] : T_185550 := UInt<4>(11)
    wire T_185551 : UInt<5>
    T_185551 := T_185550
    when T_185545[10] : T_185551 := UInt<4>(10)
    wire T_185552 : UInt<5>
    T_185552 := T_185551
    when T_185545[9] : T_185552 := UInt<4>(9)
    wire T_185553 : UInt<5>
    T_185553 := T_185552
    when T_185545[8] : T_185553 := UInt<4>(8)
    wire T_185554 : UInt<5>
    T_185554 := T_185553
    when T_185545[7] : T_185554 := UInt<3>(7)
    wire T_185555 : UInt<5>
    T_185555 := T_185554
    when T_185545[6] : T_185555 := UInt<3>(6)
    wire T_185556 : UInt<5>
    T_185556 := T_185555
    when T_185545[5] : T_185556 := UInt<3>(5)
    wire T_185557 : UInt<5>
    T_185557 := T_185556
    when T_185545[4] : T_185557 := UInt<3>(4)
    wire T_185558 : UInt<5>
    T_185558 := T_185557
    when T_185545[3] : T_185558 := UInt<2>(3)
    wire T_185559 : UInt<5>
    T_185559 := T_185558
    when T_185545[2] : T_185559 := UInt<2>(2)
    wire T_185560 : UInt<5>
    T_185560 := T_185559
    when T_185545[1] : T_185560 := UInt<1>(1)
    wire sdq_alloc_id : UInt<5>
    sdq_alloc_id := T_185560
    when T_185545[0] : sdq_alloc_id := UInt<1>(0)
    node T_185561 = eq(sdq_val, UInt<1>(-1))
    node sdq_rdy = eq(T_185561, UInt<1>(0))
    node T_185562 = and(req.valid, req.ready)
    node T_185563 = eq(req.bits.cmd, UInt<5>(1))
    node T_185564 = eq(req.bits.cmd, UInt<5>(7))
    node T_185565 = or(T_185563, T_185564)
    node T_185566 = bit(req.bits.cmd, 3)
    node T_185567 = eq(req.bits.cmd, UInt<5>(4))
    node T_185568 = or(T_185566, T_185567)
    node T_185569 = or(T_185565, T_185568)
    node sdq_enq = and(T_185562, T_185569)
    cmem sdq : UInt<64>[17]
    when sdq_enq : 
      accessor T_185570 = sdq[sdq_alloc_id]
      T_185570 := req.bits.data
    wire idxMatch : UInt<1>[2]
    wire tagList : UInt[2]
    wire T_185571 : UInt<1>
    T_185571 := UInt<1>(0)
    when idxMatch[0] : T_185571 := tagList[0]
    wire T_185572 : UInt<1>
    T_185572 := UInt<1>(0)
    when idxMatch[1] : T_185572 := tagList[1]
    node T_185573 = or(T_185571, T_185572)
    wire T_185574 : UInt
    node T_185575 = bits(T_185573, -2, 0)
    T_185574 := T_185575
    node T_185576 = shr(req.bits.addr, 12)
    node tag_match = eq(T_185574, T_185576)
    wire wbTagList : UInt[2]
    wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2]
    inst meta_read_arb of Arbiter_135527
    wire T_185577 : UInt<3>[3]
    T_185577[0] := UInt<3>(0)
    T_185577[1] := UInt<3>(1)
    T_185577[2] := UInt<3>(2)
    wire T_185578 : UInt<2>[2]
    T_185578[0] := UInt<2>(0)
    T_185578[1] := UInt<2>(1)
    wire T_185579 : UInt<2>[3]
    T_185579[0] := UInt<2>(1)
    T_185579[1] := UInt<2>(2)
    T_185579[2] := UInt<2>(3)
    wire T_185580 : UInt<2>[2]
    T_185580[0] := UInt<2>(2)
    T_185580[1] := UInt<2>(3)
    wire T_185581 : UInt<2>[1]
    T_185581[0] := UInt<2>(3)
    wire T_185582 : UInt<3>[3]
    T_185582[0] := UInt<3>(0)
    T_185582[1] := UInt<3>(1)
    T_185582[2] := UInt<3>(2)
    wire T_185583 : UInt<2>[2]
    T_185583[0] := UInt<2>(0)
    T_185583[1] := UInt<2>(1)
    wire T_185584 : UInt<2>[3]
    T_185584[0] := UInt<2>(1)
    T_185584[1] := UInt<2>(2)
    T_185584[2] := UInt<2>(3)
    wire T_185585 : UInt<2>[2]
    T_185585[0] := UInt<2>(2)
    T_185585[1] := UInt<2>(3)
    wire T_185586 : UInt<2>[1]
    T_185586[0] := UInt<2>(3)
    inst meta_write_arb of Arbiter_136117
    wire T_185587 : UInt<3>[3]
    T_185587[0] := UInt<3>(0)
    T_185587[1] := UInt<3>(1)
    T_185587[2] := UInt<3>(2)
    wire T_185588 : UInt<2>[2]
    T_185588[0] := UInt<2>(0)
    T_185588[1] := UInt<2>(1)
    wire T_185589 : UInt<2>[3]
    T_185589[0] := UInt<2>(1)
    T_185589[1] := UInt<2>(2)
    T_185589[2] := UInt<2>(3)
    wire T_185590 : UInt<2>[2]
    T_185590[0] := UInt<2>(2)
    T_185590[1] := UInt<2>(3)
    wire T_185591 : UInt<2>[1]
    T_185591[0] := UInt<2>(3)
    inst mem_req_arb of LockingArbiter
    wire T_185592 : UInt<3>[3]
    T_185592[0] := UInt<3>(0)
    T_185592[1] := UInt<3>(1)
    T_185592[2] := UInt<3>(2)
    wire T_185593 : UInt<2>[2]
    T_185593[0] := UInt<2>(0)
    T_185593[1] := UInt<2>(1)
    wire T_185594 : UInt<2>[3]
    T_185594[0] := UInt<2>(1)
    T_185594[1] := UInt<2>(2)
    T_185594[2] := UInt<2>(3)
    wire T_185595 : UInt<2>[2]
    T_185595[0] := UInt<2>(2)
    T_185595[1] := UInt<2>(3)
    wire T_185596 : UInt<2>[1]
    T_185596[0] := UInt<2>(3)
    inst wb_req_arb of Arbiter_137146
    inst replay_arb of Arbiter_137247
    inst alloc_arb of Arbiter_137299
    fence_rdy := UInt<1>(1)
    probe_rdy := UInt<1>(1)
    inst T_185597 of MSHR
    idxMatch[0] := T_185597.idx_match
    tagList[0] := T_185597.tag
    node T_185598 = dshr(T_185597.wb_req.bits.addr_block, UInt<3>(6))
    wbTagList[0] := T_185598
    alloc_arb.in[0].valid := T_185597.req_pri_rdy
    T_185597.req_pri_val := alloc_arb.in[0].ready
    node T_185599 = and(req.valid, sdq_rdy)
    node T_185600 = and(T_185599, tag_match)
    T_185597.req_sec_val := T_185600
    T_185597.req_bits := req.bits
    T_185597.req_bits.sdq_id := sdq_alloc_id
    T_185597.meta_read <> meta_read_arb.in[0]
    T_185597.meta_write <> meta_write_arb.in[0]
    T_185597.mem_req <> mem_req_arb.in[0]
    T_185597.wb_req <> wb_req_arb.in[0]
    T_185597.replay <> replay_arb.in[0]
    node T_185601 = eq(mem_grant.bits.client_xact_id, UInt<1>(0))
    node T_185602 = and(mem_grant.valid, T_185601)
    T_185597.mem_grant.valid := T_185602
    T_185597.mem_grant.bits := mem_grant.bits
    refillMux[0] := T_185597.refill
    node T_185603 = or(UInt<1>(0), T_185597.req_pri_rdy)
    node T_185604 = or(UInt<1>(0), T_185597.req_sec_rdy)
    node T_185605 = or(UInt<1>(0), T_185597.idx_match)
    
    node T_185606 = eq(T_185597.req_pri_rdy, UInt<1>(0))
    when T_185606 : fence_rdy := UInt<1>(0)
    
    node T_185607 = eq(T_185597.probe_rdy, UInt<1>(0))
    when T_185607 : probe_rdy := UInt<1>(0)
    inst T_185608 of MSHR_141857
    idxMatch[1] := T_185608.idx_match
    tagList[1] := T_185608.tag
    node T_185609 = dshr(T_185608.wb_req.bits.addr_block, UInt<3>(6))
    wbTagList[1] := T_185609
    alloc_arb.in[1].valid := T_185608.req_pri_rdy
    T_185608.req_pri_val := alloc_arb.in[1].ready
    node T_185610 = and(req.valid, sdq_rdy)
    node T_185611 = and(T_185610, tag_match)
    T_185608.req_sec_val := T_185611
    T_185608.req_bits := req.bits
    T_185608.req_bits.sdq_id := sdq_alloc_id
    T_185608.meta_read <> meta_read_arb.in[1]
    T_185608.meta_write <> meta_write_arb.in[1]
    T_185608.mem_req <> mem_req_arb.in[1]
    T_185608.wb_req <> wb_req_arb.in[1]
    T_185608.replay <> replay_arb.in[1]
    node T_185612 = eq(mem_grant.bits.client_xact_id, UInt<1>(1))
    node T_185613 = and(mem_grant.valid, T_185612)
    T_185608.mem_grant.valid := T_185613
    T_185608.mem_grant.bits := mem_grant.bits
    refillMux[1] := T_185608.refill
    node pri_rdy = or(T_185603, T_185608.req_pri_rdy)
    node sec_rdy = or(T_185604, T_185608.req_sec_rdy)
    node idx_match = or(T_185605, T_185608.idx_match)
    
    node T_185614 = eq(T_185608.req_pri_rdy, UInt<1>(0))
    when T_185614 : fence_rdy := UInt<1>(0)
    
    node T_185615 = eq(T_185608.probe_rdy, UInt<1>(0))
    when T_185615 : probe_rdy := UInt<1>(0)
    node T_185616 = and(req.valid, sdq_rdy)
    node T_185617 = eq(idx_match, UInt<1>(0))
    node T_185618 = and(T_185616, T_185617)
    alloc_arb.out.ready := T_185618
    meta_read_arb.out <> meta_read
    meta_write_arb.out <> meta_write
    mem_req_arb.out <> mem_req
    wb_req_arb.out <> wb_req
    node T_185619 = and(tag_match, sec_rdy)
    wire T_185620 : UInt<1>
    T_185620 := pri_rdy
    when idx_match : T_185620 := T_185619
    node T_185621 = and(T_185620, sdq_rdy)
    req.ready := T_185621
    secondary_miss := idx_match
    accessor T_185622 = refillMux[mem_grant.bits.client_xact_id]
    refill := T_185622
    node T_185623 = and(replay.ready, replay.valid)
    node T_185624 = eq(replay.bits.cmd, UInt<5>(1))
    node T_185625 = eq(replay.bits.cmd, UInt<5>(7))
    node T_185626 = or(T_185624, T_185625)
    node T_185627 = bit(replay.bits.cmd, 3)
    node T_185628 = eq(replay.bits.cmd, UInt<5>(4))
    node T_185629 = or(T_185627, T_185628)
    node T_185630 = or(T_185626, T_185629)
    node free_sdq = and(T_185623, T_185630)
    reg T_185631 : UInt<5>
    when free_sdq : T_185631 := replay_arb.out.bits.sdq_id
    accessor T_185632 = sdq[T_185631]
    replay.bits.data := T_185632
    replay <> replay_arb.out
    
    node T_185633 = or(replay.valid, sdq_enq)
    when T_185633 : 
      node T_185634 = dshl(UInt<1>(1), replay_arb.out.bits.sdq_id)
      node T_185635 = subw(UInt<17>(0), UInt<5>(17))
      node T_185636 = and(T_185634, T_185635)
      node T_185637 = not(T_185636)
      node T_185638 = and(sdq_val, T_185637)
      node T_185639 = bits(sdq_val, 16, 0)
      node T_185640 = not(T_185639)
      node T_185641 = bit(T_185640, 0)
      node T_185642 = bit(T_185640, 1)
      node T_185643 = bit(T_185640, 2)
      node T_185644 = bit(T_185640, 3)
      node T_185645 = bit(T_185640, 4)
      node T_185646 = bit(T_185640, 5)
      node T_185647 = bit(T_185640, 6)
      node T_185648 = bit(T_185640, 7)
      node T_185649 = bit(T_185640, 8)
      node T_185650 = bit(T_185640, 9)
      node T_185651 = bit(T_185640, 10)
      node T_185652 = bit(T_185640, 11)
      node T_185653 = bit(T_185640, 12)
      node T_185654 = bit(T_185640, 13)
      node T_185655 = bit(T_185640, 14)
      node T_185656 = bit(T_185640, 15)
      node T_185657 = bit(T_185640, 16)
      wire T_185658 : UInt<17>[17]
      T_185658[0] := UInt<17>(1)
      T_185658[1] := UInt<17>(2)
      T_185658[2] := UInt<17>(4)
      T_185658[3] := UInt<17>(8)
      T_185658[4] := UInt<17>(16)
      T_185658[5] := UInt<17>(32)
      T_185658[6] := UInt<17>(64)
      T_185658[7] := UInt<17>(128)
      T_185658[8] := UInt<17>(256)
      T_185658[9] := UInt<17>(512)
      T_185658[10] := UInt<17>(1024)
      T_185658[11] := UInt<17>(2048)
      T_185658[12] := UInt<17>(4096)
      T_185658[13] := UInt<17>(8192)
      T_185658[14] := UInt<17>(16384)
      T_185658[15] := UInt<17>(32768)
      T_185658[16] := UInt<17>(65536)
      wire T_185659 : UInt<17>
      T_185659 := UInt<17>(0)
      when T_185657 : T_185659 := T_185658[16]
      wire T_185660 : UInt<17>
      T_185660 := T_185659
      when T_185656 : T_185660 := T_185658[15]
      wire T_185661 : UInt<17>
      T_185661 := T_185660
      when T_185655 : T_185661 := T_185658[14]
      wire T_185662 : UInt<17>
      T_185662 := T_185661
      when T_185654 : T_185662 := T_185658[13]
      wire T_185663 : UInt<17>
      T_185663 := T_185662
      when T_185653 : T_185663 := T_185658[12]
      wire T_185664 : UInt<17>
      T_185664 := T_185663
      when T_185652 : T_185664 := T_185658[11]
      wire T_185665 : UInt<17>
      T_185665 := T_185664
      when T_185651 : T_185665 := T_185658[10]
      wire T_185666 : UInt<17>
      T_185666 := T_185665
      when T_185650 : T_185666 := T_185658[9]
      wire T_185667 : UInt<17>
      T_185667 := T_185666
      when T_185649 : T_185667 := T_185658[8]
      wire T_185668 : UInt<17>
      T_185668 := T_185667
      when T_185648 : T_185668 := T_185658[7]
      wire T_185669 : UInt<17>
      T_185669 := T_185668
      when T_185647 : T_185669 := T_185658[6]
      wire T_185670 : UInt<17>
      T_185670 := T_185669
      when T_185646 : T_185670 := T_185658[5]
      wire T_185671 : UInt<17>
      T_185671 := T_185670
      when T_185645 : T_185671 := T_185658[4]
      wire T_185672 : UInt<17>
      T_185672 := T_185671
      when T_185644 : T_185672 := T_185658[3]
      wire T_185673 : UInt<17>
      T_185673 := T_185672
      when T_185643 : T_185673 := T_185658[2]
      wire T_185674 : UInt<17>
      T_185674 := T_185673
      when T_185642 : T_185674 := T_185658[1]
      wire T_185675 : UInt<17>
      T_185675 := T_185674
      when T_185641 : T_185675 := T_185658[0]
      node T_185676 = subw(UInt<17>(0), UInt<5>(17))
      node T_185677 = and(T_185675, T_185676)
      node T_185678 = or(T_185638, T_185677)
      sdq_val := T_185678
  module RocketCAM_142285 : 
    input clear : UInt<1>
    input clear_mask : UInt<8>
    input tag : UInt<34>
    output hit : UInt<1>
    output hits : UInt<8>
    output valid_bits : UInt<8>
    input write : UInt<1>
    input write_tag : UInt<34>
    input write_addr : UInt<3>
    
    cmem cam_tags : UInt<34>[8]
    reg vb_array : UInt<8>
    onreset vb_array := UInt<8>(0)
    when write : 
      node T_185679 = dshl(UInt<1>(1), write_addr)
      node T_185680 = or(vb_array, T_185679)
      node T_185681 = not(vb_array)
      node T_185682 = or(T_185681, T_185679)
      node T_185683 = not(T_185682)
      wire T_185684 : UInt<9>
      T_185684 := T_185683
      when UInt<1>(1) : T_185684 := T_185680
      vb_array := T_185684
      accessor T_185685 = cam_tags[write_addr]
      T_185685 := write_tag
    when clear : 
      node T_185686 = not(clear_mask)
      node T_185687 = and(vb_array, T_185686)
      vb_array := T_185687
    node T_185688 = bit(vb_array, 0)
    accessor T_185689 = cam_tags[UInt<1>(0)]
    node T_185690 = eq(T_185689, tag)
    node T_185691 = and(T_185688, T_185690)
    node T_185692 = bit(vb_array, 1)
    accessor T_185693 = cam_tags[UInt<1>(1)]
    node T_185694 = eq(T_185693, tag)
    node T_185695 = and(T_185692, T_185694)
    node T_185696 = bit(vb_array, 2)
    accessor T_185697 = cam_tags[UInt<2>(2)]
    node T_185698 = eq(T_185697, tag)
    node T_185699 = and(T_185696, T_185698)
    node T_185700 = bit(vb_array, 3)
    accessor T_185701 = cam_tags[UInt<2>(3)]
    node T_185702 = eq(T_185701, tag)
    node T_185703 = and(T_185700, T_185702)
    node T_185704 = bit(vb_array, 4)
    accessor T_185705 = cam_tags[UInt<3>(4)]
    node T_185706 = eq(T_185705, tag)
    node T_185707 = and(T_185704, T_185706)
    node T_185708 = bit(vb_array, 5)
    accessor T_185709 = cam_tags[UInt<3>(5)]
    node T_185710 = eq(T_185709, tag)
    node T_185711 = and(T_185708, T_185710)
    node T_185712 = bit(vb_array, 6)
    accessor T_185713 = cam_tags[UInt<3>(6)]
    node T_185714 = eq(T_185713, tag)
    node T_185715 = and(T_185712, T_185714)
    node T_185716 = bit(vb_array, 7)
    accessor T_185717 = cam_tags[UInt<3>(7)]
    node T_185718 = eq(T_185717, tag)
    node T_185719 = and(T_185716, T_185718)
    valid_bits := vb_array
    wire T_185720 : UInt<1>[8]
    T_185720[0] := T_185691
    T_185720[1] := T_185695
    T_185720[2] := T_185699
    T_185720[3] := T_185703
    T_185720[4] := T_185707
    T_185720[5] := T_185711
    T_185720[6] := T_185715
    T_185720[7] := T_185719
    node T_185721 = cat(T_185720[7], T_185720[6])
    node T_185722 = cat(T_185720[5], T_185720[4])
    node T_185723 = cat(T_185721, T_185722)
    node T_185724 = cat(T_185720[3], T_185720[2])
    node T_185725 = cat(T_185720[1], T_185720[0])
    node T_185726 = cat(T_185724, T_185725)
    node T_185727 = cat(T_185723, T_185726)
    hits := T_185727
    node T_185728 = eq(hits, UInt<1>(0))
    node T_185729 = eq(T_185728, UInt<1>(0))
    hit := T_185729
  module TLB_142822 : 
    input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}
    output resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}
    output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}
    
    reg state : UInt<2>
    onreset state := UInt<2>(0)
    reg r_refill_tag : UInt
    reg r_refill_waddr : UInt
    reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}
    inst tag_cam of RocketCAM_142285
    cmem tag_ram : UInt<20>[8]
    node lookup_tag = cat(req.bits.asid, req.bits.vpn)
    tag_cam.tag := lookup_tag
    node T_185730 = eq(state, UInt<2>(2))
    node T_185731 = and(T_185730, ptw.resp.valid)
    tag_cam.write := T_185731
    tag_cam.write_tag := r_refill_tag
    tag_cam.write_addr := r_refill_waddr
    node T_185732 = bits(tag_cam.hits, 7, 4)
    node T_185733 = bits(tag_cam.hits, 3, 0)
    node T_185734 = eq(T_185732, UInt<1>(0))
    node T_185735 = eq(T_185734, UInt<1>(0))
    node T_185736 = or(T_185732, T_185733)
    node T_185737 = bits(T_185736, 3, 2)
    node T_185738 = bits(T_185736, 1, 0)
    node T_185739 = eq(T_185737, UInt<1>(0))
    node T_185740 = eq(T_185739, UInt<1>(0))
    node T_185741 = or(T_185737, T_185738)
    node T_185742 = bit(T_185741, 1)
    node T_185743 = cat(T_185740, T_185742)
    node tag_hit_addr = cat(T_185735, T_185743)
    reg valid_array : UInt<1>[8]
    reg ur_array : UInt<1>[8]
    reg uw_array : UInt<1>[8]
    reg ux_array : UInt<1>[8]
    reg sr_array : UInt<1>[8]
    reg sw_array : UInt<1>[8]
    reg sx_array : UInt<1>[8]
    reg dirty_array : UInt<1>[8]
    when ptw.resp.valid : 
      accessor T_185744 = tag_ram[r_refill_waddr]
      T_185744 := ptw.resp.bits.pte.ppn
      accessor T_185745 = valid_array[r_refill_waddr]
      node T_185746 = eq(ptw.resp.bits.error, UInt<1>(0))
      T_185745 := T_185746
      accessor T_185747 = ur_array[r_refill_waddr]
      node T_185748 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_185749 = and(ptw.resp.bits.pte.v, T_185748)
      node T_185750 = lt(ptw.resp.bits.pte.typ, UInt<4>(8))
      node T_185751 = and(T_185749, T_185750)
      node T_185752 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_185753 = and(T_185751, T_185752)
      T_185747 := T_185753
      accessor T_185754 = uw_array[r_refill_waddr]
      node T_185755 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_185756 = and(ptw.resp.bits.pte.v, T_185755)
      node T_185757 = lt(ptw.resp.bits.pte.typ, UInt<4>(8))
      node T_185758 = and(T_185756, T_185757)
      node T_185759 = bit(ptw.resp.bits.pte.typ, 0)
      node T_185760 = and(T_185758, T_185759)
      node T_185761 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_185762 = and(T_185760, T_185761)
      T_185754 := T_185762
      accessor T_185763 = ux_array[r_refill_waddr]
      node T_185764 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_185765 = and(ptw.resp.bits.pte.v, T_185764)
      node T_185766 = lt(ptw.resp.bits.pte.typ, UInt<4>(8))
      node T_185767 = and(T_185765, T_185766)
      node T_185768 = bit(ptw.resp.bits.pte.typ, 1)
      node T_185769 = and(T_185767, T_185768)
      node T_185770 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_185771 = and(T_185769, T_185770)
      T_185763 := T_185771
      accessor T_185772 = sr_array[r_refill_waddr]
      node T_185773 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_185774 = and(ptw.resp.bits.pte.v, T_185773)
      node T_185775 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_185776 = and(T_185774, T_185775)
      T_185772 := T_185776
      accessor T_185777 = sw_array[r_refill_waddr]
      node T_185778 = geq(ptw.resp.bits.pte.typ, UInt<2>(2))
      node T_185779 = and(ptw.resp.bits.pte.v, T_185778)
      node T_185780 = bit(ptw.resp.bits.pte.typ, 0)
      node T_185781 = and(T_185779, T_185780)
      node T_185782 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_185783 = and(T_185781, T_185782)
      T_185777 := T_185783
      accessor T_185784 = sx_array[r_refill_waddr]
      node T_185785 = geq(ptw.resp.bits.pte.typ, UInt<3>(4))
      node T_185786 = and(ptw.resp.bits.pte.v, T_185785)
      node T_185787 = bit(ptw.resp.bits.pte.typ, 1)
      node T_185788 = and(T_185786, T_185787)
      node T_185789 = eq(ptw.resp.bits.error, UInt<1>(0))
      node T_185790 = and(T_185788, T_185789)
      T_185784 := T_185790
      accessor T_185791 = dirty_array[r_refill_waddr]
      T_185791 := ptw.resp.bits.pte.d
    node T_185792 = eq(tag_cam.valid_bits, UInt<1>(-1))
    node has_invalid_entry = eq(T_185792, UInt<1>(0))
    node T_185793 = not(tag_cam.valid_bits)
    node T_185794 = bit(T_185793, 0)
    node T_185795 = bit(T_185793, 1)
    node T_185796 = bit(T_185793, 2)
    node T_185797 = bit(T_185793, 3)
    node T_185798 = bit(T_185793, 4)
    node T_185799 = bit(T_185793, 5)
    node T_185800 = bit(T_185793, 6)
    node T_185801 = bit(T_185793, 7)
    wire T_185802 : UInt<1>[8]
    T_185802[0] := T_185794
    T_185802[1] := T_185795
    T_185802[2] := T_185796
    T_185802[3] := T_185797
    T_185802[4] := T_185798
    T_185802[5] := T_185799
    T_185802[6] := T_185800
    T_185802[7] := T_185801
    wire T_185803 : UInt<3>
    T_185803 := UInt<3>(7)
    when T_185802[6] : T_185803 := UInt<3>(6)
    wire T_185804 : UInt<3>
    T_185804 := T_185803
    when T_185802[5] : T_185804 := UInt<3>(5)
    wire T_185805 : UInt<3>
    T_185805 := T_185804
    when T_185802[4] : T_185805 := UInt<3>(4)
    wire T_185806 : UInt<3>
    T_185806 := T_185805
    when T_185802[3] : T_185806 := UInt<2>(3)
    wire T_185807 : UInt<3>
    T_185807 := T_185806
    when T_185802[2] : T_185807 := UInt<2>(2)
    wire T_185808 : UInt<3>
    T_185808 := T_185807
    when T_185802[1] : T_185808 := UInt<1>(1)
    wire invalid_entry : UInt<3>
    invalid_entry := T_185808
    when T_185802[0] : invalid_entry := UInt<1>(0)
    reg T_185809 : UInt<8>
    node T_185810 = dshr(T_185809, UInt<1>(1))
    node T_185811 = bit(T_185810, 0)
    node T_185812 = cat(UInt<1>(1), T_185811)
    node T_185813 = dshr(T_185809, T_185812)
    node T_185814 = bit(T_185813, 0)
    node T_185815 = cat(T_185812, T_185814)
    node T_185816 = dshr(T_185809, T_185815)
    node T_185817 = bit(T_185816, 0)
    node T_185818 = cat(T_185815, T_185817)
    node T_185819 = bits(T_185818, 2, 0)
    wire repl_waddr : UInt<3>
    repl_waddr := T_185819
    when has_invalid_entry : repl_waddr := invalid_entry
    node T_185820 = eq(req.bits.instruction, UInt<1>(0))
    node T_185821 = and(ptw.status.mprv, T_185820)
    wire priv : UInt<2>
    priv := ptw.status.prv
    when T_185821 : priv := ptw.status.prv1
    node priv_s = eq(priv, UInt<1>(1))
    node priv_uses_vm = leq(priv, UInt<1>(1))
    node T_185822 = eq(r_req.store, UInt<1>(0))
    node T_185823 = or(r_req.instruction, r_req.store)
    node T_185824 = eq(T_185823, UInt<1>(0))
    node T_185825 = cat(r_req.store, T_185824)
    node req_xwr = cat(T_185822, T_185825)
    node T_185826 = cat(sr_array[7], sr_array[6])
    node T_185827 = cat(sr_array[5], sr_array[4])
    node T_185828 = cat(T_185826, T_185827)
    node T_185829 = cat(sr_array[3], sr_array[2])
    node T_185830 = cat(sr_array[1], sr_array[0])
    node T_185831 = cat(T_185829, T_185830)
    node T_185832 = cat(T_185828, T_185831)
    node T_185833 = cat(ur_array[7], ur_array[6])
    node T_185834 = cat(ur_array[5], ur_array[4])
    node T_185835 = cat(T_185833, T_185834)
    node T_185836 = cat(ur_array[3], ur_array[2])
    node T_185837 = cat(ur_array[1], ur_array[0])
    node T_185838 = cat(T_185836, T_185837)
    node T_185839 = cat(T_185835, T_185838)
    wire r_array : UInt<8>
    r_array := T_185839
    when priv_s : r_array := T_185832
    node T_185840 = cat(sw_array[7], sw_array[6])
    node T_185841 = cat(sw_array[5], sw_array[4])
    node T_185842 = cat(T_185840, T_185841)
    node T_185843 = cat(sw_array[3], sw_array[2])
    node T_185844 = cat(sw_array[1], sw_array[0])
    node T_185845 = cat(T_185843, T_185844)
    node T_185846 = cat(T_185842, T_185845)
    node T_185847 = cat(uw_array[7], uw_array[6])
    node T_185848 = cat(uw_array[5], uw_array[4])
    node T_185849 = cat(T_185847, T_185848)
    node T_185850 = cat(uw_array[3], uw_array[2])
    node T_185851 = cat(uw_array[1], uw_array[0])
    node T_185852 = cat(T_185850, T_185851)
    node T_185853 = cat(T_185849, T_185852)
    wire w_array : UInt<8>
    w_array := T_185853
    when priv_s : w_array := T_185846
    node T_185854 = cat(sx_array[7], sx_array[6])
    node T_185855 = cat(sx_array[5], sx_array[4])
    node T_185856 = cat(T_185854, T_185855)
    node T_185857 = cat(sx_array[3], sx_array[2])
    node T_185858 = cat(sx_array[1], sx_array[0])
    node T_185859 = cat(T_185857, T_185858)
    node T_185860 = cat(T_185856, T_185859)
    node T_185861 = cat(ux_array[7], ux_array[6])
    node T_185862 = cat(ux_array[5], ux_array[4])
    node T_185863 = cat(T_185861, T_185862)
    node T_185864 = cat(ux_array[3], ux_array[2])
    node T_185865 = cat(ux_array[1], ux_array[0])
    node T_185866 = cat(T_185864, T_185865)
    node T_185867 = cat(T_185863, T_185866)
    wire x_array : UInt<8>
    x_array := T_185867
    when priv_s : x_array := T_185860
    node T_185868 = bit(ptw.status.vm, 3)
    node vm_enabled = and(T_185868, priv_uses_vm)
    node T_185869 = bit(req.bits.vpn, 27)
    node T_185870 = bit(req.bits.vpn, 26)
    node bad_va = neq(T_185869, T_185870)
    node T_185871 = cat(dirty_array[7], dirty_array[6])
    node T_185872 = cat(dirty_array[5], dirty_array[4])
    node T_185873 = cat(T_185871, T_185872)
    node T_185874 = cat(dirty_array[3], dirty_array[2])
    node T_185875 = cat(dirty_array[1], dirty_array[0])
    node T_185876 = cat(T_185874, T_185875)
    node T_185877 = cat(T_185873, T_185876)
    wire T_185878 : UInt<1>
    T_185878 := UInt<1>(0)
    when req.bits.store : T_185878 := w_array
    node T_185879 = not(T_185878)
    node T_185880 = or(T_185877, T_185879)
    node tag_hits = and(tag_cam.hits, T_185880)
    node T_185881 = eq(tag_hits, UInt<1>(0))
    node tag_hit = eq(T_185881, UInt<1>(0))
    node tlb_hit = and(vm_enabled, tag_hit)
    node T_185882 = eq(tag_hit, UInt<1>(0))
    node T_185883 = and(vm_enabled, T_185882)
    node T_185884 = eq(bad_va, UInt<1>(0))
    node tlb_miss = and(T_185883, T_185884)
    
    node T_185885 = and(req.valid, tlb_hit)
    when T_185885 : 
      node T_185886 = bits(tag_cam.hits, 7, 4)
      node T_185887 = bits(tag_cam.hits, 3, 0)
      node T_185888 = eq(T_185886, UInt<1>(0))
      node T_185889 = eq(T_185888, UInt<1>(0))
      node T_185890 = or(T_185886, T_185887)
      node T_185891 = bits(T_185890, 3, 2)
      node T_185892 = bits(T_185890, 1, 0)
      node T_185893 = eq(T_185891, UInt<1>(0))
      node T_185894 = eq(T_185893, UInt<1>(0))
      node T_185895 = or(T_185891, T_185892)
      node T_185896 = bit(T_185895, 1)
      node T_185897 = cat(T_185894, T_185896)
      node T_185898 = cat(T_185889, T_185897)
      node T_185899 = bit(T_185898, 2)
      node T_185900 = dshl(UInt<8>(1), UInt<1>(1))
      node T_185901 = bits(T_185900, 7, 0)
      node T_185902 = not(T_185901)
      node T_185903 = and(T_185809, T_185902)
      wire T_185904 : UInt<8>
      T_185904 := T_185901
      when T_185899 : T_185904 := UInt<1>(0)
      node T_185905 = or(T_185903, T_185904)
      node T_185906 = cat(UInt<1>(1), T_185899)
      node T_185907 = bit(T_185898, 1)
      node T_185908 = dshl(UInt<8>(1), T_185906)
      node T_185909 = bits(T_185908, 7, 0)
      node T_185910 = not(T_185909)
      node T_185911 = and(T_185905, T_185910)
      wire T_185912 : UInt<8>
      T_185912 := T_185909
      when T_185907 : T_185912 := UInt<1>(0)
      node T_185913 = or(T_185911, T_185912)
      node T_185914 = cat(T_185906, T_185907)
      node T_185915 = bit(T_185898, 0)
      node T_185916 = dshl(UInt<8>(1), T_185914)
      node T_185917 = bits(T_185916, 7, 0)
      node T_185918 = not(T_185917)
      node T_185919 = and(T_185913, T_185918)
      wire T_185920 : UInt<8>
      T_185920 := T_185917
      when T_185915 : T_185920 := UInt<1>(0)
      node T_185921 = or(T_185919, T_185920)
      node T_185922 = cat(T_185914, T_185915)
      T_185809 := T_185921
    node T_185923 = eq(state, UInt<2>(0))
    req.ready := T_185923
    node T_185924 = and(r_array, tag_cam.hits)
    node T_185925 = eq(T_185924, UInt<1>(0))
    node T_185926 = eq(T_185925, UInt<1>(0))
    node T_185927 = eq(T_185926, UInt<1>(0))
    node T_185928 = and(tlb_hit, T_185927)
    node T_185929 = or(bad_va, T_185928)
    resp.xcpt_ld := T_185929
    node T_185930 = and(w_array, tag_cam.hits)
    node T_185931 = eq(T_185930, UInt<1>(0))
    node T_185932 = eq(T_185931, UInt<1>(0))
    node T_185933 = eq(T_185932, UInt<1>(0))
    node T_185934 = and(tlb_hit, T_185933)
    node T_185935 = or(bad_va, T_185934)
    resp.xcpt_st := T_185935
    node T_185936 = and(x_array, tag_cam.hits)
    node T_185937 = eq(T_185936, UInt<1>(0))
    node T_185938 = eq(T_185937, UInt<1>(0))
    node T_185939 = eq(T_185938, UInt<1>(0))
    node T_185940 = and(tlb_hit, T_185939)
    node T_185941 = or(bad_va, T_185940)
    resp.xcpt_if := T_185941
    resp.miss := tlb_miss
    node T_185942 = eq(req.bits.passthrough, UInt<1>(0))
    node T_185943 = and(vm_enabled, T_185942)
    node T_185944 = bit(tag_cam.hits, 0)
    node T_185945 = bit(tag_cam.hits, 1)
    node T_185946 = bit(tag_cam.hits, 2)
    node T_185947 = bit(tag_cam.hits, 3)
    node T_185948 = bit(tag_cam.hits, 4)
    node T_185949 = bit(tag_cam.hits, 5)
    node T_185950 = bit(tag_cam.hits, 6)
    node T_185951 = bit(tag_cam.hits, 7)
    accessor T_185952 = tag_ram[UInt<1>(0)]
    accessor T_185953 = tag_ram[UInt<1>(1)]
    accessor T_185954 = tag_ram[UInt<2>(2)]
    accessor T_185955 = tag_ram[UInt<2>(3)]
    accessor T_185956 = tag_ram[UInt<3>(4)]
    accessor T_185957 = tag_ram[UInt<3>(5)]
    accessor T_185958 = tag_ram[UInt<3>(6)]
    accessor T_185959 = tag_ram[UInt<3>(7)]
    wire T_185960 : UInt<1>
    T_185960 := UInt<1>(0)
    when T_185944 : T_185960 := T_185952
    wire T_185961 : UInt<1>
    T_185961 := UInt<1>(0)
    when T_185945 : T_185961 := T_185953
    wire T_185962 : UInt<1>
    T_185962 := UInt<1>(0)
    when T_185946 : T_185962 := T_185954
    wire T_185963 : UInt<1>
    T_185963 := UInt<1>(0)
    when T_185947 : T_185963 := T_185955
    wire T_185964 : UInt<1>
    T_185964 := UInt<1>(0)
    when T_185948 : T_185964 := T_185956
    wire T_185965 : UInt<1>
    T_185965 := UInt<1>(0)
    when T_185949 : T_185965 := T_185957
    wire T_185966 : UInt<1>
    T_185966 := UInt<1>(0)
    when T_185950 : T_185966 := T_185958
    wire T_185967 : UInt<1>
    T_185967 := UInt<1>(0)
    when T_185951 : T_185967 := T_185959
    node T_185968 = or(T_185960, T_185961)
    node T_185969 = or(T_185968, T_185962)
    node T_185970 = or(T_185969, T_185963)
    node T_185971 = or(T_185970, T_185964)
    node T_185972 = or(T_185971, T_185965)
    node T_185973 = or(T_185972, T_185966)
    node T_185974 = or(T_185973, T_185967)
    wire T_185975 : UInt<20>
    node T_185976 = bits(T_185974, 19, 0)
    T_185975 := T_185976
    node T_185977 = bits(req.bits.vpn, 19, 0)
    wire T_185978 : UInt<20>
    T_185978 := T_185977
    when T_185943 : T_185978 := T_185975
    resp.ppn := T_185978
    resp.hit_idx := tag_cam.hits
    node T_185979 = and(req.ready, req.valid)
    node T_185980 = or(ptw.invalidate, T_185979)
    tag_cam.clear := T_185980
    node T_185981 = cat(valid_array[7], valid_array[6])
    node T_185982 = cat(valid_array[5], valid_array[4])
    node T_185983 = cat(T_185981, T_185982)
    node T_185984 = cat(valid_array[3], valid_array[2])
    node T_185985 = cat(valid_array[1], valid_array[0])
    node T_185986 = cat(T_185984, T_185985)
    node T_185987 = cat(T_185983, T_185986)
    node T_185988 = not(T_185987)
    node T_185989 = not(tag_hits)
    node T_185990 = and(tag_cam.hits, T_185989)
    node T_185991 = or(T_185988, T_185990)
    tag_cam.clear_mask := T_185991
    when ptw.invalidate : tag_cam.clear_mask := SInt<1>(-1)
    node T_185992 = eq(state, UInt<2>(1))
    ptw.req.valid := T_185992
    ptw.req.bits.addr := r_refill_tag
    ptw.req.bits.prv := ptw.status.prv
    ptw.req.bits.store := r_req.store
    ptw.req.bits.fetch := r_req.instruction
    
    
    node T_185993 = and(req.ready, req.valid)
    node T_185994 = and(T_185993, tlb_miss)
    when T_185994 : 
      state := UInt<2>(1)
      r_refill_tag := lookup_tag
      r_refill_waddr := repl_waddr
      r_req := req.bits
    
    node T_185995 = eq(state, UInt<2>(1))
    when T_185995 : 
      when ptw.invalidate : state := UInt<2>(0)
      when ptw.req.ready : 
        state := UInt<2>(2)
        when ptw.invalidate : state := UInt<2>(3)
    
    
    node T_185996 = eq(state, UInt<2>(2))
    node T_185997 = and(T_185996, ptw.invalidate)
    when T_185997 : state := UInt<2>(3)
    when ptw.resp.valid : state := UInt<2>(0)
  module MetadataArray_144779 : 
    input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}
    input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output resp : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}[4]
    
    wire T_185998 : UInt<3>[3]
    T_185998[0] := UInt<3>(0)
    T_185998[1] := UInt<3>(1)
    T_185998[2] := UInt<3>(2)
    wire T_185999 : UInt<2>[2]
    T_185999[0] := UInt<2>(0)
    T_185999[1] := UInt<2>(1)
    wire T_186000 : UInt<2>[3]
    T_186000[0] := UInt<2>(1)
    T_186000[1] := UInt<2>(2)
    T_186000[2] := UInt<2>(3)
    wire T_186001 : UInt<2>[2]
    T_186001[0] := UInt<2>(2)
    T_186001[1] := UInt<2>(3)
    wire T_186002 : UInt<2>[1]
    T_186002[0] := UInt<2>(3)
    wire T_186003 : UInt<3>[3]
    T_186003[0] := UInt<3>(0)
    T_186003[1] := UInt<3>(1)
    T_186003[2] := UInt<3>(2)
    wire T_186004 : UInt<2>[2]
    T_186004[0] := UInt<2>(0)
    T_186004[1] := UInt<2>(1)
    wire T_186005 : UInt<2>[3]
    T_186005[0] := UInt<2>(1)
    T_186005[1] := UInt<2>(2)
    T_186005[2] := UInt<2>(3)
    wire T_186006 : UInt<2>[2]
    T_186006[0] := UInt<2>(2)
    T_186006[1] := UInt<2>(3)
    wire T_186007 : UInt<2>[1]
    T_186007[0] := UInt<2>(3)
    wire T_186008 : UInt<3>[3]
    T_186008[0] := UInt<3>(0)
    T_186008[1] := UInt<3>(1)
    T_186008[2] := UInt<3>(2)
    wire T_186009 : UInt<2>[2]
    T_186009[0] := UInt<2>(0)
    T_186009[1] := UInt<2>(1)
    wire T_186010 : UInt<2>[3]
    T_186010[0] := UInt<2>(1)
    T_186010[1] := UInt<2>(2)
    T_186010[2] := UInt<2>(3)
    wire T_186011 : UInt<2>[2]
    T_186011[0] := UInt<2>(2)
    T_186011[1] := UInt<2>(3)
    wire T_186012 : UInt<2>[1]
    T_186012[0] := UInt<2>(3)
    wire T_186013 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_186013.state := UInt<2>(0)
    wire T_186014 : UInt<3>[3]
    T_186014[0] := UInt<3>(0)
    T_186014[1] := UInt<3>(1)
    T_186014[2] := UInt<3>(2)
    wire T_186015 : UInt<2>[2]
    T_186015[0] := UInt<2>(0)
    T_186015[1] := UInt<2>(1)
    wire T_186016 : UInt<2>[3]
    T_186016[0] := UInt<2>(1)
    T_186016[1] := UInt<2>(2)
    T_186016[2] := UInt<2>(3)
    wire T_186017 : UInt<2>[2]
    T_186017[0] := UInt<2>(2)
    T_186017[1] := UInt<2>(3)
    wire T_186018 : UInt<2>[1]
    T_186018[0] := UInt<2>(3)
    wire T_186019 : UInt<3>[3]
    T_186019[0] := UInt<3>(0)
    T_186019[1] := UInt<3>(1)
    T_186019[2] := UInt<3>(2)
    wire T_186020 : UInt<2>[2]
    T_186020[0] := UInt<2>(0)
    T_186020[1] := UInt<2>(1)
    wire T_186021 : UInt<2>[3]
    T_186021[0] := UInt<2>(1)
    T_186021[1] := UInt<2>(2)
    T_186021[2] := UInt<2>(3)
    wire T_186022 : UInt<2>[2]
    T_186022[0] := UInt<2>(2)
    T_186022[1] := UInt<2>(3)
    wire T_186023 : UInt<2>[1]
    T_186023[0] := UInt<2>(3)
    wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    rstVal.tag := UInt<1>(0)
    rstVal.coh := T_186013
    wire T_186024 : UInt<3>[3]
    T_186024[0] := UInt<3>(0)
    T_186024[1] := UInt<3>(1)
    T_186024[2] := UInt<3>(2)
    wire T_186025 : UInt<2>[2]
    T_186025[0] := UInt<2>(0)
    T_186025[1] := UInt<2>(1)
    wire T_186026 : UInt<2>[3]
    T_186026[0] := UInt<2>(1)
    T_186026[1] := UInt<2>(2)
    T_186026[2] := UInt<2>(3)
    wire T_186027 : UInt<2>[2]
    T_186027[0] := UInt<2>(2)
    T_186027[1] := UInt<2>(3)
    wire T_186028 : UInt<2>[1]
    T_186028[0] := UInt<2>(3)
    wire T_186029 : UInt<3>[3]
    T_186029[0] := UInt<3>(0)
    T_186029[1] := UInt<3>(1)
    T_186029[2] := UInt<3>(2)
    wire T_186030 : UInt<2>[2]
    T_186030[0] := UInt<2>(0)
    T_186030[1] := UInt<2>(1)
    wire T_186031 : UInt<2>[3]
    T_186031[0] := UInt<2>(1)
    T_186031[1] := UInt<2>(2)
    T_186031[2] := UInt<2>(3)
    wire T_186032 : UInt<2>[2]
    T_186032[0] := UInt<2>(2)
    T_186032[1] := UInt<2>(3)
    wire T_186033 : UInt<2>[1]
    T_186033[0] := UInt<2>(3)
    wire T_186034 : UInt<3>[3]
    T_186034[0] := UInt<3>(0)
    T_186034[1] := UInt<3>(1)
    T_186034[2] := UInt<3>(2)
    wire T_186035 : UInt<2>[2]
    T_186035[0] := UInt<2>(0)
    T_186035[1] := UInt<2>(1)
    wire T_186036 : UInt<2>[3]
    T_186036[0] := UInt<2>(1)
    T_186036[1] := UInt<2>(2)
    T_186036[2] := UInt<2>(3)
    wire T_186037 : UInt<2>[2]
    T_186037[0] := UInt<2>(2)
    T_186037[1] := UInt<2>(3)
    wire T_186038 : UInt<2>[1]
    T_186038[0] := UInt<2>(3)
    wire T_186039 : UInt<3>[3]
    T_186039[0] := UInt<3>(0)
    T_186039[1] := UInt<3>(1)
    T_186039[2] := UInt<3>(2)
    wire T_186040 : UInt<2>[2]
    T_186040[0] := UInt<2>(0)
    T_186040[1] := UInt<2>(1)
    wire T_186041 : UInt<2>[3]
    T_186041[0] := UInt<2>(1)
    T_186041[1] := UInt<2>(2)
    T_186041[2] := UInt<2>(3)
    wire T_186042 : UInt<2>[2]
    T_186042[0] := UInt<2>(2)
    T_186042[1] := UInt<2>(3)
    wire T_186043 : UInt<2>[1]
    T_186043[0] := UInt<2>(3)
    wire T_186044 : UInt<3>[3]
    T_186044[0] := UInt<3>(0)
    T_186044[1] := UInt<3>(1)
    T_186044[2] := UInt<3>(2)
    wire T_186045 : UInt<2>[2]
    T_186045[0] := UInt<2>(0)
    T_186045[1] := UInt<2>(1)
    wire T_186046 : UInt<2>[3]
    T_186046[0] := UInt<2>(1)
    T_186046[1] := UInt<2>(2)
    T_186046[2] := UInt<2>(3)
    wire T_186047 : UInt<2>[2]
    T_186047[0] := UInt<2>(2)
    T_186047[1] := UInt<2>(3)
    wire T_186048 : UInt<2>[1]
    T_186048[0] := UInt<2>(3)
    wire T_186049 : UInt<3>[3]
    T_186049[0] := UInt<3>(0)
    T_186049[1] := UInt<3>(1)
    T_186049[2] := UInt<3>(2)
    wire T_186050 : UInt<2>[2]
    T_186050[0] := UInt<2>(0)
    T_186050[1] := UInt<2>(1)
    wire T_186051 : UInt<2>[3]
    T_186051[0] := UInt<2>(1)
    T_186051[1] := UInt<2>(2)
    T_186051[2] := UInt<2>(3)
    wire T_186052 : UInt<2>[2]
    T_186052[0] := UInt<2>(2)
    T_186052[1] := UInt<2>(3)
    wire T_186053 : UInt<2>[1]
    T_186053[0] := UInt<2>(3)
    wire T_186054 : UInt<3>[3]
    T_186054[0] := UInt<3>(0)
    T_186054[1] := UInt<3>(1)
    T_186054[2] := UInt<3>(2)
    wire T_186055 : UInt<2>[2]
    T_186055[0] := UInt<2>(0)
    T_186055[1] := UInt<2>(1)
    wire T_186056 : UInt<2>[3]
    T_186056[0] := UInt<2>(1)
    T_186056[1] := UInt<2>(2)
    T_186056[2] := UInt<2>(3)
    wire T_186057 : UInt<2>[2]
    T_186057[0] := UInt<2>(2)
    T_186057[1] := UInt<2>(3)
    wire T_186058 : UInt<2>[1]
    T_186058[0] := UInt<2>(3)
    wire T_186059 : UInt<3>[3]
    T_186059[0] := UInt<3>(0)
    T_186059[1] := UInt<3>(1)
    T_186059[2] := UInt<3>(2)
    wire T_186060 : UInt<2>[2]
    T_186060[0] := UInt<2>(0)
    T_186060[1] := UInt<2>(1)
    wire T_186061 : UInt<2>[3]
    T_186061[0] := UInt<2>(1)
    T_186061[1] := UInt<2>(2)
    T_186061[2] := UInt<2>(3)
    wire T_186062 : UInt<2>[2]
    T_186062[0] := UInt<2>(2)
    T_186062[1] := UInt<2>(3)
    wire T_186063 : UInt<2>[1]
    T_186063[0] := UInt<2>(3)
    wire T_186064 : UInt<3>[3]
    T_186064[0] := UInt<3>(0)
    T_186064[1] := UInt<3>(1)
    T_186064[2] := UInt<3>(2)
    wire T_186065 : UInt<2>[2]
    T_186065[0] := UInt<2>(0)
    T_186065[1] := UInt<2>(1)
    wire T_186066 : UInt<2>[3]
    T_186066[0] := UInt<2>(1)
    T_186066[1] := UInt<2>(2)
    T_186066[2] := UInt<2>(3)
    wire T_186067 : UInt<2>[2]
    T_186067[0] := UInt<2>(2)
    T_186067[1] := UInt<2>(3)
    wire T_186068 : UInt<2>[1]
    T_186068[0] := UInt<2>(3)
    wire T_186069 : UInt<3>[3]
    T_186069[0] := UInt<3>(0)
    T_186069[1] := UInt<3>(1)
    T_186069[2] := UInt<3>(2)
    wire T_186070 : UInt<2>[2]
    T_186070[0] := UInt<2>(0)
    T_186070[1] := UInt<2>(1)
    wire T_186071 : UInt<2>[3]
    T_186071[0] := UInt<2>(1)
    T_186071[1] := UInt<2>(2)
    T_186071[2] := UInt<2>(3)
    wire T_186072 : UInt<2>[2]
    T_186072[0] := UInt<2>(2)
    T_186072[1] := UInt<2>(3)
    wire T_186073 : UInt<2>[1]
    T_186073[0] := UInt<2>(3)
    wire resp : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}[4]
    resp[0] := T_186074
    resp[1] := T_186075
    resp[2] := T_186076
    resp[3] := T_186077
    reg rst_cnt : UInt<7>
    onreset rst_cnt := UInt<7>(0)
    node rst = lt(rst_cnt, UInt<7>(64))
    wire waddr : UInt<6>
    waddr := write.bits.idx
    when rst : waddr := rst_cnt
    wire T_186078 : UInt<3>[3]
    T_186078[0] := UInt<3>(0)
    T_186078[1] := UInt<3>(1)
    T_186078[2] := UInt<3>(2)
    wire T_186079 : UInt<2>[2]
    T_186079[0] := UInt<2>(0)
    T_186079[1] := UInt<2>(1)
    wire T_186080 : UInt<2>[3]
    T_186080[0] := UInt<2>(1)
    T_186080[1] := UInt<2>(2)
    T_186080[2] := UInt<2>(3)
    wire T_186081 : UInt<2>[2]
    T_186081[0] := UInt<2>(2)
    T_186081[1] := UInt<2>(3)
    wire T_186082 : UInt<2>[1]
    T_186082[0] := UInt<2>(3)
    wire T_186083 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    T_186083 := write.bits.data
    when rst : T_186083 := rstVal
    node T_186084 = cat(T_186083.coh.state, UInt<1>(0))
    node T_186085 = cat(T_186083.tag, T_186084)
    node T_186086 = cat(T_186085, UInt<4>(0))
    node T_186087 = cat(UInt<1>(0), T_186083.coh.state)
    node T_186088 = cat(T_186087, UInt<2>(0))
    node T_186089 = cat(T_186088, UInt<4>(0))
    node wdata = cat(T_186086, T_186089)
    node T_186090 = asSInt(write.bits.way_en)
    wire T_186091 : SInt<4>
    T_186091 := T_186090
    when rst : T_186091 := SInt<1>(-1)
    node wmask = asUInt(T_186091)
    when rst : 
      node T_186092 = addw(rst_cnt, UInt<1>(1))
      rst_cnt := T_186092
    cmem T_186093 : UInt<144>[64]
    
    node T_186094 = or(rst, write.valid)
    when T_186094 : 
      node T_186095 = cat(wdata, wdata)
      node T_186096 = cat(T_186095, T_186095)
      node T_186097 = bit(wmask, 0)
      node T_186098 = bit(wmask, 1)
      node T_186099 = bit(wmask, 2)
      node T_186100 = bit(wmask, 3)
      wire T_186101 : UInt<1>[4]
      T_186101[0] := T_186097
      T_186101[1] := T_186098
      T_186101[2] := T_186099
      T_186101[3] := T_186100
      node T_186102 = subw(UInt<36>(0), UInt<6>(36))
      node T_186103 = subw(UInt<36>(0), UInt<6>(36))
      node T_186104 = subw(UInt<36>(0), UInt<6>(36))
      node T_186105 = subw(UInt<36>(0), UInt<6>(36))
      wire T_186106 : UInt<36>[4]
      T_186106[0] := T_186102
      T_186106[1] := T_186103
      T_186106[2] := T_186104
      T_186106[3] := T_186105
      node T_186107 = cat(T_186106[3], T_186106[2])
      node T_186108 = cat(T_186106[1], T_186106[0])
      node T_186109 = cat(T_186107, T_186108)
      accessor T_186110 = T_186093[waddr]
      node T_186111 = not(T_186109)
      node T_186112 = and(T_186110, T_186111)
      node T_186113 = and(T_186096, T_186109)
      node T_186114 = or(T_186112, T_186113)
      wire T_186115 : UInt<144>
      node T_186116 = bits(T_186114, 143, 0)
      T_186115 := T_186116
      accessor T_186117 = T_186093[waddr]
      T_186117 := T_186115
    reg T_186118 : UInt<6>
    when read.valid : T_186118 := read.bits.idx
    accessor tags = T_186093[T_186118]
    wire T_186119 : UInt<3>[3]
    T_186119[0] := UInt<3>(0)
    T_186119[1] := UInt<3>(1)
    T_186119[2] := UInt<3>(2)
    wire T_186120 : UInt<2>[2]
    T_186120[0] := UInt<2>(0)
    T_186120[1] := UInt<2>(1)
    wire T_186121 : UInt<2>[3]
    T_186121[0] := UInt<2>(1)
    T_186121[1] := UInt<2>(2)
    T_186121[2] := UInt<2>(3)
    wire T_186122 : UInt<2>[2]
    T_186122[0] := UInt<2>(2)
    T_186122[1] := UInt<2>(3)
    wire T_186123 : UInt<2>[1]
    T_186123[0] := UInt<2>(3)
    wire T_186124 : UInt<3>[3]
    T_186124[0] := UInt<3>(0)
    T_186124[1] := UInt<3>(1)
    T_186124[2] := UInt<3>(2)
    wire T_186125 : UInt<2>[2]
    T_186125[0] := UInt<2>(0)
    T_186125[1] := UInt<2>(1)
    wire T_186126 : UInt<2>[3]
    T_186126[0] := UInt<2>(1)
    T_186126[1] := UInt<2>(2)
    T_186126[2] := UInt<2>(3)
    wire T_186127 : UInt<2>[2]
    T_186127[0] := UInt<2>(2)
    T_186127[1] := UInt<2>(3)
    wire T_186128 : UInt<2>[1]
    T_186128[0] := UInt<2>(3)
    wire T_186129 : UInt<3>[3]
    T_186129[0] := UInt<3>(0)
    T_186129[1] := UInt<3>(1)
    T_186129[2] := UInt<3>(2)
    wire T_186130 : UInt<2>[2]
    T_186130[0] := UInt<2>(0)
    T_186130[1] := UInt<2>(1)
    wire T_186131 : UInt<2>[3]
    T_186131[0] := UInt<2>(1)
    T_186131[1] := UInt<2>(2)
    T_186131[2] := UInt<2>(3)
    wire T_186132 : UInt<2>[2]
    T_186132[0] := UInt<2>(2)
    T_186132[1] := UInt<2>(3)
    wire T_186133 : UInt<2>[1]
    T_186133[0] := UInt<2>(3)
    wire T_186134 : UInt<3>[3]
    T_186134[0] := UInt<3>(0)
    T_186134[1] := UInt<3>(1)
    T_186134[2] := UInt<3>(2)
    wire T_186135 : UInt<2>[2]
    T_186135[0] := UInt<2>(0)
    T_186135[1] := UInt<2>(1)
    wire T_186136 : UInt<2>[3]
    T_186136[0] := UInt<2>(1)
    T_186136[1] := UInt<2>(2)
    T_186136[2] := UInt<2>(3)
    wire T_186137 : UInt<2>[2]
    T_186137[0] := UInt<2>(2)
    T_186137[1] := UInt<2>(3)
    wire T_186138 : UInt<2>[1]
    T_186138[0] := UInt<2>(3)
    wire T_186139 : UInt<3>[3]
    T_186139[0] := UInt<3>(0)
    T_186139[1] := UInt<3>(1)
    T_186139[2] := UInt<3>(2)
    wire T_186140 : UInt<2>[2]
    T_186140[0] := UInt<2>(0)
    T_186140[1] := UInt<2>(1)
    wire T_186141 : UInt<2>[3]
    T_186141[0] := UInt<2>(1)
    T_186141[1] := UInt<2>(2)
    T_186141[2] := UInt<2>(3)
    wire T_186142 : UInt<2>[2]
    T_186142[0] := UInt<2>(2)
    T_186142[1] := UInt<2>(3)
    wire T_186143 : UInt<2>[1]
    T_186143[0] := UInt<2>(3)
    wire T_186144 : UInt<3>[3]
    T_186144[0] := UInt<3>(0)
    T_186144[1] := UInt<3>(1)
    T_186144[2] := UInt<3>(2)
    wire T_186145 : UInt<2>[2]
    T_186145[0] := UInt<2>(0)
    T_186145[1] := UInt<2>(1)
    wire T_186146 : UInt<2>[3]
    T_186146[0] := UInt<2>(1)
    T_186146[1] := UInt<2>(2)
    T_186146[2] := UInt<2>(3)
    wire T_186147 : UInt<2>[2]
    T_186147[0] := UInt<2>(2)
    T_186147[1] := UInt<2>(3)
    wire T_186148 : UInt<2>[1]
    T_186148[0] := UInt<2>(3)
    wire T_186149 : UInt<3>[3]
    T_186149[0] := UInt<3>(0)
    T_186149[1] := UInt<3>(1)
    T_186149[2] := UInt<3>(2)
    wire T_186150 : UInt<2>[2]
    T_186150[0] := UInt<2>(0)
    T_186150[1] := UInt<2>(1)
    wire T_186151 : UInt<2>[3]
    T_186151[0] := UInt<2>(1)
    T_186151[1] := UInt<2>(2)
    T_186151[2] := UInt<2>(3)
    wire T_186152 : UInt<2>[2]
    T_186152[0] := UInt<2>(2)
    T_186152[1] := UInt<2>(3)
    wire T_186153 : UInt<2>[1]
    T_186153[0] := UInt<2>(3)
    wire T_186154 : UInt<3>[3]
    T_186154[0] := UInt<3>(0)
    T_186154[1] := UInt<3>(1)
    T_186154[2] := UInt<3>(2)
    wire T_186155 : UInt<2>[2]
    T_186155[0] := UInt<2>(0)
    T_186155[1] := UInt<2>(1)
    wire T_186156 : UInt<2>[3]
    T_186156[0] := UInt<2>(1)
    T_186156[1] := UInt<2>(2)
    T_186156[2] := UInt<2>(3)
    wire T_186157 : UInt<2>[2]
    T_186157[0] := UInt<2>(2)
    T_186157[1] := UInt<2>(3)
    wire T_186158 : UInt<2>[1]
    T_186158[0] := UInt<2>(3)
    wire T_186159 : UInt<3>[3]
    T_186159[0] := UInt<3>(0)
    T_186159[1] := UInt<3>(1)
    T_186159[2] := UInt<3>(2)
    wire T_186160 : UInt<2>[2]
    T_186160[0] := UInt<2>(0)
    T_186160[1] := UInt<2>(1)
    wire T_186161 : UInt<2>[3]
    T_186161[0] := UInt<2>(1)
    T_186161[1] := UInt<2>(2)
    T_186161[2] := UInt<2>(3)
    wire T_186162 : UInt<2>[2]
    T_186162[0] := UInt<2>(2)
    T_186162[1] := UInt<2>(3)
    wire T_186163 : UInt<2>[1]
    T_186163[0] := UInt<2>(3)
    wire T_186164 : UInt<3>[3]
    T_186164[0] := UInt<3>(0)
    T_186164[1] := UInt<3>(1)
    T_186164[2] := UInt<3>(2)
    wire T_186165 : UInt<2>[2]
    T_186165[0] := UInt<2>(0)
    T_186165[1] := UInt<2>(1)
    wire T_186166 : UInt<2>[3]
    T_186166[0] := UInt<2>(1)
    T_186166[1] := UInt<2>(2)
    T_186166[2] := UInt<2>(3)
    wire T_186167 : UInt<2>[2]
    T_186167[0] := UInt<2>(2)
    T_186167[1] := UInt<2>(3)
    wire T_186168 : UInt<2>[1]
    T_186168[0] := UInt<2>(3)
    wire T_186169 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}[4]
    node T_186170 = bits(tags, 0, 0)
    T_186169[0].coh.makeVoluntaryWriteback$default$4 := T_186170
    node T_186171 = bits(tags, 1, 1)
    T_186169[0].coh.makeVoluntaryWriteback$default$3 := T_186171
    node T_186172 = bits(tags, 2, 2)
    T_186169[0].coh.makeVoluntaryRelease$default$5 := T_186172
    node T_186173 = bits(tags, 3, 3)
    T_186169[0].coh.makeVoluntaryRelease$default$4 := T_186173
    node T_186174 = bits(tags, 4, 4)
    T_186169[0].coh.makeRelease$default$3 := T_186174
    node T_186175 = bits(tags, 5, 5)
    T_186169[0].coh.makeRelease$default$2 := T_186175
    node T_186176 = bits(tags, 7, 6)
    T_186169[0].coh.state := T_186176
    node T_186177 = bits(tags, 8, 8)
    T_186169[0].coh.makeVoluntaryWriteback$default$4 := T_186177
    node T_186178 = bits(tags, 9, 9)
    T_186169[0].coh.makeVoluntaryWriteback$default$3 := T_186178
    node T_186179 = bits(tags, 10, 10)
    T_186169[0].coh.makeVoluntaryRelease$default$5 := T_186179
    node T_186180 = bits(tags, 11, 11)
    T_186169[0].coh.makeVoluntaryRelease$default$4 := T_186180
    node T_186181 = bits(tags, 12, 12)
    T_186169[0].coh.makeRelease$default$3 := T_186181
    node T_186182 = bits(tags, 13, 13)
    T_186169[0].coh.makeRelease$default$2 := T_186182
    node T_186183 = bits(tags, 15, 14)
    T_186169[0].coh.state := T_186183
    node T_186184 = bits(tags, 35, 16)
    T_186169[0].tag := T_186184
    node T_186185 = bits(tags, 36, 36)
    T_186169[1].coh.makeVoluntaryWriteback$default$4 := T_186185
    node T_186186 = bits(tags, 37, 37)
    T_186169[1].coh.makeVoluntaryWriteback$default$3 := T_186186
    node T_186187 = bits(tags, 38, 38)
    T_186169[1].coh.makeVoluntaryRelease$default$5 := T_186187
    node T_186188 = bits(tags, 39, 39)
    T_186169[1].coh.makeVoluntaryRelease$default$4 := T_186188
    node T_186189 = bits(tags, 40, 40)
    T_186169[1].coh.makeRelease$default$3 := T_186189
    node T_186190 = bits(tags, 41, 41)
    T_186169[1].coh.makeRelease$default$2 := T_186190
    node T_186191 = bits(tags, 43, 42)
    T_186169[1].coh.state := T_186191
    node T_186192 = bits(tags, 44, 44)
    T_186169[1].coh.makeVoluntaryWriteback$default$4 := T_186192
    node T_186193 = bits(tags, 45, 45)
    T_186169[1].coh.makeVoluntaryWriteback$default$3 := T_186193
    node T_186194 = bits(tags, 46, 46)
    T_186169[1].coh.makeVoluntaryRelease$default$5 := T_186194
    node T_186195 = bits(tags, 47, 47)
    T_186169[1].coh.makeVoluntaryRelease$default$4 := T_186195
    node T_186196 = bits(tags, 48, 48)
    T_186169[1].coh.makeRelease$default$3 := T_186196
    node T_186197 = bits(tags, 49, 49)
    T_186169[1].coh.makeRelease$default$2 := T_186197
    node T_186198 = bits(tags, 51, 50)
    T_186169[1].coh.state := T_186198
    node T_186199 = bits(tags, 71, 52)
    T_186169[1].tag := T_186199
    node T_186200 = bits(tags, 72, 72)
    T_186169[2].coh.makeVoluntaryWriteback$default$4 := T_186200
    node T_186201 = bits(tags, 73, 73)
    T_186169[2].coh.makeVoluntaryWriteback$default$3 := T_186201
    node T_186202 = bits(tags, 74, 74)
    T_186169[2].coh.makeVoluntaryRelease$default$5 := T_186202
    node T_186203 = bits(tags, 75, 75)
    T_186169[2].coh.makeVoluntaryRelease$default$4 := T_186203
    node T_186204 = bits(tags, 76, 76)
    T_186169[2].coh.makeRelease$default$3 := T_186204
    node T_186205 = bits(tags, 77, 77)
    T_186169[2].coh.makeRelease$default$2 := T_186205
    node T_186206 = bits(tags, 79, 78)
    T_186169[2].coh.state := T_186206
    node T_186207 = bits(tags, 80, 80)
    T_186169[2].coh.makeVoluntaryWriteback$default$4 := T_186207
    node T_186208 = bits(tags, 81, 81)
    T_186169[2].coh.makeVoluntaryWriteback$default$3 := T_186208
    node T_186209 = bits(tags, 82, 82)
    T_186169[2].coh.makeVoluntaryRelease$default$5 := T_186209
    node T_186210 = bits(tags, 83, 83)
    T_186169[2].coh.makeVoluntaryRelease$default$4 := T_186210
    node T_186211 = bits(tags, 84, 84)
    T_186169[2].coh.makeRelease$default$3 := T_186211
    node T_186212 = bits(tags, 85, 85)
    T_186169[2].coh.makeRelease$default$2 := T_186212
    node T_186213 = bits(tags, 87, 86)
    T_186169[2].coh.state := T_186213
    node T_186214 = bits(tags, 107, 88)
    T_186169[2].tag := T_186214
    node T_186215 = bits(tags, 108, 108)
    T_186169[3].coh.makeVoluntaryWriteback$default$4 := T_186215
    node T_186216 = bits(tags, 109, 109)
    T_186169[3].coh.makeVoluntaryWriteback$default$3 := T_186216
    node T_186217 = bits(tags, 110, 110)
    T_186169[3].coh.makeVoluntaryRelease$default$5 := T_186217
    node T_186218 = bits(tags, 111, 111)
    T_186169[3].coh.makeVoluntaryRelease$default$4 := T_186218
    node T_186219 = bits(tags, 112, 112)
    T_186169[3].coh.makeRelease$default$3 := T_186219
    node T_186220 = bits(tags, 113, 113)
    T_186169[3].coh.makeRelease$default$2 := T_186220
    node T_186221 = bits(tags, 115, 114)
    T_186169[3].coh.state := T_186221
    node T_186222 = bits(tags, 116, 116)
    T_186169[3].coh.makeVoluntaryWriteback$default$4 := T_186222
    node T_186223 = bits(tags, 117, 117)
    T_186169[3].coh.makeVoluntaryWriteback$default$3 := T_186223
    node T_186224 = bits(tags, 118, 118)
    T_186169[3].coh.makeVoluntaryRelease$default$5 := T_186224
    node T_186225 = bits(tags, 119, 119)
    T_186169[3].coh.makeVoluntaryRelease$default$4 := T_186225
    node T_186226 = bits(tags, 120, 120)
    T_186169[3].coh.makeRelease$default$3 := T_186226
    node T_186227 = bits(tags, 121, 121)
    T_186169[3].coh.makeRelease$default$2 := T_186227
    node T_186228 = bits(tags, 123, 122)
    T_186169[3].coh.state := T_186228
    node T_186229 = bits(tags, 143, 124)
    T_186169[3].tag := T_186229
    resp[0] := T_186169[0]
    resp[1] := T_186169[1]
    resp[2] := T_186169[2]
    resp[3] := T_186169[3]
    node T_186230 = eq(rst, UInt<1>(0))
    node T_186231 = eq(write.valid, UInt<1>(0))
    node T_186232 = and(T_186230, T_186231)
    read.ready := T_186232
    node T_186233 = eq(rst, UInt<1>(0))
    write.ready := T_186233
  module Arbiter_144889 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}
    output chosen : UInt<3>
    
    wire T_186234 : UInt<3>
    node T_186235 = or(UInt<1>(0), in[0].valid)
    node T_186236 = eq(T_186235, UInt<1>(0))
    node T_186237 = or(UInt<1>(0), in[0].valid)
    node T_186238 = or(T_186237, in[1].valid)
    node T_186239 = eq(T_186238, UInt<1>(0))
    node T_186240 = or(UInt<1>(0), in[0].valid)
    node T_186241 = or(T_186240, in[1].valid)
    node T_186242 = or(T_186241, in[2].valid)
    node T_186243 = eq(T_186242, UInt<1>(0))
    node T_186244 = or(UInt<1>(0), in[0].valid)
    node T_186245 = or(T_186244, in[1].valid)
    node T_186246 = or(T_186245, in[2].valid)
    node T_186247 = or(T_186246, in[3].valid)
    node T_186248 = eq(T_186247, UInt<1>(0))
    node T_186249 = eq(UInt<3>(4), UInt<1>(0))
    wire T_186250 : UInt<1>
    T_186250 := UInt<1>(1)
    when UInt<1>(0) : T_186250 := T_186249
    node T_186251 = and(T_186250, out.ready)
    in[0].ready := T_186251
    node T_186252 = eq(UInt<3>(4), UInt<1>(1))
    wire T_186253 : UInt<1>
    T_186253 := T_186236
    when UInt<1>(0) : T_186253 := T_186252
    node T_186254 = and(T_186253, out.ready)
    in[1].ready := T_186254
    node T_186255 = eq(UInt<3>(4), UInt<2>(2))
    wire T_186256 : UInt<1>
    T_186256 := T_186239
    when UInt<1>(0) : T_186256 := T_186255
    node T_186257 = and(T_186256, out.ready)
    in[2].ready := T_186257
    node T_186258 = eq(UInt<3>(4), UInt<2>(3))
    wire T_186259 : UInt<1>
    T_186259 := T_186243
    when UInt<1>(0) : T_186259 := T_186258
    node T_186260 = and(T_186259, out.ready)
    in[3].ready := T_186260
    node T_186261 = eq(UInt<3>(4), UInt<3>(4))
    wire T_186262 : UInt<1>
    T_186262 := T_186248
    when UInt<1>(0) : T_186262 := T_186261
    node T_186263 = and(T_186262, out.ready)
    in[4].ready := T_186263
    accessor T_186264 = in[T_186234]
    out.valid := T_186264.valid
    accessor T_186265 = in[T_186234]
    out.bits := T_186265.bits
    chosen := T_186234
    wire T_186266 : UInt<3>
    T_186266 := UInt<3>(4)
    when in[3].valid : T_186266 := UInt<2>(3)
    wire T_186267 : UInt<3>
    T_186267 := T_186266
    when in[2].valid : T_186267 := UInt<2>(2)
    wire T_186268 : UInt<3>
    T_186268 := T_186267
    when in[1].valid : T_186268 := UInt<1>(1)
    wire T_186269 : UInt<3>
    T_186269 := T_186268
    when in[0].valid : T_186269 := UInt<1>(0)
    wire T_186270 : UInt<3>
    T_186270 := T_186269
    when UInt<1>(0) : T_186270 := UInt<3>(4)
    T_186234 := T_186270
  module Arbiter_145479 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}}}
    output chosen : UInt<1>
    
    wire T_186271 : UInt<3>[3]
    T_186271[0] := UInt<3>(0)
    T_186271[1] := UInt<3>(1)
    T_186271[2] := UInt<3>(2)
    wire T_186272 : UInt<2>[2]
    T_186272[0] := UInt<2>(0)
    T_186272[1] := UInt<2>(1)
    wire T_186273 : UInt<2>[3]
    T_186273[0] := UInt<2>(1)
    T_186273[1] := UInt<2>(2)
    T_186273[2] := UInt<2>(3)
    wire T_186274 : UInt<2>[2]
    T_186274[0] := UInt<2>(2)
    T_186274[1] := UInt<2>(3)
    wire T_186275 : UInt<2>[1]
    T_186275[0] := UInt<2>(3)
    wire T_186276 : UInt<3>[3]
    T_186276[0] := UInt<3>(0)
    T_186276[1] := UInt<3>(1)
    T_186276[2] := UInt<3>(2)
    wire T_186277 : UInt<2>[2]
    T_186277[0] := UInt<2>(0)
    T_186277[1] := UInt<2>(1)
    wire T_186278 : UInt<2>[3]
    T_186278[0] := UInt<2>(1)
    T_186278[1] := UInt<2>(2)
    T_186278[2] := UInt<2>(3)
    wire T_186279 : UInt<2>[2]
    T_186279[0] := UInt<2>(2)
    T_186279[1] := UInt<2>(3)
    wire T_186280 : UInt<2>[1]
    T_186280[0] := UInt<2>(3)
    wire T_186281 : UInt<3>[3]
    T_186281[0] := UInt<3>(0)
    T_186281[1] := UInt<3>(1)
    T_186281[2] := UInt<3>(2)
    wire T_186282 : UInt<2>[2]
    T_186282[0] := UInt<2>(0)
    T_186282[1] := UInt<2>(1)
    wire T_186283 : UInt<2>[3]
    T_186283[0] := UInt<2>(1)
    T_186283[1] := UInt<2>(2)
    T_186283[2] := UInt<2>(3)
    wire T_186284 : UInt<2>[2]
    T_186284[0] := UInt<2>(2)
    T_186284[1] := UInt<2>(3)
    wire T_186285 : UInt<2>[1]
    T_186285[0] := UInt<2>(3)
    wire T_186286 : UInt<3>[3]
    T_186286[0] := UInt<3>(0)
    T_186286[1] := UInt<3>(1)
    T_186286[2] := UInt<3>(2)
    wire T_186287 : UInt<2>[2]
    T_186287[0] := UInt<2>(0)
    T_186287[1] := UInt<2>(1)
    wire T_186288 : UInt<2>[3]
    T_186288[0] := UInt<2>(1)
    T_186288[1] := UInt<2>(2)
    T_186288[2] := UInt<2>(3)
    wire T_186289 : UInt<2>[2]
    T_186289[0] := UInt<2>(2)
    T_186289[1] := UInt<2>(3)
    wire T_186290 : UInt<2>[1]
    T_186290[0] := UInt<2>(3)
    wire T_186291 : UInt<1>
    node T_186292 = or(UInt<1>(0), in[0].valid)
    node T_186293 = eq(T_186292, UInt<1>(0))
    node T_186294 = eq(UInt<1>(1), UInt<1>(0))
    wire T_186295 : UInt<1>
    T_186295 := UInt<1>(1)
    when UInt<1>(0) : T_186295 := T_186294
    node T_186296 = and(T_186295, out.ready)
    in[0].ready := T_186296
    node T_186297 = eq(UInt<1>(1), UInt<1>(1))
    wire T_186298 : UInt<1>
    T_186298 := T_186293
    when UInt<1>(0) : T_186298 := T_186297
    node T_186299 = and(T_186298, out.ready)
    in[1].ready := T_186299
    wire T_186300 : UInt<3>[3]
    T_186300[0] := UInt<3>(0)
    T_186300[1] := UInt<3>(1)
    T_186300[2] := UInt<3>(2)
    wire T_186301 : UInt<2>[2]
    T_186301[0] := UInt<2>(0)
    T_186301[1] := UInt<2>(1)
    wire T_186302 : UInt<2>[3]
    T_186302[0] := UInt<2>(1)
    T_186302[1] := UInt<2>(2)
    T_186302[2] := UInt<2>(3)
    wire T_186303 : UInt<2>[2]
    T_186303[0] := UInt<2>(2)
    T_186303[1] := UInt<2>(3)
    wire T_186304 : UInt<2>[1]
    T_186304[0] := UInt<2>(3)
    accessor T_186305 = in[T_186291]
    out.valid := T_186305.valid
    wire T_186306 : UInt<3>[3]
    T_186306[0] := UInt<3>(0)
    T_186306[1] := UInt<3>(1)
    T_186306[2] := UInt<3>(2)
    wire T_186307 : UInt<2>[2]
    T_186307[0] := UInt<2>(0)
    T_186307[1] := UInt<2>(1)
    wire T_186308 : UInt<2>[3]
    T_186308[0] := UInt<2>(1)
    T_186308[1] := UInt<2>(2)
    T_186308[2] := UInt<2>(3)
    wire T_186309 : UInt<2>[2]
    T_186309[0] := UInt<2>(2)
    T_186309[1] := UInt<2>(3)
    wire T_186310 : UInt<2>[1]
    T_186310[0] := UInt<2>(3)
    accessor T_186311 = in[T_186291]
    out.bits := T_186311.bits
    chosen := T_186291
    wire T_186312 : UInt<1>
    T_186312 := UInt<1>(1)
    when in[0].valid : T_186312 := UInt<1>(0)
    wire T_186313 : UInt<1>
    T_186313 := T_186312
    when UInt<1>(0) : T_186313 := UInt<1>(1)
    T_186291 := T_186313
  module DataArray : 
    input read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}
    input write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}
    output resp : UInt<128>[4]
    
    wire resp : UInt<128>[4]
    resp[0] := T_186314
    resp[1] := T_186315
    resp[2] := T_186316
    resp[3] := T_186317
    node waddr = shr(write.bits.addr, 4)
    node raddr = shr(read.bits.addr, 4)
    node T_186318 = bits(write.bits.way_en, 1, 0)
    node T_186319 = bits(read.bits.way_en, 1, 0)
    wire T_186320 : UInt<128>[2]
    reg T_186321 : UInt<12>
    when read.valid : T_186321 := read.bits.addr
    cmem T_186322 : UInt<128>[256]
    
    
    node T_186323 = eq(T_186318, UInt<1>(0))
    node T_186324 = eq(T_186323, UInt<1>(0))
    node T_186325 = and(T_186324, write.valid)
    node T_186326 = bit(write.bits.wmask, 0)
    node T_186327 = and(T_186325, T_186326)
    when T_186327 : 
      node T_186328 = bits(write.bits.data, 63, 0)
      node T_186329 = cat(T_186328, T_186328)
      node T_186330 = bit(T_186318, 0)
      node T_186331 = bit(T_186318, 1)
      wire T_186332 : UInt<1>[2]
      T_186332[0] := T_186330
      T_186332[1] := T_186331
      node T_186333 = subw(UInt<64>(0), UInt<7>(64))
      node T_186334 = subw(UInt<64>(0), UInt<7>(64))
      wire T_186335 : UInt<64>[2]
      T_186335[0] := T_186333
      T_186335[1] := T_186334
      node T_186336 = cat(T_186335[1], T_186335[0])
      accessor T_186337 = T_186322[waddr]
      node T_186338 = not(T_186336)
      node T_186339 = and(T_186337, T_186338)
      node T_186340 = and(T_186329, T_186336)
      node T_186341 = or(T_186339, T_186340)
      wire T_186342 : UInt<128>
      node T_186343 = bits(T_186341, 127, 0)
      T_186342 := T_186343
      accessor T_186344 = T_186322[waddr]
      T_186344 := T_186342
    node T_186345 = eq(T_186319, UInt<1>(0))
    node T_186346 = eq(T_186345, UInt<1>(0))
    node T_186347 = and(T_186346, read.valid)
    reg T_186348 : UInt<8>
    when T_186347 : T_186348 := raddr
    accessor T_186349 = T_186322[T_186348]
    T_186320[0] := T_186349
    cmem T_186350 : UInt<128>[256]
    
    
    node T_186351 = eq(T_186318, UInt<1>(0))
    node T_186352 = eq(T_186351, UInt<1>(0))
    node T_186353 = and(T_186352, write.valid)
    node T_186354 = bit(write.bits.wmask, 1)
    node T_186355 = and(T_186353, T_186354)
    when T_186355 : 
      node T_186356 = bits(write.bits.data, 127, 64)
      node T_186357 = cat(T_186356, T_186356)
      node T_186358 = bit(T_186318, 0)
      node T_186359 = bit(T_186318, 1)
      wire T_186360 : UInt<1>[2]
      T_186360[0] := T_186358
      T_186360[1] := T_186359
      node T_186361 = subw(UInt<64>(0), UInt<7>(64))
      node T_186362 = subw(UInt<64>(0), UInt<7>(64))
      wire T_186363 : UInt<64>[2]
      T_186363[0] := T_186361
      T_186363[1] := T_186362
      node T_186364 = cat(T_186363[1], T_186363[0])
      accessor T_186365 = T_186350[waddr]
      node T_186366 = not(T_186364)
      node T_186367 = and(T_186365, T_186366)
      node T_186368 = and(T_186357, T_186364)
      node T_186369 = or(T_186367, T_186368)
      wire T_186370 : UInt<128>
      node T_186371 = bits(T_186369, 127, 0)
      T_186370 := T_186371
      accessor T_186372 = T_186350[waddr]
      T_186372 := T_186370
    node T_186373 = eq(T_186319, UInt<1>(0))
    node T_186374 = eq(T_186373, UInt<1>(0))
    node T_186375 = and(T_186374, read.valid)
    reg T_186376 : UInt<8>
    when T_186375 : T_186376 := raddr
    accessor T_186377 = T_186350[T_186376]
    T_186320[1] := T_186377
    node T_186378 = bits(T_186320[0], 63, 0)
    node T_186379 = bits(T_186320[1], 63, 0)
    wire T_186380 : UInt<64>[2]
    T_186380[0] := T_186378
    T_186380[1] := T_186379
    node T_186381 = bits(T_186321, 3, 3)
    accessor T_186382 = T_186380[T_186381]
    wire T_186383 : UInt<64>[2]
    T_186383[0] := T_186382
    T_186383[1] := T_186380[1]
    node T_186384 = cat(T_186383[1], T_186383[0])
    resp[0] := T_186384
    node T_186385 = bits(T_186320[0], 127, 64)
    node T_186386 = bits(T_186320[1], 127, 64)
    wire T_186387 : UInt<64>[2]
    T_186387[0] := T_186385
    T_186387[1] := T_186386
    node T_186388 = bits(T_186321, 3, 3)
    accessor T_186389 = T_186387[T_186388]
    wire T_186390 : UInt<64>[2]
    T_186390[0] := T_186389
    T_186390[1] := T_186387[1]
    node T_186391 = cat(T_186390[1], T_186390[0])
    resp[1] := T_186391
    node T_186392 = bits(write.bits.way_en, 3, 2)
    node T_186393 = bits(read.bits.way_en, 3, 2)
    wire T_186394 : UInt<128>[2]
    reg T_186395 : UInt<12>
    when read.valid : T_186395 := read.bits.addr
    cmem T_186396 : UInt<128>[256]
    
    
    node T_186397 = eq(T_186392, UInt<1>(0))
    node T_186398 = eq(T_186397, UInt<1>(0))
    node T_186399 = and(T_186398, write.valid)
    node T_186400 = bit(write.bits.wmask, 0)
    node T_186401 = and(T_186399, T_186400)
    when T_186401 : 
      node T_186402 = bits(write.bits.data, 63, 0)
      node T_186403 = cat(T_186402, T_186402)
      node T_186404 = bit(T_186392, 0)
      node T_186405 = bit(T_186392, 1)
      wire T_186406 : UInt<1>[2]
      T_186406[0] := T_186404
      T_186406[1] := T_186405
      node T_186407 = subw(UInt<64>(0), UInt<7>(64))
      node T_186408 = subw(UInt<64>(0), UInt<7>(64))
      wire T_186409 : UInt<64>[2]
      T_186409[0] := T_186407
      T_186409[1] := T_186408
      node T_186410 = cat(T_186409[1], T_186409[0])
      accessor T_186411 = T_186396[waddr]
      node T_186412 = not(T_186410)
      node T_186413 = and(T_186411, T_186412)
      node T_186414 = and(T_186403, T_186410)
      node T_186415 = or(T_186413, T_186414)
      wire T_186416 : UInt<128>
      node T_186417 = bits(T_186415, 127, 0)
      T_186416 := T_186417
      accessor T_186418 = T_186396[waddr]
      T_186418 := T_186416
    node T_186419 = eq(T_186393, UInt<1>(0))
    node T_186420 = eq(T_186419, UInt<1>(0))
    node T_186421 = and(T_186420, read.valid)
    reg T_186422 : UInt<8>
    when T_186421 : T_186422 := raddr
    accessor T_186423 = T_186396[T_186422]
    T_186394[0] := T_186423
    cmem T_186424 : UInt<128>[256]
    
    
    node T_186425 = eq(T_186392, UInt<1>(0))
    node T_186426 = eq(T_186425, UInt<1>(0))
    node T_186427 = and(T_186426, write.valid)
    node T_186428 = bit(write.bits.wmask, 1)
    node T_186429 = and(T_186427, T_186428)
    when T_186429 : 
      node T_186430 = bits(write.bits.data, 127, 64)
      node T_186431 = cat(T_186430, T_186430)
      node T_186432 = bit(T_186392, 0)
      node T_186433 = bit(T_186392, 1)
      wire T_186434 : UInt<1>[2]
      T_186434[0] := T_186432
      T_186434[1] := T_186433
      node T_186435 = subw(UInt<64>(0), UInt<7>(64))
      node T_186436 = subw(UInt<64>(0), UInt<7>(64))
      wire T_186437 : UInt<64>[2]
      T_186437[0] := T_186435
      T_186437[1] := T_186436
      node T_186438 = cat(T_186437[1], T_186437[0])
      accessor T_186439 = T_186424[waddr]
      node T_186440 = not(T_186438)
      node T_186441 = and(T_186439, T_186440)
      node T_186442 = and(T_186431, T_186438)
      node T_186443 = or(T_186441, T_186442)
      wire T_186444 : UInt<128>
      node T_186445 = bits(T_186443, 127, 0)
      T_186444 := T_186445
      accessor T_186446 = T_186424[waddr]
      T_186446 := T_186444
    node T_186447 = eq(T_186393, UInt<1>(0))
    node T_186448 = eq(T_186447, UInt<1>(0))
    node T_186449 = and(T_186448, read.valid)
    reg T_186450 : UInt<8>
    when T_186449 : T_186450 := raddr
    accessor T_186451 = T_186424[T_186450]
    T_186394[1] := T_186451
    node T_186452 = bits(T_186394[0], 63, 0)
    node T_186453 = bits(T_186394[1], 63, 0)
    wire T_186454 : UInt<64>[2]
    T_186454[0] := T_186452
    T_186454[1] := T_186453
    node T_186455 = bits(T_186395, 3, 3)
    accessor T_186456 = T_186454[T_186455]
    wire T_186457 : UInt<64>[2]
    T_186457[0] := T_186456
    T_186457[1] := T_186454[1]
    node T_186458 = cat(T_186457[1], T_186457[0])
    resp[2] := T_186458
    node T_186459 = bits(T_186394[0], 127, 64)
    node T_186460 = bits(T_186394[1], 127, 64)
    wire T_186461 : UInt<64>[2]
    T_186461[0] := T_186459
    T_186461[1] := T_186460
    node T_186462 = bits(T_186395, 3, 3)
    accessor T_186463 = T_186461[T_186462]
    wire T_186464 : UInt<64>[2]
    T_186464[0] := T_186463
    T_186464[1] := T_186461[1]
    node T_186465 = cat(T_186464[1], T_186464[0])
    resp[3] := T_186465
    read.ready := UInt<1>(1)
    write.ready := UInt<1>(1)
  module Arbiter_145852 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}
    output chosen : UInt<2>
    
    wire T_186466 : UInt<2>
    node T_186467 = or(UInt<1>(0), in[0].valid)
    node T_186468 = eq(T_186467, UInt<1>(0))
    node T_186469 = or(UInt<1>(0), in[0].valid)
    node T_186470 = or(T_186469, in[1].valid)
    node T_186471 = eq(T_186470, UInt<1>(0))
    node T_186472 = or(UInt<1>(0), in[0].valid)
    node T_186473 = or(T_186472, in[1].valid)
    node T_186474 = or(T_186473, in[2].valid)
    node T_186475 = eq(T_186474, UInt<1>(0))
    node T_186476 = eq(UInt<2>(3), UInt<1>(0))
    wire T_186477 : UInt<1>
    T_186477 := UInt<1>(1)
    when UInt<1>(0) : T_186477 := T_186476
    node T_186478 = and(T_186477, out.ready)
    in[0].ready := T_186478
    node T_186479 = eq(UInt<2>(3), UInt<1>(1))
    wire T_186480 : UInt<1>
    T_186480 := T_186468
    when UInt<1>(0) : T_186480 := T_186479
    node T_186481 = and(T_186480, out.ready)
    in[1].ready := T_186481
    node T_186482 = eq(UInt<2>(3), UInt<2>(2))
    wire T_186483 : UInt<1>
    T_186483 := T_186471
    when UInt<1>(0) : T_186483 := T_186482
    node T_186484 = and(T_186483, out.ready)
    in[2].ready := T_186484
    node T_186485 = eq(UInt<2>(3), UInt<2>(3))
    wire T_186486 : UInt<1>
    T_186486 := T_186475
    when UInt<1>(0) : T_186486 := T_186485
    node T_186487 = and(T_186486, out.ready)
    in[3].ready := T_186487
    accessor T_186488 = in[T_186466]
    out.valid := T_186488.valid
    accessor T_186489 = in[T_186466]
    out.bits := T_186489.bits
    chosen := T_186466
    wire T_186490 : UInt<2>
    T_186490 := UInt<2>(3)
    when in[2].valid : T_186490 := UInt<2>(2)
    wire T_186491 : UInt<2>
    T_186491 := T_186490
    when in[1].valid : T_186491 := UInt<1>(1)
    wire T_186492 : UInt<2>
    T_186492 := T_186491
    when in[0].valid : T_186492 := UInt<1>(0)
    wire T_186493 : UInt<2>
    T_186493 := T_186492
    when UInt<1>(0) : T_186493 := UInt<2>(3)
    T_186466 := T_186493
  module Arbiter_145932 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}
    output chosen : UInt<1>
    
    wire T_186494 : UInt<1>
    node T_186495 = or(UInt<1>(0), in[0].valid)
    node T_186496 = eq(T_186495, UInt<1>(0))
    node T_186497 = eq(UInt<1>(1), UInt<1>(0))
    wire T_186498 : UInt<1>
    T_186498 := UInt<1>(1)
    when UInt<1>(0) : T_186498 := T_186497
    node T_186499 = and(T_186498, out.ready)
    in[0].ready := T_186499
    node T_186500 = eq(UInt<1>(1), UInt<1>(1))
    wire T_186501 : UInt<1>
    T_186501 := T_186496
    when UInt<1>(0) : T_186501 := T_186500
    node T_186502 = and(T_186501, out.ready)
    in[1].ready := T_186502
    accessor T_186503 = in[T_186494]
    out.valid := T_186503.valid
    accessor T_186504 = in[T_186494]
    out.bits := T_186504.bits
    chosen := T_186494
    wire T_186505 : UInt<1>
    T_186505 := UInt<1>(1)
    when in[0].valid : T_186505 := UInt<1>(0)
    wire T_186506 : UInt<1>
    T_186506 := T_186505
    when UInt<1>(0) : T_186506 := UInt<1>(1)
    T_186494 := T_186506
  module AMOALU_147223 : 
    input addr : UInt<6>
    input cmd : UInt<5>
    input typ : UInt<3>
    input lhs : UInt<64>
    input rhs : UInt<64>
    output out : UInt<64>
    
    node T_186507 = eq(typ, UInt<3>(0))
    node T_186508 = eq(typ, UInt<3>(4))
    node T_186509 = or(T_186507, T_186508)
    node T_186510 = eq(typ, UInt<3>(1))
    node T_186511 = eq(typ, UInt<3>(5))
    node T_186512 = or(T_186510, T_186511)
    node T_186513 = eq(typ, UInt<3>(2))
    node T_186514 = eq(typ, UInt<3>(6))
    node T_186515 = or(T_186513, T_186514)
    node T_186516 = bits(rhs, 31, 0)
    node T_186517 = cat(T_186516, T_186516)
    wire rhs : UInt<64>
    rhs := rhs
    when T_186515 : rhs := T_186517
    node T_186518 = eq(cmd, UInt<5>(12))
    node T_186519 = eq(cmd, UInt<5>(13))
    node sgned = or(T_186518, T_186519)
    node T_186520 = eq(cmd, UInt<5>(13))
    node T_186521 = eq(cmd, UInt<5>(15))
    node max = or(T_186520, T_186521)
    node T_186522 = eq(cmd, UInt<5>(12))
    node T_186523 = eq(cmd, UInt<5>(14))
    node min = or(T_186522, T_186523)
    node T_186524 = eq(typ, UInt<3>(2))
    node T_186525 = eq(typ, UInt<3>(6))
    node T_186526 = or(T_186524, T_186525)
    node T_186527 = eq(typ, UInt<3>(0))
    node T_186528 = or(T_186526, T_186527)
    node T_186529 = eq(typ, UInt<3>(4))
    node word = or(T_186528, T_186529)
    node T_186530 = not(UInt<64>(0))
    node T_186531 = bit(addr, 2)
    node T_186532 = dshl(T_186531, UInt<5>(31))
    node mask = xor(T_186530, T_186532)
    node T_186533 = and(lhs, mask)
    node T_186534 = and(rhs, mask)
    node adder_out = addw(T_186533, T_186534)
    node T_186535 = bit(addr, 2)
    node T_186536 = eq(T_186535, UInt<1>(0))
    node T_186537 = and(word, T_186536)
    node T_186538 = bit(lhs, 31)
    node T_186539 = bit(lhs, 63)
    wire cmp_lhs : UInt<1>
    cmp_lhs := T_186539
    when T_186537 : cmp_lhs := T_186538
    node T_186540 = bit(addr, 2)
    node T_186541 = eq(T_186540, UInt<1>(0))
    node T_186542 = and(word, T_186541)
    node T_186543 = bit(rhs, 31)
    node T_186544 = bit(rhs, 63)
    wire cmp_rhs : UInt<1>
    cmp_rhs := T_186544
    when T_186542 : cmp_rhs := T_186543
    node T_186545 = bits(lhs, 31, 0)
    node T_186546 = bits(rhs, 31, 0)
    node lt_lo = lt(T_186545, T_186546)
    node T_186547 = bits(lhs, 63, 32)
    node T_186548 = bits(rhs, 63, 32)
    node lt_hi = lt(T_186547, T_186548)
    node T_186549 = bits(lhs, 63, 32)
    node T_186550 = bits(rhs, 63, 32)
    node eq_hi = eq(T_186549, T_186550)
    node T_186551 = bit(addr, 2)
    wire T_186552 : UInt<1>
    T_186552 := lt_lo
    when T_186551 : T_186552 := lt_hi
    node T_186553 = and(eq_hi, lt_lo)
    node T_186554 = or(lt_hi, T_186553)
    wire lt : UInt<1>
    lt := T_186554
    when word : lt := T_186552
    node T_186555 = eq(cmp_lhs, cmp_rhs)
    wire T_186556 : UInt<1>
    T_186556 := cmp_rhs
    when sgned : T_186556 := cmp_lhs
    wire less : UInt<1>
    less := T_186556
    when T_186555 : less := lt
    node T_186557 = eq(cmd, UInt<5>(8))
    node T_186558 = eq(cmd, UInt<5>(11))
    node T_186559 = and(lhs, rhs)
    node T_186560 = eq(cmd, UInt<5>(10))
    node T_186561 = or(lhs, rhs)
    node T_186562 = eq(cmd, UInt<5>(9))
    node T_186563 = xor(lhs, rhs)
    wire T_186564 : UInt<1>
    T_186564 := max
    when less : T_186564 := min
    node T_186565 = bits(rhs, 7, 0)
    node T_186566 = cat(T_186565, T_186565)
    node T_186567 = cat(T_186566, T_186566)
    node T_186568 = cat(T_186567, T_186567)
    node T_186569 = bits(rhs, 15, 0)
    node T_186570 = cat(T_186569, T_186569)
    node T_186571 = cat(T_186570, T_186570)
    wire T_186572 : UInt<64>
    T_186572 := rhs
    when T_186512 : T_186572 := T_186571
    wire T_186573 : UInt<64>
    T_186573 := T_186572
    when T_186509 : T_186573 := T_186568
    wire T_186574 : UInt<64>
    T_186574 := T_186573
    when T_186564 : T_186574 := lhs
    wire T_186575 : UInt<64>
    T_186575 := T_186574
    when T_186562 : T_186575 := T_186563
    wire T_186576 : UInt<64>
    T_186576 := T_186575
    when T_186560 : T_186576 := T_186561
    wire T_186577 : UInt<64>
    T_186577 := T_186576
    when T_186558 : T_186577 := T_186559
    wire out : UInt<64>
    out := T_186577
    when T_186557 : out := adder_out
    node T_186578 = bits(addr, 2, 0)
    node T_186579 = dshl(UInt<1>(1), T_186578)
    node T_186580 = bits(addr, 2, 1)
    node T_186581 = cat(T_186580, UInt<1>(0))
    node T_186582 = dshl(UInt<2>(3), T_186581)
    node T_186583 = bit(addr, 2)
    node T_186584 = cat(T_186583, UInt<2>(0))
    node T_186585 = dshl(UInt<4>(15), T_186584)
    wire T_186586 : UInt<8>
    T_186586 := UInt<8>(255)
    when T_186515 : T_186586 := T_186585
    wire T_186587 : UInt<8>
    T_186587 := T_186586
    when T_186512 : T_186587 := T_186582
    wire T_186588 : UInt<8>
    T_186588 := T_186587
    when T_186509 : T_186588 := T_186579
    node T_186589 = bit(T_186588, 0)
    node T_186590 = bit(T_186588, 1)
    node T_186591 = bit(T_186588, 2)
    node T_186592 = bit(T_186588, 3)
    node T_186593 = bit(T_186588, 4)
    node T_186594 = bit(T_186588, 5)
    node T_186595 = bit(T_186588, 6)
    node T_186596 = bit(T_186588, 7)
    wire T_186597 : UInt<1>[8]
    T_186597[0] := T_186589
    T_186597[1] := T_186590
    T_186597[2] := T_186591
    T_186597[3] := T_186592
    T_186597[4] := T_186593
    T_186597[5] := T_186594
    T_186597[6] := T_186595
    T_186597[7] := T_186596
    node T_186598 = subw(UInt<8>(0), UInt<4>(8))
    node T_186599 = subw(UInt<8>(0), UInt<4>(8))
    node T_186600 = subw(UInt<8>(0), UInt<4>(8))
    node T_186601 = subw(UInt<8>(0), UInt<4>(8))
    node T_186602 = subw(UInt<8>(0), UInt<4>(8))
    node T_186603 = subw(UInt<8>(0), UInt<4>(8))
    node T_186604 = subw(UInt<8>(0), UInt<4>(8))
    node T_186605 = subw(UInt<8>(0), UInt<4>(8))
    wire T_186606 : UInt<8>[8]
    T_186606[0] := T_186598
    T_186606[1] := T_186599
    T_186606[2] := T_186600
    T_186606[3] := T_186601
    T_186606[4] := T_186602
    T_186606[5] := T_186603
    T_186606[6] := T_186604
    T_186606[7] := T_186605
    node T_186607 = cat(T_186606[7], T_186606[6])
    node T_186608 = cat(T_186606[5], T_186606[4])
    node T_186609 = cat(T_186607, T_186608)
    node T_186610 = cat(T_186606[3], T_186606[2])
    node T_186611 = cat(T_186606[1], T_186606[0])
    node T_186612 = cat(T_186610, T_186611)
    node wmask = cat(T_186609, T_186612)
    node T_186613 = and(wmask, out)
    node T_186614 = not(wmask)
    node T_186615 = and(T_186614, lhs)
    node T_186616 = or(T_186613, T_186615)
    out := T_186616
  module LockingArbiter_148764 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}
    output chosen : UInt<1>
    
    wire T_186617 : UInt<3>[3]
    T_186617[0] := UInt<3>(0)
    T_186617[1] := UInt<3>(1)
    T_186617[2] := UInt<3>(2)
    wire T_186618 : UInt<2>[2]
    T_186618[0] := UInt<2>(0)
    T_186618[1] := UInt<2>(1)
    wire T_186619 : UInt<2>[3]
    T_186619[0] := UInt<2>(1)
    T_186619[1] := UInt<2>(2)
    T_186619[2] := UInt<2>(3)
    wire T_186620 : UInt<2>[2]
    T_186620[0] := UInt<2>(2)
    T_186620[1] := UInt<2>(3)
    wire T_186621 : UInt<2>[1]
    T_186621[0] := UInt<2>(3)
    wire T_186622 : UInt<3>[3]
    T_186622[0] := UInt<3>(0)
    T_186622[1] := UInt<3>(1)
    T_186622[2] := UInt<3>(2)
    wire T_186623 : UInt<2>[2]
    T_186623[0] := UInt<2>(0)
    T_186623[1] := UInt<2>(1)
    wire T_186624 : UInt<2>[3]
    T_186624[0] := UInt<2>(1)
    T_186624[1] := UInt<2>(2)
    T_186624[2] := UInt<2>(3)
    wire T_186625 : UInt<2>[2]
    T_186625[0] := UInt<2>(2)
    T_186625[1] := UInt<2>(3)
    wire T_186626 : UInt<2>[1]
    T_186626[0] := UInt<2>(3)
    wire T_186627 : UInt<3>[3]
    T_186627[0] := UInt<3>(0)
    T_186627[1] := UInt<3>(1)
    T_186627[2] := UInt<3>(2)
    wire T_186628 : UInt<2>[2]
    T_186628[0] := UInt<2>(0)
    T_186628[1] := UInt<2>(1)
    wire T_186629 : UInt<2>[3]
    T_186629[0] := UInt<2>(1)
    T_186629[1] := UInt<2>(2)
    T_186629[2] := UInt<2>(3)
    wire T_186630 : UInt<2>[2]
    T_186630[0] := UInt<2>(2)
    T_186630[1] := UInt<2>(3)
    wire T_186631 : UInt<2>[1]
    T_186631[0] := UInt<2>(3)
    wire T_186632 : UInt<3>[3]
    T_186632[0] := UInt<3>(0)
    T_186632[1] := UInt<3>(1)
    T_186632[2] := UInt<3>(2)
    wire T_186633 : UInt<2>[2]
    T_186633[0] := UInt<2>(0)
    T_186633[1] := UInt<2>(1)
    wire T_186634 : UInt<2>[3]
    T_186634[0] := UInt<2>(1)
    T_186634[1] := UInt<2>(2)
    T_186634[2] := UInt<2>(3)
    wire T_186635 : UInt<2>[2]
    T_186635[0] := UInt<2>(2)
    T_186635[1] := UInt<2>(3)
    wire T_186636 : UInt<2>[1]
    T_186636[0] := UInt<2>(3)
    reg T_186637 : UInt<1>
    onreset T_186637 := UInt<1>(0)
    reg T_186638 : UInt<1>
    onreset T_186638 := UInt<1>(1)
    wire T_186639 : UInt<1>
    node T_186640 = or(UInt<1>(0), in[0].valid)
    node T_186641 = eq(T_186640, UInt<1>(0))
    node T_186642 = eq(T_186638, UInt<1>(0))
    wire T_186643 : UInt<1>
    T_186643 := UInt<1>(1)
    when T_186637 : T_186643 := T_186642
    node T_186644 = and(T_186643, out.ready)
    in[0].ready := T_186644
    node T_186645 = eq(T_186638, UInt<1>(1))
    wire T_186646 : UInt<1>
    T_186646 := T_186641
    when T_186637 : T_186646 := T_186645
    node T_186647 = and(T_186646, out.ready)
    in[1].ready := T_186647
    wire T_186648 : UInt<3>[3]
    T_186648[0] := UInt<3>(0)
    T_186648[1] := UInt<3>(1)
    T_186648[2] := UInt<3>(2)
    wire T_186649 : UInt<2>[2]
    T_186649[0] := UInt<2>(0)
    T_186649[1] := UInt<2>(1)
    wire T_186650 : UInt<2>[3]
    T_186650[0] := UInt<2>(1)
    T_186650[1] := UInt<2>(2)
    T_186650[2] := UInt<2>(3)
    wire T_186651 : UInt<2>[2]
    T_186651[0] := UInt<2>(2)
    T_186651[1] := UInt<2>(3)
    wire T_186652 : UInt<2>[1]
    T_186652[0] := UInt<2>(3)
    accessor T_186653 = in[T_186639]
    out.valid := T_186653.valid
    wire T_186654 : UInt<3>[3]
    T_186654[0] := UInt<3>(0)
    T_186654[1] := UInt<3>(1)
    T_186654[2] := UInt<3>(2)
    wire T_186655 : UInt<2>[2]
    T_186655[0] := UInt<2>(0)
    T_186655[1] := UInt<2>(1)
    wire T_186656 : UInt<2>[3]
    T_186656[0] := UInt<2>(1)
    T_186656[1] := UInt<2>(2)
    T_186656[2] := UInt<2>(3)
    wire T_186657 : UInt<2>[2]
    T_186657[0] := UInt<2>(2)
    T_186657[1] := UInt<2>(3)
    wire T_186658 : UInt<2>[1]
    T_186658[0] := UInt<2>(3)
    accessor T_186659 = in[T_186639]
    out.bits := T_186659.bits
    chosen := T_186639
    reg T_186660 : UInt<2>
    onreset T_186660 := UInt<2>(0)
    node T_186661 = addw(T_186660, UInt<1>(1))
    
    node T_186662 = and(out.ready, out.valid)
    when T_186662 : 
      
      
      node T_186663 = eq(T_186632[0], out.bits.r_type)
      node T_186664 = eq(T_186632[1], out.bits.r_type)
      node T_186665 = eq(T_186632[2], out.bits.r_type)
      node T_186666 = or(UInt<1>(0), T_186663)
      node T_186667 = or(T_186666, T_186664)
      node T_186668 = or(T_186667, T_186665)
      node T_186669 = and(UInt<1>(1), T_186668)
      when T_186669 : 
        T_186660 := T_186661
        
        node T_186670 = eq(T_186637, UInt<1>(0))
        when T_186670 : 
          T_186637 := UInt<1>(1)
          node T_186671 = and(in[0].ready, in[0].valid)
          node T_186672 = and(in[1].ready, in[1].valid)
          wire T_186673 : UInt<1>[2]
          T_186673[0] := T_186671
          T_186673[1] := T_186672
          wire T_186674 : UInt<1>
          T_186674 := UInt<1>(1)
          when T_186673[0] : T_186674 := UInt<1>(0)
          T_186638 := T_186674
      
      node T_186675 = eq(T_186661, UInt<1>(0))
      when T_186675 : T_186637 := UInt<1>(0)
    wire choose : UInt<1>
    choose := UInt<1>(1)
    when in[0].valid : choose := UInt<1>(0)
    wire T_186676 : UInt<1>
    T_186676 := choose
    when T_186637 : T_186676 := T_186638
    T_186639 := T_186676
  module FlowThroughSerializer_148912 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}
    output cnt : UInt<1>
    output done : UInt<1>
    
    wire T_186677 : UInt<3>[3]
    T_186677[0] := UInt<3>(0)
    T_186677[1] := UInt<3>(1)
    T_186677[2] := UInt<3>(2)
    wire T_186678 : UInt<2>[2]
    T_186678[0] := UInt<2>(0)
    T_186678[1] := UInt<2>(1)
    wire T_186679 : UInt<2>[3]
    T_186679[0] := UInt<2>(1)
    T_186679[1] := UInt<2>(2)
    T_186679[2] := UInt<2>(3)
    wire T_186680 : UInt<2>[2]
    T_186680[0] := UInt<2>(2)
    T_186680[1] := UInt<2>(3)
    wire T_186681 : UInt<2>[1]
    T_186681[0] := UInt<2>(3)
    wire T_186682 : UInt<3>[3]
    T_186682[0] := UInt<3>(0)
    T_186682[1] := UInt<3>(1)
    T_186682[2] := UInt<3>(2)
    wire T_186683 : UInt<2>[2]
    T_186683[0] := UInt<2>(0)
    T_186683[1] := UInt<2>(1)
    wire T_186684 : UInt<2>[3]
    T_186684[0] := UInt<2>(1)
    T_186684[1] := UInt<2>(2)
    T_186684[2] := UInt<2>(3)
    wire T_186685 : UInt<2>[2]
    T_186685[0] := UInt<2>(2)
    T_186685[1] := UInt<2>(3)
    wire T_186686 : UInt<2>[1]
    T_186686[0] := UInt<2>(3)
    in <> out
    cnt := T_186687
    done := UInt<1>(1)
  module Arbiter_149454 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>, way_en : UInt<4>}}
    output chosen : UInt<1>
    
    wire T_186688 : UInt<3>[3]
    T_186688[0] := UInt<3>(0)
    T_186688[1] := UInt<3>(1)
    T_186688[2] := UInt<3>(2)
    wire T_186689 : UInt<2>[2]
    T_186689[0] := UInt<2>(0)
    T_186689[1] := UInt<2>(1)
    wire T_186690 : UInt<2>[3]
    T_186690[0] := UInt<2>(1)
    T_186690[1] := UInt<2>(2)
    T_186690[2] := UInt<2>(3)
    wire T_186691 : UInt<2>[2]
    T_186691[0] := UInt<2>(2)
    T_186691[1] := UInt<2>(3)
    wire T_186692 : UInt<2>[1]
    T_186692[0] := UInt<2>(3)
    wire T_186693 : UInt<3>[3]
    T_186693[0] := UInt<3>(0)
    T_186693[1] := UInt<3>(1)
    T_186693[2] := UInt<3>(2)
    wire T_186694 : UInt<2>[2]
    T_186694[0] := UInt<2>(0)
    T_186694[1] := UInt<2>(1)
    wire T_186695 : UInt<2>[3]
    T_186695[0] := UInt<2>(1)
    T_186695[1] := UInt<2>(2)
    T_186695[2] := UInt<2>(3)
    wire T_186696 : UInt<2>[2]
    T_186696[0] := UInt<2>(2)
    T_186696[1] := UInt<2>(3)
    wire T_186697 : UInt<2>[1]
    T_186697[0] := UInt<2>(3)
    wire T_186698 : UInt<3>[3]
    T_186698[0] := UInt<3>(0)
    T_186698[1] := UInt<3>(1)
    T_186698[2] := UInt<3>(2)
    wire T_186699 : UInt<2>[2]
    T_186699[0] := UInt<2>(0)
    T_186699[1] := UInt<2>(1)
    wire T_186700 : UInt<2>[3]
    T_186700[0] := UInt<2>(1)
    T_186700[1] := UInt<2>(2)
    T_186700[2] := UInt<2>(3)
    wire T_186701 : UInt<2>[2]
    T_186701[0] := UInt<2>(2)
    T_186701[1] := UInt<2>(3)
    wire T_186702 : UInt<2>[1]
    T_186702[0] := UInt<2>(3)
    wire T_186703 : UInt<3>[3]
    T_186703[0] := UInt<3>(0)
    T_186703[1] := UInt<3>(1)
    T_186703[2] := UInt<3>(2)
    wire T_186704 : UInt<2>[2]
    T_186704[0] := UInt<2>(0)
    T_186704[1] := UInt<2>(1)
    wire T_186705 : UInt<2>[3]
    T_186705[0] := UInt<2>(1)
    T_186705[1] := UInt<2>(2)
    T_186705[2] := UInt<2>(3)
    wire T_186706 : UInt<2>[2]
    T_186706[0] := UInt<2>(2)
    T_186706[1] := UInt<2>(3)
    wire T_186707 : UInt<2>[1]
    T_186707[0] := UInt<2>(3)
    wire T_186708 : UInt<1>
    node T_186709 = or(UInt<1>(0), in[0].valid)
    node T_186710 = eq(T_186709, UInt<1>(0))
    node T_186711 = eq(UInt<1>(1), UInt<1>(0))
    wire T_186712 : UInt<1>
    T_186712 := UInt<1>(1)
    when UInt<1>(0) : T_186712 := T_186711
    node T_186713 = and(T_186712, out.ready)
    in[0].ready := T_186713
    node T_186714 = eq(UInt<1>(1), UInt<1>(1))
    wire T_186715 : UInt<1>
    T_186715 := T_186710
    when UInt<1>(0) : T_186715 := T_186714
    node T_186716 = and(T_186715, out.ready)
    in[1].ready := T_186716
    wire T_186717 : UInt<3>[3]
    T_186717[0] := UInt<3>(0)
    T_186717[1] := UInt<3>(1)
    T_186717[2] := UInt<3>(2)
    wire T_186718 : UInt<2>[2]
    T_186718[0] := UInt<2>(0)
    T_186718[1] := UInt<2>(1)
    wire T_186719 : UInt<2>[3]
    T_186719[0] := UInt<2>(1)
    T_186719[1] := UInt<2>(2)
    T_186719[2] := UInt<2>(3)
    wire T_186720 : UInt<2>[2]
    T_186720[0] := UInt<2>(2)
    T_186720[1] := UInt<2>(3)
    wire T_186721 : UInt<2>[1]
    T_186721[0] := UInt<2>(3)
    accessor T_186722 = in[T_186708]
    out.valid := T_186722.valid
    wire T_186723 : UInt<3>[3]
    T_186723[0] := UInt<3>(0)
    T_186723[1] := UInt<3>(1)
    T_186723[2] := UInt<3>(2)
    wire T_186724 : UInt<2>[2]
    T_186724[0] := UInt<2>(0)
    T_186724[1] := UInt<2>(1)
    wire T_186725 : UInt<2>[3]
    T_186725[0] := UInt<2>(1)
    T_186725[1] := UInt<2>(2)
    T_186725[2] := UInt<2>(3)
    wire T_186726 : UInt<2>[2]
    T_186726[0] := UInt<2>(2)
    T_186726[1] := UInt<2>(3)
    wire T_186727 : UInt<2>[1]
    T_186727[0] := UInt<2>(3)
    accessor T_186728 = in[T_186708]
    out.bits := T_186728.bits
    chosen := T_186708
    wire T_186729 : UInt<1>
    T_186729 := UInt<1>(1)
    when in[0].valid : T_186729 := UInt<1>(0)
    wire T_186730 : UInt<1>
    T_186730 := T_186729
    when UInt<1>(0) : T_186730 := UInt<1>(1)
    T_186708 := T_186730
  module HellaCache : 
    input cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}
    output ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}
    output mem__ : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    
    wire T_186731 : UInt<3>[3]
    T_186731[0] := UInt<3>(0)
    T_186731[1] := UInt<3>(1)
    T_186731[2] := UInt<3>(2)
    wire T_186732 : UInt<2>[2]
    T_186732[0] := UInt<2>(0)
    T_186732[1] := UInt<2>(1)
    wire T_186733 : UInt<2>[3]
    T_186733[0] := UInt<2>(1)
    T_186733[1] := UInt<2>(2)
    T_186733[2] := UInt<2>(3)
    wire T_186734 : UInt<2>[2]
    T_186734[0] := UInt<2>(2)
    T_186734[1] := UInt<2>(3)
    wire T_186735 : UInt<2>[1]
    T_186735[0] := UInt<2>(3)
    wire T_186736 : UInt<3>[3]
    T_186736[0] := UInt<3>(0)
    T_186736[1] := UInt<3>(1)
    T_186736[2] := UInt<3>(2)
    wire T_186737 : UInt<2>[2]
    T_186737[0] := UInt<2>(0)
    T_186737[1] := UInt<2>(1)
    wire T_186738 : UInt<2>[3]
    T_186738[0] := UInt<2>(1)
    T_186738[1] := UInt<2>(2)
    T_186738[2] := UInt<2>(3)
    wire T_186739 : UInt<2>[2]
    T_186739[0] := UInt<2>(2)
    T_186739[1] := UInt<2>(3)
    wire T_186740 : UInt<2>[1]
    T_186740[0] := UInt<2>(3)
    wire T_186741 : UInt<3>[3]
    T_186741[0] := UInt<3>(0)
    T_186741[1] := UInt<3>(1)
    T_186741[2] := UInt<3>(2)
    wire T_186742 : UInt<2>[2]
    T_186742[0] := UInt<2>(0)
    T_186742[1] := UInt<2>(1)
    wire T_186743 : UInt<2>[3]
    T_186743[0] := UInt<2>(1)
    T_186743[1] := UInt<2>(2)
    T_186743[2] := UInt<2>(3)
    wire T_186744 : UInt<2>[2]
    T_186744[0] := UInt<2>(2)
    T_186744[1] := UInt<2>(3)
    wire T_186745 : UInt<2>[1]
    T_186745[0] := UInt<2>(3)
    wire T_186746 : UInt<3>[3]
    T_186746[0] := UInt<3>(0)
    T_186746[1] := UInt<3>(1)
    T_186746[2] := UInt<3>(2)
    wire T_186747 : UInt<2>[2]
    T_186747[0] := UInt<2>(0)
    T_186747[1] := UInt<2>(1)
    wire T_186748 : UInt<2>[3]
    T_186748[0] := UInt<2>(1)
    T_186748[1] := UInt<2>(2)
    T_186748[2] := UInt<2>(3)
    wire T_186749 : UInt<2>[2]
    T_186749[0] := UInt<2>(2)
    T_186749[1] := UInt<2>(3)
    wire T_186750 : UInt<2>[1]
    T_186750[0] := UInt<2>(3)
    wire T_186751 : UInt<3>[3]
    T_186751[0] := UInt<3>(0)
    T_186751[1] := UInt<3>(1)
    T_186751[2] := UInt<3>(2)
    wire T_186752 : UInt<2>[2]
    T_186752[0] := UInt<2>(0)
    T_186752[1] := UInt<2>(1)
    wire T_186753 : UInt<2>[3]
    T_186753[0] := UInt<2>(1)
    T_186753[1] := UInt<2>(2)
    T_186753[2] := UInt<2>(3)
    wire T_186754 : UInt<2>[2]
    T_186754[0] := UInt<2>(2)
    T_186754[1] := UInt<2>(3)
    wire T_186755 : UInt<2>[1]
    T_186755[0] := UInt<2>(3)
    wire T_186756 : UInt<3>[3]
    T_186756[0] := UInt<3>(0)
    T_186756[1] := UInt<3>(1)
    T_186756[2] := UInt<3>(2)
    wire T_186757 : UInt<2>[2]
    T_186757[0] := UInt<2>(0)
    T_186757[1] := UInt<2>(1)
    wire T_186758 : UInt<2>[3]
    T_186758[0] := UInt<2>(1)
    T_186758[1] := UInt<2>(2)
    T_186758[2] := UInt<2>(3)
    wire T_186759 : UInt<2>[2]
    T_186759[0] := UInt<2>(2)
    T_186759[1] := UInt<2>(3)
    wire T_186760 : UInt<2>[1]
    T_186760[0] := UInt<2>(3)
    wire T_186761 : UInt<3>[3]
    T_186761[0] := UInt<3>(0)
    T_186761[1] := UInt<3>(1)
    T_186761[2] := UInt<3>(2)
    wire T_186762 : UInt<2>[2]
    T_186762[0] := UInt<2>(0)
    T_186762[1] := UInt<2>(1)
    wire T_186763 : UInt<2>[3]
    T_186763[0] := UInt<2>(1)
    T_186763[1] := UInt<2>(2)
    T_186763[2] := UInt<2>(3)
    wire T_186764 : UInt<2>[2]
    T_186764[0] := UInt<2>(2)
    T_186764[1] := UInt<2>(3)
    wire T_186765 : UInt<2>[1]
    T_186765[0] := UInt<2>(3)
    wire T_186766 : UInt<3>[3]
    T_186766[0] := UInt<3>(0)
    T_186766[1] := UInt<3>(1)
    T_186766[2] := UInt<3>(2)
    wire T_186767 : UInt<2>[2]
    T_186767[0] := UInt<2>(0)
    T_186767[1] := UInt<2>(1)
    wire T_186768 : UInt<2>[3]
    T_186768[0] := UInt<2>(1)
    T_186768[1] := UInt<2>(2)
    T_186768[2] := UInt<2>(3)
    wire T_186769 : UInt<2>[2]
    T_186769[0] := UInt<2>(2)
    T_186769[1] := UInt<2>(3)
    wire T_186770 : UInt<2>[1]
    T_186770[0] := UInt<2>(3)
    wire T_186771 : UInt<3>[3]
    T_186771[0] := UInt<3>(0)
    T_186771[1] := UInt<3>(1)
    T_186771[2] := UInt<3>(2)
    wire T_186772 : UInt<2>[2]
    T_186772[0] := UInt<2>(0)
    T_186772[1] := UInt<2>(1)
    wire T_186773 : UInt<2>[3]
    T_186773[0] := UInt<2>(1)
    T_186773[1] := UInt<2>(2)
    T_186773[2] := UInt<2>(3)
    wire T_186774 : UInt<2>[2]
    T_186774[0] := UInt<2>(2)
    T_186774[1] := UInt<2>(3)
    wire T_186775 : UInt<2>[1]
    T_186775[0] := UInt<2>(3)
    inst wb of WritebackUnit
    inst prober of ProbeUnit
    inst mshrs of MSHRFile
    cpu.req.ready := UInt<1>(1)
    node T_186776 = and(cpu.req.ready, cpu.req.valid)
    reg s1_valid : UInt<1>
    onreset s1_valid := UInt<1>(0)
    s1_valid := T_186776
    reg s1_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}
    node T_186777 = eq(cpu.req.bits.kill, UInt<1>(0))
    node s1_valid_masked = and(s1_valid, T_186777)
    reg s1_replay : UInt<1>
    onreset s1_replay := UInt<1>(0)
    reg s1_clk_en : UInt<1>
    reg s2_valid : UInt<1>
    onreset s2_valid := UInt<1>(0)
    s2_valid := s1_valid_masked
    reg s2_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}
    reg T_186778 : UInt<1>
    onreset T_186778 := UInt<1>(0)
    T_186778 := s1_replay
    node T_186779 = neq(s2_req.cmd, UInt<5>(5))
    node s2_replay = and(T_186778, T_186779)
    wire s2_recycle : UInt<1>
    wire s2_valid_masked : UInt<1>
    reg s3_valid : UInt<1>
    onreset s3_valid := UInt<1>(0)
    reg s3_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}
    reg s3_way : UInt
    reg s1_recycled : UInt<1>
    onreset s1_recycled := UInt<1>(0)
    when s1_clk_en : s1_recycled := s2_recycle
    node T_186780 = eq(s1_req.cmd, UInt<5>(0))
    node T_186781 = eq(s1_req.cmd, UInt<5>(6))
    node T_186782 = or(T_186780, T_186781)
    node T_186783 = bit(s1_req.cmd, 3)
    node T_186784 = eq(s1_req.cmd, UInt<5>(4))
    node T_186785 = or(T_186783, T_186784)
    node s1_read = or(T_186782, T_186785)
    node T_186786 = eq(s1_req.cmd, UInt<5>(1))
    node T_186787 = eq(s1_req.cmd, UInt<5>(7))
    node T_186788 = or(T_186786, T_186787)
    node T_186789 = bit(s1_req.cmd, 3)
    node T_186790 = eq(s1_req.cmd, UInt<5>(4))
    node T_186791 = or(T_186789, T_186790)
    node s1_write = or(T_186788, T_186791)
    node s1_sc = eq(s1_req.cmd, UInt<5>(7))
    node T_186792 = or(s1_read, s1_write)
    node T_186793 = eq(s1_req.cmd, UInt<5>(2))
    node T_186794 = eq(s1_req.cmd, UInt<5>(3))
    node T_186795 = or(T_186793, T_186794)
    node s1_readwrite = or(T_186792, T_186795)
    inst dtlb of TLB_142822
    dtlb.ptw <> ptw
    node T_186796 = and(s1_valid_masked, s1_readwrite)
    node T_186797 = eq(s1_req.phys, UInt<1>(0))
    node T_186798 = and(T_186796, T_186797)
    dtlb.req.valid := T_186798
    dtlb.req.bits.passthrough := s1_req.phys
    dtlb.req.bits.asid := UInt<1>(0)
    node T_186799 = shr(s1_req.addr, 12)
    dtlb.req.bits.vpn := T_186799
    dtlb.req.bits.instruction := UInt<1>(0)
    dtlb.req.bits.store := s1_write
    
    
    node T_186800 = eq(dtlb.req.ready, UInt<1>(0))
    node T_186801 = eq(cpu.req.bits.phys, UInt<1>(0))
    node T_186802 = and(T_186800, T_186801)
    when T_186802 : cpu.req.ready := UInt<1>(0)
    when cpu.req.valid : s1_req := cpu.req.bits
    when wb.meta_read.valid : 
      node T_186803 = cat(wb.meta_read.bits.tag, wb.meta_read.bits.idx)
      node T_186804 = shl(T_186803, 6)
      s1_req.addr := T_186804
      s1_req.phys := UInt<1>(1)
    when prober.meta_read.valid : 
      node T_186805 = cat(prober.meta_read.bits.tag, prober.meta_read.bits.idx)
      node T_186806 = shl(T_186805, 6)
      s1_req.addr := T_186806
      s1_req.phys := UInt<1>(1)
    when mshrs.replay.valid : s1_req := mshrs.replay.bits
    when s2_recycle : s1_req := s2_req
    node T_186807 = bits(s1_req.addr, 11, 0)
    node s1_addr = cat(dtlb.resp.ppn, T_186807)
    when s1_clk_en : 
      s2_req.kill := s1_req.kill
      s2_req.typ := s1_req.typ
      s2_req.phys := s1_req.phys
      s2_req.addr := s1_addr
      when s1_write : 
        wire T_186808 : UInt<64>
        T_186808 := cpu.req.bits.data
        when s1_replay : T_186808 := mshrs.replay.bits.data
        s2_req.data := T_186808
      when s1_recycled : s2_req.data := s1_req.data
      s2_req.tag := s1_req.tag
      s2_req.cmd := s1_req.cmd
    node T_186809 = eq(s1_req.typ, UInt<3>(1))
    node T_186810 = eq(s1_req.typ, UInt<3>(5))
    node T_186811 = or(T_186809, T_186810)
    node T_186812 = bit(s1_req.addr, 0)
    node T_186813 = neq(T_186812, UInt<1>(0))
    node T_186814 = and(T_186811, T_186813)
    node T_186815 = eq(s1_req.typ, UInt<3>(2))
    node T_186816 = eq(s1_req.typ, UInt<3>(6))
    node T_186817 = or(T_186815, T_186816)
    node T_186818 = bits(s1_req.addr, 1, 0)
    node T_186819 = neq(T_186818, UInt<1>(0))
    node T_186820 = and(T_186817, T_186819)
    node T_186821 = or(T_186814, T_186820)
    node T_186822 = eq(s1_req.typ, UInt<3>(3))
    node T_186823 = bits(s1_req.addr, 2, 0)
    node T_186824 = neq(T_186823, UInt<1>(0))
    node T_186825 = and(T_186822, T_186824)
    node misaligned = or(T_186821, T_186825)
    node T_186826 = and(s1_read, misaligned)
    cpu.xcpt.ma.ld := T_186826
    node T_186827 = and(s1_write, misaligned)
    cpu.xcpt.ma.st := T_186827
    node T_186828 = eq(s1_req.phys, UInt<1>(0))
    node T_186829 = and(T_186828, s1_read)
    node T_186830 = and(T_186829, dtlb.resp.xcpt_ld)
    cpu.xcpt.pf.ld := T_186830
    node T_186831 = eq(s1_req.phys, UInt<1>(0))
    node T_186832 = and(T_186831, s1_write)
    node T_186833 = and(T_186832, dtlb.resp.xcpt_st)
    cpu.xcpt.pf.st := T_186833
    node T_186834 = or(cpu.xcpt.ma.ld, cpu.xcpt.ma.st)
    node T_186835 = or(T_186834, cpu.xcpt.pf.ld)
    node T_186836 = or(T_186835, cpu.xcpt.pf.st)
    reg T_186837 : UInt<1>
    T_186837 := T_186836
    node T_186838 = and(T_186837, cpu.resp.valid)
    node T_186839 = eq(T_186838, UInt<1>(0))
    inst meta of MetadataArray_144779
    inst metaReadArb of Arbiter_144889
    wire T_186840 : UInt<3>[3]
    T_186840[0] := UInt<3>(0)
    T_186840[1] := UInt<3>(1)
    T_186840[2] := UInt<3>(2)
    wire T_186841 : UInt<2>[2]
    T_186841[0] := UInt<2>(0)
    T_186841[1] := UInt<2>(1)
    wire T_186842 : UInt<2>[3]
    T_186842[0] := UInt<2>(1)
    T_186842[1] := UInt<2>(2)
    T_186842[2] := UInt<2>(3)
    wire T_186843 : UInt<2>[2]
    T_186843[0] := UInt<2>(2)
    T_186843[1] := UInt<2>(3)
    wire T_186844 : UInt<2>[1]
    T_186844[0] := UInt<2>(3)
    wire T_186845 : UInt<3>[3]
    T_186845[0] := UInt<3>(0)
    T_186845[1] := UInt<3>(1)
    T_186845[2] := UInt<3>(2)
    wire T_186846 : UInt<2>[2]
    T_186846[0] := UInt<2>(0)
    T_186846[1] := UInt<2>(1)
    wire T_186847 : UInt<2>[3]
    T_186847[0] := UInt<2>(1)
    T_186847[1] := UInt<2>(2)
    T_186847[2] := UInt<2>(3)
    wire T_186848 : UInt<2>[2]
    T_186848[0] := UInt<2>(2)
    T_186848[1] := UInt<2>(3)
    wire T_186849 : UInt<2>[1]
    T_186849[0] := UInt<2>(3)
    inst metaWriteArb of Arbiter_145479
    metaReadArb.out <> meta.read
    metaWriteArb.out <> meta.write
    inst data of DataArray
    inst readArb of Arbiter_145852
    inst writeArb of Arbiter_145932
    data.write.valid := writeArb.out.valid
    writeArb.out.ready := data.write.ready
    data.write.bits := writeArb.out.bits
    node T_186850 = bits(writeArb.out.bits.data, 63, 0)
    node T_186851 = bits(writeArb.out.bits.data, 127, 64)
    wire T_186852 : UInt<64>[2]
    T_186852[0] := T_186850
    T_186852[1] := T_186851
    node T_186853 = cat(T_186852[1], T_186852[0])
    data.write.bits.data := T_186853
    metaReadArb.in[4].valid := cpu.req.valid
    node T_186854 = shr(cpu.req.bits.addr, 6)
    metaReadArb.in[4].bits.idx := T_186854
    
    node T_186855 = eq(metaReadArb.in[4].ready, UInt<1>(0))
    when T_186855 : cpu.req.ready := UInt<1>(0)
    readArb.in[3].valid := cpu.req.valid
    readArb.in[3].bits.addr := cpu.req.bits.addr
    readArb.in[3].bits.way_en := SInt<1>(-1)
    
    node T_186856 = eq(readArb.in[3].ready, UInt<1>(0))
    when T_186856 : cpu.req.ready := UInt<1>(0)
    metaReadArb.in[0].valid := s2_recycle
    node T_186857 = shr(s2_req.addr, 6)
    metaReadArb.in[0].bits.idx := T_186857
    readArb.in[0].valid := s2_recycle
    readArb.in[0].bits.addr := s2_req.addr
    readArb.in[0].bits.way_en := SInt<1>(-1)
    node T_186858 = shr(s1_addr, 12)
    node T_186859 = eq(meta.resp[0].tag, T_186858)
    node T_186860 = shr(s1_addr, 12)
    node T_186861 = eq(meta.resp[1].tag, T_186860)
    node T_186862 = shr(s1_addr, 12)
    node T_186863 = eq(meta.resp[2].tag, T_186862)
    node T_186864 = shr(s1_addr, 12)
    node T_186865 = eq(meta.resp[3].tag, T_186864)
    wire T_186866 : UInt<1>[4]
    T_186866[0] := T_186859
    T_186866[1] := T_186861
    T_186866[2] := T_186863
    T_186866[3] := T_186865
    node T_186867 = cat(T_186866[3], T_186866[2])
    node T_186868 = cat(T_186866[1], T_186866[0])
    node s1_tag_eq_way = cat(T_186867, T_186868)
    node T_186869 = bit(s1_tag_eq_way, 0)
    node T_186870 = neq(meta.resp[0].coh.state, UInt<2>(0))
    node T_186871 = and(T_186869, T_186870)
    node T_186872 = bit(s1_tag_eq_way, 1)
    node T_186873 = neq(meta.resp[1].coh.state, UInt<2>(0))
    node T_186874 = and(T_186872, T_186873)
    node T_186875 = bit(s1_tag_eq_way, 2)
    node T_186876 = neq(meta.resp[2].coh.state, UInt<2>(0))
    node T_186877 = and(T_186875, T_186876)
    node T_186878 = bit(s1_tag_eq_way, 3)
    node T_186879 = neq(meta.resp[3].coh.state, UInt<2>(0))
    node T_186880 = and(T_186878, T_186879)
    wire T_186881 : UInt<1>[4]
    T_186881[0] := T_186871
    T_186881[1] := T_186874
    T_186881[2] := T_186877
    T_186881[3] := T_186880
    node T_186882 = cat(T_186881[3], T_186881[2])
    node T_186883 = cat(T_186881[1], T_186881[0])
    node s1_tag_match_way = cat(T_186882, T_186883)
    s1_clk_en := metaReadArb.out.valid
    node T_186884 = eq(s1_valid, UInt<1>(0))
    node T_186885 = and(s1_clk_en, T_186884)
    node T_186886 = eq(s1_replay, UInt<1>(0))
    node s1_writeback = and(T_186885, T_186886)
    reg s2_tag_match_way : UInt<4>
    when s1_clk_en : s2_tag_match_way := s1_tag_match_way
    node T_186887 = eq(s2_tag_match_way, UInt<1>(0))
    node s2_tag_match = eq(T_186887, UInt<1>(0))
    wire T_186888 : UInt<3>[3]
    T_186888[0] := UInt<3>(0)
    T_186888[1] := UInt<3>(1)
    T_186888[2] := UInt<3>(2)
    wire T_186889 : UInt<2>[2]
    T_186889[0] := UInt<2>(0)
    T_186889[1] := UInt<2>(1)
    wire T_186890 : UInt<2>[3]
    T_186890[0] := UInt<2>(1)
    T_186890[1] := UInt<2>(2)
    T_186890[2] := UInt<2>(3)
    wire T_186891 : UInt<2>[2]
    T_186891[0] := UInt<2>(2)
    T_186891[1] := UInt<2>(3)
    wire T_186892 : UInt<2>[1]
    T_186892[0] := UInt<2>(3)
    reg T_186893 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    when s1_clk_en : T_186893 := meta.resp[0].coh
    wire T_186894 : UInt<3>[3]
    T_186894[0] := UInt<3>(0)
    T_186894[1] := UInt<3>(1)
    T_186894[2] := UInt<3>(2)
    wire T_186895 : UInt<2>[2]
    T_186895[0] := UInt<2>(0)
    T_186895[1] := UInt<2>(1)
    wire T_186896 : UInt<2>[3]
    T_186896[0] := UInt<2>(1)
    T_186896[1] := UInt<2>(2)
    T_186896[2] := UInt<2>(3)
    wire T_186897 : UInt<2>[2]
    T_186897[0] := UInt<2>(2)
    T_186897[1] := UInt<2>(3)
    wire T_186898 : UInt<2>[1]
    T_186898[0] := UInt<2>(3)
    reg T_186899 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    when s1_clk_en : T_186899 := meta.resp[1].coh
    wire T_186900 : UInt<3>[3]
    T_186900[0] := UInt<3>(0)
    T_186900[1] := UInt<3>(1)
    T_186900[2] := UInt<3>(2)
    wire T_186901 : UInt<2>[2]
    T_186901[0] := UInt<2>(0)
    T_186901[1] := UInt<2>(1)
    wire T_186902 : UInt<2>[3]
    T_186902[0] := UInt<2>(1)
    T_186902[1] := UInt<2>(2)
    T_186902[2] := UInt<2>(3)
    wire T_186903 : UInt<2>[2]
    T_186903[0] := UInt<2>(2)
    T_186903[1] := UInt<2>(3)
    wire T_186904 : UInt<2>[1]
    T_186904[0] := UInt<2>(3)
    reg T_186905 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    when s1_clk_en : T_186905 := meta.resp[2].coh
    wire T_186906 : UInt<3>[3]
    T_186906[0] := UInt<3>(0)
    T_186906[1] := UInt<3>(1)
    T_186906[2] := UInt<3>(2)
    wire T_186907 : UInt<2>[2]
    T_186907[0] := UInt<2>(0)
    T_186907[1] := UInt<2>(1)
    wire T_186908 : UInt<2>[3]
    T_186908[0] := UInt<2>(1)
    T_186908[1] := UInt<2>(2)
    T_186908[2] := UInt<2>(3)
    wire T_186909 : UInt<2>[2]
    T_186909[0] := UInt<2>(2)
    T_186909[1] := UInt<2>(3)
    wire T_186910 : UInt<2>[1]
    T_186910[0] := UInt<2>(3)
    reg T_186911 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    when s1_clk_en : T_186911 := meta.resp[3].coh
    wire T_186912 : UInt<3>[3]
    T_186912[0] := UInt<3>(0)
    T_186912[1] := UInt<3>(1)
    T_186912[2] := UInt<3>(2)
    wire T_186913 : UInt<2>[2]
    T_186913[0] := UInt<2>(0)
    T_186913[1] := UInt<2>(1)
    wire T_186914 : UInt<2>[3]
    T_186914[0] := UInt<2>(1)
    T_186914[1] := UInt<2>(2)
    T_186914[2] := UInt<2>(3)
    wire T_186915 : UInt<2>[2]
    T_186915[0] := UInt<2>(2)
    T_186915[1] := UInt<2>(3)
    wire T_186916 : UInt<2>[1]
    T_186916[0] := UInt<2>(3)
    wire T_186917 : UInt<3>[3]
    T_186917[0] := UInt<3>(0)
    T_186917[1] := UInt<3>(1)
    T_186917[2] := UInt<3>(2)
    wire T_186918 : UInt<2>[2]
    T_186918[0] := UInt<2>(0)
    T_186918[1] := UInt<2>(1)
    wire T_186919 : UInt<2>[3]
    T_186919[0] := UInt<2>(1)
    T_186919[1] := UInt<2>(2)
    T_186919[2] := UInt<2>(3)
    wire T_186920 : UInt<2>[2]
    T_186920[0] := UInt<2>(2)
    T_186920[1] := UInt<2>(3)
    wire T_186921 : UInt<2>[1]
    T_186921[0] := UInt<2>(3)
    wire T_186922 : UInt<3>[3]
    T_186922[0] := UInt<3>(0)
    T_186922[1] := UInt<3>(1)
    T_186922[2] := UInt<3>(2)
    wire T_186923 : UInt<2>[2]
    T_186923[0] := UInt<2>(0)
    T_186923[1] := UInt<2>(1)
    wire T_186924 : UInt<2>[3]
    T_186924[0] := UInt<2>(1)
    T_186924[1] := UInt<2>(2)
    T_186924[2] := UInt<2>(3)
    wire T_186925 : UInt<2>[2]
    T_186925[0] := UInt<2>(2)
    T_186925[1] := UInt<2>(3)
    wire T_186926 : UInt<2>[1]
    T_186926[0] := UInt<2>(3)
    wire T_186927 : UInt<3>[3]
    T_186927[0] := UInt<3>(0)
    T_186927[1] := UInt<3>(1)
    T_186927[2] := UInt<3>(2)
    wire T_186928 : UInt<2>[2]
    T_186928[0] := UInt<2>(0)
    T_186928[1] := UInt<2>(1)
    wire T_186929 : UInt<2>[3]
    T_186929[0] := UInt<2>(1)
    T_186929[1] := UInt<2>(2)
    T_186929[2] := UInt<2>(3)
    wire T_186930 : UInt<2>[2]
    T_186930[0] := UInt<2>(2)
    T_186930[1] := UInt<2>(3)
    wire T_186931 : UInt<2>[1]
    T_186931[0] := UInt<2>(3)
    wire T_186932 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}[4]
    T_186932[0] := T_186893
    T_186932[1] := T_186899
    T_186932[2] := T_186905
    T_186932[3] := T_186911
    node T_186933 = bit(s2_tag_match_way, 0)
    node T_186934 = bit(s2_tag_match_way, 1)
    node T_186935 = bit(s2_tag_match_way, 2)
    node T_186936 = bit(s2_tag_match_way, 3)
    node T_186937 = cat(T_186932[0].state, UInt<2>(0))
    node T_186938 = cat(T_186937, UInt<4>(0))
    wire T_186939 : UInt<1>
    T_186939 := UInt<1>(0)
    when T_186933 : T_186939 := T_186938
    node T_186940 = cat(T_186932[1].state, UInt<2>(0))
    node T_186941 = cat(T_186940, UInt<4>(0))
    wire T_186942 : UInt<1>
    T_186942 := UInt<1>(0)
    when T_186934 : T_186942 := T_186941
    node T_186943 = cat(T_186932[2].state, UInt<2>(0))
    node T_186944 = cat(T_186943, UInt<4>(0))
    wire T_186945 : UInt<1>
    T_186945 := UInt<1>(0)
    when T_186935 : T_186945 := T_186944
    node T_186946 = cat(T_186932[3].state, UInt<2>(0))
    node T_186947 = cat(T_186946, UInt<4>(0))
    wire T_186948 : UInt<1>
    T_186948 := UInt<1>(0)
    when T_186936 : T_186948 := T_186947
    node T_186949 = or(T_186939, T_186942)
    node T_186950 = or(T_186949, T_186945)
    node T_186951 = or(T_186950, T_186948)
    wire T_186952 : UInt<3>[3]
    T_186952[0] := UInt<3>(0)
    T_186952[1] := UInt<3>(1)
    T_186952[2] := UInt<3>(2)
    wire T_186953 : UInt<2>[2]
    T_186953[0] := UInt<2>(0)
    T_186953[1] := UInt<2>(1)
    wire T_186954 : UInt<2>[3]
    T_186954[0] := UInt<2>(1)
    T_186954[1] := UInt<2>(2)
    T_186954[2] := UInt<2>(3)
    wire T_186955 : UInt<2>[2]
    T_186955[0] := UInt<2>(2)
    T_186955[1] := UInt<2>(3)
    wire T_186956 : UInt<2>[1]
    T_186956[0] := UInt<2>(3)
    wire T_186957 : UInt<3>[3]
    T_186957[0] := UInt<3>(0)
    T_186957[1] := UInt<3>(1)
    T_186957[2] := UInt<3>(2)
    wire T_186958 : UInt<2>[2]
    T_186958[0] := UInt<2>(0)
    T_186958[1] := UInt<2>(1)
    wire T_186959 : UInt<2>[3]
    T_186959[0] := UInt<2>(1)
    T_186959[1] := UInt<2>(2)
    T_186959[2] := UInt<2>(3)
    wire T_186960 : UInt<2>[2]
    T_186960[0] := UInt<2>(2)
    T_186960[1] := UInt<2>(3)
    wire T_186961 : UInt<2>[1]
    T_186961[0] := UInt<2>(3)
    wire s2_hit_state : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    node T_186962 = bits(T_186951, 0, 0)
    s2_hit_state.makeVoluntaryWriteback$default$4 := T_186962
    node T_186963 = bits(T_186951, 1, 1)
    s2_hit_state.makeVoluntaryWriteback$default$3 := T_186963
    node T_186964 = bits(T_186951, 2, 2)
    s2_hit_state.makeVoluntaryRelease$default$5 := T_186964
    node T_186965 = bits(T_186951, 3, 3)
    s2_hit_state.makeVoluntaryRelease$default$4 := T_186965
    node T_186966 = bits(T_186951, 4, 4)
    s2_hit_state.makeRelease$default$3 := T_186966
    node T_186967 = bits(T_186951, 5, 5)
    s2_hit_state.makeRelease$default$2 := T_186967
    node T_186968 = bits(T_186951, 7, 6)
    s2_hit_state.state := T_186968
    node T_186969 = eq(s2_req.cmd, UInt<5>(1))
    node T_186970 = eq(s2_req.cmd, UInt<5>(7))
    node T_186971 = or(T_186969, T_186970)
    node T_186972 = bit(s2_req.cmd, 3)
    node T_186973 = eq(s2_req.cmd, UInt<5>(4))
    node T_186974 = or(T_186972, T_186973)
    node T_186975 = or(T_186971, T_186974)
    node T_186976 = eq(s2_req.cmd, UInt<5>(3))
    node T_186977 = or(T_186975, T_186976)
    node T_186978 = eq(s2_req.cmd, UInt<5>(6))
    node T_186979 = or(T_186977, T_186978)
    node T_186980 = eq(T_186960[0], s2_hit_state.state)
    node T_186981 = eq(T_186960[1], s2_hit_state.state)
    node T_186982 = or(UInt<1>(0), T_186980)
    node T_186983 = or(T_186982, T_186981)
    node T_186984 = eq(T_186959[0], s2_hit_state.state)
    node T_186985 = eq(T_186959[1], s2_hit_state.state)
    node T_186986 = eq(T_186959[2], s2_hit_state.state)
    node T_186987 = or(UInt<1>(0), T_186984)
    node T_186988 = or(T_186987, T_186985)
    node T_186989 = or(T_186988, T_186986)
    wire T_186990 : UInt<1>
    T_186990 := T_186989
    when T_186979 : T_186990 := T_186983
    node T_186991 = and(s2_tag_match, T_186990)
    node T_186992 = eq(s2_req.cmd, UInt<5>(1))
    node T_186993 = eq(s2_req.cmd, UInt<5>(7))
    node T_186994 = or(T_186992, T_186993)
    node T_186995 = bit(s2_req.cmd, 3)
    node T_186996 = eq(s2_req.cmd, UInt<5>(4))
    node T_186997 = or(T_186995, T_186996)
    node T_186998 = or(T_186994, T_186997)
    wire T_186999 : UInt<2>
    T_186999 := s2_hit_state.state
    when T_186998 : T_186999 := UInt<2>(3)
    wire T_187000 : UInt<3>[3]
    T_187000[0] := UInt<3>(0)
    T_187000[1] := UInt<3>(1)
    T_187000[2] := UInt<3>(2)
    wire T_187001 : UInt<2>[2]
    T_187001[0] := UInt<2>(0)
    T_187001[1] := UInt<2>(1)
    wire T_187002 : UInt<2>[3]
    T_187002[0] := UInt<2>(1)
    T_187002[1] := UInt<2>(2)
    T_187002[2] := UInt<2>(3)
    wire T_187003 : UInt<2>[2]
    T_187003[0] := UInt<2>(2)
    T_187003[1] := UInt<2>(3)
    wire T_187004 : UInt<2>[1]
    T_187004[0] := UInt<2>(3)
    wire T_187005 : UInt<3>[3]
    T_187005[0] := UInt<3>(0)
    T_187005[1] := UInt<3>(1)
    T_187005[2] := UInt<3>(2)
    wire T_187006 : UInt<2>[2]
    T_187006[0] := UInt<2>(0)
    T_187006[1] := UInt<2>(1)
    wire T_187007 : UInt<2>[3]
    T_187007[0] := UInt<2>(1)
    T_187007[1] := UInt<2>(2)
    T_187007[2] := UInt<2>(3)
    wire T_187008 : UInt<2>[2]
    T_187008[0] := UInt<2>(2)
    T_187008[1] := UInt<2>(3)
    wire T_187009 : UInt<2>[1]
    T_187009[0] := UInt<2>(3)
    wire T_187010 : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}
    T_187010.state := T_186999
    node T_187011 = eq(s2_hit_state.state, T_187010.state)
    node s2_hit = and(T_186991, T_187011)
    reg lrsc_count : UInt<1>
    onreset lrsc_count := UInt<1>(0)
    node T_187012 = eq(lrsc_count, UInt<1>(0))
    node lrsc_valid = eq(T_187012, UInt<1>(0))
    reg lrsc_addr : UInt
    node s2_lr = eq(s2_req.cmd, UInt<5>(6))
    node s2_sc = eq(s2_req.cmd, UInt<5>(7))
    node T_187013 = shr(s2_req.addr, 6)
    node T_187014 = eq(lrsc_addr, T_187013)
    node s2_lrsc_addr_match = and(lrsc_valid, T_187014)
    node T_187015 = eq(s2_lrsc_addr_match, UInt<1>(0))
    node s2_sc_fail = and(s2_sc, T_187015)
    when lrsc_valid : 
      node T_187016 = subw(lrsc_count, UInt<1>(1))
      lrsc_count := T_187016
    
    
    node T_187017 = and(s2_valid_masked, s2_hit)
    node T_187018 = or(T_187017, s2_replay)
    when T_187018 : 
      when s2_lr : 
        
        node T_187019 = eq(lrsc_valid, UInt<1>(0))
        when T_187019 : lrsc_count := UInt<5>(31)
        node T_187020 = shr(s2_req.addr, 6)
        lrsc_addr := T_187020
      when s2_sc : lrsc_count := UInt<1>(0)
    when cpu.invalidate_lr : lrsc_count := UInt<1>(0)
    wire s2_data : UInt<128>[4]
    wire T_187021 : UInt<64>[2]
    T_187021[0] := T_187022
    T_187021[1] := T_187023
    reg T_187024 : UInt<64>[2]
    node T_187025 = bit(s1_tag_eq_way, 0)
    node T_187026 = and(s1_clk_en, T_187025)
    node T_187027 = eq(UInt<1>(1), UInt<1>(0))
    node T_187028 = or(UInt<1>(1), T_187027)
    node T_187029 = or(T_187028, s1_writeback)
    node T_187030 = and(T_187026, T_187029)
    when T_187030 : 
      node T_187031 = shr(data.resp[0], 0)
      T_187024[0] := T_187031
    node T_187032 = eq(UInt<1>(1), UInt<1>(0))
    node T_187033 = or(UInt<1>(0), T_187032)
    node T_187034 = or(T_187033, s1_writeback)
    node T_187035 = and(T_187026, T_187034)
    when T_187035 : 
      node T_187036 = shr(data.resp[0], 64)
      T_187024[1] := T_187036
    node T_187037 = cat(T_187024[1], T_187024[0])
    s2_data[0] := T_187037
    wire T_187038 : UInt<64>[2]
    T_187038[0] := T_187039
    T_187038[1] := T_187040
    reg T_187041 : UInt<64>[2]
    node T_187042 = bit(s1_tag_eq_way, 1)
    node T_187043 = and(s1_clk_en, T_187042)
    node T_187044 = eq(UInt<1>(1), UInt<1>(0))
    node T_187045 = or(UInt<1>(1), T_187044)
    node T_187046 = or(T_187045, s1_writeback)
    node T_187047 = and(T_187043, T_187046)
    when T_187047 : 
      node T_187048 = shr(data.resp[1], 0)
      T_187041[0] := T_187048
    node T_187049 = eq(UInt<1>(1), UInt<1>(0))
    node T_187050 = or(UInt<1>(0), T_187049)
    node T_187051 = or(T_187050, s1_writeback)
    node T_187052 = and(T_187043, T_187051)
    when T_187052 : 
      node T_187053 = shr(data.resp[1], 64)
      T_187041[1] := T_187053
    node T_187054 = cat(T_187041[1], T_187041[0])
    s2_data[1] := T_187054
    wire T_187055 : UInt<64>[2]
    T_187055[0] := T_187056
    T_187055[1] := T_187057
    reg T_187058 : UInt<64>[2]
    node T_187059 = bit(s1_tag_eq_way, 2)
    node T_187060 = and(s1_clk_en, T_187059)
    node T_187061 = eq(UInt<1>(1), UInt<1>(0))
    node T_187062 = or(UInt<1>(1), T_187061)
    node T_187063 = or(T_187062, s1_writeback)
    node T_187064 = and(T_187060, T_187063)
    when T_187064 : 
      node T_187065 = shr(data.resp[2], 0)
      T_187058[0] := T_187065
    node T_187066 = eq(UInt<1>(1), UInt<1>(0))
    node T_187067 = or(UInt<1>(0), T_187066)
    node T_187068 = or(T_187067, s1_writeback)
    node T_187069 = and(T_187060, T_187068)
    when T_187069 : 
      node T_187070 = shr(data.resp[2], 64)
      T_187058[1] := T_187070
    node T_187071 = cat(T_187058[1], T_187058[0])
    s2_data[2] := T_187071
    wire T_187072 : UInt<64>[2]
    T_187072[0] := T_187073
    T_187072[1] := T_187074
    reg T_187075 : UInt<64>[2]
    node T_187076 = bit(s1_tag_eq_way, 3)
    node T_187077 = and(s1_clk_en, T_187076)
    node T_187078 = eq(UInt<1>(1), UInt<1>(0))
    node T_187079 = or(UInt<1>(1), T_187078)
    node T_187080 = or(T_187079, s1_writeback)
    node T_187081 = and(T_187077, T_187080)
    when T_187081 : 
      node T_187082 = shr(data.resp[3], 0)
      T_187075[0] := T_187082
    node T_187083 = eq(UInt<1>(1), UInt<1>(0))
    node T_187084 = or(UInt<1>(0), T_187083)
    node T_187085 = or(T_187084, s1_writeback)
    node T_187086 = and(T_187077, T_187085)
    when T_187086 : 
      node T_187087 = shr(data.resp[3], 64)
      T_187075[1] := T_187087
    node T_187088 = cat(T_187075[1], T_187075[0])
    s2_data[3] := T_187088
    node T_187089 = bit(s2_tag_match_way, 0)
    node T_187090 = bit(s2_tag_match_way, 1)
    node T_187091 = bit(s2_tag_match_way, 2)
    node T_187092 = bit(s2_tag_match_way, 3)
    wire T_187093 : UInt<1>
    T_187093 := UInt<1>(0)
    when T_187089 : T_187093 := s2_data[0]
    wire T_187094 : UInt<1>
    T_187094 := UInt<1>(0)
    when T_187090 : T_187094 := s2_data[1]
    wire T_187095 : UInt<1>
    T_187095 := UInt<1>(0)
    when T_187091 : T_187095 := s2_data[2]
    wire T_187096 : UInt<1>
    T_187096 := UInt<1>(0)
    when T_187092 : T_187096 := s2_data[3]
    node T_187097 = or(T_187093, T_187094)
    node T_187098 = or(T_187097, T_187095)
    node T_187099 = or(T_187098, T_187096)
    wire s2_data_muxed : UInt<128>
    node T_187100 = bits(T_187099, 127, 0)
    s2_data_muxed := T_187100
    node T_187101 = bits(s2_data_muxed, 63, 0)
    node T_187102 = bits(s2_data_muxed, 127, 64)
    wire T_187103 : UInt<64>[2]
    T_187103[0] := T_187101
    T_187103[1] := T_187102
    node s2_data_corrected = cat(T_187103[1], T_187103[0])
    wire T_187104 : UInt<64>[2]
    T_187104[0] := T_187101
    T_187104[1] := T_187102
    node s2_data_uncorrected = cat(T_187104[1], T_187104[0])
    wire T_187105 : UInt<1>[2]
    T_187105[0] := UInt<1>(0)
    T_187105[1] := UInt<1>(0)
    node T_187106 = cat(T_187105[1], T_187105[0])
    node T_187107 = dshr(T_187106, UInt<1>(0))
    node s2_data_correctable = bit(T_187107, 0)
    node T_187108 = and(s2_valid_masked, s2_hit)
    node T_187109 = or(T_187108, s2_replay)
    node T_187110 = eq(s2_sc_fail, UInt<1>(0))
    node T_187111 = and(T_187109, T_187110)
    node T_187112 = eq(s2_req.cmd, UInt<5>(1))
    node T_187113 = eq(s2_req.cmd, UInt<5>(7))
    node T_187114 = or(T_187112, T_187113)
    node T_187115 = bit(s2_req.cmd, 3)
    node T_187116 = eq(s2_req.cmd, UInt<5>(4))
    node T_187117 = or(T_187115, T_187116)
    node T_187118 = or(T_187114, T_187117)
    node T_187119 = and(T_187111, T_187118)
    s3_valid := T_187119
    inst amoalu of AMOALU_147223
    
    
    node T_187120 = or(s2_valid, s2_replay)
    node T_187121 = eq(s2_req.cmd, UInt<5>(1))
    node T_187122 = eq(s2_req.cmd, UInt<5>(7))
    node T_187123 = or(T_187121, T_187122)
    node T_187124 = bit(s2_req.cmd, 3)
    node T_187125 = eq(s2_req.cmd, UInt<5>(4))
    node T_187126 = or(T_187124, T_187125)
    node T_187127 = or(T_187123, T_187126)
    node T_187128 = or(T_187127, s2_data_correctable)
    node T_187129 = and(T_187120, T_187128)
    when T_187129 : 
      s3_req := s2_req
      wire T_187130 : UInt<64>
      T_187130 := amoalu.out
      when s2_data_correctable : T_187130 := s2_data_corrected
      s3_req.data := T_187130
      s3_way := s2_tag_match_way
    writeArb.in[0].bits.addr := s3_req.addr
    node rowIdx = bits(s3_req.addr, 3, 3)
    node rowWMask = dshl(UInt<1>(1), rowIdx)
    writeArb.in[0].bits.wmask := rowWMask
    node T_187131 = cat(s3_req.data, s3_req.data)
    writeArb.in[0].bits.data := T_187131
    writeArb.in[0].valid := s3_valid
    writeArb.in[0].bits.way_en := s3_way
    wire T_187132 : UInt<1>
    T_187132 := UInt<1>(0)
    reg T_187133 : UInt<16>
    onreset T_187133 := UInt<16>(1)
    when T_187132 : 
      node T_187134 = bit(T_187133, 0)
      node T_187135 = bit(T_187133, 2)
      node T_187136 = xor(T_187134, T_187135)
      node T_187137 = bit(T_187133, 3)
      node T_187138 = xor(T_187136, T_187137)
      node T_187139 = bit(T_187133, 5)
      node T_187140 = xor(T_187138, T_187139)
      node T_187141 = bits(T_187133, 15, 1)
      node T_187142 = cat(T_187140, T_187141)
      T_187133 := T_187142
    node T_187143 = bits(T_187133, 1, 0)
    node s1_replaced_way_en = dshl(UInt<1>(1), T_187143)
    node T_187144 = bits(T_187133, 1, 0)
    reg T_187145 : UInt<2>
    when s1_clk_en : T_187145 := T_187144
    node s2_replaced_way_en = dshl(UInt<1>(1), T_187145)
    node T_187146 = bit(s1_replaced_way_en, 0)
    node T_187147 = and(s1_clk_en, T_187146)
    wire T_187148 : UInt<3>[3]
    T_187148[0] := UInt<3>(0)
    T_187148[1] := UInt<3>(1)
    T_187148[2] := UInt<3>(2)
    wire T_187149 : UInt<2>[2]
    T_187149[0] := UInt<2>(0)
    T_187149[1] := UInt<2>(1)
    wire T_187150 : UInt<2>[3]
    T_187150[0] := UInt<2>(1)
    T_187150[1] := UInt<2>(2)
    T_187150[2] := UInt<2>(3)
    wire T_187151 : UInt<2>[2]
    T_187151[0] := UInt<2>(2)
    T_187151[1] := UInt<2>(3)
    wire T_187152 : UInt<2>[1]
    T_187152[0] := UInt<2>(3)
    reg T_187153 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when T_187147 : T_187153 := meta.resp[0]
    node T_187154 = bit(s1_replaced_way_en, 1)
    node T_187155 = and(s1_clk_en, T_187154)
    wire T_187156 : UInt<3>[3]
    T_187156[0] := UInt<3>(0)
    T_187156[1] := UInt<3>(1)
    T_187156[2] := UInt<3>(2)
    wire T_187157 : UInt<2>[2]
    T_187157[0] := UInt<2>(0)
    T_187157[1] := UInt<2>(1)
    wire T_187158 : UInt<2>[3]
    T_187158[0] := UInt<2>(1)
    T_187158[1] := UInt<2>(2)
    T_187158[2] := UInt<2>(3)
    wire T_187159 : UInt<2>[2]
    T_187159[0] := UInt<2>(2)
    T_187159[1] := UInt<2>(3)
    wire T_187160 : UInt<2>[1]
    T_187160[0] := UInt<2>(3)
    reg T_187161 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when T_187155 : T_187161 := meta.resp[1]
    node T_187162 = bit(s1_replaced_way_en, 2)
    node T_187163 = and(s1_clk_en, T_187162)
    wire T_187164 : UInt<3>[3]
    T_187164[0] := UInt<3>(0)
    T_187164[1] := UInt<3>(1)
    T_187164[2] := UInt<3>(2)
    wire T_187165 : UInt<2>[2]
    T_187165[0] := UInt<2>(0)
    T_187165[1] := UInt<2>(1)
    wire T_187166 : UInt<2>[3]
    T_187166[0] := UInt<2>(1)
    T_187166[1] := UInt<2>(2)
    T_187166[2] := UInt<2>(3)
    wire T_187167 : UInt<2>[2]
    T_187167[0] := UInt<2>(2)
    T_187167[1] := UInt<2>(3)
    wire T_187168 : UInt<2>[1]
    T_187168[0] := UInt<2>(3)
    reg T_187169 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when T_187163 : T_187169 := meta.resp[2]
    node T_187170 = bit(s1_replaced_way_en, 3)
    node T_187171 = and(s1_clk_en, T_187170)
    wire T_187172 : UInt<3>[3]
    T_187172[0] := UInt<3>(0)
    T_187172[1] := UInt<3>(1)
    T_187172[2] := UInt<3>(2)
    wire T_187173 : UInt<2>[2]
    T_187173[0] := UInt<2>(0)
    T_187173[1] := UInt<2>(1)
    wire T_187174 : UInt<2>[3]
    T_187174[0] := UInt<2>(1)
    T_187174[1] := UInt<2>(2)
    T_187174[2] := UInt<2>(3)
    wire T_187175 : UInt<2>[2]
    T_187175[0] := UInt<2>(2)
    T_187175[1] := UInt<2>(3)
    wire T_187176 : UInt<2>[1]
    T_187176[0] := UInt<2>(3)
    reg T_187177 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    when T_187171 : T_187177 := meta.resp[3]
    wire T_187178 : UInt<3>[3]
    T_187178[0] := UInt<3>(0)
    T_187178[1] := UInt<3>(1)
    T_187178[2] := UInt<3>(2)
    wire T_187179 : UInt<2>[2]
    T_187179[0] := UInt<2>(0)
    T_187179[1] := UInt<2>(1)
    wire T_187180 : UInt<2>[3]
    T_187180[0] := UInt<2>(1)
    T_187180[1] := UInt<2>(2)
    T_187180[2] := UInt<2>(3)
    wire T_187181 : UInt<2>[2]
    T_187181[0] := UInt<2>(2)
    T_187181[1] := UInt<2>(3)
    wire T_187182 : UInt<2>[1]
    T_187182[0] := UInt<2>(3)
    wire T_187183 : UInt<3>[3]
    T_187183[0] := UInt<3>(0)
    T_187183[1] := UInt<3>(1)
    T_187183[2] := UInt<3>(2)
    wire T_187184 : UInt<2>[2]
    T_187184[0] := UInt<2>(0)
    T_187184[1] := UInt<2>(1)
    wire T_187185 : UInt<2>[3]
    T_187185[0] := UInt<2>(1)
    T_187185[1] := UInt<2>(2)
    T_187185[2] := UInt<2>(3)
    wire T_187186 : UInt<2>[2]
    T_187186[0] := UInt<2>(2)
    T_187186[1] := UInt<2>(3)
    wire T_187187 : UInt<2>[1]
    T_187187[0] := UInt<2>(3)
    wire T_187188 : UInt<3>[3]
    T_187188[0] := UInt<3>(0)
    T_187188[1] := UInt<3>(1)
    T_187188[2] := UInt<3>(2)
    wire T_187189 : UInt<2>[2]
    T_187189[0] := UInt<2>(0)
    T_187189[1] := UInt<2>(1)
    wire T_187190 : UInt<2>[3]
    T_187190[0] := UInt<2>(1)
    T_187190[1] := UInt<2>(2)
    T_187190[2] := UInt<2>(3)
    wire T_187191 : UInt<2>[2]
    T_187191[0] := UInt<2>(2)
    T_187191[1] := UInt<2>(3)
    wire T_187192 : UInt<2>[1]
    T_187192[0] := UInt<2>(3)
    wire T_187193 : UInt<3>[3]
    T_187193[0] := UInt<3>(0)
    T_187193[1] := UInt<3>(1)
    T_187193[2] := UInt<3>(2)
    wire T_187194 : UInt<2>[2]
    T_187194[0] := UInt<2>(0)
    T_187194[1] := UInt<2>(1)
    wire T_187195 : UInt<2>[3]
    T_187195[0] := UInt<2>(1)
    T_187195[1] := UInt<2>(2)
    T_187195[2] := UInt<2>(3)
    wire T_187196 : UInt<2>[2]
    T_187196[0] := UInt<2>(2)
    T_187196[1] := UInt<2>(3)
    wire T_187197 : UInt<2>[1]
    T_187197[0] := UInt<2>(3)
    wire T_187198 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}[4]
    T_187198[0] := T_187153
    T_187198[1] := T_187161
    T_187198[2] := T_187169
    T_187198[3] := T_187177
    node T_187199 = bit(s2_replaced_way_en, 0)
    node T_187200 = bit(s2_replaced_way_en, 1)
    node T_187201 = bit(s2_replaced_way_en, 2)
    node T_187202 = bit(s2_replaced_way_en, 3)
    node T_187203 = cat(T_187198[0].coh.state, UInt<1>(0))
    node T_187204 = cat(T_187198[0].tag, T_187203)
    node T_187205 = cat(T_187204, UInt<4>(0))
    node T_187206 = cat(UInt<1>(0), T_187198[0].coh.state)
    node T_187207 = cat(T_187206, UInt<2>(0))
    node T_187208 = cat(T_187207, UInt<4>(0))
    node T_187209 = cat(T_187205, T_187208)
    wire T_187210 : UInt<1>
    T_187210 := UInt<1>(0)
    when T_187199 : T_187210 := T_187209
    node T_187211 = cat(T_187198[1].coh.state, UInt<1>(0))
    node T_187212 = cat(T_187198[1].tag, T_187211)
    node T_187213 = cat(T_187212, UInt<4>(0))
    node T_187214 = cat(UInt<1>(0), T_187198[1].coh.state)
    node T_187215 = cat(T_187214, UInt<2>(0))
    node T_187216 = cat(T_187215, UInt<4>(0))
    node T_187217 = cat(T_187213, T_187216)
    wire T_187218 : UInt<1>
    T_187218 := UInt<1>(0)
    when T_187200 : T_187218 := T_187217
    node T_187219 = cat(T_187198[2].coh.state, UInt<1>(0))
    node T_187220 = cat(T_187198[2].tag, T_187219)
    node T_187221 = cat(T_187220, UInt<4>(0))
    node T_187222 = cat(UInt<1>(0), T_187198[2].coh.state)
    node T_187223 = cat(T_187222, UInt<2>(0))
    node T_187224 = cat(T_187223, UInt<4>(0))
    node T_187225 = cat(T_187221, T_187224)
    wire T_187226 : UInt<1>
    T_187226 := UInt<1>(0)
    when T_187201 : T_187226 := T_187225
    node T_187227 = cat(T_187198[3].coh.state, UInt<1>(0))
    node T_187228 = cat(T_187198[3].tag, T_187227)
    node T_187229 = cat(T_187228, UInt<4>(0))
    node T_187230 = cat(UInt<1>(0), T_187198[3].coh.state)
    node T_187231 = cat(T_187230, UInt<2>(0))
    node T_187232 = cat(T_187231, UInt<4>(0))
    node T_187233 = cat(T_187229, T_187232)
    wire T_187234 : UInt<1>
    T_187234 := UInt<1>(0)
    when T_187202 : T_187234 := T_187233
    node T_187235 = or(T_187210, T_187218)
    node T_187236 = or(T_187235, T_187226)
    node T_187237 = or(T_187236, T_187234)
    wire T_187238 : UInt<3>[3]
    T_187238[0] := UInt<3>(0)
    T_187238[1] := UInt<3>(1)
    T_187238[2] := UInt<3>(2)
    wire T_187239 : UInt<2>[2]
    T_187239[0] := UInt<2>(0)
    T_187239[1] := UInt<2>(1)
    wire T_187240 : UInt<2>[3]
    T_187240[0] := UInt<2>(1)
    T_187240[1] := UInt<2>(2)
    T_187240[2] := UInt<2>(3)
    wire T_187241 : UInt<2>[2]
    T_187241[0] := UInt<2>(2)
    T_187241[1] := UInt<2>(3)
    wire T_187242 : UInt<2>[1]
    T_187242[0] := UInt<2>(3)
    wire T_187243 : UInt<3>[3]
    T_187243[0] := UInt<3>(0)
    T_187243[1] := UInt<3>(1)
    T_187243[2] := UInt<3>(2)
    wire T_187244 : UInt<2>[2]
    T_187244[0] := UInt<2>(0)
    T_187244[1] := UInt<2>(1)
    wire T_187245 : UInt<2>[3]
    T_187245[0] := UInt<2>(1)
    T_187245[1] := UInt<2>(2)
    T_187245[2] := UInt<2>(3)
    wire T_187246 : UInt<2>[2]
    T_187246[0] := UInt<2>(2)
    T_187246[1] := UInt<2>(3)
    wire T_187247 : UInt<2>[1]
    T_187247[0] := UInt<2>(3)
    wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    node T_187248 = bits(T_187237, 0, 0)
    s2_repl_meta.coh.makeVoluntaryWriteback$default$4 := T_187248
    node T_187249 = bits(T_187237, 1, 1)
    s2_repl_meta.coh.makeVoluntaryWriteback$default$3 := T_187249
    node T_187250 = bits(T_187237, 2, 2)
    s2_repl_meta.coh.makeVoluntaryRelease$default$5 := T_187250
    node T_187251 = bits(T_187237, 3, 3)
    s2_repl_meta.coh.makeVoluntaryRelease$default$4 := T_187251
    node T_187252 = bits(T_187237, 4, 4)
    s2_repl_meta.coh.makeRelease$default$3 := T_187252
    node T_187253 = bits(T_187237, 5, 5)
    s2_repl_meta.coh.makeRelease$default$2 := T_187253
    node T_187254 = bits(T_187237, 7, 6)
    s2_repl_meta.coh.state := T_187254
    node T_187255 = bits(T_187237, 8, 8)
    s2_repl_meta.coh.makeVoluntaryWriteback$default$4 := T_187255
    node T_187256 = bits(T_187237, 9, 9)
    s2_repl_meta.coh.makeVoluntaryWriteback$default$3 := T_187256
    node T_187257 = bits(T_187237, 10, 10)
    s2_repl_meta.coh.makeVoluntaryRelease$default$5 := T_187257
    node T_187258 = bits(T_187237, 11, 11)
    s2_repl_meta.coh.makeVoluntaryRelease$default$4 := T_187258
    node T_187259 = bits(T_187237, 12, 12)
    s2_repl_meta.coh.makeRelease$default$3 := T_187259
    node T_187260 = bits(T_187237, 13, 13)
    s2_repl_meta.coh.makeRelease$default$2 := T_187260
    node T_187261 = bits(T_187237, 15, 14)
    s2_repl_meta.coh.state := T_187261
    node T_187262 = bits(T_187237, 35, 16)
    s2_repl_meta.tag := T_187262
    node T_187263 = eq(s2_hit, UInt<1>(0))
    node T_187264 = and(s2_valid_masked, T_187263)
    node T_187265 = eq(s2_req.cmd, UInt<5>(2))
    node T_187266 = eq(s2_req.cmd, UInt<5>(3))
    node T_187267 = or(T_187265, T_187266)
    node T_187268 = eq(s2_req.cmd, UInt<5>(0))
    node T_187269 = eq(s2_req.cmd, UInt<5>(6))
    node T_187270 = or(T_187268, T_187269)
    node T_187271 = bit(s2_req.cmd, 3)
    node T_187272 = eq(s2_req.cmd, UInt<5>(4))
    node T_187273 = or(T_187271, T_187272)
    node T_187274 = or(T_187270, T_187273)
    node T_187275 = or(T_187267, T_187274)
    node T_187276 = eq(s2_req.cmd, UInt<5>(1))
    node T_187277 = eq(s2_req.cmd, UInt<5>(7))
    node T_187278 = or(T_187276, T_187277)
    node T_187279 = bit(s2_req.cmd, 3)
    node T_187280 = eq(s2_req.cmd, UInt<5>(4))
    node T_187281 = or(T_187279, T_187280)
    node T_187282 = or(T_187278, T_187281)
    node T_187283 = or(T_187275, T_187282)
    node T_187284 = and(T_187264, T_187283)
    mshrs.req.valid := T_187284
    mshrs.req.bits := s2_req
    mshrs.req.bits.tag_match := s2_tag_match
    wire T_187285 : UInt<3>[3]
    T_187285[0] := UInt<3>(0)
    T_187285[1] := UInt<3>(1)
    T_187285[2] := UInt<3>(2)
    wire T_187286 : UInt<2>[2]
    T_187286[0] := UInt<2>(0)
    T_187286[1] := UInt<2>(1)
    wire T_187287 : UInt<2>[3]
    T_187287[0] := UInt<2>(1)
    T_187287[1] := UInt<2>(2)
    T_187287[2] := UInt<2>(3)
    wire T_187288 : UInt<2>[2]
    T_187288[0] := UInt<2>(2)
    T_187288[1] := UInt<2>(3)
    wire T_187289 : UInt<2>[1]
    T_187289[0] := UInt<2>(3)
    wire T_187290 : UInt<3>[3]
    T_187290[0] := UInt<3>(0)
    T_187290[1] := UInt<3>(1)
    T_187290[2] := UInt<3>(2)
    wire T_187291 : UInt<2>[2]
    T_187291[0] := UInt<2>(0)
    T_187291[1] := UInt<2>(1)
    wire T_187292 : UInt<2>[3]
    T_187292[0] := UInt<2>(1)
    T_187292[1] := UInt<2>(2)
    T_187292[2] := UInt<2>(3)
    wire T_187293 : UInt<2>[2]
    T_187293[0] := UInt<2>(2)
    T_187293[1] := UInt<2>(3)
    wire T_187294 : UInt<2>[1]
    T_187294[0] := UInt<2>(3)
    wire T_187295 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    T_187295.tag := s2_repl_meta.tag
    T_187295.coh := s2_hit_state
    wire T_187296 : UInt<3>[3]
    T_187296[0] := UInt<3>(0)
    T_187296[1] := UInt<3>(1)
    T_187296[2] := UInt<3>(2)
    wire T_187297 : UInt<2>[2]
    T_187297[0] := UInt<2>(0)
    T_187297[1] := UInt<2>(1)
    wire T_187298 : UInt<2>[3]
    T_187298[0] := UInt<2>(1)
    T_187298[1] := UInt<2>(2)
    T_187298[2] := UInt<2>(3)
    wire T_187299 : UInt<2>[2]
    T_187299[0] := UInt<2>(2)
    T_187299[1] := UInt<2>(3)
    wire T_187300 : UInt<2>[1]
    T_187300[0] := UInt<2>(3)
    wire T_187301 : {tag : UInt<20>, coh : {state : UInt<2>, makeRelease$default$2 : UInt<1>, makeRelease$default$3 : UInt<1>, makeVoluntaryRelease$default$4 : UInt<1>, makeVoluntaryRelease$default$5 : UInt<1>, makeVoluntaryWriteback$default$3 : UInt<1>, makeVoluntaryWriteback$default$4 : UInt<1>}}
    T_187301 := s2_repl_meta
    when s2_tag_match : T_187301 := T_187295
    mshrs.req.bits.old_meta := T_187301
    wire T_187302 : UInt<5>
    T_187302 := s2_replaced_way_en
    when s2_tag_match : T_187302 := s2_tag_match_way
    mshrs.req.bits.way_en := T_187302
    mshrs.req.bits.data := s2_req.data
    
    node T_187303 = and(mshrs.req.ready, mshrs.req.valid)
    when T_187303 : T_187132 := UInt<1>(1)
    mem__.acquire <> mshrs.mem_req
    readArb.in[1].valid := mshrs.replay.valid
    readArb.in[1].bits := mshrs.replay.bits
    readArb.in[1].bits.way_en := SInt<1>(-1)
    mshrs.replay.ready := readArb.in[1].ready
    node T_187304 = and(mshrs.replay.valid, readArb.in[1].ready)
    s1_replay := T_187304
    metaReadArb.in[1] <> mshrs.meta_read
    metaWriteArb.in[0] <> mshrs.meta_write
    wire T_187305 : UInt<3>[3]
    T_187305[0] := UInt<3>(0)
    T_187305[1] := UInt<3>(1)
    T_187305[2] := UInt<3>(2)
    wire T_187306 : UInt<2>[2]
    T_187306[0] := UInt<2>(0)
    T_187306[1] := UInt<2>(1)
    wire T_187307 : UInt<2>[3]
    T_187307[0] := UInt<2>(1)
    T_187307[1] := UInt<2>(2)
    T_187307[2] := UInt<2>(3)
    wire T_187308 : UInt<2>[2]
    T_187308[0] := UInt<2>(2)
    T_187308[1] := UInt<2>(3)
    wire T_187309 : UInt<2>[1]
    T_187309[0] := UInt<2>(3)
    inst releaseArb of LockingArbiter_148764
    releaseArb.out <> mem__.release
    node T_187310 = eq(lrsc_valid, UInt<1>(0))
    node T_187311 = and(mem__.probe.valid, T_187310)
    prober.req.valid := T_187311
    node T_187312 = eq(lrsc_valid, UInt<1>(0))
    node T_187313 = and(prober.req.ready, T_187312)
    mem__.probe.ready := T_187313
    prober.req.bits := mem__.probe.bits
    prober.rep <> releaseArb.in[1]
    prober.way_en := s2_tag_match_way
    prober.block_state := s2_hit_state
    prober.meta_read <> metaReadArb.in[2]
    prober.meta_write <> metaWriteArb.in[1]
    prober.mshr_rdy := mshrs.probe_rdy
    inst T_187314 of FlowThroughSerializer_148912
    T_187314.in.valid := mem__.grant.valid
    T_187314.in.bits := mem__.grant.bits
    mem__.grant.ready := T_187314.in.ready
    node T_187315 = and(T_187314.out.ready, T_187314.out.valid)
    mshrs.mem_grant.valid := T_187315
    mshrs.mem_grant.bits := T_187314.out.bits
    wire T_187316 : UInt<3>[2]
    T_187316[0] := UInt<3>(5)
    T_187316[1] := UInt<3>(4)
    node T_187317 = eq(T_187316[0], T_187314.out.bits.g_type)
    node T_187318 = eq(T_187316[1], T_187314.out.bits.g_type)
    node T_187319 = or(UInt<1>(0), T_187317)
    node T_187320 = or(T_187319, T_187318)
    node T_187321 = eq(T_186683[0], T_187314.out.bits.g_type)
    node T_187322 = eq(T_186683[1], T_187314.out.bits.g_type)
    node T_187323 = or(UInt<1>(0), T_187321)
    node T_187324 = or(T_187323, T_187322)
    wire T_187325 : UInt<1>
    T_187325 := T_187324
    when T_187314.out.bits.is_builtin_type : T_187325 := T_187320
    node T_187326 = eq(T_187325, UInt<1>(0))
    node T_187327 = or(writeArb.in[1].ready, T_187326)
    T_187314.out.ready := T_187327
    wire T_187328 : UInt<3>[2]
    T_187328[0] := UInt<3>(5)
    T_187328[1] := UInt<3>(4)
    node T_187329 = eq(T_187328[0], T_187314.out.bits.g_type)
    node T_187330 = eq(T_187328[1], T_187314.out.bits.g_type)
    node T_187331 = or(UInt<1>(0), T_187329)
    node T_187332 = or(T_187331, T_187330)
    node T_187333 = eq(T_186683[0], T_187314.out.bits.g_type)
    node T_187334 = eq(T_186683[1], T_187314.out.bits.g_type)
    node T_187335 = or(UInt<1>(0), T_187333)
    node T_187336 = or(T_187335, T_187334)
    wire T_187337 : UInt<1>
    T_187337 := T_187336
    when T_187314.out.bits.is_builtin_type : T_187337 := T_187332
    node T_187338 = and(T_187314.out.valid, T_187337)
    writeArb.in[1].valid := T_187338
    writeArb.in[1].bits.addr := mshrs.refill.addr
    writeArb.in[1].bits.way_en := mshrs.refill.way_en
    writeArb.in[1].bits.wmask := SInt<1>(-1)
    node T_187339 = bits(T_187314.out.bits.data, 127, 0)
    writeArb.in[1].bits.data := T_187339
    node T_187340 = eq(T_187314.out.valid, UInt<1>(0))
    node T_187341 = or(T_187340, T_187314.out.ready)
    readArb.out.ready := T_187341
    readArb.out <> data.read
    wire T_187342 : UInt<3>[3]
    T_187342[0] := UInt<3>(0)
    T_187342[1] := UInt<3>(1)
    T_187342[2] := UInt<3>(2)
    wire T_187343 : UInt<2>[2]
    T_187343[0] := UInt<2>(0)
    T_187343[1] := UInt<2>(1)
    wire T_187344 : UInt<2>[3]
    T_187344[0] := UInt<2>(1)
    T_187344[1] := UInt<2>(2)
    T_187344[2] := UInt<2>(3)
    wire T_187345 : UInt<2>[2]
    T_187345[0] := UInt<2>(2)
    T_187345[1] := UInt<2>(3)
    wire T_187346 : UInt<2>[1]
    T_187346[0] := UInt<2>(3)
    inst wbArb of Arbiter_149454
    prober.wb_req <> wbArb.in[0]
    mshrs.wb_req <> wbArb.in[1]
    wbArb.out <> wb.req
    wb.meta_read <> metaReadArb.in[3]
    wb.data_req <> readArb.in[2]
    wb.data_resp := s2_data_corrected
    releaseArb.in[0] <> wb.release
    reg s4_valid : UInt<1>
    onreset s4_valid := UInt<1>(0)
    s4_valid := s3_valid
    node T_187347 = and(s3_valid, metaReadArb.out.valid)
    reg s4_req : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}
    when T_187347 : s4_req := s3_req
    node T_187348 = or(s2_valid_masked, s2_replay)
    node T_187349 = eq(s2_sc_fail, UInt<1>(0))
    node T_187350 = and(T_187348, T_187349)
    node T_187351 = shr(s1_addr, 3)
    node T_187352 = shr(s2_req.addr, 3)
    node T_187353 = eq(T_187351, T_187352)
    node T_187354 = and(T_187350, T_187353)
    node T_187355 = eq(s2_req.cmd, UInt<5>(1))
    node T_187356 = eq(s2_req.cmd, UInt<5>(7))
    node T_187357 = or(T_187355, T_187356)
    node T_187358 = bit(s2_req.cmd, 3)
    node T_187359 = eq(s2_req.cmd, UInt<5>(4))
    node T_187360 = or(T_187358, T_187359)
    node T_187361 = or(T_187357, T_187360)
    node T_187362 = and(T_187354, T_187361)
    node T_187363 = shr(s1_addr, 3)
    node T_187364 = shr(s3_req.addr, 3)
    node T_187365 = eq(T_187363, T_187364)
    node T_187366 = and(s3_valid, T_187365)
    node T_187367 = eq(s3_req.cmd, UInt<5>(1))
    node T_187368 = eq(s3_req.cmd, UInt<5>(7))
    node T_187369 = or(T_187367, T_187368)
    node T_187370 = bit(s3_req.cmd, 3)
    node T_187371 = eq(s3_req.cmd, UInt<5>(4))
    node T_187372 = or(T_187370, T_187371)
    node T_187373 = or(T_187369, T_187372)
    node T_187374 = and(T_187366, T_187373)
    node T_187375 = shr(s1_addr, 3)
    node T_187376 = shr(s4_req.addr, 3)
    node T_187377 = eq(T_187375, T_187376)
    node T_187378 = and(s4_valid, T_187377)
    node T_187379 = eq(s4_req.cmd, UInt<5>(1))
    node T_187380 = eq(s4_req.cmd, UInt<5>(7))
    node T_187381 = or(T_187379, T_187380)
    node T_187382 = bit(s4_req.cmd, 3)
    node T_187383 = eq(s4_req.cmd, UInt<5>(4))
    node T_187384 = or(T_187382, T_187383)
    node T_187385 = or(T_187381, T_187384)
    node T_187386 = and(T_187378, T_187385)
    reg s2_store_bypass_data : UInt<64>
    reg s2_store_bypass : UInt<1>
    when s1_clk_en : 
      s2_store_bypass := UInt<1>(0)
      
      
      node T_187387 = or(T_187362, T_187374)
      node T_187388 = or(T_187387, T_187386)
      when T_187388 : 
        wire T_187389 : UInt<64>
        T_187389 := s4_req.data
        when T_187374 : T_187389 := s3_req.data
        wire T_187390 : UInt<64>
        T_187390 := T_187389
        when T_187362 : T_187390 := amoalu.out
        s2_store_bypass_data := T_187390
        s2_store_bypass := UInt<1>(1)
    node s2_data_word_prebypass = dshr(s2_data_uncorrected, UInt<7>(0))
    wire s2_data_word : UInt<128>
    s2_data_word := s2_data_word_prebypass
    when s2_store_bypass : s2_data_word := s2_store_bypass_data
    node T_187391 = eq(s2_req.typ, UInt<3>(0))
    node T_187392 = eq(s2_req.typ, UInt<3>(4))
    node T_187393 = or(T_187391, T_187392)
    node T_187394 = eq(s2_req.typ, UInt<3>(1))
    node T_187395 = eq(s2_req.typ, UInt<3>(5))
    node T_187396 = or(T_187394, T_187395)
    node T_187397 = eq(s2_req.typ, UInt<3>(2))
    node T_187398 = eq(s2_req.typ, UInt<3>(6))
    node T_187399 = or(T_187397, T_187398)
    node T_187400 = eq(s2_req.typ, UInt<3>(0))
    node T_187401 = eq(s2_req.typ, UInt<3>(1))
    node T_187402 = or(T_187400, T_187401)
    node T_187403 = eq(s2_req.typ, UInt<3>(2))
    node T_187404 = or(T_187402, T_187403)
    node T_187405 = eq(s2_req.typ, UInt<3>(3))
    node T_187406 = or(T_187404, T_187405)
    node T_187407 = bit(s2_req.addr, 2)
    node T_187408 = bits(s2_data_word, 63, 32)
    node T_187409 = bits(s2_data_word, 31, 0)
    wire T_187410 : UInt<32>
    T_187410 := T_187409
    when T_187407 : T_187410 := T_187408
    node T_187411 = bit(T_187410, 31)
    node T_187412 = and(T_187406, T_187411)
    node T_187413 = subw(UInt<32>(0), UInt<6>(32))
    node T_187414 = bits(s2_data_word, 63, 32)
    wire T_187415 : UInt<32>
    T_187415 := T_187414
    when T_187399 : T_187415 := T_187413
    node T_187416 = cat(T_187415, T_187410)
    node T_187417 = bit(s2_req.addr, 1)
    node T_187418 = bits(T_187416, 31, 16)
    node T_187419 = bits(T_187416, 15, 0)
    wire T_187420 : UInt<16>
    T_187420 := T_187419
    when T_187417 : T_187420 := T_187418
    node T_187421 = bit(T_187420, 15)
    node T_187422 = and(T_187406, T_187421)
    node T_187423 = subw(UInt<48>(0), UInt<6>(48))
    node T_187424 = bits(T_187416, 63, 16)
    wire T_187425 : UInt<48>
    T_187425 := T_187424
    when T_187396 : T_187425 := T_187423
    node T_187426 = cat(T_187425, T_187420)
    node T_187427 = bit(s2_req.addr, 0)
    node T_187428 = bits(T_187426, 15, 8)
    node T_187429 = bits(T_187426, 7, 0)
    wire T_187430 : UInt<8>
    T_187430 := T_187429
    when T_187427 : T_187430 := T_187428
    wire T_187431 : UInt<8>
    T_187431 := T_187430
    when s2_sc : T_187431 := UInt<1>(0)
    node T_187432 = or(s2_sc, T_187393)
    node T_187433 = bit(T_187431, 7)
    node T_187434 = and(T_187406, T_187433)
    node T_187435 = subw(UInt<56>(0), UInt<6>(56))
    node T_187436 = bits(T_187426, 63, 8)
    wire T_187437 : UInt<56>
    T_187437 := T_187436
    when T_187432 : T_187437 := T_187435
    node T_187438 = cat(T_187437, T_187431)
    amoalu := s2_req
    amoalu.lhs := s2_data_word
    amoalu.rhs := s2_req.data
    node T_187439 = and(dtlb.req.valid, dtlb.resp.miss)
    node T_187440 = bits(s1_req.addr, 11, 6)
    node T_187441 = eq(T_187440, prober.meta_write.bits.idx)
    node T_187442 = eq(prober.req.ready, UInt<1>(0))
    node T_187443 = and(T_187441, T_187442)
    node s1_nack = or(T_187439, T_187443)
    node T_187444 = or(s1_valid, s1_replay)
    reg s2_nack_hit : UInt<1>
    when T_187444 : s2_nack_hit := s1_nack
    when s2_nack_hit : mshrs.req.valid := UInt<1>(0)
    node s2_nack_victim = and(s2_hit, mshrs.secondary_miss)
    node T_187445 = eq(s2_hit, UInt<1>(0))
    node T_187446 = eq(mshrs.req.ready, UInt<1>(0))
    node s2_nack_miss = and(T_187445, T_187446)
    node T_187447 = or(s2_nack_hit, s2_nack_victim)
    node s2_nack = or(T_187447, s2_nack_miss)
    node T_187448 = eq(s2_nack, UInt<1>(0))
    node T_187449 = and(s2_valid, T_187448)
    s2_valid_masked := T_187449
    node T_187450 = or(s2_valid, s2_replay)
    node T_187451 = and(T_187450, s2_hit)
    node s2_recycle_ecc = and(T_187451, s2_data_correctable)
    reg s2_recycle_next : UInt<1>
    onreset s2_recycle_next := UInt<1>(0)
    
    node T_187452 = or(s1_valid, s1_replay)
    when T_187452 : s2_recycle_next := s2_recycle_ecc
    node T_187453 = or(s2_recycle_ecc, s2_recycle_next)
    s2_recycle := T_187453
    reg block_miss : UInt<1>
    onreset block_miss := UInt<1>(0)
    node T_187454 = or(s2_valid, block_miss)
    node T_187455 = and(T_187454, s2_nack_miss)
    block_miss := T_187455
    when block_miss : cpu.req.ready := UInt<1>(0)
    node T_187456 = and(s2_valid_masked, s2_hit)
    node T_187457 = or(s2_replay, T_187456)
    node T_187458 = eq(s2_data_correctable, UInt<1>(0))
    node T_187459 = and(T_187457, T_187458)
    cpu.resp.valid := T_187459
    node T_187460 = and(s2_valid, s2_nack)
    cpu.resp.bits.nack := T_187460
    cpu.resp.bits := s2_req
    node T_187461 = eq(s2_req.cmd, UInt<5>(0))
    node T_187462 = eq(s2_req.cmd, UInt<5>(6))
    node T_187463 = or(T_187461, T_187462)
    node T_187464 = bit(s2_req.cmd, 3)
    node T_187465 = eq(s2_req.cmd, UInt<5>(4))
    node T_187466 = or(T_187464, T_187465)
    node T_187467 = or(T_187463, T_187466)
    node T_187468 = or(T_187467, s2_sc)
    cpu.resp.bits.has_data := T_187468
    cpu.resp.bits.replay := s2_replay
    cpu.resp.bits.data := T_187416
    node T_187469 = or(T_187438, s2_sc_fail)
    cpu.resp.bits.data_subword := T_187469
    cpu.resp.bits.store_data := s2_req.data
    node T_187470 = eq(s1_valid, UInt<1>(0))
    node T_187471 = and(mshrs.fence_rdy, T_187470)
    node T_187472 = eq(s2_valid, UInt<1>(0))
    node T_187473 = and(T_187471, T_187472)
    cpu.ordered := T_187473
    node T_187474 = or(s1_read, s1_sc)
    node T_187475 = and(s1_replay, T_187474)
    cpu.replay_next.valid := T_187475
    cpu.replay_next.bits := s1_req.tag
  module RRArbiter_150123 : 
    input in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2]
    output out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}
    output chosen : UInt<1>
    
    wire T_187476 : UInt<1>
    reg T_187477 : UInt<1>
    onreset T_187477 := UInt<1>(0)
    node T_187478 = gt(UInt<1>(0), T_187477)
    node T_187479 = and(in[0].valid, T_187478)
    node T_187480 = gt(UInt<1>(1), T_187477)
    node T_187481 = and(in[1].valid, T_187480)
    node T_187482 = or(UInt<1>(0), T_187479)
    node T_187483 = eq(T_187482, UInt<1>(0))
    node T_187484 = or(UInt<1>(0), T_187479)
    node T_187485 = or(T_187484, T_187481)
    node T_187486 = eq(T_187485, UInt<1>(0))
    node T_187487 = or(UInt<1>(0), T_187479)
    node T_187488 = or(T_187487, T_187481)
    node T_187489 = or(T_187488, in[0].valid)
    node T_187490 = eq(T_187489, UInt<1>(0))
    node T_187491 = gt(UInt<1>(0), T_187477)
    node T_187492 = and(UInt<1>(1), T_187491)
    node T_187493 = or(T_187492, T_187486)
    node T_187494 = gt(UInt<1>(1), T_187477)
    node T_187495 = and(T_187483, T_187494)
    node T_187496 = or(T_187495, T_187490)
    node T_187497 = eq(UInt<1>(1), UInt<1>(0))
    wire T_187498 : UInt<1>
    T_187498 := T_187493
    when UInt<1>(0) : T_187498 := T_187497
    node T_187499 = and(T_187498, out.ready)
    in[0].ready := T_187499
    node T_187500 = eq(UInt<1>(1), UInt<1>(1))
    wire T_187501 : UInt<1>
    T_187501 := T_187496
    when UInt<1>(0) : T_187501 := T_187500
    node T_187502 = and(T_187501, out.ready)
    in[1].ready := T_187502
    accessor T_187503 = in[T_187476]
    out.valid := T_187503.valid
    accessor T_187504 = in[T_187476]
    out.bits := T_187504.bits
    chosen := T_187476
    wire T_187505 : UInt<1>
    T_187505 := UInt<1>(1)
    when in[0].valid : T_187505 := UInt<1>(0)
    node T_187506 = gt(UInt<1>(1), T_187477)
    node T_187507 = and(in[1].valid, T_187506)
    wire T_187508 : UInt<1>
    T_187508 := T_187505
    when T_187507 : T_187508 := UInt<1>(1)
    wire T_187509 : UInt<1>
    T_187509 := T_187508
    when UInt<1>(0) : T_187509 := UInt<1>(1)
    T_187476 := T_187509
    
    node T_187510 = and(out.ready, out.valid)
    when T_187510 : T_187477 := T_187476
  module PTW : 
    input requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2]
    output mem__ : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}
    output dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}
    
    wire requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2]
    requestor[0] := T_187511
    requestor[1] := T_187512
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    reg count : UInt<2>
    reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}
    reg r_req_dest : UInt
    reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    node T_187513 = shr(r_req.addr, 18)
    node T_187514 = bits(T_187513, 8, 0)
    node T_187515 = shr(r_req.addr, 9)
    node T_187516 = bits(T_187515, 8, 0)
    node T_187517 = shr(r_req.addr, 0)
    node T_187518 = bits(T_187517, 8, 0)
    wire T_187519 : UInt<9>[3]
    T_187519[0] := T_187514
    T_187519[1] := T_187516
    T_187519[2] := T_187518
    accessor vpn_idx = T_187519[count]
    inst arb of RRArbiter_150123
    arb.in[0] <> requestor[0].req
    arb.in[1] <> requestor[1].req
    node T_187520 = eq(state, UInt<3>(0))
    arb.out.ready := T_187520
    wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    node T_187521 = bits(mem__.resp.bits.data, 0, 0)
    pte.v := T_187521
    node T_187522 = bits(mem__.resp.bits.data, 4, 1)
    pte.typ := T_187522
    node T_187523 = bits(mem__.resp.bits.data, 5, 5)
    pte.r := T_187523
    node T_187524 = bits(mem__.resp.bits.data, 6, 6)
    pte.d := T_187524
    node T_187525 = bits(mem__.resp.bits.data, 9, 7)
    pte.reserved_for_software := T_187525
    node T_187526 = bits(mem__.resp.bits.data, 29, 10)
    pte.ppn := T_187526
    node T_187527 = cat(r_pte.ppn, vpn_idx)
    node pte_addr = shl(T_187527, 3)
    
    node T_187528 = and(arb.out.ready, arb.out.valid)
    when T_187528 : 
      r_req := arb.out.bits
      r_req_dest := arb.chosen
      node T_187529 = bits(dpath.ptbr, 31, 12)
      r_pte.ppn := T_187529
    reg T_187530 : UInt<3>
    reg T_187531 : UInt<1>[3]
    onreset T_187531 := T_187532
    node T_187533 = cat(T_187531[1], T_187531[0])
    node T_187534 = cat(T_187531[2], T_187533)
    cmem T_187535 : UInt<32>[3]
    cmem T_187536 : UInt<20>[3]
    accessor T_187537 = T_187535[UInt<1>(0)]
    node T_187538 = eq(T_187537, pte_addr)
    accessor T_187539 = T_187535[UInt<1>(1)]
    node T_187540 = eq(T_187539, pte_addr)
    accessor T_187541 = T_187535[UInt<2>(2)]
    node T_187542 = eq(T_187541, pte_addr)
    wire T_187543 : UInt<1>[3]
    T_187543[0] := T_187538
    T_187543[1] := T_187540
    T_187543[2] := T_187542
    node T_187544 = cat(T_187543[1], T_187543[0])
    node T_187545 = cat(T_187543[2], T_187544)
    node T_187546 = and(T_187545, T_187534)
    node T_187547 = eq(T_187546, UInt<1>(0))
    node pte_cache_hit = eq(T_187547, UInt<1>(0))
    
    
    node T_187548 = lt(pte.typ, UInt<2>(2))
    node T_187549 = and(pte.v, T_187548)
    node T_187550 = and(mem__.resp.valid, T_187549)
    node T_187551 = eq(pte_cache_hit, UInt<1>(0))
    node T_187552 = and(T_187550, T_187551)
    when T_187552 : 
      node T_187553 = eq(T_187534, UInt<1>(-1))
      node T_187554 = dshr(T_187530, UInt<1>(1))
      node T_187555 = bit(T_187554, 0)
      node T_187556 = cat(UInt<1>(1), T_187555)
      node T_187557 = dshr(T_187530, T_187556)
      node T_187558 = bit(T_187557, 0)
      node T_187559 = cat(T_187556, T_187558)
      node T_187560 = bits(T_187559, 1, 0)
      node T_187561 = not(T_187534)
      node T_187562 = bit(T_187561, 0)
      node T_187563 = bit(T_187561, 1)
      node T_187564 = bit(T_187561, 2)
      wire T_187565 : UInt<1>[3]
      T_187565[0] := T_187562
      T_187565[1] := T_187563
      T_187565[2] := T_187564
      wire T_187566 : UInt<2>
      T_187566 := UInt<2>(2)
      when T_187565[1] : T_187566 := UInt<1>(1)
      wire T_187567 : UInt<2>
      T_187567 := T_187566
      when T_187565[0] : T_187567 := UInt<1>(0)
      wire T_187568 : UInt<2>
      T_187568 := T_187567
      when T_187553 : T_187568 := T_187560
      accessor T_187569 = T_187531[T_187568]
      T_187569 := UInt<1>(1)
      accessor T_187570 = T_187535[T_187568]
      T_187570 := pte_addr
      accessor T_187571 = T_187536[T_187568]
      T_187571 := pte.ppn
    
    
    node T_187572 = eq(state, UInt<3>(1))
    node T_187573 = and(pte_cache_hit, T_187572)
    when T_187573 : 
      node T_187574 = bits(T_187546, 2, 2)
      node T_187575 = bits(T_187546, 1, 0)
      node T_187576 = eq(T_187574, UInt<1>(0))
      node T_187577 = eq(T_187576, UInt<1>(0))
      node T_187578 = or(T_187574, T_187575)
      node T_187579 = bit(T_187578, 1)
      node T_187580 = cat(T_187577, T_187579)
      node T_187581 = bit(T_187580, 1)
      node T_187582 = dshl(UInt<3>(1), UInt<1>(1))
      node T_187583 = bits(T_187582, 2, 0)
      node T_187584 = not(T_187583)
      node T_187585 = and(T_187530, T_187584)
      wire T_187586 : UInt<3>
      T_187586 := T_187583
      when T_187581 : T_187586 := UInt<1>(0)
      node T_187587 = or(T_187585, T_187586)
      node T_187588 = cat(UInt<1>(1), T_187581)
      node T_187589 = bit(T_187580, 0)
      node T_187590 = dshl(UInt<3>(1), T_187588)
      node T_187591 = bits(T_187590, 2, 0)
      node T_187592 = not(T_187591)
      node T_187593 = and(T_187587, T_187592)
      wire T_187594 : UInt<3>
      T_187594 := T_187591
      when T_187589 : T_187594 := UInt<1>(0)
      node T_187595 = or(T_187593, T_187594)
      node T_187596 = cat(T_187588, T_187589)
      T_187530 := T_187595
    
    node T_187597 = or(reset, dpath.invalidate)
    when T_187597 : 
      T_187531[0] := UInt<1>(0)
      T_187531[1] := UInt<1>(0)
      T_187531[2] := UInt<1>(0)
    node T_187598 = bit(T_187546, 0)
    node T_187599 = bit(T_187546, 1)
    node T_187600 = bit(T_187546, 2)
    accessor T_187601 = T_187536[UInt<1>(0)]
    accessor T_187602 = T_187536[UInt<1>(1)]
    accessor T_187603 = T_187536[UInt<2>(2)]
    wire T_187604 : UInt<1>
    T_187604 := UInt<1>(0)
    when T_187598 : T_187604 := T_187601
    wire T_187605 : UInt<1>
    T_187605 := UInt<1>(0)
    when T_187599 : T_187605 := T_187602
    wire T_187606 : UInt<1>
    T_187606 := UInt<1>(0)
    when T_187600 : T_187606 := T_187603
    node T_187607 = or(T_187604, T_187605)
    node T_187608 = or(T_187607, T_187606)
    wire pte_cache_data : UInt<20>
    node T_187609 = bits(T_187608, 19, 0)
    pte_cache_data := T_187609
    node T_187610 = bit(r_req.prv, 0)
    node T_187611 = geq(pte.typ, UInt<3>(4))
    node T_187612 = and(pte.v, T_187611)
    node T_187613 = bit(pte.typ, 1)
    node T_187614 = and(T_187612, T_187613)
    node T_187615 = geq(pte.typ, UInt<2>(2))
    node T_187616 = and(pte.v, T_187615)
    node T_187617 = bit(pte.typ, 0)
    node T_187618 = and(T_187616, T_187617)
    node T_187619 = geq(pte.typ, UInt<2>(2))
    node T_187620 = and(pte.v, T_187619)
    wire T_187621 : UInt<1>
    T_187621 := T_187620
    when r_req.store : T_187621 := T_187618
    wire T_187622 : UInt<1>
    T_187622 := T_187621
    when r_req.fetch : T_187622 := T_187614
    node T_187623 = geq(pte.typ, UInt<2>(2))
    node T_187624 = and(pte.v, T_187623)
    node T_187625 = lt(pte.typ, UInt<4>(8))
    node T_187626 = and(T_187624, T_187625)
    node T_187627 = bit(pte.typ, 1)
    node T_187628 = and(T_187626, T_187627)
    node T_187629 = geq(pte.typ, UInt<2>(2))
    node T_187630 = and(pte.v, T_187629)
    node T_187631 = lt(pte.typ, UInt<4>(8))
    node T_187632 = and(T_187630, T_187631)
    node T_187633 = bit(pte.typ, 0)
    node T_187634 = and(T_187632, T_187633)
    node T_187635 = geq(pte.typ, UInt<2>(2))
    node T_187636 = and(pte.v, T_187635)
    node T_187637 = lt(pte.typ, UInt<4>(8))
    node T_187638 = and(T_187636, T_187637)
    wire T_187639 : UInt<1>
    T_187639 := T_187638
    when r_req.store : T_187639 := T_187634
    wire T_187640 : UInt<1>
    T_187640 := T_187639
    when r_req.fetch : T_187640 := T_187628
    wire perm_ok : UInt<1>
    perm_ok := T_187640
    when T_187610 : perm_ok := T_187622
    node T_187641 = eq(pte.r, UInt<1>(0))
    node T_187642 = eq(pte.d, UInt<1>(0))
    node T_187643 = and(r_req.store, T_187642)
    node T_187644 = or(T_187641, T_187643)
    node set_dirty_bit = and(perm_ok, T_187644)
    
    
    node T_187645 = eq(state, UInt<3>(2))
    node T_187646 = and(mem__.resp.valid, T_187645)
    node T_187647 = eq(set_dirty_bit, UInt<1>(0))
    node T_187648 = and(T_187646, T_187647)
    when T_187648 : r_pte := pte
    wire T_187649 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    T_187649.v := UInt<1>(0)
    T_187649.typ := UInt<4>(0)
    T_187649.r := UInt<1>(0)
    T_187649.d := UInt<1>(0)
    T_187649.reserved_for_software := UInt<3>(0)
    T_187649.ppn := UInt<20>(0)
    wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}
    pte_wdata := T_187649
    pte_wdata.r := UInt<1>(1)
    pte_wdata.d := r_req.store
    node T_187650 = eq(state, UInt<3>(1))
    node T_187651 = eq(state, UInt<3>(3))
    node T_187652 = or(T_187650, T_187651)
    mem__.req.valid := T_187652
    mem__.req.bits.phys := UInt<1>(1)
    node T_187653 = eq(state, UInt<3>(3))
    wire T_187654 : UInt<5>
    T_187654 := UInt<5>(0)
    when T_187653 : T_187654 := UInt<5>(10)
    mem__.req.bits.cmd := T_187654
    mem__.req.bits.typ := UInt<3>(3)
    mem__.req.bits.addr := pte_addr
    mem__.req.bits.kill := UInt<1>(0)
    node T_187655 = cat(pte_wdata.reserved_for_software, pte_wdata.d)
    node T_187656 = cat(pte_wdata.ppn, T_187655)
    node T_187657 = cat(pte_wdata.typ, pte_wdata.v)
    node T_187658 = cat(pte_wdata.r, T_187657)
    node T_187659 = cat(T_187656, T_187658)
    mem__.req.bits.data := T_187659
    node resp_err = eq(state, UInt<3>(6))
    node T_187660 = eq(state, UInt<3>(5))
    node resp_val = or(T_187660, resp_err)
    node r_resp_ppn = dshr(mem__.req.bits.addr, UInt<4>(12))
    node T_187661 = shr(r_resp_ppn, 18)
    node T_187662 = bits(r_req.addr, 17, 0)
    node T_187663 = cat(T_187661, T_187662)
    node T_187664 = shr(r_resp_ppn, 9)
    node T_187665 = bits(r_req.addr, 8, 0)
    node T_187666 = cat(T_187664, T_187665)
    wire T_187667 : UInt<40>[3]
    T_187667[0] := T_187663
    T_187667[1] := T_187666
    T_187667[2] := r_resp_ppn
    accessor resp_ppn = T_187667[count]
    node T_187668 = eq(r_req_dest, UInt<1>(0))
    node T_187669 = and(resp_val, T_187668)
    requestor[0].resp.valid := T_187669
    requestor[0].resp.bits.error := resp_err
    requestor[0].resp.bits.pte := r_pte
    requestor[0].resp.bits.pte.ppn := resp_ppn
    requestor[0].invalidate := dpath.invalidate
    requestor[0].status := dpath.status
    node T_187670 = eq(r_req_dest, UInt<1>(1))
    node T_187671 = and(resp_val, T_187670)
    requestor[1].resp.valid := T_187671
    requestor[1].resp.bits.error := resp_err
    requestor[1].resp.bits.pte := r_pte
    requestor[1].resp.bits.pte.ppn := resp_ppn
    requestor[1].invalidate := dpath.invalidate
    requestor[1].status := dpath.status
    
    node T_187672 = eq(UInt<3>(0), state)
    when T_187672 : 
      when arb.out.valid : state := UInt<3>(1)
      count := UInt<1>(0)
    
    node T_187673 = eq(UInt<3>(1), state)
    when T_187673 : 
      
      node T_187674 = lt(count, UInt<2>(2))
      node T_187675 = and(pte_cache_hit, T_187674)
      when T_187675 : 
        mem__.req.valid := UInt<1>(0)
        state := UInt<3>(1)
        node T_187676 = addw(count, UInt<1>(1))
        count := T_187676
        r_pte.ppn := pte_cache_data
      else : 
        when mem__.req.ready : state := UInt<3>(2)
    
    node T_187677 = eq(UInt<3>(2), state)
    when T_187677 : 
      when mem__.resp.bits.nack : state := UInt<3>(1)
      when mem__.resp.valid : 
        state := UInt<3>(6)
        
        
        node T_187678 = lt(pte.typ, UInt<2>(2))
        node T_187679 = and(pte.v, T_187678)
        node T_187680 = lt(count, UInt<2>(2))
        node T_187681 = and(T_187679, T_187680)
        when T_187681 : 
          state := UInt<3>(1)
          node T_187682 = addw(count, UInt<1>(1))
          count := T_187682
        
        
        node T_187683 = geq(pte.typ, UInt<2>(2))
        node T_187684 = and(pte.v, T_187683)
        when T_187684 : 
          wire T_187685 : UInt<3>
          T_187685 := UInt<3>(5)
          when set_dirty_bit : T_187685 := UInt<3>(3)
          state := T_187685
    
    node T_187686 = eq(UInt<3>(3), state)
    when T_187686 : when mem__.req.ready : state := UInt<3>(4)
    
    node T_187687 = eq(UInt<3>(4), state)
    when T_187687 : 
      when mem__.resp.bits.nack : state := UInt<3>(3)
      when mem__.resp.valid : state := UInt<3>(1)
    
    node T_187688 = eq(UInt<3>(5), state)
    when T_187688 : state := UInt<3>(0)
    
    node T_187689 = eq(UInt<3>(6), state)
    when T_187689 : state := UInt<3>(0)
  module CSRFile : 
    output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}
    output rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}
    output csr_replay : UInt<1>
    output csr_stall : UInt<1>
    output csr_xcpt : UInt<1>
    output eret : UInt<1>
    output status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}
    output ptbr : UInt<32>
    output evec : UInt<40>
    input exception : UInt<1>
    input retire : UInt<1>
    input uarch_counters : UInt<1>[16]
    output custom_mrw_csrs : UInt[0]
    input cause : UInt<64>
    input pc : UInt<40>
    output fatc : UInt<1>
    output time : UInt<64>
    output fcsr_rm : UInt<3>
    input fcsr_flags : {valid : UInt<1>, bits : UInt<5>}
    input rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst__ : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem__ : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>}
    output interrupt : UInt<1>
    output interrupt_cause : UInt<64>
    
    wire uarch_counters : UInt<1>[16]
    uarch_counters[0] := T_187690
    uarch_counters[1] := T_187691
    uarch_counters[2] := T_187692
    uarch_counters[3] := T_187693
    uarch_counters[4] := T_187694
    uarch_counters[5] := T_187695
    uarch_counters[6] := T_187696
    uarch_counters[7] := T_187697
    uarch_counters[8] := T_187698
    uarch_counters[9] := T_187699
    uarch_counters[10] := T_187700
    uarch_counters[11] := T_187701
    uarch_counters[12] := T_187702
    uarch_counters[13] := T_187703
    uarch_counters[14] := T_187704
    uarch_counters[15] := T_187705
    wire custom_mrw_csrs : UInt[0]
    wire T_187706 : UInt<3>[3]
    T_187706[0] := UInt<3>(0)
    T_187706[1] := UInt<3>(1)
    T_187706[2] := UInt<3>(2)
    wire T_187707 : UInt<2>[2]
    T_187707[0] := UInt<2>(0)
    T_187707[1] := UInt<2>(1)
    wire T_187708 : UInt<2>[3]
    T_187708[0] := UInt<2>(1)
    T_187708[1] := UInt<2>(2)
    T_187708[2] := UInt<2>(3)
    wire T_187709 : UInt<2>[2]
    T_187709[0] := UInt<2>(2)
    T_187709[1] := UInt<2>(3)
    wire T_187710 : UInt<2>[1]
    T_187710[0] := UInt<2>(3)
    wire T_187711 : UInt<3>[3]
    T_187711[0] := UInt<3>(0)
    T_187711[1] := UInt<3>(1)
    T_187711[2] := UInt<3>(2)
    wire T_187712 : UInt<2>[2]
    T_187712[0] := UInt<2>(0)
    T_187712[1] := UInt<2>(1)
    wire T_187713 : UInt<2>[3]
    T_187713[0] := UInt<2>(1)
    T_187713[1] := UInt<2>(2)
    T_187713[2] := UInt<2>(3)
    wire T_187714 : UInt<2>[2]
    T_187714[0] := UInt<2>(2)
    T_187714[1] := UInt<2>(3)
    wire T_187715 : UInt<2>[1]
    T_187715[0] := UInt<2>(3)
    wire T_187716 : UInt<3>[3]
    T_187716[0] := UInt<3>(0)
    T_187716[1] := UInt<3>(1)
    T_187716[2] := UInt<3>(2)
    wire T_187717 : UInt<2>[2]
    T_187717[0] := UInt<2>(0)
    T_187717[1] := UInt<2>(1)
    wire T_187718 : UInt<2>[3]
    T_187718[0] := UInt<2>(1)
    T_187718[1] := UInt<2>(2)
    T_187718[2] := UInt<2>(3)
    wire T_187719 : UInt<2>[2]
    T_187719[0] := UInt<2>(2)
    T_187719[1] := UInt<2>(3)
    wire T_187720 : UInt<2>[1]
    T_187720[0] := UInt<2>(3)
    wire T_187721 : UInt<3>[3]
    T_187721[0] := UInt<3>(0)
    T_187721[1] := UInt<3>(1)
    T_187721[2] := UInt<3>(2)
    wire T_187722 : UInt<2>[2]
    T_187722[0] := UInt<2>(0)
    T_187722[1] := UInt<2>(1)
    wire T_187723 : UInt<2>[3]
    T_187723[0] := UInt<2>(1)
    T_187723[1] := UInt<2>(2)
    T_187723[2] := UInt<2>(3)
    wire T_187724 : UInt<2>[2]
    T_187724[0] := UInt<2>(2)
    T_187724[1] := UInt<2>(3)
    wire T_187725 : UInt<2>[1]
    T_187725[0] := UInt<2>(3)
    wire T_187726 : UInt<3>[3]
    T_187726[0] := UInt<3>(0)
    T_187726[1] := UInt<3>(1)
    T_187726[2] := UInt<3>(2)
    wire T_187727 : UInt<2>[2]
    T_187727[0] := UInt<2>(0)
    T_187727[1] := UInt<2>(1)
    wire T_187728 : UInt<2>[3]
    T_187728[0] := UInt<2>(1)
    T_187728[1] := UInt<2>(2)
    T_187728[2] := UInt<2>(3)
    wire T_187729 : UInt<2>[2]
    T_187729[0] := UInt<2>(2)
    T_187729[1] := UInt<2>(3)
    wire T_187730 : UInt<2>[1]
    T_187730[0] := UInt<2>(3)
    wire T_187731 : UInt<3>[3]
    T_187731[0] := UInt<3>(0)
    T_187731[1] := UInt<3>(1)
    T_187731[2] := UInt<3>(2)
    wire T_187732 : UInt<2>[2]
    T_187732[0] := UInt<2>(0)
    T_187732[1] := UInt<2>(1)
    wire T_187733 : UInt<2>[3]
    T_187733[0] := UInt<2>(1)
    T_187733[1] := UInt<2>(2)
    T_187733[2] := UInt<2>(3)
    wire T_187734 : UInt<2>[2]
    T_187734[0] := UInt<2>(2)
    T_187734[1] := UInt<2>(3)
    wire T_187735 : UInt<2>[1]
    T_187735[0] := UInt<2>(3)
    wire T_187736 : UInt<3>[3]
    T_187736[0] := UInt<3>(0)
    T_187736[1] := UInt<3>(1)
    T_187736[2] := UInt<3>(2)
    wire T_187737 : UInt<2>[2]
    T_187737[0] := UInt<2>(0)
    T_187737[1] := UInt<2>(1)
    wire T_187738 : UInt<2>[3]
    T_187738[0] := UInt<2>(1)
    T_187738[1] := UInt<2>(2)
    T_187738[2] := UInt<2>(3)
    wire T_187739 : UInt<2>[2]
    T_187739[0] := UInt<2>(2)
    T_187739[1] := UInt<2>(3)
    wire T_187740 : UInt<2>[1]
    T_187740[0] := UInt<2>(3)
    wire T_187741 : UInt<3>[3]
    T_187741[0] := UInt<3>(0)
    T_187741[1] := UInt<3>(1)
    T_187741[2] := UInt<3>(2)
    wire T_187742 : UInt<2>[2]
    T_187742[0] := UInt<2>(0)
    T_187742[1] := UInt<2>(1)
    wire T_187743 : UInt<2>[3]
    T_187743[0] := UInt<2>(1)
    T_187743[1] := UInt<2>(2)
    T_187743[2] := UInt<2>(3)
    wire T_187744 : UInt<2>[2]
    T_187744[0] := UInt<2>(2)
    T_187744[1] := UInt<2>(3)
    wire T_187745 : UInt<2>[1]
    T_187745[0] := UInt<2>(3)
    wire T_187746 : UInt<3>[3]
    T_187746[0] := UInt<3>(0)
    T_187746[1] := UInt<3>(1)
    T_187746[2] := UInt<3>(2)
    wire T_187747 : UInt<2>[2]
    T_187747[0] := UInt<2>(0)
    T_187747[1] := UInt<2>(1)
    wire T_187748 : UInt<2>[3]
    T_187748[0] := UInt<2>(1)
    T_187748[1] := UInt<2>(2)
    T_187748[2] := UInt<2>(3)
    wire T_187749 : UInt<2>[2]
    T_187749[0] := UInt<2>(2)
    T_187749[1] := UInt<2>(3)
    wire T_187750 : UInt<2>[1]
    T_187750[0] := UInt<2>(3)
    wire T_187751 : UInt<3>[3]
    T_187751[0] := UInt<3>(0)
    T_187751[1] := UInt<3>(1)
    T_187751[2] := UInt<3>(2)
    wire T_187752 : UInt<2>[2]
    T_187752[0] := UInt<2>(0)
    T_187752[1] := UInt<2>(1)
    wire T_187753 : UInt<2>[3]
    T_187753[0] := UInt<2>(1)
    T_187753[1] := UInt<2>(2)
    T_187753[2] := UInt<2>(3)
    wire T_187754 : UInt<2>[2]
    T_187754[0] := UInt<2>(2)
    T_187754[1] := UInt<2>(3)
    wire T_187755 : UInt<2>[1]
    T_187755[0] := UInt<2>(3)
    reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}
    wire T_187756 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_187756.usip := UInt<1>(0)
    T_187756.ssip := UInt<1>(0)
    T_187756.hsip := UInt<1>(0)
    T_187756.msip := UInt<1>(0)
    T_187756.utip := UInt<1>(0)
    T_187756.stip := UInt<1>(0)
    T_187756.htip := UInt<1>(0)
    T_187756.mtip := UInt<1>(0)
    reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    onreset reg_mie := T_187756
    wire T_187757 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_187757.usip := UInt<1>(0)
    T_187757.ssip := UInt<1>(0)
    T_187757.hsip := UInt<1>(0)
    T_187757.msip := UInt<1>(0)
    T_187757.utip := UInt<1>(0)
    T_187757.stip := UInt<1>(0)
    T_187757.htip := UInt<1>(0)
    T_187757.mtip := UInt<1>(0)
    reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    onreset reg_mip := T_187757
    reg reg_mepc : UInt<40>
    reg reg_mcause : UInt<64>
    reg reg_mbadaddr : UInt<40>
    reg reg_mscratch : UInt<64>
    reg reg_sepc : UInt<40>
    reg reg_scause : UInt<64>
    reg reg_sbadaddr : UInt<40>
    reg reg_sscratch : UInt<64>
    reg reg_stvec : UInt<39>
    reg reg_mtimecmp : UInt<64>
    reg reg_sptbr : UInt<32>
    reg reg_wfi : UInt<1>
    onreset reg_wfi := UInt<1>(0)
    reg reg_tohost : UInt<64>
    onreset reg_tohost := UInt<64>(0)
    reg reg_fromhost : UInt<64>
    onreset reg_fromhost := UInt<64>(0)
    reg reg_stats : UInt<1>
    onreset reg_stats := UInt<1>(0)
    reg reg_time : UInt<64>
    reg T_187758 : UInt<6>
    onreset T_187758 := UInt<6>(0)
    node T_187759 = eq(UInt<1>(1), UInt<1>(0))
    node T_187760 = eq(T_187759, UInt<1>(0))
    node T_187761 = addw(T_187758, UInt<7>(1))
    when T_187760 : 
      node T_187762 = bits(T_187761, 5, 0)
      T_187758 := T_187762
    reg T_187763 : UInt<58>
    onreset T_187763 := UInt<58>(0)
    
    
    node T_187764 = bit(T_187761, 6)
    node T_187765 = and(T_187760, T_187764)
    when T_187765 : 
      node T_187766 = addw(T_187763, UInt<1>(1))
      T_187763 := T_187766
    node T_187767 = cat(T_187763, T_187758)
    reg T_187768 : UInt<6>
    onreset T_187768 := UInt<6>(0)
    node T_187769 = eq(retire, UInt<1>(0))
    node T_187770 = eq(T_187769, UInt<1>(0))
    node T_187771 = addw(T_187768, UInt<7>(1))
    when T_187770 : 
      node T_187772 = bits(T_187771, 5, 0)
      T_187768 := T_187772
    reg T_187773 : UInt<58>
    onreset T_187773 := UInt<58>(0)
    
    
    node T_187774 = bit(T_187771, 6)
    node T_187775 = and(T_187770, T_187774)
    when T_187775 : 
      node T_187776 = addw(T_187773, UInt<1>(1))
      T_187773 := T_187776
    node T_187777 = cat(T_187773, T_187768)
    reg T_187778 : UInt<6>
    onreset T_187778 := UInt<6>(0)
    node T_187779 = eq(uarch_counters[0], UInt<1>(0))
    node T_187780 = eq(T_187779, UInt<1>(0))
    node T_187781 = addw(T_187778, UInt<7>(1))
    when T_187780 : 
      node T_187782 = bits(T_187781, 5, 0)
      T_187778 := T_187782
    reg T_187783 : UInt<58>
    onreset T_187783 := UInt<58>(0)
    
    
    node T_187784 = bit(T_187781, 6)
    node T_187785 = and(T_187780, T_187784)
    when T_187785 : 
      node T_187786 = addw(T_187783, UInt<1>(1))
      T_187783 := T_187786
    node T_187787 = cat(T_187783, T_187778)
    reg T_187788 : UInt<6>
    onreset T_187788 := UInt<6>(0)
    node T_187789 = eq(uarch_counters[1], UInt<1>(0))
    node T_187790 = eq(T_187789, UInt<1>(0))
    node T_187791 = addw(T_187788, UInt<7>(1))
    when T_187790 : 
      node T_187792 = bits(T_187791, 5, 0)
      T_187788 := T_187792
    reg T_187793 : UInt<58>
    onreset T_187793 := UInt<58>(0)
    
    
    node T_187794 = bit(T_187791, 6)
    node T_187795 = and(T_187790, T_187794)
    when T_187795 : 
      node T_187796 = addw(T_187793, UInt<1>(1))
      T_187793 := T_187796
    node T_187797 = cat(T_187793, T_187788)
    reg T_187798 : UInt<6>
    onreset T_187798 := UInt<6>(0)
    node T_187799 = eq(uarch_counters[2], UInt<1>(0))
    node T_187800 = eq(T_187799, UInt<1>(0))
    node T_187801 = addw(T_187798, UInt<7>(1))
    when T_187800 : 
      node T_187802 = bits(T_187801, 5, 0)
      T_187798 := T_187802
    reg T_187803 : UInt<58>
    onreset T_187803 := UInt<58>(0)
    
    
    node T_187804 = bit(T_187801, 6)
    node T_187805 = and(T_187800, T_187804)
    when T_187805 : 
      node T_187806 = addw(T_187803, UInt<1>(1))
      T_187803 := T_187806
    node T_187807 = cat(T_187803, T_187798)
    reg T_187808 : UInt<6>
    onreset T_187808 := UInt<6>(0)
    node T_187809 = eq(uarch_counters[3], UInt<1>(0))
    node T_187810 = eq(T_187809, UInt<1>(0))
    node T_187811 = addw(T_187808, UInt<7>(1))
    when T_187810 : 
      node T_187812 = bits(T_187811, 5, 0)
      T_187808 := T_187812
    reg T_187813 : UInt<58>
    onreset T_187813 := UInt<58>(0)
    
    
    node T_187814 = bit(T_187811, 6)
    node T_187815 = and(T_187810, T_187814)
    when T_187815 : 
      node T_187816 = addw(T_187813, UInt<1>(1))
      T_187813 := T_187816
    node T_187817 = cat(T_187813, T_187808)
    reg T_187818 : UInt<6>
    onreset T_187818 := UInt<6>(0)
    node T_187819 = eq(uarch_counters[4], UInt<1>(0))
    node T_187820 = eq(T_187819, UInt<1>(0))
    node T_187821 = addw(T_187818, UInt<7>(1))
    when T_187820 : 
      node T_187822 = bits(T_187821, 5, 0)
      T_187818 := T_187822
    reg T_187823 : UInt<58>
    onreset T_187823 := UInt<58>(0)
    
    
    node T_187824 = bit(T_187821, 6)
    node T_187825 = and(T_187820, T_187824)
    when T_187825 : 
      node T_187826 = addw(T_187823, UInt<1>(1))
      T_187823 := T_187826
    node T_187827 = cat(T_187823, T_187818)
    reg T_187828 : UInt<6>
    onreset T_187828 := UInt<6>(0)
    node T_187829 = eq(uarch_counters[5], UInt<1>(0))
    node T_187830 = eq(T_187829, UInt<1>(0))
    node T_187831 = addw(T_187828, UInt<7>(1))
    when T_187830 : 
      node T_187832 = bits(T_187831, 5, 0)
      T_187828 := T_187832
    reg T_187833 : UInt<58>
    onreset T_187833 := UInt<58>(0)
    
    
    node T_187834 = bit(T_187831, 6)
    node T_187835 = and(T_187830, T_187834)
    when T_187835 : 
      node T_187836 = addw(T_187833, UInt<1>(1))
      T_187833 := T_187836
    node T_187837 = cat(T_187833, T_187828)
    reg T_187838 : UInt<6>
    onreset T_187838 := UInt<6>(0)
    node T_187839 = eq(uarch_counters[6], UInt<1>(0))
    node T_187840 = eq(T_187839, UInt<1>(0))
    node T_187841 = addw(T_187838, UInt<7>(1))
    when T_187840 : 
      node T_187842 = bits(T_187841, 5, 0)
      T_187838 := T_187842
    reg T_187843 : UInt<58>
    onreset T_187843 := UInt<58>(0)
    
    
    node T_187844 = bit(T_187841, 6)
    node T_187845 = and(T_187840, T_187844)
    when T_187845 : 
      node T_187846 = addw(T_187843, UInt<1>(1))
      T_187843 := T_187846
    node T_187847 = cat(T_187843, T_187838)
    reg T_187848 : UInt<6>
    onreset T_187848 := UInt<6>(0)
    node T_187849 = eq(uarch_counters[7], UInt<1>(0))
    node T_187850 = eq(T_187849, UInt<1>(0))
    node T_187851 = addw(T_187848, UInt<7>(1))
    when T_187850 : 
      node T_187852 = bits(T_187851, 5, 0)
      T_187848 := T_187852
    reg T_187853 : UInt<58>
    onreset T_187853 := UInt<58>(0)
    
    
    node T_187854 = bit(T_187851, 6)
    node T_187855 = and(T_187850, T_187854)
    when T_187855 : 
      node T_187856 = addw(T_187853, UInt<1>(1))
      T_187853 := T_187856
    node T_187857 = cat(T_187853, T_187848)
    reg T_187858 : UInt<6>
    onreset T_187858 := UInt<6>(0)
    node T_187859 = eq(uarch_counters[8], UInt<1>(0))
    node T_187860 = eq(T_187859, UInt<1>(0))
    node T_187861 = addw(T_187858, UInt<7>(1))
    when T_187860 : 
      node T_187862 = bits(T_187861, 5, 0)
      T_187858 := T_187862
    reg T_187863 : UInt<58>
    onreset T_187863 := UInt<58>(0)
    
    
    node T_187864 = bit(T_187861, 6)
    node T_187865 = and(T_187860, T_187864)
    when T_187865 : 
      node T_187866 = addw(T_187863, UInt<1>(1))
      T_187863 := T_187866
    node T_187867 = cat(T_187863, T_187858)
    reg T_187868 : UInt<6>
    onreset T_187868 := UInt<6>(0)
    node T_187869 = eq(uarch_counters[9], UInt<1>(0))
    node T_187870 = eq(T_187869, UInt<1>(0))
    node T_187871 = addw(T_187868, UInt<7>(1))
    when T_187870 : 
      node T_187872 = bits(T_187871, 5, 0)
      T_187868 := T_187872
    reg T_187873 : UInt<58>
    onreset T_187873 := UInt<58>(0)
    
    
    node T_187874 = bit(T_187871, 6)
    node T_187875 = and(T_187870, T_187874)
    when T_187875 : 
      node T_187876 = addw(T_187873, UInt<1>(1))
      T_187873 := T_187876
    node T_187877 = cat(T_187873, T_187868)
    reg T_187878 : UInt<6>
    onreset T_187878 := UInt<6>(0)
    node T_187879 = eq(uarch_counters[10], UInt<1>(0))
    node T_187880 = eq(T_187879, UInt<1>(0))
    node T_187881 = addw(T_187878, UInt<7>(1))
    when T_187880 : 
      node T_187882 = bits(T_187881, 5, 0)
      T_187878 := T_187882
    reg T_187883 : UInt<58>
    onreset T_187883 := UInt<58>(0)
    
    
    node T_187884 = bit(T_187881, 6)
    node T_187885 = and(T_187880, T_187884)
    when T_187885 : 
      node T_187886 = addw(T_187883, UInt<1>(1))
      T_187883 := T_187886
    node T_187887 = cat(T_187883, T_187878)
    reg T_187888 : UInt<6>
    onreset T_187888 := UInt<6>(0)
    node T_187889 = eq(uarch_counters[11], UInt<1>(0))
    node T_187890 = eq(T_187889, UInt<1>(0))
    node T_187891 = addw(T_187888, UInt<7>(1))
    when T_187890 : 
      node T_187892 = bits(T_187891, 5, 0)
      T_187888 := T_187892
    reg T_187893 : UInt<58>
    onreset T_187893 := UInt<58>(0)
    
    
    node T_187894 = bit(T_187891, 6)
    node T_187895 = and(T_187890, T_187894)
    when T_187895 : 
      node T_187896 = addw(T_187893, UInt<1>(1))
      T_187893 := T_187896
    node T_187897 = cat(T_187893, T_187888)
    reg T_187898 : UInt<6>
    onreset T_187898 := UInt<6>(0)
    node T_187899 = eq(uarch_counters[12], UInt<1>(0))
    node T_187900 = eq(T_187899, UInt<1>(0))
    node T_187901 = addw(T_187898, UInt<7>(1))
    when T_187900 : 
      node T_187902 = bits(T_187901, 5, 0)
      T_187898 := T_187902
    reg T_187903 : UInt<58>
    onreset T_187903 := UInt<58>(0)
    
    
    node T_187904 = bit(T_187901, 6)
    node T_187905 = and(T_187900, T_187904)
    when T_187905 : 
      node T_187906 = addw(T_187903, UInt<1>(1))
      T_187903 := T_187906
    node T_187907 = cat(T_187903, T_187898)
    reg T_187908 : UInt<6>
    onreset T_187908 := UInt<6>(0)
    node T_187909 = eq(uarch_counters[13], UInt<1>(0))
    node T_187910 = eq(T_187909, UInt<1>(0))
    node T_187911 = addw(T_187908, UInt<7>(1))
    when T_187910 : 
      node T_187912 = bits(T_187911, 5, 0)
      T_187908 := T_187912
    reg T_187913 : UInt<58>
    onreset T_187913 := UInt<58>(0)
    
    
    node T_187914 = bit(T_187911, 6)
    node T_187915 = and(T_187910, T_187914)
    when T_187915 : 
      node T_187916 = addw(T_187913, UInt<1>(1))
      T_187913 := T_187916
    node T_187917 = cat(T_187913, T_187908)
    reg T_187918 : UInt<6>
    onreset T_187918 := UInt<6>(0)
    node T_187919 = eq(uarch_counters[14], UInt<1>(0))
    node T_187920 = eq(T_187919, UInt<1>(0))
    node T_187921 = addw(T_187918, UInt<7>(1))
    when T_187920 : 
      node T_187922 = bits(T_187921, 5, 0)
      T_187918 := T_187922
    reg T_187923 : UInt<58>
    onreset T_187923 := UInt<58>(0)
    
    
    node T_187924 = bit(T_187921, 6)
    node T_187925 = and(T_187920, T_187924)
    when T_187925 : 
      node T_187926 = addw(T_187923, UInt<1>(1))
      T_187923 := T_187926
    node T_187927 = cat(T_187923, T_187918)
    reg T_187928 : UInt<6>
    onreset T_187928 := UInt<6>(0)
    node T_187929 = eq(uarch_counters[15], UInt<1>(0))
    node T_187930 = eq(T_187929, UInt<1>(0))
    node T_187931 = addw(T_187928, UInt<7>(1))
    when T_187930 : 
      node T_187932 = bits(T_187931, 5, 0)
      T_187928 := T_187932
    reg T_187933 : UInt<58>
    onreset T_187933 := UInt<58>(0)
    
    
    node T_187934 = bit(T_187931, 6)
    node T_187935 = and(T_187930, T_187934)
    when T_187935 : 
      node T_187936 = addw(T_187933, UInt<1>(1))
      T_187933 := T_187936
    node T_187937 = cat(T_187933, T_187928)
    reg reg_fflags : UInt<5>
    reg reg_frm : UInt<3>
    node irq_rocc = and(UInt<1>(0), rocc.interrupt)
    interrupt_cause := UInt<1>(0)
    node T_187938 = bit(interrupt_cause, 63)
    interrupt := T_187938
    wire some_interrupt_pending : UInt<1>
    some_interrupt_pending := UInt<1>(0)
    node T_187939 = and(reg_mie.ssip, reg_mip.ssip)
    
    
    node T_187940 = lt(reg_mstatus.prv, UInt<1>(1))
    node T_187941 = eq(reg_mstatus.prv, UInt<1>(1))
    node T_187942 = and(T_187941, reg_mstatus.ie)
    node T_187943 = or(T_187940, T_187942)
    node T_187944 = and(T_187939, T_187943)
    when T_187944 : interrupt_cause := UInt<64>(9223372036854775808)
    
    
    node T_187945 = leq(reg_mstatus.prv, UInt<1>(1))
    node T_187946 = and(T_187939, T_187945)
    when T_187946 : some_interrupt_pending := UInt<1>(1)
    node T_187947 = and(reg_mie.msip, reg_mip.msip)
    
    
    node T_187948 = lt(reg_mstatus.prv, UInt<2>(3))
    node T_187949 = eq(reg_mstatus.prv, UInt<2>(3))
    node T_187950 = and(T_187949, reg_mstatus.ie)
    node T_187951 = or(T_187948, T_187950)
    node T_187952 = and(T_187947, T_187951)
    when T_187952 : interrupt_cause := UInt<64>(9223372036854775808)
    
    
    node T_187953 = leq(reg_mstatus.prv, UInt<2>(3))
    node T_187954 = and(T_187947, T_187953)
    when T_187954 : some_interrupt_pending := UInt<1>(1)
    node T_187955 = and(reg_mie.stip, reg_mip.stip)
    
    
    node T_187956 = lt(reg_mstatus.prv, UInt<1>(1))
    node T_187957 = eq(reg_mstatus.prv, UInt<1>(1))
    node T_187958 = and(T_187957, reg_mstatus.ie)
    node T_187959 = or(T_187956, T_187958)
    node T_187960 = and(T_187955, T_187959)
    when T_187960 : interrupt_cause := UInt<64>(9223372036854775809)
    
    
    node T_187961 = leq(reg_mstatus.prv, UInt<1>(1))
    node T_187962 = and(T_187955, T_187961)
    when T_187962 : some_interrupt_pending := UInt<1>(1)
    node T_187963 = and(reg_mie.mtip, reg_mip.mtip)
    
    
    node T_187964 = lt(reg_mstatus.prv, UInt<2>(3))
    node T_187965 = eq(reg_mstatus.prv, UInt<2>(3))
    node T_187966 = and(T_187965, reg_mstatus.ie)
    node T_187967 = or(T_187964, T_187966)
    node T_187968 = and(T_187963, T_187967)
    when T_187968 : interrupt_cause := UInt<64>(9223372036854775809)
    
    
    node T_187969 = leq(reg_mstatus.prv, UInt<2>(3))
    node T_187970 = and(T_187963, T_187969)
    when T_187970 : some_interrupt_pending := UInt<1>(1)
    node T_187971 = neq(reg_fromhost, UInt<1>(0))
    
    
    node T_187972 = lt(reg_mstatus.prv, UInt<2>(3))
    node T_187973 = eq(reg_mstatus.prv, UInt<2>(3))
    node T_187974 = and(T_187973, reg_mstatus.ie)
    node T_187975 = or(T_187972, T_187974)
    node T_187976 = and(T_187971, T_187975)
    when T_187976 : interrupt_cause := UInt<64>(9223372036854775810)
    
    
    node T_187977 = leq(reg_mstatus.prv, UInt<2>(3))
    node T_187978 = and(T_187971, T_187977)
    when T_187978 : some_interrupt_pending := UInt<1>(1)
    
    
    node T_187979 = lt(reg_mstatus.prv, UInt<2>(3))
    node T_187980 = eq(reg_mstatus.prv, UInt<2>(3))
    node T_187981 = and(T_187980, reg_mstatus.ie)
    node T_187982 = or(T_187979, T_187981)
    node T_187983 = and(irq_rocc, T_187982)
    when T_187983 : interrupt_cause := UInt<64>(9223372036854775811)
    
    
    node T_187984 = leq(reg_mstatus.prv, UInt<2>(3))
    node T_187985 = and(irq_rocc, T_187984)
    when T_187985 : some_interrupt_pending := UInt<1>(1)
    node system_insn = eq(rw.cmd, UInt<3>(4))
    node T_187986 = neq(rw.cmd, UInt<3>(0))
    node T_187987 = eq(system_insn, UInt<1>(0))
    node cpu_ren = and(T_187986, T_187987)
    reg host_pcr_req_valid : UInt<1>
    node T_187988 = eq(cpu_ren, UInt<1>(0))
    node host_pcr_req_fire = and(host_pcr_req_valid, T_187988)
    reg host_pcr_rep_valid : UInt<1>
    reg host_pcr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}
    node T_187989 = eq(host_pcr_req_valid, UInt<1>(0))
    node T_187990 = eq(host_pcr_rep_valid, UInt<1>(0))
    node T_187991 = and(T_187989, T_187990)
    host.pcr_req.ready := T_187991
    host.pcr_rep.valid := host_pcr_rep_valid
    host.pcr_rep.bits := host_pcr_bits.data
    
    node T_187992 = and(host.pcr_req.ready, host.pcr_req.valid)
    when T_187992 : 
      host_pcr_req_valid := UInt<1>(1)
      host_pcr_bits := host.pcr_req.bits
    when host_pcr_req_fire : 
      host_pcr_req_valid := UInt<1>(0)
      host_pcr_rep_valid := UInt<1>(1)
      host_pcr_bits.data := rw.rdata
    
    node T_187993 = and(host.pcr_rep.ready, host.pcr_rep.valid)
    when T_187993 : host_pcr_rep_valid := UInt<1>(0)
    host.debug_stats_pcr := reg_stats
    node T_187994 = cat(status.sd, status.zero2)
    node T_187995 = cat(status.sd_rv32, status.zero1)
    node T_187996 = cat(T_187994, T_187995)
    node T_187997 = cat(status.vm, status.mprv)
    node T_187998 = cat(status.xs, status.fs)
    node T_187999 = cat(T_187997, T_187998)
    node T_188000 = cat(T_187996, T_187999)
    node T_188001 = cat(status.prv3, status.ie3)
    node T_188002 = cat(status.prv2, status.ie2)
    node T_188003 = cat(T_188001, T_188002)
    node T_188004 = cat(status.prv1, status.ie1)
    node T_188005 = cat(status.prv, status.ie)
    node T_188006 = cat(T_188004, T_188005)
    node T_188007 = cat(T_188003, T_188006)
    node read_mstatus = cat(T_188000, T_188007)
    node T_188008 = cat(reg_frm, reg_fflags)
    node T_188009 = cat(reg_mip.mtip, reg_mip.htip)
    node T_188010 = cat(reg_mip.stip, reg_mip.utip)
    node T_188011 = cat(T_188009, T_188010)
    node T_188012 = cat(reg_mip.msip, reg_mip.hsip)
    node T_188013 = cat(reg_mip.ssip, reg_mip.usip)
    node T_188014 = cat(T_188012, T_188013)
    node T_188015 = cat(T_188011, T_188014)
    node T_188016 = cat(reg_mie.mtip, reg_mie.htip)
    node T_188017 = cat(reg_mie.stip, reg_mie.utip)
    node T_188018 = cat(T_188016, T_188017)
    node T_188019 = cat(reg_mie.msip, reg_mie.hsip)
    node T_188020 = cat(reg_mie.ssip, reg_mie.usip)
    node T_188021 = cat(T_188019, T_188020)
    node T_188022 = cat(T_188018, T_188021)
    node T_188023 = bit(reg_mepc, 39)
    node T_188024 = subw(UInt<24>(0), UInt<5>(24))
    node T_188025 = cat(T_188024, reg_mepc)
    node T_188026 = bit(reg_mbadaddr, 39)
    node T_188027 = subw(UInt<24>(0), UInt<5>(24))
    node T_188028 = cat(T_188027, reg_mbadaddr)
    wire T_188029 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>}
    node T_188030 = bits(read_mstatus, 0, 0)
    T_188029.ie := T_188030
    node T_188031 = bits(read_mstatus, 2, 1)
    T_188029.zero1 := T_188031
    node T_188032 = bits(read_mstatus, 3, 3)
    T_188029.pie := T_188032
    node T_188033 = bits(read_mstatus, 4, 4)
    T_188029.ps := T_188033
    node T_188034 = bits(read_mstatus, 11, 5)
    T_188029.zero2 := T_188034
    node T_188035 = bits(read_mstatus, 13, 12)
    T_188029.fs := T_188035
    node T_188036 = bits(read_mstatus, 15, 14)
    T_188029.xs := T_188036
    node T_188037 = bits(read_mstatus, 16, 16)
    T_188029.mprv := T_188037
    node T_188038 = bits(read_mstatus, 30, 17)
    T_188029.zero3 := T_188038
    node T_188039 = bits(read_mstatus, 31, 31)
    T_188029.sd_rv32 := T_188039
    node T_188040 = bits(read_mstatus, 62, 32)
    T_188029.zero4 := T_188040
    node T_188041 = bits(read_mstatus, 63, 63)
    T_188029.sd := T_188041
    wire T_188042 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>}
    T_188042 := T_188029
    T_188042.zero1 := UInt<1>(0)
    T_188042.zero2 := UInt<1>(0)
    T_188042.zero3 := UInt<1>(0)
    T_188042.zero4 := UInt<1>(0)
    wire T_188043 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_188043.usip := UInt<1>(0)
    T_188043.ssip := UInt<1>(0)
    T_188043.hsip := UInt<1>(0)
    T_188043.msip := UInt<1>(0)
    T_188043.utip := UInt<1>(0)
    T_188043.stip := UInt<1>(0)
    T_188043.htip := UInt<1>(0)
    T_188043.mtip := UInt<1>(0)
    wire T_188044 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_188044 := T_188043
    T_188044.ssip := reg_mip.ssip
    T_188044.stip := reg_mip.stip
    wire T_188045 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_188045.usip := UInt<1>(0)
    T_188045.ssip := UInt<1>(0)
    T_188045.hsip := UInt<1>(0)
    T_188045.msip := UInt<1>(0)
    T_188045.utip := UInt<1>(0)
    T_188045.stip := UInt<1>(0)
    T_188045.htip := UInt<1>(0)
    T_188045.mtip := UInt<1>(0)
    wire T_188046 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
    T_188046 := T_188045
    T_188046.ssip := reg_mie.ssip
    T_188046.stip := reg_mie.stip
    node T_188047 = cat(T_188042.zero4, T_188042.sd_rv32)
    node T_188048 = cat(T_188042.sd, T_188047)
    node T_188049 = cat(T_188042.mprv, T_188042.xs)
    node T_188050 = cat(T_188042.zero3, T_188049)
    node T_188051 = cat(T_188048, T_188050)
    node T_188052 = cat(T_188042.zero2, T_188042.ps)
    node T_188053 = cat(T_188042.fs, T_188052)
    node T_188054 = cat(T_188042.zero1, T_188042.ie)
    node T_188055 = cat(T_188042.pie, T_188054)
    node T_188056 = cat(T_188053, T_188055)
    node T_188057 = cat(T_188051, T_188056)
    node T_188058 = cat(T_188044.mtip, T_188044.htip)
    node T_188059 = cat(T_188044.stip, T_188044.utip)
    node T_188060 = cat(T_188058, T_188059)
    node T_188061 = cat(T_188044.msip, T_188044.hsip)
    node T_188062 = cat(T_188044.ssip, T_188044.usip)
    node T_188063 = cat(T_188061, T_188062)
    node T_188064 = cat(T_188060, T_188063)
    node T_188065 = cat(T_188046.mtip, T_188046.htip)
    node T_188066 = cat(T_188046.stip, T_188046.utip)
    node T_188067 = cat(T_188065, T_188066)
    node T_188068 = cat(T_188046.msip, T_188046.hsip)
    node T_188069 = cat(T_188046.ssip, T_188046.usip)
    node T_188070 = cat(T_188068, T_188069)
    node T_188071 = cat(T_188067, T_188070)
    node T_188072 = bit(reg_sbadaddr, 39)
    node T_188073 = subw(UInt<24>(0), UInt<5>(24))
    node T_188074 = cat(T_188073, reg_sbadaddr)
    node T_188075 = bit(reg_sepc, 39)
    node T_188076 = subw(UInt<24>(0), UInt<5>(24))
    node T_188077 = cat(T_188076, reg_sepc)
    node T_188078 = bit(reg_stvec, 38)
    node T_188079 = subw(UInt<25>(0), UInt<5>(25))
    node T_188080 = cat(T_188079, reg_stvec)
    wire addr : UInt<12>
    addr := host_pcr_bits.addr
    when cpu_ren : addr := rw.addr
    node T_188081 = eq(addr, UInt<1>(1))
    node T_188082 = eq(addr, UInt<2>(2))
    node T_188083 = eq(addr, UInt<2>(3))
    node T_188084 = eq(addr, UInt<12>(3072))
    node T_188085 = eq(addr, UInt<12>(2304))
    node T_188086 = eq(addr, UInt<12>(3074))
    node T_188087 = eq(addr, UInt<12>(2306))
    node T_188088 = eq(addr, UInt<12>(3073))
    node T_188089 = eq(addr, UInt<12>(2305))
    node T_188090 = eq(addr, UInt<12>(3329))
    node T_188091 = eq(addr, UInt<12>(2561))
    node T_188092 = eq(addr, UInt<11>(1793))
    node T_188093 = eq(addr, UInt<12>(3840))
    node T_188094 = eq(addr, UInt<12>(3841))
    node T_188095 = eq(addr, UInt<10>(768))
    node T_188096 = eq(addr, UInt<10>(770))
    node T_188097 = eq(addr, UInt<11>(1922))
    node T_188098 = eq(addr, UInt<10>(769))
    node T_188099 = eq(addr, UInt<10>(836))
    node T_188100 = eq(addr, UInt<10>(772))
    node T_188101 = eq(addr, UInt<10>(832))
    node T_188102 = eq(addr, UInt<10>(833))
    node T_188103 = eq(addr, UInt<10>(835))
    node T_188104 = eq(addr, UInt<10>(834))
    node T_188105 = eq(addr, UInt<10>(801))
    node T_188106 = eq(addr, UInt<12>(3856))
    node T_188107 = eq(addr, UInt<11>(1923))
    node T_188108 = eq(addr, UInt<8>(192))
    node T_188109 = eq(addr, UInt<11>(1920))
    node T_188110 = eq(addr, UInt<11>(1921))
    node T_188111 = eq(addr, UInt<9>(256))
    node T_188112 = eq(addr, UInt<9>(324))
    node T_188113 = eq(addr, UInt<9>(260))
    node T_188114 = eq(addr, UInt<9>(320))
    node T_188115 = eq(addr, UInt<12>(3394))
    node T_188116 = eq(addr, UInt<12>(3395))
    node T_188117 = eq(addr, UInt<9>(384))
    node T_188118 = eq(addr, UInt<9>(385))
    node T_188119 = eq(addr, UInt<9>(321))
    node T_188120 = eq(addr, UInt<9>(257))
    node T_188121 = eq(addr, UInt<12>(3264))
    node T_188122 = eq(addr, UInt<12>(3265))
    node T_188123 = eq(addr, UInt<12>(3266))
    node T_188124 = eq(addr, UInt<12>(3267))
    node T_188125 = eq(addr, UInt<12>(3268))
    node T_188126 = eq(addr, UInt<12>(3269))
    node T_188127 = eq(addr, UInt<12>(3270))
    node T_188128 = eq(addr, UInt<12>(3271))
    node T_188129 = eq(addr, UInt<12>(3272))
    node T_188130 = eq(addr, UInt<12>(3273))
    node T_188131 = eq(addr, UInt<12>(3274))
    node T_188132 = eq(addr, UInt<12>(3275))
    node T_188133 = eq(addr, UInt<12>(3276))
    node T_188134 = eq(addr, UInt<12>(3277))
    node T_188135 = eq(addr, UInt<12>(3278))
    node T_188136 = eq(addr, UInt<12>(3279))
    node T_188137 = or(T_188081, T_188082)
    node T_188138 = or(T_188137, T_188083)
    node T_188139 = or(T_188138, T_188084)
    node T_188140 = or(T_188139, T_188085)
    node T_188141 = or(T_188140, T_188086)
    node T_188142 = or(T_188141, T_188087)
    node T_188143 = or(T_188142, T_188088)
    node T_188144 = or(T_188143, T_188089)
    node T_188145 = or(T_188144, T_188090)
    node T_188146 = or(T_188145, T_188091)
    node T_188147 = or(T_188146, T_188092)
    node T_188148 = or(T_188147, T_188093)
    node T_188149 = or(T_188148, T_188094)
    node T_188150 = or(T_188149, T_188095)
    node T_188151 = or(T_188150, T_188096)
    node T_188152 = or(T_188151, T_188097)
    node T_188153 = or(T_188152, T_188098)
    node T_188154 = or(T_188153, T_188099)
    node T_188155 = or(T_188154, T_188100)
    node T_188156 = or(T_188155, T_188101)
    node T_188157 = or(T_188156, T_188102)
    node T_188158 = or(T_188157, T_188103)
    node T_188159 = or(T_188158, T_188104)
    node T_188160 = or(T_188159, T_188105)
    node T_188161 = or(T_188160, T_188106)
    node T_188162 = or(T_188161, T_188107)
    node T_188163 = or(T_188162, T_188108)
    node T_188164 = or(T_188163, T_188109)
    node T_188165 = or(T_188164, T_188110)
    node T_188166 = or(T_188165, T_188111)
    node T_188167 = or(T_188166, T_188112)
    node T_188168 = or(T_188167, T_188113)
    node T_188169 = or(T_188168, T_188114)
    node T_188170 = or(T_188169, T_188115)
    node T_188171 = or(T_188170, T_188116)
    node T_188172 = or(T_188171, T_188117)
    node T_188173 = or(T_188172, T_188118)
    node T_188174 = or(T_188173, T_188119)
    node T_188175 = or(T_188174, T_188120)
    node T_188176 = or(T_188175, T_188121)
    node T_188177 = or(T_188176, T_188122)
    node T_188178 = or(T_188177, T_188123)
    node T_188179 = or(T_188178, T_188124)
    node T_188180 = or(T_188179, T_188125)
    node T_188181 = or(T_188180, T_188126)
    node T_188182 = or(T_188181, T_188127)
    node T_188183 = or(T_188182, T_188128)
    node T_188184 = or(T_188183, T_188129)
    node T_188185 = or(T_188184, T_188130)
    node T_188186 = or(T_188185, T_188131)
    node T_188187 = or(T_188186, T_188132)
    node T_188188 = or(T_188187, T_188133)
    node T_188189 = or(T_188188, T_188134)
    node T_188190 = or(T_188189, T_188135)
    node addr_valid = or(T_188190, T_188136)
    node T_188191 = or(T_188081, T_188082)
    node fp_csr = or(T_188191, T_188083)
    node csr_addr_priv = bits(rw.addr, 9, 8)
    node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv)
    node T_188192 = bits(rw.addr, 11, 10)
    node read_only = eq(T_188192, UInt<1>(-1))
    node T_188193 = neq(rw.cmd, UInt<3>(5))
    node T_188194 = and(cpu_ren, T_188193)
    node cpu_wen = and(T_188194, priv_sufficient)
    node T_188195 = eq(read_only, UInt<1>(0))
    node T_188196 = and(cpu_wen, T_188195)
    node T_188197 = and(host_pcr_req_fire, host_pcr_bits.rw)
    node wen = or(T_188196, T_188197)
    node T_188198 = eq(rw.cmd, UInt<3>(1))
    node T_188199 = eq(rw.cmd, UInt<3>(3))
    node T_188200 = not(rw.wdata)
    node T_188201 = and(rw.rdata, T_188200)
    node T_188202 = eq(rw.cmd, UInt<3>(2))
    node T_188203 = or(rw.rdata, rw.wdata)
    wire T_188204 : UInt<64>
    T_188204 := host_pcr_bits.data
    when T_188202 : T_188204 := T_188203
    wire T_188205 : UInt<64>
    T_188205 := T_188204
    when T_188199 : T_188205 := T_188201
    wire wdata : UInt<64>
    wdata := T_188205
    when T_188198 : wdata := rw.wdata
    node T_188206 = bit(rw.addr, 8)
    node T_188207 = eq(T_188206, UInt<1>(0))
    node T_188208 = bit(rw.addr, 0)
    node T_188209 = eq(T_188208, UInt<1>(0))
    node T_188210 = and(T_188207, T_188209)
    node insn_call = and(T_188210, system_insn)
    node T_188211 = bit(rw.addr, 8)
    node T_188212 = eq(T_188211, UInt<1>(0))
    node T_188213 = bit(rw.addr, 0)
    node T_188214 = and(T_188212, T_188213)
    node insn_break = and(T_188214, system_insn)
    node T_188215 = bit(rw.addr, 8)
    node T_188216 = bit(rw.addr, 1)
    node T_188217 = eq(T_188216, UInt<1>(0))
    node T_188218 = and(T_188215, T_188217)
    node T_188219 = bit(rw.addr, 0)
    node T_188220 = eq(T_188219, UInt<1>(0))
    node T_188221 = and(T_188218, T_188220)
    node T_188222 = and(T_188221, system_insn)
    node insn_ret = and(T_188222, priv_sufficient)
    node T_188223 = bit(rw.addr, 8)
    node T_188224 = bit(rw.addr, 1)
    node T_188225 = eq(T_188224, UInt<1>(0))
    node T_188226 = and(T_188223, T_188225)
    node T_188227 = bit(rw.addr, 0)
    node T_188228 = and(T_188226, T_188227)
    node T_188229 = and(T_188228, system_insn)
    node insn_sfence_vm = and(T_188229, priv_sufficient)
    node T_188230 = bit(rw.addr, 2)
    node maybe_insn_redirect_trap = and(T_188230, system_insn)
    node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient)
    node T_188231 = bit(rw.addr, 8)
    node T_188232 = bit(rw.addr, 1)
    node T_188233 = and(T_188231, T_188232)
    node T_188234 = bit(rw.addr, 0)
    node T_188235 = eq(T_188234, UInt<1>(0))
    node T_188236 = and(T_188233, T_188235)
    node T_188237 = and(T_188236, system_insn)
    node insn_wfi = and(T_188237, priv_sufficient)
    node T_188238 = and(cpu_wen, read_only)
    node T_188239 = eq(priv_sufficient, UInt<1>(0))
    node T_188240 = eq(addr_valid, UInt<1>(0))
    node T_188241 = or(T_188239, T_188240)
    node T_188242 = eq(status.fs, UInt<1>(0))
    node T_188243 = eq(T_188242, UInt<1>(0))
    node T_188244 = eq(T_188243, UInt<1>(0))
    node T_188245 = and(fp_csr, T_188244)
    node T_188246 = or(T_188241, T_188245)
    node T_188247 = and(cpu_ren, T_188246)
    node T_188248 = or(T_188238, T_188247)
    node T_188249 = eq(priv_sufficient, UInt<1>(0))
    node T_188250 = and(system_insn, T_188249)
    node T_188251 = or(T_188248, T_188250)
    node T_188252 = or(T_188251, insn_call)
    node csr_xcpt = or(T_188252, insn_break)
    when insn_wfi : reg_wfi := UInt<1>(1)
    when some_interrupt_pending : reg_wfi := UInt<1>(0)
    fatc := insn_sfence_vm
    node T_188253 = or(exception, csr_xcpt)
    node T_188254 = shl(reg_mstatus.prv, 6)
    node T_188255 = addw(T_188254, UInt<9>(256))
    node T_188256 = bit(reg_stvec, 38)
    node T_188257 = cat(T_188256, reg_stvec)
    node T_188258 = bit(reg_mstatus.prv, 1)
    wire T_188259 : UInt<40>
    T_188259 := reg_sepc
    when T_188258 : T_188259 := reg_mepc
    wire T_188260 : UInt<40>
    T_188260 := T_188259
    when maybe_insn_redirect_trap : T_188260 := T_188257
    wire T_188261 : UInt<40>
    T_188261 := T_188260
    when T_188253 : T_188261 := T_188255
    evec := T_188261
    ptbr := reg_sptbr
    csr_xcpt := csr_xcpt
    node T_188262 = or(insn_ret, insn_redirect_trap)
    eret := T_188262
    status := reg_mstatus
    node T_188263 = eq(reg_mstatus.fs, UInt<1>(0))
    node T_188264 = eq(T_188263, UInt<1>(0))
    node T_188265 = asSInt(T_188264)
    status.fs := T_188265
    node T_188266 = eq(reg_mstatus.xs, UInt<1>(0))
    node T_188267 = eq(T_188266, UInt<1>(0))
    node T_188268 = asSInt(T_188267)
    status.xs := T_188268
    node T_188269 = eq(reg_mstatus.xs, UInt<1>(0))
    node T_188270 = eq(T_188269, UInt<1>(0))
    node T_188271 = eq(reg_mstatus.fs, UInt<1>(0))
    node T_188272 = eq(T_188271, UInt<1>(0))
    node T_188273 = or(T_188270, T_188272)
    status.sd := T_188273
    
    node T_188274 = or(exception, csr_xcpt)
    when T_188274 : 
      reg_mstatus.ie := UInt<1>(0)
      reg_mstatus.prv := UInt<2>(3)
      reg_mstatus.mprv := UInt<1>(0)
      reg_mstatus.prv1 := reg_mstatus.prv
      reg_mstatus.ie1 := reg_mstatus.ie
      reg_mstatus.prv2 := reg_mstatus.prv1
      reg_mstatus.ie2 := reg_mstatus.ie1
      node T_188275 = not(pc)
      node T_188276 = or(T_188275, UInt<2>(3))
      node T_188277 = not(T_188276)
      reg_mepc := T_188277
      reg_mcause := cause
      when csr_xcpt : 
        reg_mcause := UInt<2>(2)
        when insn_break : reg_mcause := UInt<2>(3)
        when insn_call : 
          node T_188278 = addw(reg_mstatus.prv, UInt<4>(8))
          reg_mcause := T_188278
      reg_mbadaddr := pc
      
      
      node T_188279 = eq(cause, UInt<3>(5))
      node T_188280 = eq(cause, UInt<3>(4))
      node T_188281 = or(T_188279, T_188280)
      node T_188282 = eq(cause, UInt<3>(7))
      node T_188283 = or(T_188281, T_188282)
      node T_188284 = eq(cause, UInt<3>(6))
      node T_188285 = or(T_188283, T_188284)
      when T_188285 : 
        node T_188286 = bits(rw.wdata, 63, 39)
        node T_188287 = bits(rw.wdata, 38, 0)
        node T_188288 = asSInt(T_188287)
        node T_188289 = lt(T_188288, SInt<1>(0))
        node T_188290 = eq(T_188286, UInt<1>(-1))
        node T_188291 = eq(T_188286, UInt<1>(0))
        node T_188292 = eq(T_188291, UInt<1>(0))
        wire T_188293 : UInt<1>
        T_188293 := T_188292
        when T_188289 : T_188293 := T_188290
        node T_188294 = cat(T_188293, T_188287)
        reg_mbadaddr := T_188294
    when insn_ret : 
      reg_mstatus.ie := reg_mstatus.ie1
      reg_mstatus.prv := reg_mstatus.prv1
      reg_mstatus.prv1 := reg_mstatus.prv2
      reg_mstatus.ie1 := reg_mstatus.ie2
      reg_mstatus.prv2 := UInt<1>(0)
      reg_mstatus.ie2 := UInt<1>(1)
    when insn_redirect_trap : 
      reg_mstatus.prv := UInt<1>(1)
      reg_sbadaddr := reg_mbadaddr
      reg_scause := reg_mcause
      reg_sepc := reg_mepc
    node T_188295 = cat(UInt<1>(0), insn_redirect_trap)
    node T_188296 = addw(insn_ret, T_188295)
    node T_188297 = cat(UInt<1>(0), csr_replay)
    node T_188298 = addw(csr_xcpt, T_188297)
    node T_188299 = cat(UInt<1>(0), T_188298)
    node T_188300 = addw(exception, T_188299)
    node T_188301 = cat(UInt<1>(0), T_188300)
    node T_188302 = addw(T_188296, T_188301)
    node T_188303 = leq(T_188302, UInt<1>(1))
    
    node T_188304 = geq(reg_time, reg_mtimecmp)
    when T_188304 : reg_mip.mtip := UInt<1>(1)
    time := T_187767
    node T_188305 = and(cpu_wen, T_188107)
    host.ipi_req.valid := T_188305
    host.ipi_req.bits := rw.wdata
    node T_188306 = eq(host.ipi_req.ready, UInt<1>(0))
    node T_188307 = and(host.ipi_req.valid, T_188306)
    csr_replay := T_188307
    csr_stall := reg_wfi
    
    
    node T_188308 = eq(host_pcr_bits.rw, UInt<1>(0))
    node T_188309 = and(host_pcr_req_fire, T_188308)
    node T_188310 = and(T_188309, T_188109)
    when T_188310 : reg_tohost := UInt<1>(0)
    wire T_188311 : UInt<1>
    T_188311 := UInt<1>(0)
    when T_188081 : T_188311 := reg_fflags
    wire T_188312 : UInt<1>
    T_188312 := UInt<1>(0)
    when T_188082 : T_188312 := reg_frm
    wire T_188313 : UInt<1>
    T_188313 := UInt<1>(0)
    when T_188083 : T_188313 := T_188008
    wire T_188314 : UInt<1>
    T_188314 := UInt<1>(0)
    when T_188084 : T_188314 := T_187767
    wire T_188315 : UInt<1>
    T_188315 := UInt<1>(0)
    when T_188085 : T_188315 := T_187767
    wire T_188316 : UInt<1>
    T_188316 := UInt<1>(0)
    when T_188086 : T_188316 := T_187777
    wire T_188317 : UInt<1>
    T_188317 := UInt<1>(0)
    when T_188087 : T_188317 := T_187777
    wire T_188318 : UInt<1>
    T_188318 := UInt<1>(0)
    when T_188088 : T_188318 := reg_time
    wire T_188319 : UInt<1>
    T_188319 := UInt<1>(0)
    when T_188089 : T_188319 := reg_time
    wire T_188320 : UInt<1>
    T_188320 := UInt<1>(0)
    when T_188090 : T_188320 := reg_time
    wire T_188321 : UInt<1>
    T_188321 := UInt<1>(0)
    when T_188091 : T_188321 := reg_time
    wire T_188322 : UInt<1>
    T_188322 := UInt<1>(0)
    when T_188092 : T_188322 := reg_time
    wire T_188323 : UInt<1>
    T_188323 := UInt<1>(0)
    when T_188093 : T_188323 := UInt<64>(9223372036855042345)
    wire T_188324 : UInt<1>
    T_188324 := UInt<1>(0)
    when T_188094 : T_188324 := UInt<1>(1)
    wire T_188325 : UInt<1>
    T_188325 := UInt<1>(0)
    when T_188095 : T_188325 := read_mstatus
    wire T_188326 : UInt<1>
    T_188326 := UInt<1>(0)
    when T_188096 : T_188326 := UInt<1>(0)
    wire T_188327 : UInt<1>
    T_188327 := UInt<1>(0)
    when T_188097 : T_188327 := UInt<1>(0)
    wire T_188328 : UInt<1>
    T_188328 := UInt<1>(0)
    when T_188098 : T_188328 := UInt<9>(256)
    wire T_188329 : UInt<1>
    T_188329 := UInt<1>(0)
    when T_188099 : T_188329 := T_188015
    wire T_188330 : UInt<1>
    T_188330 := UInt<1>(0)
    when T_188100 : T_188330 := T_188022
    wire T_188331 : UInt<1>
    T_188331 := UInt<1>(0)
    when T_188101 : T_188331 := reg_mscratch
    wire T_188332 : UInt<1>
    T_188332 := UInt<1>(0)
    when T_188102 : T_188332 := T_188025
    wire T_188333 : UInt<1>
    T_188333 := UInt<1>(0)
    when T_188103 : T_188333 := T_188028
    wire T_188334 : UInt<1>
    T_188334 := UInt<1>(0)
    when T_188104 : T_188334 := reg_mcause
    wire T_188335 : UInt<1>
    T_188335 := UInt<1>(0)
    when T_188105 : T_188335 := reg_mtimecmp
    wire T_188336 : UInt<1>
    T_188336 := UInt<1>(0)
    when T_188106 : T_188336 := host.id
    wire T_188337 : UInt<1>
    T_188337 := UInt<1>(0)
    when T_188107 : T_188337 := host.id
    wire T_188338 : UInt<1>
    T_188338 := UInt<1>(0)
    when T_188108 : T_188338 := reg_stats
    wire T_188339 : UInt<1>
    T_188339 := UInt<1>(0)
    when T_188109 : T_188339 := reg_tohost
    wire T_188340 : UInt<1>
    T_188340 := UInt<1>(0)
    when T_188110 : T_188340 := reg_fromhost
    wire T_188341 : UInt<1>
    T_188341 := UInt<1>(0)
    when T_188111 : T_188341 := T_188057
    wire T_188342 : UInt<1>
    T_188342 := UInt<1>(0)
    when T_188112 : T_188342 := T_188064
    wire T_188343 : UInt<1>
    T_188343 := UInt<1>(0)
    when T_188113 : T_188343 := T_188071
    wire T_188344 : UInt<1>
    T_188344 := UInt<1>(0)
    when T_188114 : T_188344 := reg_sscratch
    wire T_188345 : UInt<1>
    T_188345 := UInt<1>(0)
    when T_188115 : T_188345 := reg_scause
    wire T_188346 : UInt<1>
    T_188346 := UInt<1>(0)
    when T_188116 : T_188346 := T_188074
    wire T_188347 : UInt<1>
    T_188347 := UInt<1>(0)
    when T_188117 : T_188347 := reg_sptbr
    wire T_188348 : UInt<1>
    T_188348 := UInt<1>(0)
    when T_188118 : T_188348 := UInt<1>(0)
    wire T_188349 : UInt<1>
    T_188349 := UInt<1>(0)
    when T_188119 : T_188349 := T_188077
    wire T_188350 : UInt<1>
    T_188350 := UInt<1>(0)
    when T_188120 : T_188350 := T_188080
    wire T_188351 : UInt<1>
    T_188351 := UInt<1>(0)
    when T_188121 : T_188351 := T_187787
    wire T_188352 : UInt<1>
    T_188352 := UInt<1>(0)
    when T_188122 : T_188352 := T_187797
    wire T_188353 : UInt<1>
    T_188353 := UInt<1>(0)
    when T_188123 : T_188353 := T_187807
    wire T_188354 : UInt<1>
    T_188354 := UInt<1>(0)
    when T_188124 : T_188354 := T_187817
    wire T_188355 : UInt<1>
    T_188355 := UInt<1>(0)
    when T_188125 : T_188355 := T_187827
    wire T_188356 : UInt<1>
    T_188356 := UInt<1>(0)
    when T_188126 : T_188356 := T_187837
    wire T_188357 : UInt<1>
    T_188357 := UInt<1>(0)
    when T_188127 : T_188357 := T_187847
    wire T_188358 : UInt<1>
    T_188358 := UInt<1>(0)
    when T_188128 : T_188358 := T_187857
    wire T_188359 : UInt<1>
    T_188359 := UInt<1>(0)
    when T_188129 : T_188359 := T_187867
    wire T_188360 : UInt<1>
    T_188360 := UInt<1>(0)
    when T_188130 : T_188360 := T_187877
    wire T_188361 : UInt<1>
    T_188361 := UInt<1>(0)
    when T_188131 : T_188361 := T_187887
    wire T_188362 : UInt<1>
    T_188362 := UInt<1>(0)
    when T_188132 : T_188362 := T_187897
    wire T_188363 : UInt<1>
    T_188363 := UInt<1>(0)
    when T_188133 : T_188363 := T_187907
    wire T_188364 : UInt<1>
    T_188364 := UInt<1>(0)
    when T_188134 : T_188364 := T_187917
    wire T_188365 : UInt<1>
    T_188365 := UInt<1>(0)
    when T_188135 : T_188365 := T_187927
    wire T_188366 : UInt<1>
    T_188366 := UInt<1>(0)
    when T_188136 : T_188366 := T_187937
    node T_188367 = or(T_188311, T_188312)
    node T_188368 = or(T_188367, T_188313)
    node T_188369 = or(T_188368, T_188314)
    node T_188370 = or(T_188369, T_188315)
    node T_188371 = or(T_188370, T_188316)
    node T_188372 = or(T_188371, T_188317)
    node T_188373 = or(T_188372, T_188318)
    node T_188374 = or(T_188373, T_188319)
    node T_188375 = or(T_188374, T_188320)
    node T_188376 = or(T_188375, T_188321)
    node T_188377 = or(T_188376, T_188322)
    node T_188378 = or(T_188377, T_188323)
    node T_188379 = or(T_188378, T_188324)
    node T_188380 = or(T_188379, T_188325)
    node T_188381 = or(T_188380, T_188326)
    node T_188382 = or(T_188381, T_188327)
    node T_188383 = or(T_188382, T_188328)
    node T_188384 = or(T_188383, T_188329)
    node T_188385 = or(T_188384, T_188330)
    node T_188386 = or(T_188385, T_188331)
    node T_188387 = or(T_188386, T_188332)
    node T_188388 = or(T_188387, T_188333)
    node T_188389 = or(T_188388, T_188334)
    node T_188390 = or(T_188389, T_188335)
    node T_188391 = or(T_188390, T_188336)
    node T_188392 = or(T_188391, T_188337)
    node T_188393 = or(T_188392, T_188338)
    node T_188394 = or(T_188393, T_188339)
    node T_188395 = or(T_188394, T_188340)
    node T_188396 = or(T_188395, T_188341)
    node T_188397 = or(T_188396, T_188342)
    node T_188398 = or(T_188397, T_188343)
    node T_188399 = or(T_188398, T_188344)
    node T_188400 = or(T_188399, T_188345)
    node T_188401 = or(T_188400, T_188346)
    node T_188402 = or(T_188401, T_188347)
    node T_188403 = or(T_188402, T_188348)
    node T_188404 = or(T_188403, T_188349)
    node T_188405 = or(T_188404, T_188350)
    node T_188406 = or(T_188405, T_188351)
    node T_188407 = or(T_188406, T_188352)
    node T_188408 = or(T_188407, T_188353)
    node T_188409 = or(T_188408, T_188354)
    node T_188410 = or(T_188409, T_188355)
    node T_188411 = or(T_188410, T_188356)
    node T_188412 = or(T_188411, T_188357)
    node T_188413 = or(T_188412, T_188358)
    node T_188414 = or(T_188413, T_188359)
    node T_188415 = or(T_188414, T_188360)
    node T_188416 = or(T_188415, T_188361)
    node T_188417 = or(T_188416, T_188362)
    node T_188418 = or(T_188417, T_188363)
    node T_188419 = or(T_188418, T_188364)
    node T_188420 = or(T_188419, T_188365)
    node T_188421 = or(T_188420, T_188366)
    wire T_188422 : UInt<5>
    node T_188423 = bits(T_188421, 4, 0)
    T_188422 := T_188423
    rw.rdata := T_188422
    fcsr_rm := reg_frm
    when fcsr_flags.valid : 
      node T_188424 = or(reg_fflags, fcsr_flags.bits)
      reg_fflags := T_188424
    when wen : 
      when T_188095 : 
        wire T_188425 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}
        node T_188426 = bits(wdata, 0, 0)
        T_188425.ie := T_188426
        node T_188427 = bits(wdata, 2, 1)
        T_188425.prv := T_188427
        node T_188428 = bits(wdata, 3, 3)
        T_188425.ie1 := T_188428
        node T_188429 = bits(wdata, 5, 4)
        T_188425.prv1 := T_188429
        node T_188430 = bits(wdata, 6, 6)
        T_188425.ie2 := T_188430
        node T_188431 = bits(wdata, 8, 7)
        T_188425.prv2 := T_188431
        node T_188432 = bits(wdata, 9, 9)
        T_188425.ie3 := T_188432
        node T_188433 = bits(wdata, 11, 10)
        T_188425.prv3 := T_188433
        node T_188434 = bits(wdata, 13, 12)
        T_188425.fs := T_188434
        node T_188435 = bits(wdata, 15, 14)
        T_188425.xs := T_188435
        node T_188436 = bits(wdata, 16, 16)
        T_188425.mprv := T_188436
        node T_188437 = bits(wdata, 21, 17)
        T_188425.vm := T_188437
        node T_188438 = bits(wdata, 30, 22)
        T_188425.zero1 := T_188438
        node T_188439 = bits(wdata, 31, 31)
        T_188425.sd_rv32 := T_188439
        node T_188440 = bits(wdata, 62, 32)
        T_188425.zero2 := T_188440
        node T_188441 = bits(wdata, 63, 63)
        T_188425.sd := T_188441
        reg_mstatus.ie := T_188425.ie
        reg_mstatus.ie1 := T_188425.ie1
        wire T_188442 : UInt<2>[3]
        T_188442[0] := UInt<2>(3)
        T_188442[1] := UInt<1>(0)
        T_188442[2] := UInt<1>(1)
        reg_mstatus.mprv := T_188425.mprv
        
        
        node T_188443 = eq(T_188442[0], T_188425.prv)
        node T_188444 = eq(T_188442[1], T_188425.prv)
        node T_188445 = eq(T_188442[2], T_188425.prv)
        node T_188446 = or(UInt<1>(0), T_188443)
        node T_188447 = or(T_188446, T_188444)
        node T_188448 = or(T_188447, T_188445)
        when T_188448 : reg_mstatus.prv := T_188425.prv
        
        
        node T_188449 = eq(T_188442[0], T_188425.prv1)
        node T_188450 = eq(T_188442[1], T_188425.prv1)
        node T_188451 = eq(T_188442[2], T_188425.prv1)
        node T_188452 = or(UInt<1>(0), T_188449)
        node T_188453 = or(T_188452, T_188450)
        node T_188454 = or(T_188453, T_188451)
        when T_188454 : reg_mstatus.prv1 := T_188425.prv1
        
        
        node T_188455 = eq(T_188442[0], T_188425.prv2)
        node T_188456 = eq(T_188442[1], T_188425.prv2)
        node T_188457 = eq(T_188442[2], T_188425.prv2)
        node T_188458 = or(UInt<1>(0), T_188455)
        node T_188459 = or(T_188458, T_188456)
        node T_188460 = or(T_188459, T_188457)
        when T_188460 : reg_mstatus.prv2 := T_188425.prv2
        reg_mstatus.ie2 := T_188425.ie2
        
        node T_188461 = eq(T_188425.vm, UInt<1>(0))
        when T_188461 : reg_mstatus.vm := UInt<1>(0)
        
        node T_188462 = eq(T_188425.vm, UInt<4>(9))
        when T_188462 : reg_mstatus.vm := UInt<4>(9)
        reg_mstatus.fs := T_188425.fs
      when T_188099 : 
        wire T_188463 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        node T_188464 = bits(wdata, 0, 0)
        T_188463.usip := T_188464
        node T_188465 = bits(wdata, 1, 1)
        T_188463.ssip := T_188465
        node T_188466 = bits(wdata, 2, 2)
        T_188463.hsip := T_188466
        node T_188467 = bits(wdata, 3, 3)
        T_188463.msip := T_188467
        node T_188468 = bits(wdata, 4, 4)
        T_188463.utip := T_188468
        node T_188469 = bits(wdata, 5, 5)
        T_188463.stip := T_188469
        node T_188470 = bits(wdata, 6, 6)
        T_188463.htip := T_188470
        node T_188471 = bits(wdata, 7, 7)
        T_188463.mtip := T_188471
        reg_mip.ssip := T_188463.ssip
        reg_mip.stip := T_188463.stip
        reg_mip.msip := T_188463.msip
      when T_188100 : 
        wire T_188472 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        node T_188473 = bits(wdata, 0, 0)
        T_188472.usip := T_188473
        node T_188474 = bits(wdata, 1, 1)
        T_188472.ssip := T_188474
        node T_188475 = bits(wdata, 2, 2)
        T_188472.hsip := T_188475
        node T_188476 = bits(wdata, 3, 3)
        T_188472.msip := T_188476
        node T_188477 = bits(wdata, 4, 4)
        T_188472.utip := T_188477
        node T_188478 = bits(wdata, 5, 5)
        T_188472.stip := T_188478
        node T_188479 = bits(wdata, 6, 6)
        T_188472.htip := T_188479
        node T_188480 = bits(wdata, 7, 7)
        T_188472.mtip := T_188480
        reg_mie.ssip := T_188472.ssip
        reg_mie.stip := T_188472.stip
        reg_mie.msip := T_188472.msip
        reg_mie.mtip := T_188472.mtip
      when T_188081 : reg_fflags := wdata
      when T_188082 : reg_frm := wdata
      when T_188083 : 
        reg_fflags := wdata
        node T_188481 = shr(wdata, 5)
        reg_frm := T_188481
      when T_188102 : 
        node T_188482 = bits(wdata, 39, 0)
        node T_188483 = asSInt(T_188482)
        node T_188484 = and(T_188483, SInt<3>(-4))
        reg_mepc := T_188484
      when T_188101 : reg_mscratch := wdata
      when T_188104 : 
        node T_188485 = and(wdata, UInt<64>(9223372036854775839))
        reg_mcause := T_188485
      when T_188103 : 
        node T_188486 = bits(wdata, 39, 0)
        reg_mbadaddr := T_188486
      when T_188087 : 
        node T_188487 = bits(wdata, 5, 0)
        T_187768 := T_188487
        node T_188488 = bits(wdata, 63, 6)
        T_187773 := T_188488
      when T_188105 : 
        reg_mtimecmp := wdata
        reg_mip.mtip := UInt<1>(0)
      when T_188097 : reg_time := wdata
      when T_188110 : 
        
        node T_188489 = eq(reg_fromhost, UInt<1>(0))
        node T_188490 = eq(host_pcr_req_fire, UInt<1>(0))
        node T_188491 = or(T_188489, T_188490)
        when T_188491 : reg_fromhost := wdata
      when T_188109 : 
        
        node T_188492 = eq(reg_tohost, UInt<1>(0))
        node T_188493 = or(T_188492, host_pcr_req_fire)
        when T_188493 : reg_tohost := wdata
      when T_188108 : 
        node T_188494 = bit(wdata, 0)
        reg_stats := T_188494
      when T_188111 : 
        wire T_188495 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>}
        node T_188496 = bits(wdata, 0, 0)
        T_188495.ie := T_188496
        node T_188497 = bits(wdata, 2, 1)
        T_188495.zero1 := T_188497
        node T_188498 = bits(wdata, 3, 3)
        T_188495.pie := T_188498
        node T_188499 = bits(wdata, 4, 4)
        T_188495.ps := T_188499
        node T_188500 = bits(wdata, 11, 5)
        T_188495.zero2 := T_188500
        node T_188501 = bits(wdata, 13, 12)
        T_188495.fs := T_188501
        node T_188502 = bits(wdata, 15, 14)
        T_188495.xs := T_188502
        node T_188503 = bits(wdata, 16, 16)
        T_188495.mprv := T_188503
        node T_188504 = bits(wdata, 30, 17)
        T_188495.zero3 := T_188504
        node T_188505 = bits(wdata, 31, 31)
        T_188495.sd_rv32 := T_188505
        node T_188506 = bits(wdata, 62, 32)
        T_188495.zero4 := T_188506
        node T_188507 = bits(wdata, 63, 63)
        T_188495.sd := T_188507
        reg_mstatus.ie := T_188495.ie
        reg_mstatus.ie1 := T_188495.pie
        wire T_188508 : UInt<1>
        T_188508 := UInt<1>(0)
        when T_188495.ps : T_188508 := UInt<1>(1)
        reg_mstatus.prv1 := T_188508
        reg_mstatus.mprv := T_188495.mprv
        reg_mstatus.fs := T_188495.fs
      when T_188112 : 
        wire T_188509 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        node T_188510 = bits(wdata, 0, 0)
        T_188509.usip := T_188510
        node T_188511 = bits(wdata, 1, 1)
        T_188509.ssip := T_188511
        node T_188512 = bits(wdata, 2, 2)
        T_188509.hsip := T_188512
        node T_188513 = bits(wdata, 3, 3)
        T_188509.msip := T_188513
        node T_188514 = bits(wdata, 4, 4)
        T_188509.utip := T_188514
        node T_188515 = bits(wdata, 5, 5)
        T_188509.stip := T_188515
        node T_188516 = bits(wdata, 6, 6)
        T_188509.htip := T_188516
        node T_188517 = bits(wdata, 7, 7)
        T_188509.mtip := T_188517
        reg_mip.ssip := T_188509.ssip
      when T_188113 : 
        wire T_188518 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
        node T_188519 = bits(wdata, 0, 0)
        T_188518.usip := T_188519
        node T_188520 = bits(wdata, 1, 1)
        T_188518.ssip := T_188520
        node T_188521 = bits(wdata, 2, 2)
        T_188518.hsip := T_188521
        node T_188522 = bits(wdata, 3, 3)
        T_188518.msip := T_188522
        node T_188523 = bits(wdata, 4, 4)
        T_188518.utip := T_188523
        node T_188524 = bits(wdata, 5, 5)
        T_188518.stip := T_188524
        node T_188525 = bits(wdata, 6, 6)
        T_188518.htip := T_188525
        node T_188526 = bits(wdata, 7, 7)
        T_188518.mtip := T_188526
        reg_mie.ssip := T_188518.ssip
        reg_mie.stip := T_188518.stip
      when T_188114 : reg_sscratch := wdata
      when T_188117 : 
        node T_188527 = bits(wdata, 31, 12)
        node T_188528 = cat(T_188527, UInt<12>(0))
        reg_sptbr := T_188528
      when T_188119 : 
        node T_188529 = bits(wdata, 39, 0)
        node T_188530 = asSInt(T_188529)
        node T_188531 = and(T_188530, SInt<3>(-4))
        reg_sepc := T_188531
      when T_188120 : 
        node T_188532 = bits(wdata, 38, 0)
        node T_188533 = asSInt(T_188532)
        node T_188534 = and(T_188533, SInt<3>(-4))
        reg_stvec := T_188534
    host.ipi_rep.ready := UInt<1>(1)
    when host.ipi_rep.valid : reg_mip.msip := UInt<1>(1)
    when reset : 
      reg_mstatus.zero1 := UInt<1>(0)
      reg_mstatus.zero2 := UInt<1>(0)
      reg_mstatus.ie := UInt<1>(0)
      reg_mstatus.prv := UInt<2>(3)
      reg_mstatus.ie1 := UInt<1>(0)
      reg_mstatus.prv1 := UInt<2>(3)
      reg_mstatus.ie2 := UInt<1>(0)
      reg_mstatus.prv2 := UInt<1>(0)
      reg_mstatus.ie3 := UInt<1>(0)
      reg_mstatus.prv3 := UInt<1>(0)
      reg_mstatus.mprv := UInt<1>(0)
      reg_mstatus.vm := UInt<1>(0)
      reg_mstatus.fs := UInt<1>(0)
      reg_mstatus.xs := UInt<1>(0)
      reg_mstatus.sd_rv32 := UInt<1>(0)
      reg_mstatus.sd := UInt<1>(0)
  module ALU : 
    input dw : UInt<1>
    input fn : UInt<4>
    input in2 : UInt<64>
    input in1 : UInt<64>
    output out : UInt<64>
    output adder_out : UInt<64>
    
    node T_188535 = bit(fn, 3)
    node T_188536 = subw(UInt<1>(0), in2)
    wire T_188537 : UInt<64>
    T_188537 := in2
    when T_188535 : T_188537 := T_188536
    node sum = addw(in1, T_188537)
    node T_188538 = bit(fn, 0)
    node T_188539 = bit(fn, 2)
    node T_188540 = eq(T_188539, UInt<1>(0))
    node T_188541 = eq(sum, UInt<1>(0))
    node T_188542 = bit(in1, 63)
    node T_188543 = bit(in2, 63)
    node T_188544 = eq(T_188542, T_188543)
    node T_188545 = bit(sum, 63)
    node T_188546 = bit(fn, 1)
    node T_188547 = bit(in2, 63)
    node T_188548 = bit(in1, 63)
    wire T_188549 : UInt<1>
    T_188549 := T_188548
    when T_188546 : T_188549 := T_188547
    wire T_188550 : UInt<1>
    T_188550 := T_188549
    when T_188544 : T_188550 := T_188545
    wire T_188551 : UInt<1>
    T_188551 := T_188550
    when T_188540 : T_188551 := T_188541
    node cmp = xor(T_188538, T_188551)
    node T_188552 = bit(in2, 5)
    node T_188553 = and(dw, UInt<1>(1))
    node T_188554 = eq(UInt<1>(1), T_188553)
    node T_188555 = and(T_188552, T_188554)
    node T_188556 = bits(in2, 4, 0)
    node shamt = cat(T_188555, T_188556)
    node T_188557 = bit(fn, 3)
    node T_188558 = bit(in1, 31)
    node T_188559 = subw(UInt<32>(0), UInt<6>(32))
    wire shin_hi_32 : UInt<32>
    shin_hi_32 := UInt<32>(0)
    when T_188557 : shin_hi_32 := T_188559
    node T_188560 = and(dw, UInt<1>(1))
    node T_188561 = eq(UInt<1>(1), T_188560)
    node T_188562 = bits(in1, 63, 32)
    wire shin_hi : UInt<32>
    shin_hi := shin_hi_32
    when T_188561 : shin_hi := T_188562
    node T_188563 = bits(in1, 31, 0)
    node shin_r = cat(shin_hi, T_188563)
    node T_188564 = eq(fn, UInt<3>(5))
    node T_188565 = eq(fn, UInt<4>(11))
    node T_188566 = or(T_188564, T_188565)
    node T_188567 = dshl(UInt<32>(4294967295), UInt<6>(32))
    node T_188568 = xor(UInt<64>(18446744073709551615), T_188567)
    node T_188569 = dshr(shin_r, UInt<6>(32))
    node T_188570 = and(T_188569, T_188568)
    node T_188571 = bits(shin_r, 31, 0)
    node T_188572 = dshl(T_188571, UInt<6>(32))
    node T_188573 = not(T_188568)
    node T_188574 = and(T_188572, T_188573)
    node T_188575 = or(T_188570, T_188574)
    node T_188576 = bits(T_188568, 47, 0)
    node T_188577 = dshl(T_188576, UInt<5>(16))
    node T_188578 = xor(T_188568, T_188577)
    node T_188579 = dshr(T_188575, UInt<5>(16))
    node T_188580 = and(T_188579, T_188578)
    node T_188581 = bits(T_188575, 47, 0)
    node T_188582 = dshl(T_188581, UInt<5>(16))
    node T_188583 = not(T_188578)
    node T_188584 = and(T_188582, T_188583)
    node T_188585 = or(T_188580, T_188584)
    node T_188586 = bits(T_188578, 55, 0)
    node T_188587 = dshl(T_188586, UInt<4>(8))
    node T_188588 = xor(T_188578, T_188587)
    node T_188589 = dshr(T_188585, UInt<4>(8))
    node T_188590 = and(T_188589, T_188588)
    node T_188591 = bits(T_188585, 55, 0)
    node T_188592 = dshl(T_188591, UInt<4>(8))
    node T_188593 = not(T_188588)
    node T_188594 = and(T_188592, T_188593)
    node T_188595 = or(T_188590, T_188594)
    node T_188596 = bits(T_188588, 59, 0)
    node T_188597 = dshl(T_188596, UInt<3>(4))
    node T_188598 = xor(T_188588, T_188597)
    node T_188599 = dshr(T_188595, UInt<3>(4))
    node T_188600 = and(T_188599, T_188598)
    node T_188601 = bits(T_188595, 59, 0)
    node T_188602 = dshl(T_188601, UInt<3>(4))
    node T_188603 = not(T_188598)
    node T_188604 = and(T_188602, T_188603)
    node T_188605 = or(T_188600, T_188604)
    node T_188606 = bits(T_188598, 61, 0)
    node T_188607 = dshl(T_188606, UInt<2>(2))
    node T_188608 = xor(T_188598, T_188607)
    node T_188609 = dshr(T_188605, UInt<2>(2))
    node T_188610 = and(T_188609, T_188608)
    node T_188611 = bits(T_188605, 61, 0)
    node T_188612 = dshl(T_188611, UInt<2>(2))
    node T_188613 = not(T_188608)
    node T_188614 = and(T_188612, T_188613)
    node T_188615 = or(T_188610, T_188614)
    node T_188616 = bits(T_188608, 62, 0)
    node T_188617 = dshl(T_188616, UInt<1>(1))
    node T_188618 = xor(T_188608, T_188617)
    node T_188619 = dshr(T_188615, UInt<1>(1))
    node T_188620 = and(T_188619, T_188618)
    node T_188621 = bits(T_188615, 62, 0)
    node T_188622 = dshl(T_188621, UInt<1>(1))
    node T_188623 = not(T_188618)
    node T_188624 = and(T_188622, T_188623)
    node T_188625 = or(T_188620, T_188624)
    wire shin : UInt<96>
    shin := T_188625
    when T_188566 : shin := shin_r
    node T_188626 = bit(fn, 3)
    node T_188627 = bit(shin, 63)
    node T_188628 = and(T_188626, T_188627)
    node T_188629 = cat(T_188628, shin)
    node T_188630 = asSInt(T_188629)
    node T_188631 = dshr(T_188630, shamt)
    node shout_r = bits(T_188631, 63, 0)
    node T_188632 = dshl(UInt<32>(4294967295), UInt<6>(32))
    node T_188633 = xor(UInt<64>(18446744073709551615), T_188632)
    node T_188634 = dshr(shout_r, UInt<6>(32))
    node T_188635 = and(T_188634, T_188633)
    node T_188636 = bits(shout_r, 31, 0)
    node T_188637 = dshl(T_188636, UInt<6>(32))
    node T_188638 = not(T_188633)
    node T_188639 = and(T_188637, T_188638)
    node T_188640 = or(T_188635, T_188639)
    node T_188641 = bits(T_188633, 47, 0)
    node T_188642 = dshl(T_188641, UInt<5>(16))
    node T_188643 = xor(T_188633, T_188642)
    node T_188644 = dshr(T_188640, UInt<5>(16))
    node T_188645 = and(T_188644, T_188643)
    node T_188646 = bits(T_188640, 47, 0)
    node T_188647 = dshl(T_188646, UInt<5>(16))
    node T_188648 = not(T_188643)
    node T_188649 = and(T_188647, T_188648)
    node T_188650 = or(T_188645, T_188649)
    node T_188651 = bits(T_188643, 55, 0)
    node T_188652 = dshl(T_188651, UInt<4>(8))
    node T_188653 = xor(T_188643, T_188652)
    node T_188654 = dshr(T_188650, UInt<4>(8))
    node T_188655 = and(T_188654, T_188653)
    node T_188656 = bits(T_188650, 55, 0)
    node T_188657 = dshl(T_188656, UInt<4>(8))
    node T_188658 = not(T_188653)
    node T_188659 = and(T_188657, T_188658)
    node T_188660 = or(T_188655, T_188659)
    node T_188661 = bits(T_188653, 59, 0)
    node T_188662 = dshl(T_188661, UInt<3>(4))
    node T_188663 = xor(T_188653, T_188662)
    node T_188664 = dshr(T_188660, UInt<3>(4))
    node T_188665 = and(T_188664, T_188663)
    node T_188666 = bits(T_188660, 59, 0)
    node T_188667 = dshl(T_188666, UInt<3>(4))
    node T_188668 = not(T_188663)
    node T_188669 = and(T_188667, T_188668)
    node T_188670 = or(T_188665, T_188669)
    node T_188671 = bits(T_188663, 61, 0)
    node T_188672 = dshl(T_188671, UInt<2>(2))
    node T_188673 = xor(T_188663, T_188672)
    node T_188674 = dshr(T_188670, UInt<2>(2))
    node T_188675 = and(T_188674, T_188673)
    node T_188676 = bits(T_188670, 61, 0)
    node T_188677 = dshl(T_188676, UInt<2>(2))
    node T_188678 = not(T_188673)
    node T_188679 = and(T_188677, T_188678)
    node T_188680 = or(T_188675, T_188679)
    node T_188681 = bits(T_188673, 62, 0)
    node T_188682 = dshl(T_188681, UInt<1>(1))
    node T_188683 = xor(T_188673, T_188682)
    node T_188684 = dshr(T_188680, UInt<1>(1))
    node T_188685 = and(T_188684, T_188683)
    node T_188686 = bits(T_188680, 62, 0)
    node T_188687 = dshl(T_188686, UInt<1>(1))
    node T_188688 = not(T_188683)
    node T_188689 = and(T_188687, T_188688)
    node shout_l = or(T_188685, T_188689)
    node T_188690 = eq(fn, UInt<1>(0))
    node T_188691 = eq(fn, UInt<4>(10))
    node T_188692 = or(T_188690, T_188691)
    node T_188693 = eq(fn, UInt<3>(5))
    node T_188694 = eq(fn, UInt<4>(11))
    node T_188695 = or(T_188693, T_188694)
    node T_188696 = eq(fn, UInt<1>(1))
    node T_188697 = eq(fn, UInt<3>(7))
    node T_188698 = and(in1, in2)
    node T_188699 = eq(fn, UInt<3>(6))
    node T_188700 = or(in1, in2)
    node T_188701 = eq(fn, UInt<3>(4))
    node T_188702 = xor(in1, in2)
    wire T_188703 : UInt<1>
    T_188703 := cmp
    when T_188701 : T_188703 := T_188702
    wire T_188704 : UInt<1>
    T_188704 := T_188703
    when T_188699 : T_188704 := T_188700
    wire T_188705 : UInt<1>
    T_188705 := T_188704
    when T_188697 : T_188705 := T_188698
    wire T_188706 : UInt<1>
    T_188706 := T_188705
    when T_188696 : T_188706 := shout_l
    wire T_188707 : UInt<1>
    T_188707 := T_188706
    when T_188695 : T_188707 := shout_r
    wire out64 : UInt<1>
    out64 := T_188707
    when T_188692 : out64 := sum
    node T_188708 = and(dw, UInt<1>(1))
    node T_188709 = eq(UInt<1>(1), T_188708)
    node T_188710 = bits(out64, 63, 32)
    node T_188711 = bit(out64, 31)
    node T_188712 = subw(UInt<32>(0), UInt<6>(32))
    wire out_hi : UInt<32>
    out_hi := T_188712
    when T_188709 : out_hi := T_188710
    node T_188713 = bits(out64, 31, 0)
    node T_188714 = cat(out_hi, T_188713)
    out := T_188714
    adder_out := sum
  module MulDiv : 
    input req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}
    input kill : UInt<1>
    output resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}
    
    reg state : UInt<3>
    onreset state := UInt<3>(0)
    reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}
    reg count : UInt<7>
    reg neg_out : UInt<1>
    reg isMul : UInt<1>
    reg isHi : UInt<1>
    reg divisor : UInt<65>
    reg remainder : UInt<130>
    node T_188715 = and(req.bits.fn, UInt<4>(4))
    node T_188716 = eq(T_188715, UInt<4>(0))
    node T_188717 = and(req.bits.fn, UInt<4>(8))
    node T_188718 = eq(T_188717, UInt<4>(8))
    node T_188719 = or(UInt<1>(0), T_188716)
    node T_188720 = or(T_188719, T_188718)
    node T_188721 = and(req.bits.fn, UInt<4>(5))
    node T_188722 = eq(T_188721, UInt<4>(1))
    node T_188723 = and(req.bits.fn, UInt<4>(2))
    node T_188724 = eq(T_188723, UInt<4>(2))
    node T_188725 = or(UInt<1>(0), T_188722)
    node T_188726 = or(T_188725, T_188724)
    node T_188727 = or(T_188726, T_188718)
    node T_188728 = and(req.bits.fn, UInt<4>(9))
    node T_188729 = eq(T_188728, UInt<4>(0))
    node T_188730 = and(req.bits.fn, UInt<4>(3))
    node T_188731 = eq(T_188730, UInt<4>(0))
    node T_188732 = or(UInt<1>(0), T_188729)
    node T_188733 = or(T_188732, T_188716)
    node T_188734 = or(T_188733, T_188731)
    node T_188735 = or(UInt<1>(0), T_188729)
    node T_188736 = or(T_188735, T_188716)
    node cmdMul = bit(T_188720, 0)
    node cmdHi = bit(T_188727, 0)
    node lhsSigned = bit(T_188734, 0)
    node rhsSigned = bit(T_188736, 0)
    node T_188737 = and(req.bits.dw, UInt<1>(1))
    node T_188738 = eq(UInt<1>(1), T_188737)
    node T_188739 = bit(req.bits.in1, 63)
    node T_188740 = bit(req.bits.in1, 31)
    wire T_188741 : UInt<1>
    T_188741 := T_188740
    when T_188738 : T_188741 := T_188739
    node lhs_sign = and(lhsSigned, T_188741)
    node T_188742 = and(req.bits.dw, UInt<1>(1))
    node T_188743 = eq(UInt<1>(1), T_188742)
    node T_188744 = bits(req.bits.in1, 63, 32)
    node T_188745 = subw(UInt<32>(0), UInt<6>(32))
    wire T_188746 : UInt<32>
    T_188746 := T_188745
    when T_188743 : T_188746 := T_188744
    node T_188747 = bits(req.bits.in1, 31, 0)
    node lhs_in = cat(T_188746, T_188747)
    node T_188748 = and(req.bits.dw, UInt<1>(1))
    node T_188749 = eq(UInt<1>(1), T_188748)
    node T_188750 = bit(req.bits.in2, 63)
    node T_188751 = bit(req.bits.in2, 31)
    wire T_188752 : UInt<1>
    T_188752 := T_188751
    when T_188749 : T_188752 := T_188750
    node rhs_sign = and(rhsSigned, T_188752)
    node T_188753 = and(req.bits.dw, UInt<1>(1))
    node T_188754 = eq(UInt<1>(1), T_188753)
    node T_188755 = bits(req.bits.in2, 63, 32)
    node T_188756 = subw(UInt<32>(0), UInt<6>(32))
    wire T_188757 : UInt<32>
    T_188757 := T_188756
    when T_188754 : T_188757 := T_188755
    node T_188758 = bits(req.bits.in2, 31, 0)
    node rhs_in = cat(T_188757, T_188758)
    node T_188759 = bits(remainder, 128, 64)
    node T_188760 = bits(divisor, 64, 0)
    node subtractor = subw(T_188759, T_188760)
    node less = bit(subtractor, 64)
    node T_188761 = bits(remainder, 63, 0)
    node negated_remainder = subw(UInt<1>(0), T_188761)
    
    node T_188762 = eq(state, UInt<3>(1))
    when T_188762 : 
      
      
      node T_188763 = bit(remainder, 63)
      node T_188764 = or(T_188763, isMul)
      when T_188764 : remainder := negated_remainder
      
      
      node T_188765 = bit(divisor, 63)
      node T_188766 = or(T_188765, isMul)
      when T_188766 : divisor := subtractor
      state := UInt<3>(2)
    
    node T_188767 = eq(state, UInt<3>(4))
    when T_188767 : 
      remainder := negated_remainder
      state := UInt<3>(5)
    
    node T_188768 = eq(state, UInt<3>(3))
    when T_188768 : 
      node T_188769 = bits(remainder, 128, 65)
      remainder := T_188769
      wire T_188770 : UInt<3>
      T_188770 := UInt<3>(5)
      when neg_out : T_188770 := UInt<3>(4)
      state := T_188770
    
    
    node T_188771 = eq(state, UInt<3>(2))
    node T_188772 = and(T_188771, isMul)
    when T_188772 : 
      node T_188773 = bits(remainder, 129, 65)
      node T_188774 = bits(remainder, 63, 0)
      node T_188775 = cat(T_188773, T_188774)
      node T_188776 = bits(T_188775, 63, 0)
      node T_188777 = bits(T_188775, 128, 64)
      node T_188778 = asSInt(T_188777)
      node T_188779 = asSInt(divisor)
      node T_188780 = bits(T_188776, 7, 0)
      node T_188781 = mul(T_188779, T_188780)
      node T_188782 = addw(T_188781, T_188778)
      node T_188783 = bits(T_188776, 63, 8)
      node T_188784 = asUInt(T_188782)
      node T_188785 = cat(T_188784, T_188783)
      node T_188786 = mul(count, UInt<4>(8))
      node T_188787 = bits(T_188786, 5, 0)
      node T_188788 = dshr(SInt<65>(-18446744073709551616), T_188787)
      node T_188789 = bits(T_188788, 63, 0)
      node T_188790 = neq(count, UInt<3>(7))
      node T_188791 = and(UInt<1>(1), T_188790)
      node T_188792 = neq(count, UInt<1>(0))
      node T_188793 = and(T_188791, T_188792)
      node T_188794 = eq(isHi, UInt<1>(0))
      node T_188795 = and(T_188793, T_188794)
      node T_188796 = not(T_188789)
      node T_188797 = and(T_188776, T_188796)
      node T_188798 = eq(T_188797, UInt<1>(0))
      node T_188799 = and(T_188795, T_188798)
      node T_188800 = mul(count, UInt<4>(8))
      node T_188801 = subw(UInt<7>(64), T_188800)
      node T_188802 = bits(T_188801, 5, 0)
      node T_188803 = dshr(T_188775, T_188802)
      node T_188804 = bits(T_188785, 128, 64)
      wire T_188805 : UInt<129>
      T_188805 := T_188785
      when T_188799 : T_188805 := T_188803
      node T_188806 = bits(T_188805, 63, 0)
      node T_188807 = cat(T_188804, T_188806)
      node T_188808 = shr(T_188807, 64)
      node T_188809 = bits(T_188807, 63, 0)
      node T_188810 = cat(UInt<1>(0), T_188809)
      node T_188811 = cat(T_188808, T_188810)
      node T_188812 = asSInt(T_188811)
      remainder := T_188812
      node T_188813 = addw(count, UInt<1>(1))
      count := T_188813
      
      
      node T_188814 = eq(count, UInt<3>(7))
      node T_188815 = or(T_188799, T_188814)
      when T_188815 : 
        wire T_188816 : UInt<3>
        T_188816 := UInt<3>(5)
        when isHi : T_188816 := UInt<3>(3)
        state := T_188816
    
    
    node T_188817 = eq(state, UInt<3>(2))
    node T_188818 = eq(isMul, UInt<1>(0))
    node T_188819 = and(T_188817, T_188818)
    when T_188819 : 
      
      node T_188820 = eq(count, UInt<7>(64))
      when T_188820 : 
        wire T_188821 : UInt<3>
        T_188821 := UInt<3>(5)
        when neg_out : T_188821 := UInt<3>(4)
        wire T_188822 : UInt<3>
        T_188822 := T_188821
        when isHi : T_188822 := UInt<3>(3)
        state := T_188822
      node T_188823 = addw(count, UInt<1>(1))
      count := T_188823
      node T_188824 = bits(remainder, 127, 64)
      node T_188825 = bits(subtractor, 63, 0)
      wire T_188826 : UInt<64>
      T_188826 := T_188825
      when less : T_188826 := T_188824
      node T_188827 = bits(remainder, 63, 0)
      node T_188828 = eq(less, UInt<1>(0))
      node T_188829 = cat(T_188827, T_188828)
      node T_188830 = cat(T_188826, T_188829)
      remainder := T_188830
      node T_188831 = bits(divisor, 63, 0)
      node T_188832 = bit(T_188831, 63)
      node T_188833 = bit(T_188831, 62)
      node T_188834 = bit(T_188831, 61)
      node T_188835 = bit(T_188831, 60)
      node T_188836 = bit(T_188831, 59)
      node T_188837 = bit(T_188831, 58)
      node T_188838 = bit(T_188831, 57)
      node T_188839 = bit(T_188831, 56)
      node T_188840 = bit(T_188831, 55)
      node T_188841 = bit(T_188831, 54)
      node T_188842 = bit(T_188831, 53)
      node T_188843 = bit(T_188831, 52)
      node T_188844 = bit(T_188831, 51)
      node T_188845 = bit(T_188831, 50)
      node T_188846 = bit(T_188831, 49)
      node T_188847 = bit(T_188831, 48)
      node T_188848 = bit(T_188831, 47)
      node T_188849 = bit(T_188831, 46)
      node T_188850 = bit(T_188831, 45)
      node T_188851 = bit(T_188831, 44)
      node T_188852 = bit(T_188831, 43)
      node T_188853 = bit(T_188831, 42)
      node T_188854 = bit(T_188831, 41)
      node T_188855 = bit(T_188831, 40)
      node T_188856 = bit(T_188831, 39)
      node T_188857 = bit(T_188831, 38)
      node T_188858 = bit(T_188831, 37)
      node T_188859 = bit(T_188831, 36)
      node T_188860 = bit(T_188831, 35)
      node T_188861 = bit(T_188831, 34)
      node T_188862 = bit(T_188831, 33)
      node T_188863 = bit(T_188831, 32)
      node T_188864 = bit(T_188831, 31)
      node T_188865 = bit(T_188831, 30)
      node T_188866 = bit(T_188831, 29)
      node T_188867 = bit(T_188831, 28)
      node T_188868 = bit(T_188831, 27)
      node T_188869 = bit(T_188831, 26)
      node T_188870 = bit(T_188831, 25)
      node T_188871 = bit(T_188831, 24)
      node T_188872 = bit(T_188831, 23)
      node T_188873 = bit(T_188831, 22)
      node T_188874 = bit(T_188831, 21)
      node T_188875 = bit(T_188831, 20)
      node T_188876 = bit(T_188831, 19)
      node T_188877 = bit(T_188831, 18)
      node T_188878 = bit(T_188831, 17)
      node T_188879 = bit(T_188831, 16)
      node T_188880 = bit(T_188831, 15)
      node T_188881 = bit(T_188831, 14)
      node T_188882 = bit(T_188831, 13)
      node T_188883 = bit(T_188831, 12)
      node T_188884 = bit(T_188831, 11)
      node T_188885 = bit(T_188831, 10)
      node T_188886 = bit(T_188831, 9)
      node T_188887 = bit(T_188831, 8)
      node T_188888 = bit(T_188831, 7)
      node T_188889 = bit(T_188831, 6)
      node T_188890 = bit(T_188831, 5)
      node T_188891 = bit(T_188831, 4)
      node T_188892 = bit(T_188831, 3)
      node T_188893 = bit(T_188831, 2)
      node T_188894 = bit(T_188831, 1)
      wire T_188895 : UInt<1>
      T_188895 := T_188894
      when T_188893 : T_188895 := UInt<2>(2)
      wire T_188896 : UInt<1>
      T_188896 := T_188895
      when T_188892 : T_188896 := UInt<2>(3)
      wire T_188897 : UInt<1>
      T_188897 := T_188896
      when T_188891 : T_188897 := UInt<3>(4)
      wire T_188898 : UInt<1>
      T_188898 := T_188897
      when T_188890 : T_188898 := UInt<3>(5)
      wire T_188899 : UInt<1>
      T_188899 := T_188898
      when T_188889 : T_188899 := UInt<3>(6)
      wire T_188900 : UInt<1>
      T_188900 := T_188899
      when T_188888 : T_188900 := UInt<3>(7)
      wire T_188901 : UInt<1>
      T_188901 := T_188900
      when T_188887 : T_188901 := UInt<4>(8)
      wire T_188902 : UInt<1>
      T_188902 := T_188901
      when T_188886 : T_188902 := UInt<4>(9)
      wire T_188903 : UInt<1>
      T_188903 := T_188902
      when T_188885 : T_188903 := UInt<4>(10)
      wire T_188904 : UInt<1>
      T_188904 := T_188903
      when T_188884 : T_188904 := UInt<4>(11)
      wire T_188905 : UInt<1>
      T_188905 := T_188904
      when T_188883 : T_188905 := UInt<4>(12)
      wire T_188906 : UInt<1>
      T_188906 := T_188905
      when T_188882 : T_188906 := UInt<4>(13)
      wire T_188907 : UInt<1>
      T_188907 := T_188906
      when T_188881 : T_188907 := UInt<4>(14)
      wire T_188908 : UInt<1>
      T_188908 := T_188907
      when T_188880 : T_188908 := UInt<4>(15)
      wire T_188909 : UInt<1>
      T_188909 := T_188908
      when T_188879 : T_188909 := UInt<5>(16)
      wire T_188910 : UInt<1>
      T_188910 := T_188909
      when T_188878 : T_188910 := UInt<5>(17)
      wire T_188911 : UInt<1>
      T_188911 := T_188910
      when T_188877 : T_188911 := UInt<5>(18)
      wire T_188912 : UInt<1>
      T_188912 := T_188911
      when T_188876 : T_188912 := UInt<5>(19)
      wire T_188913 : UInt<1>
      T_188913 := T_188912
      when T_188875 : T_188913 := UInt<5>(20)
      wire T_188914 : UInt<1>
      T_188914 := T_188913
      when T_188874 : T_188914 := UInt<5>(21)
      wire T_188915 : UInt<1>
      T_188915 := T_188914
      when T_188873 : T_188915 := UInt<5>(22)
      wire T_188916 : UInt<1>
      T_188916 := T_188915
      when T_188872 : T_188916 := UInt<5>(23)
      wire T_188917 : UInt<1>
      T_188917 := T_188916
      when T_188871 : T_188917 := UInt<5>(24)
      wire T_188918 : UInt<1>
      T_188918 := T_188917
      when T_188870 : T_188918 := UInt<5>(25)
      wire T_188919 : UInt<1>
      T_188919 := T_188918
      when T_188869 : T_188919 := UInt<5>(26)
      wire T_188920 : UInt<1>
      T_188920 := T_188919
      when T_188868 : T_188920 := UInt<5>(27)
      wire T_188921 : UInt<1>
      T_188921 := T_188920
      when T_188867 : T_188921 := UInt<5>(28)
      wire T_188922 : UInt<1>
      T_188922 := T_188921
      when T_188866 : T_188922 := UInt<5>(29)
      wire T_188923 : UInt<1>
      T_188923 := T_188922
      when T_188865 : T_188923 := UInt<5>(30)
      wire T_188924 : UInt<1>
      T_188924 := T_188923
      when T_188864 : T_188924 := UInt<5>(31)
      wire T_188925 : UInt<1>
      T_188925 := T_188924
      when T_188863 : T_188925 := UInt<6>(32)
      wire T_188926 : UInt<1>
      T_188926 := T_188925
      when T_188862 : T_188926 := UInt<6>(33)
      wire T_188927 : UInt<1>
      T_188927 := T_188926
      when T_188861 : T_188927 := UInt<6>(34)
      wire T_188928 : UInt<1>
      T_188928 := T_188927
      when T_188860 : T_188928 := UInt<6>(35)
      wire T_188929 : UInt<1>
      T_188929 := T_188928
      when T_188859 : T_188929 := UInt<6>(36)
      wire T_188930 : UInt<1>
      T_188930 := T_188929
      when T_188858 : T_188930 := UInt<6>(37)
      wire T_188931 : UInt<1>
      T_188931 := T_188930
      when T_188857 : T_188931 := UInt<6>(38)
      wire T_188932 : UInt<1>
      T_188932 := T_188931
      when T_188856 : T_188932 := UInt<6>(39)
      wire T_188933 : UInt<1>
      T_188933 := T_188932
      when T_188855 : T_188933 := UInt<6>(40)
      wire T_188934 : UInt<1>
      T_188934 := T_188933
      when T_188854 : T_188934 := UInt<6>(41)
      wire T_188935 : UInt<1>
      T_188935 := T_188934
      when T_188853 : T_188935 := UInt<6>(42)
      wire T_188936 : UInt<1>
      T_188936 := T_188935
      when T_188852 : T_188936 := UInt<6>(43)
      wire T_188937 : UInt<1>
      T_188937 := T_188936
      when T_188851 : T_188937 := UInt<6>(44)
      wire T_188938 : UInt<1>
      T_188938 := T_188937
      when T_188850 : T_188938 := UInt<6>(45)
      wire T_188939 : UInt<1>
      T_188939 := T_188938
      when T_188849 : T_188939 := UInt<6>(46)
      wire T_188940 : UInt<1>
      T_188940 := T_188939
      when T_188848 : T_188940 := UInt<6>(47)
      wire T_188941 : UInt<1>
      T_188941 := T_188940
      when T_188847 : T_188941 := UInt<6>(48)
      wire T_188942 : UInt<1>
      T_188942 := T_188941
      when T_188846 : T_188942 := UInt<6>(49)
      wire T_188943 : UInt<1>
      T_188943 := T_188942
      when T_188845 : T_188943 := UInt<6>(50)
      wire T_188944 : UInt<1>
      T_188944 := T_188943
      when T_188844 : T_188944 := UInt<6>(51)
      wire T_188945 : UInt<1>
      T_188945 := T_188944
      when T_188843 : T_188945 := UInt<6>(52)
      wire T_188946 : UInt<1>
      T_188946 := T_188945
      when T_188842 : T_188946 := UInt<6>(53)
      wire T_188947 : UInt<1>
      T_188947 := T_188946
      when T_188841 : T_188947 := UInt<6>(54)
      wire T_188948 : UInt<1>
      T_188948 := T_188947
      when T_188840 : T_188948 := UInt<6>(55)
      wire T_188949 : UInt<1>
      T_188949 := T_188948
      when T_188839 : T_188949 := UInt<6>(56)
      wire T_188950 : UInt<1>
      T_188950 := T_188949
      when T_188838 : T_188950 := UInt<6>(57)
      wire T_188951 : UInt<1>
      T_188951 := T_188950
      when T_188837 : T_188951 := UInt<6>(58)
      wire T_188952 : UInt<1>
      T_188952 := T_188951
      when T_188836 : T_188952 := UInt<6>(59)
      wire T_188953 : UInt<1>
      T_188953 := T_188952
      when T_188835 : T_188953 := UInt<6>(60)
      wire T_188954 : UInt<1>
      T_188954 := T_188953
      when T_188834 : T_188954 := UInt<6>(61)
      wire T_188955 : UInt<1>
      T_188955 := T_188954
      when T_188833 : T_188955 := UInt<6>(62)
      wire T_188956 : UInt<1>
      T_188956 := T_188955
      when T_188832 : T_188956 := UInt<6>(63)
      node T_188957 = bits(remainder, 63, 0)
      node T_188958 = bit(T_188957, 63)
      node T_188959 = bit(T_188957, 62)
      node T_188960 = bit(T_188957, 61)
      node T_188961 = bit(T_188957, 60)
      node T_188962 = bit(T_188957, 59)
      node T_188963 = bit(T_188957, 58)
      node T_188964 = bit(T_188957, 57)
      node T_188965 = bit(T_188957, 56)
      node T_188966 = bit(T_188957, 55)
      node T_188967 = bit(T_188957, 54)
      node T_188968 = bit(T_188957, 53)
      node T_188969 = bit(T_188957, 52)
      node T_188970 = bit(T_188957, 51)
      node T_188971 = bit(T_188957, 50)
      node T_188972 = bit(T_188957, 49)
      node T_188973 = bit(T_188957, 48)
      node T_188974 = bit(T_188957, 47)
      node T_188975 = bit(T_188957, 46)
      node T_188976 = bit(T_188957, 45)
      node T_188977 = bit(T_188957, 44)
      node T_188978 = bit(T_188957, 43)
      node T_188979 = bit(T_188957, 42)
      node T_188980 = bit(T_188957, 41)
      node T_188981 = bit(T_188957, 40)
      node T_188982 = bit(T_188957, 39)
      node T_188983 = bit(T_188957, 38)
      node T_188984 = bit(T_188957, 37)
      node T_188985 = bit(T_188957, 36)
      node T_188986 = bit(T_188957, 35)
      node T_188987 = bit(T_188957, 34)
      node T_188988 = bit(T_188957, 33)
      node T_188989 = bit(T_188957, 32)
      node T_188990 = bit(T_188957, 31)
      node T_188991 = bit(T_188957, 30)
      node T_188992 = bit(T_188957, 29)
      node T_188993 = bit(T_188957, 28)
      node T_188994 = bit(T_188957, 27)
      node T_188995 = bit(T_188957, 26)
      node T_188996 = bit(T_188957, 25)
      node T_188997 = bit(T_188957, 24)
      node T_188998 = bit(T_188957, 23)
      node T_188999 = bit(T_188957, 22)
      node T_189000 = bit(T_188957, 21)
      node T_189001 = bit(T_188957, 20)
      node T_189002 = bit(T_188957, 19)
      node T_189003 = bit(T_188957, 18)
      node T_189004 = bit(T_188957, 17)
      node T_189005 = bit(T_188957, 16)
      node T_189006 = bit(T_188957, 15)
      node T_189007 = bit(T_188957, 14)
      node T_189008 = bit(T_188957, 13)
      node T_189009 = bit(T_188957, 12)
      node T_189010 = bit(T_188957, 11)
      node T_189011 = bit(T_188957, 10)
      node T_189012 = bit(T_188957, 9)
      node T_189013 = bit(T_188957, 8)
      node T_189014 = bit(T_188957, 7)
      node T_189015 = bit(T_188957, 6)
      node T_189016 = bit(T_188957, 5)
      node T_189017 = bit(T_188957, 4)
      node T_189018 = bit(T_188957, 3)
      node T_189019 = bit(T_188957, 2)
      node T_189020 = bit(T_188957, 1)
      wire T_189021 : UInt<1>
      T_189021 := T_189020
      when T_189019 : T_189021 := UInt<2>(2)
      wire T_189022 : UInt<1>
      T_189022 := T_189021
      when T_189018 : T_189022 := UInt<2>(3)
      wire T_189023 : UInt<1>
      T_189023 := T_189022
      when T_189017 : T_189023 := UInt<3>(4)
      wire T_189024 : UInt<1>
      T_189024 := T_189023
      when T_189016 : T_189024 := UInt<3>(5)
      wire T_189025 : UInt<1>
      T_189025 := T_189024
      when T_189015 : T_189025 := UInt<3>(6)
      wire T_189026 : UInt<1>
      T_189026 := T_189025
      when T_189014 : T_189026 := UInt<3>(7)
      wire T_189027 : UInt<1>
      T_189027 := T_189026
      when T_189013 : T_189027 := UInt<4>(8)
      wire T_189028 : UInt<1>
      T_189028 := T_189027
      when T_189012 : T_189028 := UInt<4>(9)
      wire T_189029 : UInt<1>
      T_189029 := T_189028
      when T_189011 : T_189029 := UInt<4>(10)
      wire T_189030 : UInt<1>
      T_189030 := T_189029
      when T_189010 : T_189030 := UInt<4>(11)
      wire T_189031 : UInt<1>
      T_189031 := T_189030
      when T_189009 : T_189031 := UInt<4>(12)
      wire T_189032 : UInt<1>
      T_189032 := T_189031
      when T_189008 : T_189032 := UInt<4>(13)
      wire T_189033 : UInt<1>
      T_189033 := T_189032
      when T_189007 : T_189033 := UInt<4>(14)
      wire T_189034 : UInt<1>
      T_189034 := T_189033
      when T_189006 : T_189034 := UInt<4>(15)
      wire T_189035 : UInt<1>
      T_189035 := T_189034
      when T_189005 : T_189035 := UInt<5>(16)
      wire T_189036 : UInt<1>
      T_189036 := T_189035
      when T_189004 : T_189036 := UInt<5>(17)
      wire T_189037 : UInt<1>
      T_189037 := T_189036
      when T_189003 : T_189037 := UInt<5>(18)
      wire T_189038 : UInt<1>
      T_189038 := T_189037
      when T_189002 : T_189038 := UInt<5>(19)
      wire T_189039 : UInt<1>
      T_189039 := T_189038
      when T_189001 : T_189039 := UInt<5>(20)
      wire T_189040 : UInt<1>
      T_189040 := T_189039
      when T_189000 : T_189040 := UInt<5>(21)
      wire T_189041 : UInt<1>
      T_189041 := T_189040
      when T_188999 : T_189041 := UInt<5>(22)
      wire T_189042 : UInt<1>
      T_189042 := T_189041
      when T_188998 : T_189042 := UInt<5>(23)
      wire T_189043 : UInt<1>
      T_189043 := T_189042
      when T_188997 : T_189043 := UInt<5>(24)
      wire T_189044 : UInt<1>
      T_189044 := T_189043
      when T_188996 : T_189044 := UInt<5>(25)
      wire T_189045 : UInt<1>
      T_189045 := T_189044
      when T_188995 : T_189045 := UInt<5>(26)
      wire T_189046 : UInt<1>
      T_189046 := T_189045
      when T_188994 : T_189046 := UInt<5>(27)
      wire T_189047 : UInt<1>
      T_189047 := T_189046
      when T_188993 : T_189047 := UInt<5>(28)
      wire T_189048 : UInt<1>
      T_189048 := T_189047
      when T_188992 : T_189048 := UInt<5>(29)
      wire T_189049 : UInt<1>
      T_189049 := T_189048
      when T_188991 : T_189049 := UInt<5>(30)
      wire T_189050 : UInt<1>
      T_189050 := T_189049
      when T_188990 : T_189050 := UInt<5>(31)
      wire T_189051 : UInt<1>
      T_189051 := T_189050
      when T_188989 : T_189051 := UInt<6>(32)
      wire T_189052 : UInt<1>
      T_189052 := T_189051
      when T_188988 : T_189052 := UInt<6>(33)
      wire T_189053 : UInt<1>
      T_189053 := T_189052
      when T_188987 : T_189053 := UInt<6>(34)
      wire T_189054 : UInt<1>
      T_189054 := T_189053
      when T_188986 : T_189054 := UInt<6>(35)
      wire T_189055 : UInt<1>
      T_189055 := T_189054
      when T_188985 : T_189055 := UInt<6>(36)
      wire T_189056 : UInt<1>
      T_189056 := T_189055
      when T_188984 : T_189056 := UInt<6>(37)
      wire T_189057 : UInt<1>
      T_189057 := T_189056
      when T_188983 : T_189057 := UInt<6>(38)
      wire T_189058 : UInt<1>
      T_189058 := T_189057
      when T_188982 : T_189058 := UInt<6>(39)
      wire T_189059 : UInt<1>
      T_189059 := T_189058
      when T_188981 : T_189059 := UInt<6>(40)
      wire T_189060 : UInt<1>
      T_189060 := T_189059
      when T_188980 : T_189060 := UInt<6>(41)
      wire T_189061 : UInt<1>
      T_189061 := T_189060
      when T_188979 : T_189061 := UInt<6>(42)
      wire T_189062 : UInt<1>
      T_189062 := T_189061
      when T_188978 : T_189062 := UInt<6>(43)
      wire T_189063 : UInt<1>
      T_189063 := T_189062
      when T_188977 : T_189063 := UInt<6>(44)
      wire T_189064 : UInt<1>
      T_189064 := T_189063
      when T_188976 : T_189064 := UInt<6>(45)
      wire T_189065 : UInt<1>
      T_189065 := T_189064
      when T_188975 : T_189065 := UInt<6>(46)
      wire T_189066 : UInt<1>
      T_189066 := T_189065
      when T_188974 : T_189066 := UInt<6>(47)
      wire T_189067 : UInt<1>
      T_189067 := T_189066
      when T_188973 : T_189067 := UInt<6>(48)
      wire T_189068 : UInt<1>
      T_189068 := T_189067
      when T_188972 : T_189068 := UInt<6>(49)
      wire T_189069 : UInt<1>
      T_189069 := T_189068
      when T_188971 : T_189069 := UInt<6>(50)
      wire T_189070 : UInt<1>
      T_189070 := T_189069
      when T_188970 : T_189070 := UInt<6>(51)
      wire T_189071 : UInt<1>
      T_189071 := T_189070
      when T_188969 : T_189071 := UInt<6>(52)
      wire T_189072 : UInt<1>
      T_189072 := T_189071
      when T_188968 : T_189072 := UInt<6>(53)
      wire T_189073 : UInt<1>
      T_189073 := T_189072
      when T_188967 : T_189073 := UInt<6>(54)
      wire T_189074 : UInt<1>
      T_189074 := T_189073
      when T_188966 : T_189074 := UInt<6>(55)
      wire T_189075 : UInt<1>
      T_189075 := T_189074
      when T_188965 : T_189075 := UInt<6>(56)
      wire T_189076 : UInt<1>
      T_189076 := T_189075
      when T_188964 : T_189076 := UInt<6>(57)
      wire T_189077 : UInt<1>
      T_189077 := T_189076
      when T_188963 : T_189077 := UInt<6>(58)
      wire T_189078 : UInt<1>
      T_189078 := T_189077
      when T_188962 : T_189078 := UInt<6>(59)
      wire T_189079 : UInt<1>
      T_189079 := T_189078
      when T_188961 : T_189079 := UInt<6>(60)
      wire T_189080 : UInt<1>
      T_189080 := T_189079
      when T_188960 : T_189080 := UInt<6>(61)
      wire T_189081 : UInt<1>
      T_189081 := T_189080
      when T_188959 : T_189081 := UInt<6>(62)
      wire T_189082 : UInt<1>
      T_189082 := T_189081
      when T_188958 : T_189082 := UInt<6>(63)
      node T_189083 = addw(UInt<6>(63), T_188956)
      node T_189084 = subw(T_189083, T_189082)
      node T_189085 = gt(T_188956, T_189082)
      node T_189086 = eq(count, UInt<1>(0))
      node T_189087 = and(T_189086, less)
      node T_189088 = gt(T_189084, UInt<1>(0))
      node T_189089 = or(T_189088, T_189085)
      node T_189090 = and(T_189087, T_189089)
      
      node T_189091 = and(UInt<1>(1), T_189090)
      when T_189091 : 
        node T_189092 = bits(T_189084, 5, 0)
        wire T_189093 : UInt<6>
        T_189093 := T_189092
        when T_189085 : T_189093 := UInt<6>(63)
        node T_189094 = bits(remainder, 63, 0)
        node T_189095 = dshl(T_189094, T_189093)
        remainder := T_189095
        count := T_189093
      
      
      node T_189096 = eq(count, UInt<1>(0))
      node T_189097 = eq(less, UInt<1>(0))
      node T_189098 = and(T_189096, T_189097)
      node T_189099 = eq(isHi, UInt<1>(0))
      node T_189100 = and(T_189098, T_189099)
      when T_189100 : neg_out := UInt<1>(0)
    
    
    node T_189101 = and(resp.ready, resp.valid)
    node T_189102 = or(T_189101, kill)
    when T_189102 : state := UInt<3>(0)
    
    node T_189103 = and(req.ready, req.valid)
    when T_189103 : 
      node T_189104 = eq(cmdMul, UInt<1>(0))
      node T_189105 = and(rhs_sign, T_189104)
      node T_189106 = or(lhs_sign, T_189105)
      wire T_189107 : UInt<3>
      T_189107 := UInt<3>(2)
      when T_189106 : T_189107 := UInt<3>(1)
      state := T_189107
      isMul := cmdMul
      isHi := cmdHi
      count := UInt<1>(0)
      node T_189108 = eq(cmdMul, UInt<1>(0))
      node T_189109 = neq(lhs_sign, rhs_sign)
      wire T_189110 : UInt<1>
      T_189110 := T_189109
      when cmdHi : T_189110 := lhs_sign
      node T_189111 = and(T_189108, T_189110)
      neg_out := T_189111
      node T_189112 = cat(rhs_sign, rhs_in)
      divisor := T_189112
      remainder := lhs_in
      req := req.bits
    resp.bits := req
    node T_189113 = and(req.dw, UInt<1>(1))
    node T_189114 = eq(UInt<1>(0), T_189113)
    node T_189115 = bit(remainder, 31)
    node T_189116 = subw(UInt<32>(0), UInt<6>(32))
    node T_189117 = bits(remainder, 31, 0)
    node T_189118 = cat(T_189116, T_189117)
    node T_189119 = bits(remainder, 63, 0)
    wire T_189120 : UInt<64>
    T_189120 := T_189119
    when T_189114 : T_189120 := T_189118
    resp.bits.data := T_189120
    node T_189121 = eq(state, UInt<3>(5))
    resp.valid := T_189121
    node T_189122 = eq(state, UInt<3>(0))
    req.ready := T_189122
  module Rocket : 
    output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}
    output imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}
    output dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}
    input ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}
    input fpu : {flip inst__ : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>}
    input rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst__ : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem__ : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, imem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, dmem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}, iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, flip exception : UInt<1>}
    
    wire data : UInt<32>[1]
    T_189123.data[0] := T_189124
    wire data : UInt<32>[1]
    imem.resp.bits.data[0] := T_189125
    wire T_189126 : UInt<3>[3]
    T_189126[0] := UInt<3>(0)
    T_189126[1] := UInt<3>(1)
    T_189126[2] := UInt<3>(2)
    wire T_189127 : UInt<2>[2]
    T_189127[0] := UInt<2>(0)
    T_189127[1] := UInt<2>(1)
    wire T_189128 : UInt<2>[3]
    T_189128[0] := UInt<2>(1)
    T_189128[1] := UInt<2>(2)
    T_189128[2] := UInt<2>(3)
    wire T_189129 : UInt<2>[2]
    T_189129[0] := UInt<2>(2)
    T_189129[1] := UInt<2>(3)
    wire T_189130 : UInt<2>[1]
    T_189130[0] := UInt<2>(3)
    wire T_189131 : UInt<3>[3]
    T_189131[0] := UInt<3>(0)
    T_189131[1] := UInt<3>(1)
    T_189131[2] := UInt<3>(2)
    wire T_189132 : UInt<2>[2]
    T_189132[0] := UInt<2>(0)
    T_189132[1] := UInt<2>(1)
    wire T_189133 : UInt<2>[3]
    T_189133[0] := UInt<2>(1)
    T_189133[1] := UInt<2>(2)
    T_189133[2] := UInt<2>(3)
    wire T_189134 : UInt<2>[2]
    T_189134[0] := UInt<2>(2)
    T_189134[1] := UInt<2>(3)
    wire T_189135 : UInt<2>[1]
    T_189135[0] := UInt<2>(3)
    wire T_189136 : UInt<3>[3]
    T_189136[0] := UInt<3>(0)
    T_189136[1] := UInt<3>(1)
    T_189136[2] := UInt<3>(2)
    wire T_189137 : UInt<2>[2]
    T_189137[0] := UInt<2>(0)
    T_189137[1] := UInt<2>(1)
    wire T_189138 : UInt<2>[3]
    T_189138[0] := UInt<2>(1)
    T_189138[1] := UInt<2>(2)
    T_189138[2] := UInt<2>(3)
    wire T_189139 : UInt<2>[2]
    T_189139[0] := UInt<2>(2)
    T_189139[1] := UInt<2>(3)
    wire T_189140 : UInt<2>[1]
    T_189140[0] := UInt<2>(3)
    wire T_189141 : UInt<3>[3]
    T_189141[0] := UInt<3>(0)
    T_189141[1] := UInt<3>(1)
    T_189141[2] := UInt<3>(2)
    wire T_189142 : UInt<2>[2]
    T_189142[0] := UInt<2>(0)
    T_189142[1] := UInt<2>(1)
    wire T_189143 : UInt<2>[3]
    T_189143[0] := UInt<2>(1)
    T_189143[1] := UInt<2>(2)
    T_189143[2] := UInt<2>(3)
    wire T_189144 : UInt<2>[2]
    T_189144[0] := UInt<2>(2)
    T_189144[1] := UInt<2>(3)
    wire T_189145 : UInt<2>[1]
    T_189145[0] := UInt<2>(3)
    wire T_189146 : UInt<3>[3]
    T_189146[0] := UInt<3>(0)
    T_189146[1] := UInt<3>(1)
    T_189146[2] := UInt<3>(2)
    wire T_189147 : UInt<2>[2]
    T_189147[0] := UInt<2>(0)
    T_189147[1] := UInt<2>(1)
    wire T_189148 : UInt<2>[3]
    T_189148[0] := UInt<2>(1)
    T_189148[1] := UInt<2>(2)
    T_189148[2] := UInt<2>(3)
    wire T_189149 : UInt<2>[2]
    T_189149[0] := UInt<2>(2)
    T_189149[1] := UInt<2>(3)
    wire T_189150 : UInt<2>[1]
    T_189150[0] := UInt<2>(3)
    wire T_189151 : UInt<3>[3]
    T_189151[0] := UInt<3>(0)
    T_189151[1] := UInt<3>(1)
    T_189151[2] := UInt<3>(2)
    wire T_189152 : UInt<2>[2]
    T_189152[0] := UInt<2>(0)
    T_189152[1] := UInt<2>(1)
    wire T_189153 : UInt<2>[3]
    T_189153[0] := UInt<2>(1)
    T_189153[1] := UInt<2>(2)
    T_189153[2] := UInt<2>(3)
    wire T_189154 : UInt<2>[2]
    T_189154[0] := UInt<2>(2)
    T_189154[1] := UInt<2>(3)
    wire T_189155 : UInt<2>[1]
    T_189155[0] := UInt<2>(3)
    wire T_189156 : UInt<3>[3]
    T_189156[0] := UInt<3>(0)
    T_189156[1] := UInt<3>(1)
    T_189156[2] := UInt<3>(2)
    wire T_189157 : UInt<2>[2]
    T_189157[0] := UInt<2>(0)
    T_189157[1] := UInt<2>(1)
    wire T_189158 : UInt<2>[3]
    T_189158[0] := UInt<2>(1)
    T_189158[1] := UInt<2>(2)
    T_189158[2] := UInt<2>(3)
    wire T_189159 : UInt<2>[2]
    T_189159[0] := UInt<2>(2)
    T_189159[1] := UInt<2>(3)
    wire T_189160 : UInt<2>[1]
    T_189160[0] := UInt<2>(3)
    wire T_189161 : UInt<3>[3]
    T_189161[0] := UInt<3>(0)
    T_189161[1] := UInt<3>(1)
    T_189161[2] := UInt<3>(2)
    wire T_189162 : UInt<2>[2]
    T_189162[0] := UInt<2>(0)
    T_189162[1] := UInt<2>(1)
    wire T_189163 : UInt<2>[3]
    T_189163[0] := UInt<2>(1)
    T_189163[1] := UInt<2>(2)
    T_189163[2] := UInt<2>(3)
    wire T_189164 : UInt<2>[2]
    T_189164[0] := UInt<2>(2)
    T_189164[1] := UInt<2>(3)
    wire T_189165 : UInt<2>[1]
    T_189165[0] := UInt<2>(3)
    wire T_189166 : UInt<3>[3]
    T_189166[0] := UInt<3>(0)
    T_189166[1] := UInt<3>(1)
    T_189166[2] := UInt<3>(2)
    wire T_189167 : UInt<2>[2]
    T_189167[0] := UInt<2>(0)
    T_189167[1] := UInt<2>(1)
    wire T_189168 : UInt<2>[3]
    T_189168[0] := UInt<2>(1)
    T_189168[1] := UInt<2>(2)
    T_189168[2] := UInt<2>(3)
    wire T_189169 : UInt<2>[2]
    T_189169[0] := UInt<2>(2)
    T_189169[1] := UInt<2>(3)
    wire T_189170 : UInt<2>[1]
    T_189170[0] := UInt<2>(3)
    wire T_189171 : UInt<3>[3]
    T_189171[0] := UInt<3>(0)
    T_189171[1] := UInt<3>(1)
    T_189171[2] := UInt<3>(2)
    wire T_189172 : UInt<2>[2]
    T_189172[0] := UInt<2>(0)
    T_189172[1] := UInt<2>(1)
    wire T_189173 : UInt<2>[3]
    T_189173[0] := UInt<2>(1)
    T_189173[1] := UInt<2>(2)
    T_189173[2] := UInt<2>(3)
    wire T_189174 : UInt<2>[2]
    T_189174[0] := UInt<2>(2)
    T_189174[1] := UInt<2>(3)
    wire T_189175 : UInt<2>[1]
    T_189175[0] := UInt<2>(3)
    reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem__ : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}
    reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem__ : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}
    reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem__ : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}
    reg ex_reg_xcpt_interrupt : UInt<1>
    reg ex_reg_valid : UInt<1>
    reg ex_reg_btb_hit : UInt<1>
    reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}
    reg ex_reg_xcpt : UInt<1>
    reg ex_reg_flush_pipe : UInt<1>
    reg ex_reg_load_use : UInt<1>
    reg ex_reg_cause : UInt
    reg ex_reg_pc : UInt
    reg ex_reg_inst : UInt
    reg mem_reg_xcpt_interrupt : UInt<1>
    reg mem_reg_valid : UInt<1>
    reg mem_reg_btb_hit : UInt<1>
    reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}
    reg mem_reg_xcpt : UInt<1>
    reg mem_reg_replay : UInt<1>
    reg mem_reg_flush_pipe : UInt<1>
    reg mem_reg_cause : UInt
    reg mem_reg_slow_bypass : UInt<1>
    reg mem_reg_pc : UInt
    reg mem_reg_inst : UInt
    reg mem_reg_wdata : UInt
    reg mem_reg_rs2 : UInt
    wire take_pc_mem : UInt<1>
    reg wb_reg_valid : UInt<1>
    reg wb_reg_xcpt : UInt<1>
    reg wb_reg_replay : UInt<1>
    reg wb_reg_cause : UInt
    reg wb_reg_rocc_pending : UInt<1>
    onreset wb_reg_rocc_pending := UInt<1>(0)
    reg wb_reg_pc : UInt
    reg wb_reg_inst : UInt
    reg wb_reg_wdata : UInt
    reg wb_reg_rs2 : UInt
    wire take_pc_wb : UInt<1>
    node take_pc_mem_wb = or(take_pc_wb, take_pc_mem)
    wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem__ : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}
    node T_189176 = and(imem.resp.bits.data[0], UInt<32>(8319))
    node T_189177 = eq(T_189176, UInt<32>(3))
    node T_189178 = and(imem.resp.bits.data[0], UInt<32>(4207))
    node T_189179 = eq(T_189178, UInt<32>(3))
    node T_189180 = and(imem.resp.bits.data[0], UInt<32>(24703))
    node T_189181 = eq(T_189180, UInt<32>(15))
    node T_189182 = and(imem.resp.bits.data[0], UInt<32>(28791))
    node T_189183 = eq(T_189182, UInt<32>(19))
    node T_189184 = and(imem.resp.bits.data[0], UInt<32>(95))
    node T_189185 = eq(T_189184, UInt<32>(23))
    node T_189186 = and(imem.resp.bits.data[0], UInt<32>(4227858559))
    node T_189187 = eq(T_189186, UInt<32>(51))
    node T_189188 = and(imem.resp.bits.data[0], UInt<32>(3187699831))
    node T_189189 = eq(T_189188, UInt<32>(51))
    node T_189190 = and(imem.resp.bits.data[0], UInt<32>(67108979))
    node T_189191 = eq(T_189190, UInt<32>(67))
    node T_189192 = and(imem.resp.bits.data[0], UInt<32>(3825205375))
    node T_189193 = eq(T_189192, UInt<32>(83))
    node T_189194 = and(imem.resp.bits.data[0], UInt<32>(28795))
    node T_189195 = eq(T_189194, UInt<32>(99))
    node T_189196 = and(imem.resp.bits.data[0], UInt<32>(127))
    node T_189197 = eq(T_189196, UInt<32>(111))
    node T_189198 = and(imem.resp.bits.data[0], UInt<32>(4293918719))
    node T_189199 = eq(T_189198, UInt<32>(115))
    node T_189200 = and(imem.resp.bits.data[0], UInt<32>(4227870815))
    node T_189201 = eq(T_189200, UInt<32>(4115))
    node T_189202 = and(imem.resp.bits.data[0], UInt<32>(4261425247))
    node T_189203 = eq(T_189202, UInt<32>(4123))
    node T_189204 = and(imem.resp.bits.data[0], UInt<32>(24667))
    node T_189205 = eq(T_189204, UInt<32>(8195))
    node T_189206 = and(imem.resp.bits.data[0], UInt<32>(8319))
    node T_189207 = eq(T_189206, UInt<32>(8211))
    node T_189208 = and(imem.resp.bits.data[0], UInt<32>(402677887))
    node T_189209 = eq(T_189208, UInt<32>(8239))
    node T_189210 = and(imem.resp.bits.data[0], UInt<32>(8319))
    node T_189211 = eq(T_189210, UInt<32>(8307))
    node T_189212 = and(imem.resp.bits.data[0], UInt<32>(3154145407))
    node T_189213 = eq(T_189212, UInt<32>(20499))
    node T_189214 = and(imem.resp.bits.data[0], UInt<32>(3187699807))
    node T_189215 = eq(T_189214, UInt<32>(20507))
    node T_189216 = and(imem.resp.bits.data[0], UInt<32>(3187699831))
    node T_189217 = eq(T_189216, UInt<32>(20531))
    node T_189218 = and(imem.resp.bits.data[0], UInt<32>(4261429367))
    node T_189219 = eq(T_189218, UInt<32>(33570867))
    node T_189220 = and(imem.resp.bits.data[0], UInt<32>(3892338815))
    node T_189221 = eq(T_189220, UInt<32>(134225967))
    node T_189222 = and(imem.resp.bits.data[0], UInt<32>(4292870143))
    node T_189223 = eq(T_189222, UInt<32>(268435571))
    node T_189224 = and(imem.resp.bits.data[0], UInt<32>(4193280127))
    node T_189225 = eq(T_189224, UInt<32>(268443695))
    node T_189226 = and(imem.resp.bits.data[0], UInt<32>(4293951487))
    node T_189227 = eq(T_189226, UInt<32>(269484147))
    node T_189228 = and(imem.resp.bits.data[0], UInt<32>(4093665407))
    node T_189229 = eq(T_189228, UInt<32>(536870995))
    node T_189230 = and(imem.resp.bits.data[0], UInt<32>(2080399487))
    node T_189231 = eq(T_189230, UInt<32>(536870995))
    node T_189232 = and(imem.resp.bits.data[0], UInt<32>(2080395391))
    node T_189233 = eq(T_189232, UInt<32>(536870995))
    node T_189234 = eq(imem.resp.bits.data[0], UInt<32>(810549363))
    node T_189235 = and(imem.resp.bits.data[0], UInt<32>(2146435199))
    node T_189236 = eq(T_189235, UInt<32>(1074790483))
    node T_189237 = and(imem.resp.bits.data[0], UInt<32>(2146435199))
    node T_189238 = eq(T_189237, UInt<32>(1107296339))
    node T_189239 = and(imem.resp.bits.data[0], UInt<32>(4260364415))
    node T_189240 = eq(T_189239, UInt<32>(1476395091))
    node T_189241 = and(imem.resp.bits.data[0], UInt<32>(3988783231))
    node T_189242 = eq(T_189241, UInt<32>(3221225555))
    node T_189243 = and(imem.resp.bits.data[0], UInt<32>(4260388991))
    node T_189244 = eq(T_189243, UInt<32>(3758096467))
    node T_189245 = and(imem.resp.bits.data[0], UInt<32>(3991957631))
    node T_189246 = eq(T_189245, UInt<32>(3758096467))
    node T_189247 = and(imem.resp.bits.data[0], UInt<32>(24639))
    node T_189248 = eq(T_189247, UInt<32>(35))
    node T_189249 = and(imem.resp.bits.data[0], UInt<32>(12399))
    node T_189250 = eq(T_189249, UInt<32>(4195))
    node T_189251 = and(imem.resp.bits.data[0], UInt<32>(16511))
    node T_189252 = eq(T_189251, UInt<32>(16483))
    node T_189253 = and(imem.resp.bits.data[0], UInt<32>(4227887223))
    node T_189254 = eq(T_189253, UInt<32>(51))
    node T_189255 = or(UInt<1>(0), T_189177)
    node T_189256 = or(T_189255, T_189179)
    node T_189257 = or(T_189256, T_189181)
    node T_189258 = or(T_189257, T_189183)
    node T_189259 = or(T_189258, T_189185)
    node T_189260 = or(T_189259, T_189187)
    node T_189261 = or(T_189260, T_189189)
    node T_189262 = or(T_189261, T_189191)
    node T_189263 = or(T_189262, T_189193)
    node T_189264 = or(T_189263, T_189195)
    node T_189265 = or(T_189264, T_189197)
    node T_189266 = or(T_189265, T_189199)
    node T_189267 = or(T_189266, T_189201)
    node T_189268 = or(T_189267, T_189203)
    node T_189269 = or(T_189268, T_189205)
    node T_189270 = or(T_189269, T_189207)
    node T_189271 = or(T_189270, T_189209)
    node T_189272 = or(T_189271, T_189211)
    node T_189273 = or(T_189272, T_189213)
    node T_189274 = or(T_189273, T_189215)
    node T_189275 = or(T_189274, T_189217)
    node T_189276 = or(T_189275, T_189219)
    node T_189277 = or(T_189276, T_189221)
    node T_189278 = or(T_189277, T_189223)
    node T_189279 = or(T_189278, T_189225)
    node T_189280 = or(T_189279, T_189227)
    node T_189281 = or(T_189280, T_189229)
    node T_189282 = or(T_189281, T_189231)
    node T_189283 = or(T_189282, T_189233)
    node T_189284 = or(T_189283, T_189234)
    node T_189285 = or(T_189284, T_189236)
    node T_189286 = or(T_189285, T_189238)
    node T_189287 = or(T_189286, T_189240)
    node T_189288 = or(T_189287, T_189242)
    node T_189289 = or(T_189288, T_189244)
    node T_189290 = or(T_189289, T_189246)
    node T_189291 = or(T_189290, T_189248)
    node T_189292 = or(T_189291, T_189250)
    node T_189293 = or(T_189292, T_189252)
    node T_189294 = or(T_189293, T_189254)
    node T_189295 = and(imem.resp.bits.data[0], UInt<32>(92))
    node T_189296 = eq(T_189295, UInt<32>(4))
    node T_189297 = and(imem.resp.bits.data[0], UInt<32>(96))
    node T_189298 = eq(T_189297, UInt<32>(64))
    node T_189299 = or(UInt<1>(0), T_189296)
    node T_189300 = or(T_189299, T_189298)
    node T_189301 = and(imem.resp.bits.data[0], UInt<32>(116))
    node T_189302 = eq(T_189301, UInt<32>(96))
    node T_189303 = or(UInt<1>(0), T_189302)
    node T_189304 = and(imem.resp.bits.data[0], UInt<32>(104))
    node T_189305 = eq(T_189304, UInt<32>(104))
    node T_189306 = or(UInt<1>(0), T_189305)
    node T_189307 = and(imem.resp.bits.data[0], UInt<32>(8252))
    node T_189308 = eq(T_189307, UInt<32>(36))
    node T_189309 = or(UInt<1>(0), T_189308)
    node T_189310 = and(imem.resp.bits.data[0], UInt<32>(100))
    node T_189311 = eq(T_189310, UInt<32>(32))
    node T_189312 = and(imem.resp.bits.data[0], UInt<32>(52))
    node T_189313 = eq(T_189312, UInt<32>(32))
    node T_189314 = and(imem.resp.bits.data[0], UInt<32>(8264))
    node T_189315 = eq(T_189314, UInt<32>(8200))
    node T_189316 = or(UInt<1>(0), T_189311)
    node T_189317 = or(T_189316, T_189313)
    node T_189318 = or(T_189317, T_189315)
    node T_189319 = and(imem.resp.bits.data[0], UInt<32>(68))
    node T_189320 = eq(T_189319, UInt<32>(0))
    node T_189321 = and(imem.resp.bits.data[0], UInt<32>(16420))
    node T_189322 = eq(T_189321, UInt<32>(32))
    node T_189323 = and(imem.resp.bits.data[0], UInt<32>(56))
    node T_189324 = eq(T_189323, UInt<32>(32))
    node T_189325 = and(imem.resp.bits.data[0], UInt<32>(8272))
    node T_189326 = eq(T_189325, UInt<32>(8192))
    node T_189327 = and(imem.resp.bits.data[0], UInt<32>(2415919156))
    node T_189328 = eq(T_189327, UInt<32>(2415919120))
    node T_189329 = or(UInt<1>(0), T_189320)
    node T_189330 = or(T_189329, T_189322)
    node T_189331 = or(T_189330, T_189324)
    node T_189332 = or(T_189331, T_189326)
    node T_189333 = or(T_189332, T_189328)
    node T_189334 = and(imem.resp.bits.data[0], UInt<32>(88))
    node T_189335 = eq(T_189334, UInt<32>(0))
    node T_189336 = and(imem.resp.bits.data[0], UInt<32>(32))
    node T_189337 = eq(T_189336, UInt<32>(0))
    node T_189338 = and(imem.resp.bits.data[0], UInt<32>(12))
    node T_189339 = eq(T_189338, UInt<32>(4))
    node T_189340 = and(imem.resp.bits.data[0], UInt<32>(72))
    node T_189341 = eq(T_189340, UInt<32>(72))
    node T_189342 = and(imem.resp.bits.data[0], UInt<32>(16464))
    node T_189343 = eq(T_189342, UInt<32>(16464))
    node T_189344 = or(UInt<1>(0), T_189335)
    node T_189345 = or(T_189344, T_189337)
    node T_189346 = or(T_189345, T_189339)
    node T_189347 = or(T_189346, T_189341)
    node T_189348 = or(T_189347, T_189343)
    node T_189349 = and(imem.resp.bits.data[0], UInt<32>(72))
    node T_189350 = eq(T_189349, UInt<32>(0))
    node T_189351 = and(imem.resp.bits.data[0], UInt<32>(24))
    node T_189352 = eq(T_189351, UInt<32>(0))
    node T_189353 = and(imem.resp.bits.data[0], UInt<32>(16392))
    node T_189354 = eq(T_189353, UInt<32>(16384))
    node T_189355 = or(UInt<1>(0), T_189350)
    node T_189356 = or(T_189355, T_189320)
    node T_189357 = or(T_189356, T_189352)
    node T_189358 = or(T_189357, T_189354)
    node T_189359 = cat(T_189358, T_189348)
    node T_189360 = and(imem.resp.bits.data[0], UInt<32>(16388))
    node T_189361 = eq(T_189360, UInt<32>(0))
    node T_189362 = and(imem.resp.bits.data[0], UInt<32>(80))
    node T_189363 = eq(T_189362, UInt<32>(0))
    node T_189364 = and(imem.resp.bits.data[0], UInt<32>(36))
    node T_189365 = eq(T_189364, UInt<32>(0))
    node T_189366 = or(UInt<1>(0), T_189361)
    node T_189367 = or(T_189366, T_189363)
    node T_189368 = or(T_189367, T_189320)
    node T_189369 = or(T_189368, T_189365)
    node T_189370 = or(T_189369, T_189352)
    node T_189371 = and(imem.resp.bits.data[0], UInt<32>(52))
    node T_189372 = eq(T_189371, UInt<32>(20))
    node T_189373 = or(UInt<1>(0), T_189372)
    node T_189374 = or(T_189373, T_189341)
    node T_189375 = cat(T_189374, T_189370)
    node T_189376 = and(imem.resp.bits.data[0], UInt<32>(24))
    node T_189377 = eq(T_189376, UInt<32>(8))
    node T_189378 = and(imem.resp.bits.data[0], UInt<32>(68))
    node T_189379 = eq(T_189378, UInt<32>(64))
    node T_189380 = or(UInt<1>(0), T_189377)
    node T_189381 = or(T_189380, T_189379)
    node T_189382 = and(imem.resp.bits.data[0], UInt<32>(20))
    node T_189383 = eq(T_189382, UInt<32>(20))
    node T_189384 = or(UInt<1>(0), T_189377)
    node T_189385 = or(T_189384, T_189383)
    node T_189386 = and(imem.resp.bits.data[0], UInt<32>(48))
    node T_189387 = eq(T_189386, UInt<32>(0))
    node T_189388 = and(imem.resp.bits.data[0], UInt<32>(8220))
    node T_189389 = eq(T_189388, UInt<32>(4))
    node T_189390 = and(imem.resp.bits.data[0], UInt<32>(20))
    node T_189391 = eq(T_189390, UInt<32>(16))
    node T_189392 = or(UInt<1>(0), T_189387)
    node T_189393 = or(T_189392, T_189389)
    node T_189394 = or(T_189393, T_189391)
    node T_189395 = cat(T_189385, T_189381)
    node T_189396 = cat(T_189394, T_189395)
    node T_189397 = and(imem.resp.bits.data[0], UInt<32>(16))
    node T_189398 = eq(T_189397, UInt<32>(0))
    node T_189399 = and(imem.resp.bits.data[0], UInt<32>(8))
    node T_189400 = eq(T_189399, UInt<32>(0))
    node T_189401 = or(UInt<1>(0), T_189398)
    node T_189402 = or(T_189401, T_189400)
    node T_189403 = and(imem.resp.bits.data[0], UInt<32>(12372))
    node T_189404 = eq(T_189403, UInt<32>(4112))
    node T_189405 = and(imem.resp.bits.data[0], UInt<32>(4184))
    node T_189406 = eq(T_189405, UInt<32>(4160))
    node T_189407 = and(imem.resp.bits.data[0], UInt<32>(28740))
    node T_189408 = eq(T_189407, UInt<32>(28672))
    node T_189409 = or(UInt<1>(0), T_189404)
    node T_189410 = or(T_189409, T_189406)
    node T_189411 = or(T_189410, T_189408)
    node T_189412 = and(imem.resp.bits.data[0], UInt<32>(8280))
    node T_189413 = eq(T_189412, UInt<32>(8256))
    node T_189414 = and(imem.resp.bits.data[0], UInt<32>(12372))
    node T_189415 = eq(T_189414, UInt<32>(12304))
    node T_189416 = and(imem.resp.bits.data[0], UInt<32>(24660))
    node T_189417 = eq(T_189416, UInt<32>(24592))
    node T_189418 = and(imem.resp.bits.data[0], UInt<32>(1073754164))
    node T_189419 = eq(T_189418, UInt<32>(1073741872))
    node T_189420 = and(imem.resp.bits.data[0], UInt<32>(1073746004))
    node T_189421 = eq(T_189420, UInt<32>(1073745936))
    node T_189422 = or(UInt<1>(0), T_189413)
    node T_189423 = or(T_189422, T_189415)
    node T_189424 = or(T_189423, T_189417)
    node T_189425 = or(T_189424, T_189419)
    node T_189426 = or(T_189425, T_189421)
    node T_189427 = and(imem.resp.bits.data[0], UInt<32>(8276))
    node T_189428 = eq(T_189427, UInt<32>(8208))
    node T_189429 = and(imem.resp.bits.data[0], UInt<32>(1073758292))
    node T_189430 = eq(T_189429, UInt<32>(16400))
    node T_189431 = and(imem.resp.bits.data[0], UInt<32>(20564))
    node T_189432 = eq(T_189431, UInt<32>(16400))
    node T_189433 = and(imem.resp.bits.data[0], UInt<32>(16472))
    node T_189434 = eq(T_189433, UInt<32>(16448))
    node T_189435 = or(UInt<1>(0), T_189428)
    node T_189436 = or(T_189435, T_189430)
    node T_189437 = or(T_189436, T_189432)
    node T_189438 = or(T_189437, T_189434)
    node T_189439 = and(imem.resp.bits.data[0], UInt<32>(84))
    node T_189440 = eq(T_189439, UInt<32>(64))
    node T_189441 = and(imem.resp.bits.data[0], UInt<32>(24660))
    node T_189442 = eq(T_189441, UInt<32>(8208))
    node T_189443 = and(imem.resp.bits.data[0], UInt<32>(1073754196))
    node T_189444 = eq(T_189443, UInt<32>(1073745936))
    node T_189445 = or(UInt<1>(0), T_189440)
    node T_189446 = or(T_189445, T_189442)
    node T_189447 = or(T_189446, T_189419)
    node T_189448 = or(T_189447, T_189444)
    node T_189449 = cat(T_189426, T_189411)
    node T_189450 = cat(T_189438, T_189449)
    node T_189451 = cat(T_189448, T_189450)
    node T_189452 = and(imem.resp.bits.data[0], UInt<32>(16479))
    node T_189453 = eq(T_189452, UInt<32>(3))
    node T_189454 = and(imem.resp.bits.data[0], UInt<32>(4223))
    node T_189455 = eq(T_189454, UInt<32>(3))
    node T_189456 = or(UInt<1>(0), T_189453)
    node T_189457 = or(T_189456, T_189177)
    node T_189458 = or(T_189457, T_189455)
    node T_189459 = or(T_189458, T_189205)
    node T_189460 = or(T_189459, T_189209)
    node T_189461 = or(T_189460, T_189221)
    node T_189462 = or(T_189461, T_189225)
    node T_189463 = and(imem.resp.bits.data[0], UInt<32>(40))
    node T_189464 = eq(T_189463, UInt<32>(32))
    node T_189465 = and(imem.resp.bits.data[0], UInt<32>(402653216))
    node T_189466 = eq(T_189465, UInt<32>(402653216))
    node T_189467 = and(imem.resp.bits.data[0], UInt<32>(536870944))
    node T_189468 = eq(T_189467, UInt<32>(536870944))
    node T_189469 = or(UInt<1>(0), T_189464)
    node T_189470 = or(T_189469, T_189466)
    node T_189471 = or(T_189470, T_189468)
    node T_189472 = and(imem.resp.bits.data[0], UInt<32>(268435464))
    node T_189473 = eq(T_189472, UInt<32>(268435464))
    node T_189474 = and(imem.resp.bits.data[0], UInt<32>(1073741832))
    node T_189475 = eq(T_189474, UInt<32>(1073741832))
    node T_189476 = or(UInt<1>(0), T_189473)
    node T_189477 = or(T_189476, T_189475)
    node T_189478 = and(imem.resp.bits.data[0], UInt<32>(134217736))
    node T_189479 = eq(T_189478, UInt<32>(134217736))
    node T_189480 = and(imem.resp.bits.data[0], UInt<32>(2147483656))
    node T_189481 = eq(T_189480, UInt<32>(2147483656))
    node T_189482 = or(UInt<1>(0), T_189479)
    node T_189483 = or(T_189482, T_189473)
    node T_189484 = or(T_189483, T_189481)
    node T_189485 = and(imem.resp.bits.data[0], UInt<32>(402653192))
    node T_189486 = eq(T_189485, UInt<32>(8))
    node T_189487 = or(UInt<1>(0), T_189486)
    node T_189488 = cat(T_189477, T_189471)
    node T_189489 = cat(T_189484, T_189488)
    node T_189490 = cat(T_189487, T_189489)
    node T_189491 = cat(UInt<1>(0), T_189490)
    node T_189492 = and(imem.resp.bits.data[0], UInt<32>(4096))
    node T_189493 = eq(T_189492, UInt<32>(4096))
    node T_189494 = or(UInt<1>(0), T_189493)
    node T_189495 = and(imem.resp.bits.data[0], UInt<32>(8192))
    node T_189496 = eq(T_189495, UInt<32>(8192))
    node T_189497 = or(UInt<1>(0), T_189496)
    node T_189498 = and(imem.resp.bits.data[0], UInt<32>(16384))
    node T_189499 = eq(T_189498, UInt<32>(16384))
    node T_189500 = or(UInt<1>(0), T_189499)
    node T_189501 = cat(T_189497, T_189494)
    node T_189502 = cat(T_189500, T_189501)
    node T_189503 = and(imem.resp.bits.data[0], UInt<32>(2147483744))
    node T_189504 = eq(T_189503, UInt<32>(64))
    node T_189505 = and(imem.resp.bits.data[0], UInt<32>(268435552))
    node T_189506 = eq(T_189505, UInt<32>(64))
    node T_189507 = and(imem.resp.bits.data[0], UInt<32>(112))
    node T_189508 = eq(T_189507, UInt<32>(64))
    node T_189509 = or(UInt<1>(0), T_189504)
    node T_189510 = or(T_189509, T_189506)
    node T_189511 = or(T_189510, T_189508)
    node T_189512 = and(imem.resp.bits.data[0], UInt<32>(124))
    node T_189513 = eq(T_189512, UInt<32>(36))
    node T_189514 = and(imem.resp.bits.data[0], UInt<32>(1073741920))
    node T_189515 = eq(T_189514, UInt<32>(64))
    node T_189516 = and(imem.resp.bits.data[0], UInt<32>(2415919200))
    node T_189517 = eq(T_189516, UInt<32>(268435520))
    node T_189518 = or(UInt<1>(0), T_189513)
    node T_189519 = or(T_189518, T_189515)
    node T_189520 = or(T_189519, T_189508)
    node T_189521 = or(T_189520, T_189517)
    node T_189522 = or(UInt<1>(0), T_189508)
    node T_189523 = and(imem.resp.bits.data[0], UInt<32>(60))
    node T_189524 = eq(T_189523, UInt<32>(4))
    node T_189525 = and(imem.resp.bits.data[0], UInt<32>(268435552))
    node T_189526 = eq(T_189525, UInt<32>(268435520))
    node T_189527 = or(UInt<1>(0), T_189524)
    node T_189528 = or(T_189527, T_189504)
    node T_189529 = or(T_189528, T_189508)
    node T_189530 = or(T_189529, T_189526)
    node T_189531 = and(imem.resp.bits.data[0], UInt<32>(33554548))
    node T_189532 = eq(T_189531, UInt<32>(33554480))
    node T_189533 = or(UInt<1>(0), T_189532)
    node T_189534 = and(imem.resp.bits.data[0], UInt<32>(100))
    node T_189535 = eq(T_189534, UInt<32>(0))
    node T_189536 = and(imem.resp.bits.data[0], UInt<32>(80))
    node T_189537 = eq(T_189536, UInt<32>(16))
    node T_189538 = and(imem.resp.bits.data[0], UInt<32>(8228))
    node T_189539 = eq(T_189538, UInt<32>(36))
    node T_189540 = and(imem.resp.bits.data[0], UInt<32>(40))
    node T_189541 = eq(T_189540, UInt<32>(40))
    node T_189542 = and(imem.resp.bits.data[0], UInt<32>(4144))
    node T_189543 = eq(T_189542, UInt<32>(4144))
    node T_189544 = and(imem.resp.bits.data[0], UInt<32>(8240))
    node T_189545 = eq(T_189544, UInt<32>(8240))
    node T_189546 = and(imem.resp.bits.data[0], UInt<32>(2415919120))
    node T_189547 = eq(T_189546, UInt<32>(2147483664))
    node T_189548 = or(UInt<1>(0), T_189535)
    node T_189549 = or(T_189548, T_189537)
    node T_189550 = or(T_189549, T_189539)
    node T_189551 = or(T_189550, T_189541)
    node T_189552 = or(T_189551, T_189543)
    node T_189553 = or(T_189552, T_189545)
    node T_189554 = or(T_189553, T_189547)
    node T_189555 = and(imem.resp.bits.data[0], UInt<32>(4208))
    node T_189556 = eq(T_189555, UInt<32>(4208))
    node T_189557 = or(UInt<1>(0), T_189556)
    node T_189558 = and(imem.resp.bits.data[0], UInt<32>(8304))
    node T_189559 = eq(T_189558, UInt<32>(8304))
    node T_189560 = or(UInt<1>(0), T_189559)
    node T_189561 = and(imem.resp.bits.data[0], UInt<32>(12400))
    node T_189562 = eq(T_189561, UInt<32>(112))
    node T_189563 = or(UInt<1>(0), T_189562)
    node T_189564 = cat(T_189560, T_189557)
    node T_189565 = cat(T_189563, T_189564)
    node T_189566 = and(imem.resp.bits.data[0], UInt<32>(12376))
    node T_189567 = eq(T_189566, UInt<32>(4104))
    node T_189568 = or(UInt<1>(0), T_189567)
    node T_189569 = and(imem.resp.bits.data[0], UInt<32>(12376))
    node T_189570 = eq(T_189569, UInt<32>(8))
    node T_189571 = or(UInt<1>(0), T_189570)
    node T_189572 = and(imem.resp.bits.data[0], UInt<32>(24648))
    node T_189573 = eq(T_189572, UInt<32>(8200))
    node T_189574 = or(UInt<1>(0), T_189573)
    wire T_189575 : UInt<1>[26]
    T_189575[0] := id_ctrl.legal
    T_189575[1] := id_ctrl.fp
    T_189575[2] := id_ctrl.rocc
    T_189575[3] := id_ctrl.branch
    T_189575[4] := id_ctrl.jal
    T_189575[5] := id_ctrl.jalr
    T_189575[6] := id_ctrl.rxs2
    T_189575[7] := id_ctrl.rxs1
    T_189575[8] := id_ctrl.sel_alu2
    T_189575[9] := id_ctrl.sel_alu1
    T_189575[10] := id_ctrl.sel_imm
    T_189575[11] := id_ctrl.alu_dw
    T_189575[12] := id_ctrl.alu_fn
    T_189575[13] := id_ctrl.mem__
    T_189575[14] := id_ctrl.mem_cmd
    T_189575[15] := id_ctrl.mem_type
    T_189575[16] := id_ctrl.rfs1
    T_189575[17] := id_ctrl.rfs2
    T_189575[18] := id_ctrl.rfs3
    T_189575[19] := id_ctrl.wfd
    T_189575[20] := id_ctrl.div
    T_189575[21] := id_ctrl.wxd
    T_189575[22] := id_ctrl.csr
    T_189575[23] := id_ctrl.fence_i
    T_189575[24] := id_ctrl.fence
    T_189575[25] := id_ctrl.amo
    T_189575[0] := T_189294
    T_189575[1] := T_189300
    T_189575[2] := UInt<1>(0)
    T_189575[3] := T_189303
    T_189575[4] := T_189306
    T_189575[5] := T_189309
    T_189575[6] := T_189318
    T_189575[7] := T_189333
    T_189575[8] := T_189359
    T_189575[9] := T_189375
    T_189575[10] := T_189396
    T_189575[11] := T_189402
    T_189575[12] := T_189451
    T_189575[13] := T_189462
    T_189575[14] := T_189491
    T_189575[15] := T_189502
    T_189575[16] := T_189511
    T_189575[17] := T_189521
    T_189575[18] := T_189522
    T_189575[19] := T_189530
    T_189575[20] := T_189533
    T_189575[21] := T_189554
    T_189575[22] := T_189565
    T_189575[23] := T_189568
    T_189575[24] := T_189571
    T_189575[25] := T_189574
    node id_raddr3 = bits(imem.resp.bits.data[0], 31, 27)
    node id_raddr2 = bits(imem.resp.bits.data[0], 24, 20)
    node id_raddr1 = bits(imem.resp.bits.data[0], 19, 15)
    node id_waddr = bits(imem.resp.bits.data[0], 11, 7)
    wire id_load_use : UInt<1>
    reg id_reg_fence : UInt<1>
    onreset id_reg_fence := UInt<1>(0)
    cmem T_189576 : UInt<64>[31]
    wire T_189577 : UInt
    node T_189578 = not(id_raddr1)
    accessor T_189579 = T_189576[T_189578]
    T_189577 := T_189579
    wire T_189580 : UInt
    node T_189581 = not(id_raddr2)
    accessor T_189582 = T_189576[T_189581]
    T_189580 := T_189582
    wire ctrl_killd : UInt<1>
    inst csr of CSRFile
    node id_csr_en = neq(id_ctrl.csr, UInt<3>(0))
    node id_system_insn = eq(id_ctrl.csr, UInt<3>(4))
    node T_189583 = eq(id_ctrl.csr, UInt<3>(2))
    node T_189584 = eq(id_ctrl.csr, UInt<3>(3))
    node T_189585 = or(T_189583, T_189584)
    node T_189586 = eq(id_raddr1, UInt<1>(0))
    node id_csr_ren = and(T_189585, T_189586)
    wire id_csr : UInt<3>
    id_csr := id_ctrl.csr
    when id_csr_ren : id_csr := UInt<3>(5)
    node id_csr_addr = bits(imem.resp.bits.data[0], 31, 20)
    node T_189587 = eq(id_csr_ren, UInt<1>(0))
    node T_189588 = and(id_csr_en, T_189587)
    node T_189589 = and(id_csr_addr, UInt<12>(2244))
    node T_189590 = eq(T_189589, UInt<12>(64))
    node T_189591 = or(UInt<1>(0), T_189590)
    node T_189592 = bit(T_189591, 0)
    node T_189593 = eq(T_189592, UInt<1>(0))
    node T_189594 = and(T_189588, T_189593)
    node id_csr_flush = or(id_system_insn, T_189594)
    node T_189595 = eq(id_ctrl.legal, UInt<1>(0))
    node T_189596 = eq(csr.status.fs, UInt<1>(0))
    node T_189597 = eq(T_189596, UInt<1>(0))
    node T_189598 = eq(T_189597, UInt<1>(0))
    node T_189599 = and(id_ctrl.fp, T_189598)
    node T_189600 = or(T_189595, T_189599)
    node T_189601 = eq(csr.status.xs, UInt<1>(0))
    node T_189602 = eq(T_189601, UInt<1>(0))
    node T_189603 = eq(T_189602, UInt<1>(0))
    node T_189604 = and(id_ctrl.rocc, T_189603)
    node id_illegal_insn = or(T_189600, T_189604)
    node id_amo_aq = bit(imem.resp.bits.data[0], 26)
    node id_amo_rl = bit(imem.resp.bits.data[0], 25)
    node T_189605 = and(id_ctrl.amo, id_amo_rl)
    node id_fence_next = or(id_ctrl.fence, T_189605)
    node T_189606 = eq(dmem.ordered, UInt<1>(0))
    node id_mem_busy = or(T_189606, dmem.req.valid)
    node T_189607 = and(ex_reg_valid, ex_ctrl.rocc)
    node T_189608 = or(rocc.busy, T_189607)
    node T_189609 = and(mem_reg_valid, mem_ctrl.rocc)
    node T_189610 = or(T_189608, T_189609)
    node T_189611 = and(wb_reg_valid, wb_ctrl.rocc)
    node T_189612 = or(T_189610, T_189611)
    node id_rocc_busy = and(UInt<1>(0), T_189612)
    node T_189613 = and(id_reg_fence, id_mem_busy)
    node T_189614 = or(id_fence_next, T_189613)
    id_reg_fence := T_189614
    node T_189615 = and(id_rocc_busy, id_ctrl.fence)
    node T_189616 = and(id_ctrl.amo, id_amo_aq)
    node T_189617 = or(T_189616, id_ctrl.fence_i)
    node T_189618 = or(id_ctrl.mem__, id_ctrl.rocc)
    node T_189619 = and(id_reg_fence, T_189618)
    node T_189620 = or(T_189617, T_189619)
    node T_189621 = or(T_189620, id_csr_en)
    node T_189622 = and(id_mem_busy, T_189621)
    node id_do_fence = or(T_189615, T_189622)
    node T_189623 = or(csr.interrupt, imem.resp.bits.xcpt_if)
    node id_xcpt = or(T_189623, id_illegal_insn)
    wire T_189624 : UInt<2>
    T_189624 := UInt<2>(2)
    when imem.resp.bits.xcpt_if : T_189624 := UInt<1>(1)
    wire id_cause : UInt<2>
    id_cause := T_189624
    when csr.interrupt : id_cause := csr.interrupt_cause
    node ex_waddr = bits(ex_reg_inst, 11, 7)
    node mem_waddr = bits(mem_reg_inst, 11, 7)
    node wb_waddr = bits(wb_reg_inst, 11, 7)
    node T_189625 = and(ex_reg_valid, ex_ctrl.wxd)
    node T_189626 = and(mem_reg_valid, mem_ctrl.wxd)
    node T_189627 = eq(mem_ctrl.mem__, UInt<1>(0))
    node T_189628 = and(T_189626, T_189627)
    node T_189629 = and(mem_reg_valid, mem_ctrl.wxd)
    node T_189630 = eq(UInt<1>(0), id_raddr1)
    node T_189631 = and(UInt<1>(1), T_189630)
    node T_189632 = eq(ex_waddr, id_raddr1)
    node T_189633 = and(T_189625, T_189632)
    node T_189634 = eq(mem_waddr, id_raddr1)
    node T_189635 = and(T_189628, T_189634)
    node T_189636 = eq(mem_waddr, id_raddr1)
    node T_189637 = and(T_189629, T_189636)
    node T_189638 = eq(UInt<1>(0), id_raddr2)
    node T_189639 = and(UInt<1>(1), T_189638)
    node T_189640 = eq(ex_waddr, id_raddr2)
    node T_189641 = and(T_189625, T_189640)
    node T_189642 = eq(mem_waddr, id_raddr2)
    node T_189643 = and(T_189628, T_189642)
    node T_189644 = eq(mem_waddr, id_raddr2)
    node T_189645 = and(T_189629, T_189644)
    wire bypass_mux : UInt<1>[4]
    bypass_mux[0] := UInt<1>(0)
    bypass_mux[1] := mem_reg_wdata
    bypass_mux[2] := wb_reg_wdata
    bypass_mux[3] := dmem.resp.bits.data
    wire T_189646 : UInt<1>[2]
    T_189646[0] := T_189647
    T_189646[1] := T_189648
    reg ex_reg_rs_bypass : UInt<1>[2]
    wire T_189649 : UInt[2]
    T_189649[0] := T_189650
    T_189649[1] := T_189651
    reg ex_reg_rs_lsb : UInt[2]
    wire T_189652 : UInt[2]
    T_189652[0] := T_189653
    T_189652[1] := T_189654
    reg ex_reg_rs_msb : UInt[2]
    accessor T_189655 = bypass_mux[ex_reg_rs_lsb[0]]
    node T_189656 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0])
    wire T_189657 : UInt
    T_189657 := T_189656
    when ex_reg_rs_bypass[0] : T_189657 := T_189655
    accessor T_189658 = bypass_mux[ex_reg_rs_lsb[1]]
    node T_189659 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1])
    wire T_189660 : UInt
    T_189660 := T_189659
    when ex_reg_rs_bypass[1] : T_189660 := T_189658
    node T_189661 = eq(ex_ctrl.sel_imm, UInt<3>(5))
    node T_189662 = bit(ex_reg_inst, 31)
    node T_189663 = asSInt(T_189662)
    wire T_189664 : SInt<1>
    T_189664 := T_189663
    when T_189661 : T_189664 := SInt<1>(0)
    node T_189665 = eq(ex_ctrl.sel_imm, UInt<3>(2))
    node T_189666 = bits(ex_reg_inst, 30, 20)
    node T_189667 = asSInt(T_189666)
    wire T_189668 : SInt<1>
    T_189668 := T_189664
    when T_189665 : T_189668 := T_189667
    node T_189669 = neq(ex_ctrl.sel_imm, UInt<3>(2))
    node T_189670 = neq(ex_ctrl.sel_imm, UInt<3>(3))
    node T_189671 = and(T_189669, T_189670)
    node T_189672 = bits(ex_reg_inst, 19, 12)
    node T_189673 = asSInt(T_189672)
    wire T_189674 : SInt<8>
    T_189674 := T_189673
    when T_189671 : T_189674 := T_189664
    node T_189675 = eq(ex_ctrl.sel_imm, UInt<3>(2))
    node T_189676 = eq(ex_ctrl.sel_imm, UInt<3>(5))
    node T_189677 = or(T_189675, T_189676)
    node T_189678 = eq(ex_ctrl.sel_imm, UInt<3>(3))
    node T_189679 = bit(ex_reg_inst, 20)
    node T_189680 = asSInt(T_189679)
    node T_189681 = eq(ex_ctrl.sel_imm, UInt<3>(1))
    node T_189682 = bit(ex_reg_inst, 7)
    node T_189683 = asSInt(T_189682)
    wire T_189684 : SInt<1>
    T_189684 := T_189664
    when T_189681 : T_189684 := T_189683
    wire T_189685 : SInt<1>
    T_189685 := T_189684
    when T_189678 : T_189685 := T_189680
    wire T_189686 : SInt<1>
    T_189686 := T_189685
    when T_189677 : T_189686 := SInt<1>(0)
    node T_189687 = eq(ex_ctrl.sel_imm, UInt<3>(2))
    node T_189688 = eq(ex_ctrl.sel_imm, UInt<3>(5))
    node T_189689 = or(T_189687, T_189688)
    node T_189690 = bits(ex_reg_inst, 30, 25)
    wire T_189691 : UInt<6>
    T_189691 := T_189690
    when T_189689 : T_189691 := UInt<1>(0)
    node T_189692 = eq(ex_ctrl.sel_imm, UInt<3>(2))
    node T_189693 = eq(ex_ctrl.sel_imm, UInt<3>(0))
    node T_189694 = eq(ex_ctrl.sel_imm, UInt<3>(1))
    node T_189695 = or(T_189693, T_189694)
    node T_189696 = bits(ex_reg_inst, 11, 8)
    node T_189697 = eq(ex_ctrl.sel_imm, UInt<3>(5))
    node T_189698 = bits(ex_reg_inst, 19, 16)
    node T_189699 = bits(ex_reg_inst, 24, 21)
    wire T_189700 : UInt<4>
    T_189700 := T_189699
    when T_189697 : T_189700 := T_189698
    wire T_189701 : UInt<4>
    T_189701 := T_189700
    when T_189695 : T_189701 := T_189696
    wire T_189702 : UInt<4>
    T_189702 := T_189701
    when T_189692 : T_189702 := UInt<1>(0)
    node T_189703 = eq(ex_ctrl.sel_imm, UInt<3>(0))
    node T_189704 = bit(ex_reg_inst, 7)
    node T_189705 = eq(ex_ctrl.sel_imm, UInt<3>(4))
    node T_189706 = bit(ex_reg_inst, 20)
    node T_189707 = eq(ex_ctrl.sel_imm, UInt<3>(5))
    node T_189708 = bit(ex_reg_inst, 15)
    wire T_189709 : UInt<1>
    T_189709 := UInt<1>(0)
    when T_189707 : T_189709 := T_189708
    wire T_189710 : UInt<1>
    T_189710 := T_189709
    when T_189705 : T_189710 := T_189706
    wire T_189711 : UInt<1>
    T_189711 := T_189710
    when T_189703 : T_189711 := T_189704
    node T_189712 = asUInt(T_189664)
    node T_189713 = asUInt(T_189668)
    node T_189714 = asUInt(T_189674)
    node T_189715 = cat(T_189713, T_189714)
    node T_189716 = cat(T_189712, T_189715)
    node T_189717 = asUInt(T_189686)
    node T_189718 = cat(T_189717, T_189691)
    node T_189719 = cat(T_189702, T_189711)
    node T_189720 = cat(T_189718, T_189719)
    node T_189721 = cat(T_189716, T_189720)
    node ex_imm = asSInt(T_189721)
    node T_189722 = asSInt(T_189657)
    node T_189723 = asSInt(ex_reg_pc)
    node T_189724 = eq(UInt<2>(2), ex_ctrl.sel_alu1)
    wire T_189725 : SInt<1>
    T_189725 := SInt<1>(0)
    when T_189724 : T_189725 := T_189723
    node T_189726 = eq(UInt<2>(1), ex_ctrl.sel_alu1)
    wire ex_op1 : SInt<1>
    ex_op1 := T_189725
    when T_189726 : ex_op1 := T_189722
    node T_189727 = asSInt(T_189660)
    node T_189728 = eq(UInt<2>(1), ex_ctrl.sel_alu2)
    wire T_189729 : SInt<1>
    T_189729 := SInt<1>(0)
    when T_189728 : T_189729 := SInt<4>(4)
    node T_189730 = eq(UInt<2>(3), ex_ctrl.sel_alu2)
    wire T_189731 : SInt<1>
    T_189731 := T_189729
    when T_189730 : T_189731 := ex_imm
    node T_189732 = eq(UInt<2>(2), ex_ctrl.sel_alu2)
    wire ex_op2 : SInt<1>
    ex_op2 := T_189731
    when T_189732 : ex_op2 := T_189727
    inst alu of ALU
    alu.dw := ex_ctrl.alu_dw
    alu.fn := ex_ctrl.alu_fn
    node T_189733 = asUInt(ex_op2)
    alu.in2 := T_189733
    alu.in1 := ex_op1
    inst div of MulDiv
    node T_189734 = and(ex_reg_valid, ex_ctrl.div)
    div.req.valid := T_189734
    div.req.bits.dw := ex_ctrl.alu_dw
    div.req.bits.fn := ex_ctrl.alu_fn
    div.req.bits.in1 := T_189657
    div.req.bits.in2 := T_189660
    div.req.bits.tag := ex_waddr
    node T_189735 = eq(ctrl_killd, UInt<1>(0))
    ex_reg_valid := T_189735
    node T_189736 = eq(ctrl_killd, UInt<1>(0))
    node T_189737 = and(T_189736, id_xcpt)
    ex_reg_xcpt := T_189737
    node T_189738 = eq(take_pc_mem_wb, UInt<1>(0))
    node T_189739 = and(csr.interrupt, T_189738)
    node T_189740 = and(T_189739, imem.resp.valid)
    ex_reg_xcpt_interrupt := T_189740
    when id_xcpt : ex_reg_cause := id_cause
    
    node T_189741 = eq(ctrl_killd, UInt<1>(0))
    when T_189741 : 
      ex_ctrl := id_ctrl
      ex_ctrl.csr := id_csr
      ex_reg_btb_hit := imem.btb_resp.valid
      when imem.btb_resp.valid : ex_reg_btb_resp := imem.btb_resp.bits
      node T_189742 = or(id_ctrl.fence_i, id_csr_flush)
      ex_reg_flush_pipe := T_189742
      ex_reg_load_use := id_load_use
      node T_189743 = or(T_189631, T_189633)
      node T_189744 = or(T_189743, T_189635)
      node T_189745 = or(T_189744, T_189637)
      wire T_189746 : UInt<2>
      T_189746 := UInt<2>(3)
      when T_189635 : T_189746 := UInt<2>(2)
      wire T_189747 : UInt<2>
      T_189747 := T_189746
      when T_189633 : T_189747 := UInt<1>(1)
      wire T_189748 : UInt<2>
      T_189748 := T_189747
      when T_189631 : T_189748 := UInt<1>(0)
      ex_reg_rs_bypass[0] := T_189745
      ex_reg_rs_lsb[0] := T_189748
      
      
      node T_189749 = eq(T_189745, UInt<1>(0))
      node T_189750 = and(id_ctrl.rxs1, T_189749)
      when T_189750 : 
        node T_189751 = bits(T_189577, 1, 0)
        ex_reg_rs_lsb[0] := T_189751
        node T_189752 = shr(T_189577, 2)
        ex_reg_rs_msb[0] := T_189752
      node T_189753 = or(T_189639, T_189641)
      node T_189754 = or(T_189753, T_189643)
      node T_189755 = or(T_189754, T_189645)
      wire T_189756 : UInt<2>
      T_189756 := UInt<2>(3)
      when T_189643 : T_189756 := UInt<2>(2)
      wire T_189757 : UInt<2>
      T_189757 := T_189756
      when T_189641 : T_189757 := UInt<1>(1)
      wire T_189758 : UInt<2>
      T_189758 := T_189757
      when T_189639 : T_189758 := UInt<1>(0)
      ex_reg_rs_bypass[1] := T_189755
      ex_reg_rs_lsb[1] := T_189758
      
      
      node T_189759 = eq(T_189755, UInt<1>(0))
      node T_189760 = and(id_ctrl.rxs2, T_189759)
      when T_189760 : 
        node T_189761 = bits(T_189580, 1, 0)
        ex_reg_rs_lsb[1] := T_189761
        node T_189762 = shr(T_189580, 2)
        ex_reg_rs_msb[1] := T_189762
    
    
    node T_189763 = eq(ctrl_killd, UInt<1>(0))
    node T_189764 = or(T_189763, csr.interrupt)
    when T_189764 : 
      ex_reg_inst := imem.resp.bits.data[0]
      ex_reg_pc := imem.resp.bits.pc
    node T_189765 = eq(dmem.resp.valid, UInt<1>(0))
    node wb_dcache_miss = and(wb_ctrl.mem__, T_189765)
    node T_189766 = eq(dmem.req.ready, UInt<1>(0))
    node T_189767 = and(ex_ctrl.mem__, T_189766)
    node T_189768 = eq(div.req.ready, UInt<1>(0))
    node T_189769 = and(ex_ctrl.div, T_189768)
    node replay_ex_structural = or(T_189767, T_189769)
    node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use)
    node T_189770 = or(replay_ex_structural, replay_ex_load_use)
    node replay_ex = and(ex_reg_valid, T_189770)
    node T_189771 = or(take_pc_mem_wb, replay_ex)
    node T_189772 = eq(ex_reg_valid, UInt<1>(0))
    node ctrl_killx = or(T_189771, T_189772)
    node T_189773 = eq(ex_ctrl.mem_cmd, UInt<5>(7))
    wire T_189774 : UInt<3>[4]
    T_189774[0] := UInt<3>(0)
    T_189774[1] := UInt<3>(4)
    T_189774[2] := UInt<3>(1)
    T_189774[3] := UInt<3>(5)
    node T_189775 = eq(T_189774[0], ex_ctrl.mem_type)
    node T_189776 = eq(T_189774[1], ex_ctrl.mem_type)
    node T_189777 = eq(T_189774[2], ex_ctrl.mem_type)
    node T_189778 = eq(T_189774[3], ex_ctrl.mem_type)
    node T_189779 = or(UInt<1>(0), T_189775)
    node T_189780 = or(T_189779, T_189776)
    node T_189781 = or(T_189780, T_189777)
    node T_189782 = or(T_189781, T_189778)
    node ex_slow_bypass = or(T_189773, T_189782)
    node T_189783 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt)
    node T_189784 = and(ex_ctrl.fp, fpu.illegal_rm)
    node ex_xcpt = or(T_189783, T_189784)
    wire ex_cause : UInt<2>
    ex_cause := UInt<2>(2)
    when T_189783 : ex_cause := ex_reg_cause
    node mem_br_taken = bit(mem_reg_wdata, 0)
    node T_189785 = asSInt(mem_reg_pc)
    node T_189786 = and(mem_ctrl.branch, mem_br_taken)
    node T_189787 = eq(UInt<3>(1), UInt<3>(5))
    node T_189788 = bit(mem_reg_inst, 31)
    node T_189789 = asSInt(T_189788)
    wire T_189790 : SInt<1>
    T_189790 := T_189789
    when T_189787 : T_189790 := SInt<1>(0)
    node T_189791 = eq(UInt<3>(1), UInt<3>(2))
    node T_189792 = bits(mem_reg_inst, 30, 20)
    node T_189793 = asSInt(T_189792)
    wire T_189794 : SInt<1>
    T_189794 := T_189790
    when T_189791 : T_189794 := T_189793
    node T_189795 = neq(UInt<3>(1), UInt<3>(2))
    node T_189796 = neq(UInt<3>(1), UInt<3>(3))
    node T_189797 = and(T_189795, T_189796)
    node T_189798 = bits(mem_reg_inst, 19, 12)
    node T_189799 = asSInt(T_189798)
    wire T_189800 : SInt<8>
    T_189800 := T_189799
    when T_189797 : T_189800 := T_189790
    node T_189801 = eq(UInt<3>(1), UInt<3>(2))
    node T_189802 = eq(UInt<3>(1), UInt<3>(5))
    node T_189803 = or(T_189801, T_189802)
    node T_189804 = eq(UInt<3>(1), UInt<3>(3))
    node T_189805 = bit(mem_reg_inst, 20)
    node T_189806 = asSInt(T_189805)
    node T_189807 = eq(UInt<3>(1), UInt<3>(1))
    node T_189808 = bit(mem_reg_inst, 7)
    node T_189809 = asSInt(T_189808)
    wire T_189810 : SInt<1>
    T_189810 := T_189790
    when T_189807 : T_189810 := T_189809
    wire T_189811 : SInt<1>
    T_189811 := T_189810
    when T_189804 : T_189811 := T_189806
    wire T_189812 : SInt<1>
    T_189812 := T_189811
    when T_189803 : T_189812 := SInt<1>(0)
    node T_189813 = eq(UInt<3>(1), UInt<3>(2))
    node T_189814 = eq(UInt<3>(1), UInt<3>(5))
    node T_189815 = or(T_189813, T_189814)
    node T_189816 = bits(mem_reg_inst, 30, 25)
    wire T_189817 : UInt<6>
    T_189817 := T_189816
    when T_189815 : T_189817 := UInt<1>(0)
    node T_189818 = eq(UInt<3>(1), UInt<3>(2))
    node T_189819 = eq(UInt<3>(1), UInt<3>(0))
    node T_189820 = eq(UInt<3>(1), UInt<3>(1))
    node T_189821 = or(T_189819, T_189820)
    node T_189822 = bits(mem_reg_inst, 11, 8)
    node T_189823 = eq(UInt<3>(1), UInt<3>(5))
    node T_189824 = bits(mem_reg_inst, 19, 16)
    node T_189825 = bits(mem_reg_inst, 24, 21)
    wire T_189826 : UInt<4>
    T_189826 := T_189825
    when T_189823 : T_189826 := T_189824
    wire T_189827 : UInt<4>
    T_189827 := T_189826
    when T_189821 : T_189827 := T_189822
    wire T_189828 : UInt<4>
    T_189828 := T_189827
    when T_189818 : T_189828 := UInt<1>(0)
    node T_189829 = eq(UInt<3>(1), UInt<3>(0))
    node T_189830 = bit(mem_reg_inst, 7)
    node T_189831 = eq(UInt<3>(1), UInt<3>(4))
    node T_189832 = bit(mem_reg_inst, 20)
    node T_189833 = eq(UInt<3>(1), UInt<3>(5))
    node T_189834 = bit(mem_reg_inst, 15)
    wire T_189835 : UInt<1>
    T_189835 := UInt<1>(0)
    when T_189833 : T_189835 := T_189834
    wire T_189836 : UInt<1>
    T_189836 := T_189835
    when T_189831 : T_189836 := T_189832
    wire T_189837 : UInt<1>
    T_189837 := T_189836
    when T_189829 : T_189837 := T_189830
    node T_189838 = asUInt(T_189790)
    node T_189839 = asUInt(T_189794)
    node T_189840 = asUInt(T_189800)
    node T_189841 = cat(T_189839, T_189840)
    node T_189842 = cat(T_189838, T_189841)
    node T_189843 = asUInt(T_189812)
    node T_189844 = cat(T_189843, T_189817)
    node T_189845 = cat(T_189828, T_189837)
    node T_189846 = cat(T_189844, T_189845)
    node T_189847 = cat(T_189842, T_189846)
    node T_189848 = asSInt(T_189847)
    node T_189849 = eq(UInt<3>(3), UInt<3>(5))
    node T_189850 = bit(mem_reg_inst, 31)
    node T_189851 = asSInt(T_189850)
    wire T_189852 : SInt<1>
    T_189852 := T_189851
    when T_189849 : T_189852 := SInt<1>(0)
    node T_189853 = eq(UInt<3>(3), UInt<3>(2))
    node T_189854 = bits(mem_reg_inst, 30, 20)
    node T_189855 = asSInt(T_189854)
    wire T_189856 : SInt<1>
    T_189856 := T_189852
    when T_189853 : T_189856 := T_189855
    node T_189857 = neq(UInt<3>(3), UInt<3>(2))
    node T_189858 = neq(UInt<3>(3), UInt<3>(3))
    node T_189859 = and(T_189857, T_189858)
    node T_189860 = bits(mem_reg_inst, 19, 12)
    node T_189861 = asSInt(T_189860)
    wire T_189862 : SInt<8>
    T_189862 := T_189861
    when T_189859 : T_189862 := T_189852
    node T_189863 = eq(UInt<3>(3), UInt<3>(2))
    node T_189864 = eq(UInt<3>(3), UInt<3>(5))
    node T_189865 = or(T_189863, T_189864)
    node T_189866 = eq(UInt<3>(3), UInt<3>(3))
    node T_189867 = bit(mem_reg_inst, 20)
    node T_189868 = asSInt(T_189867)
    node T_189869 = eq(UInt<3>(3), UInt<3>(1))
    node T_189870 = bit(mem_reg_inst, 7)
    node T_189871 = asSInt(T_189870)
    wire T_189872 : SInt<1>
    T_189872 := T_189852
    when T_189869 : T_189872 := T_189871
    wire T_189873 : SInt<1>
    T_189873 := T_189872
    when T_189866 : T_189873 := T_189868
    wire T_189874 : SInt<1>
    T_189874 := T_189873
    when T_189865 : T_189874 := SInt<1>(0)
    node T_189875 = eq(UInt<3>(3), UInt<3>(2))
    node T_189876 = eq(UInt<3>(3), UInt<3>(5))
    node T_189877 = or(T_189875, T_189876)
    node T_189878 = bits(mem_reg_inst, 30, 25)
    wire T_189879 : UInt<6>
    T_189879 := T_189878
    when T_189877 : T_189879 := UInt<1>(0)
    node T_189880 = eq(UInt<3>(3), UInt<3>(2))
    node T_189881 = eq(UInt<3>(3), UInt<3>(0))
    node T_189882 = eq(UInt<3>(3), UInt<3>(1))
    node T_189883 = or(T_189881, T_189882)
    node T_189884 = bits(mem_reg_inst, 11, 8)
    node T_189885 = eq(UInt<3>(3), UInt<3>(5))
    node T_189886 = bits(mem_reg_inst, 19, 16)
    node T_189887 = bits(mem_reg_inst, 24, 21)
    wire T_189888 : UInt<4>
    T_189888 := T_189887
    when T_189885 : T_189888 := T_189886
    wire T_189889 : UInt<4>
    T_189889 := T_189888
    when T_189883 : T_189889 := T_189884
    wire T_189890 : UInt<4>
    T_189890 := T_189889
    when T_189880 : T_189890 := UInt<1>(0)
    node T_189891 = eq(UInt<3>(3), UInt<3>(0))
    node T_189892 = bit(mem_reg_inst, 7)
    node T_189893 = eq(UInt<3>(3), UInt<3>(4))
    node T_189894 = bit(mem_reg_inst, 20)
    node T_189895 = eq(UInt<3>(3), UInt<3>(5))
    node T_189896 = bit(mem_reg_inst, 15)
    wire T_189897 : UInt<1>
    T_189897 := UInt<1>(0)
    when T_189895 : T_189897 := T_189896
    wire T_189898 : UInt<1>
    T_189898 := T_189897
    when T_189893 : T_189898 := T_189894
    wire T_189899 : UInt<1>
    T_189899 := T_189898
    when T_189891 : T_189899 := T_189892
    node T_189900 = asUInt(T_189852)
    node T_189901 = asUInt(T_189856)
    node T_189902 = asUInt(T_189862)
    node T_189903 = cat(T_189901, T_189902)
    node T_189904 = cat(T_189900, T_189903)
    node T_189905 = asUInt(T_189874)
    node T_189906 = cat(T_189905, T_189879)
    node T_189907 = cat(T_189890, T_189899)
    node T_189908 = cat(T_189906, T_189907)
    node T_189909 = cat(T_189904, T_189908)
    node T_189910 = asSInt(T_189909)
    wire T_189911 : SInt<4>
    T_189911 := SInt<4>(4)
    when mem_ctrl.jal : T_189911 := T_189910
    wire T_189912 : SInt<4>
    T_189912 := T_189911
    when T_189786 : T_189912 := T_189848
    node mem_br_target = addw(T_189785, T_189912)
    node T_189913 = asSInt(mem_reg_wdata)
    wire T_189914 : SInt
    T_189914 := T_189913
    when mem_ctrl.jalr : T_189914 := mem_br_target
    node mem_int_wdata = asUInt(T_189914)
    node T_189915 = shr(mem_reg_wdata, 38)
    node T_189916 = bits(mem_reg_wdata, 39, 38)
    node T_189917 = eq(T_189915, UInt<1>(0))
    node T_189918 = eq(T_189915, UInt<1>(1))
    node T_189919 = or(T_189917, T_189918)
    node T_189920 = neq(T_189916, UInt<1>(0))
    node T_189921 = eq(T_189915, SInt<1>(-1))
    node T_189922 = eq(T_189915, SInt<2>(-2))
    node T_189923 = or(T_189921, T_189922)
    node T_189924 = eq(T_189916, SInt<1>(-1))
    node T_189925 = bit(T_189916, 0)
    wire T_189926 : UInt<1>
    T_189926 := T_189925
    when T_189923 : T_189926 := T_189924
    wire T_189927 : UInt<1>
    T_189927 := T_189926
    when T_189919 : T_189927 := T_189920
    node T_189928 = bits(mem_reg_wdata, 38, 0)
    node T_189929 = cat(T_189927, T_189928)
    node T_189930 = asSInt(T_189929)
    wire T_189931 : SInt
    T_189931 := mem_br_target
    when mem_ctrl.jalr : T_189931 := T_189930
    node T_189932 = and(T_189931, SInt<2>(-2))
    node mem_npc = asUInt(T_189932)
    node T_189933 = neq(mem_npc, ex_reg_pc)
    node T_189934 = eq(ex_reg_valid, UInt<1>(0))
    node mem_wrong_npc = or(T_189933, T_189934)
    node mem_npc_misaligned = bit(mem_npc, 1)
    node T_189935 = and(mem_wrong_npc, mem_reg_valid)
    node T_189936 = or(mem_ctrl.branch, mem_ctrl.jalr)
    node T_189937 = or(T_189936, mem_ctrl.jal)
    node mem_misprediction = and(T_189935, T_189937)
    node T_189938 = or(mem_misprediction, mem_reg_flush_pipe)
    node want_take_pc_mem = and(mem_reg_valid, T_189938)
    node T_189939 = eq(mem_npc_misaligned, UInt<1>(0))
    node T_189940 = and(want_take_pc_mem, T_189939)
    take_pc_mem := T_189940
    node T_189941 = eq(ctrl_killx, UInt<1>(0))
    mem_reg_valid := T_189941
    node T_189942 = eq(take_pc_mem_wb, UInt<1>(0))
    node T_189943 = and(T_189942, replay_ex)
    mem_reg_replay := T_189943
    node T_189944 = eq(ctrl_killx, UInt<1>(0))
    node T_189945 = and(T_189944, ex_xcpt)
    mem_reg_xcpt := T_189945
    node T_189946 = eq(take_pc_mem_wb, UInt<1>(0))
    node T_189947 = and(T_189946, ex_reg_xcpt_interrupt)
    mem_reg_xcpt_interrupt := T_189947
    when ex_xcpt : mem_reg_cause := ex_cause
    
    node T_189948 = or(ex_reg_valid, ex_reg_xcpt_interrupt)
    when T_189948 : 
      mem_ctrl := ex_ctrl
      mem_reg_btb_hit := ex_reg_btb_hit
      when ex_reg_btb_hit : mem_reg_btb_resp := ex_reg_btb_resp
      mem_reg_flush_pipe := ex_reg_flush_pipe
      mem_reg_slow_bypass := ex_slow_bypass
      mem_reg_inst := ex_reg_inst
      mem_reg_pc := ex_reg_pc
      mem_reg_wdata := alu.out
      
      
      node T_189949 = or(ex_ctrl.mem__, ex_ctrl.rocc)
      node T_189950 = and(ex_ctrl.rxs2, T_189949)
      when T_189950 : mem_reg_rs2 := T_189660
    node T_189951 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt)
    node T_189952 = and(want_take_pc_mem, mem_npc_misaligned)
    node T_189953 = and(mem_reg_valid, mem_ctrl.mem__)
    node T_189954 = and(T_189953, dmem.xcpt.ma.st)
    node T_189955 = and(mem_reg_valid, mem_ctrl.mem__)
    node T_189956 = and(T_189955, dmem.xcpt.ma.ld)
    node T_189957 = and(mem_reg_valid, mem_ctrl.mem__)
    node T_189958 = and(T_189957, dmem.xcpt.pf.st)
    node T_189959 = and(mem_reg_valid, mem_ctrl.mem__)
    node T_189960 = and(T_189959, dmem.xcpt.pf.ld)
    node T_189961 = or(T_189951, T_189952)
    node T_189962 = or(T_189961, T_189954)
    node T_189963 = or(T_189962, T_189956)
    node T_189964 = or(T_189963, T_189958)
    node mem_xcpt = or(T_189964, T_189960)
    wire T_189965 : UInt<3>
    T_189965 := UInt<3>(5)
    when T_189958 : T_189965 := UInt<3>(7)
    wire T_189966 : UInt<3>
    T_189966 := T_189965
    when T_189956 : T_189966 := UInt<3>(4)
    wire T_189967 : UInt<3>
    T_189967 := T_189966
    when T_189954 : T_189967 := UInt<3>(6)
    wire T_189968 : UInt<3>
    T_189968 := T_189967
    when T_189952 : T_189968 := UInt<1>(0)
    wire mem_cause : UInt<3>
    mem_cause := T_189968
    when T_189951 : mem_cause := mem_reg_cause
    node T_189969 = and(mem_reg_valid, mem_ctrl.wxd)
    node dcache_kill_mem = and(T_189969, dmem.replay_next.valid)
    node T_189970 = and(mem_reg_valid, mem_ctrl.fp)
    node fpu_kill_mem = and(T_189970, fpu.nack_mem)
    node T_189971 = or(dcache_kill_mem, mem_reg_replay)
    node replay_mem = or(T_189971, fpu_kill_mem)
    node T_189972 = or(dcache_kill_mem, take_pc_wb)
    node T_189973 = or(T_189972, mem_reg_xcpt)
    node T_189974 = eq(mem_reg_valid, UInt<1>(0))
    node killm_common = or(T_189973, T_189974)
    node T_189975 = and(div.req.ready, div.req.valid)
    reg T_189976 : UInt<1>
    T_189976 := T_189975
    node T_189977 = and(killm_common, T_189976)
    div.kill := T_189977
    node T_189978 = or(killm_common, mem_xcpt)
    node ctrl_killm = or(T_189978, fpu_kill_mem)
    node T_189979 = eq(ctrl_killm, UInt<1>(0))
    wb_reg_valid := T_189979
    node T_189980 = eq(take_pc_wb, UInt<1>(0))
    node T_189981 = and(replay_mem, T_189980)
    wb_reg_replay := T_189981
    node T_189982 = eq(take_pc_wb, UInt<1>(0))
    node T_189983 = and(mem_xcpt, T_189982)
    wb_reg_xcpt := T_189983
    when mem_xcpt : wb_reg_cause := mem_cause
    
    
    node T_189984 = or(mem_reg_valid, mem_reg_replay)
    node T_189985 = or(T_189984, mem_reg_xcpt_interrupt)
    when T_189985 : 
      wb_ctrl := mem_ctrl
      node T_189986 = and(mem_ctrl.fp, mem_ctrl.wxd)
      wire T_189987 : UInt
      T_189987 := mem_int_wdata
      when T_189986 : T_189987 := fpu.toint_data
      wb_reg_wdata := T_189987
      when mem_ctrl.rocc : wb_reg_rs2 := mem_reg_rs2
      wb_reg_inst := mem_reg_inst
      wb_reg_pc := mem_reg_pc
    node T_189988 = or(wb_ctrl.div, wb_dcache_miss)
    node wb_set_sboard = or(T_189988, wb_ctrl.rocc)
    node T_189989 = or(dmem.resp.bits.nack, wb_reg_replay)
    node replay_wb_common = or(T_189989, csr.csr_replay)
    node T_189990 = and(wb_reg_valid, wb_ctrl.rocc)
    node T_189991 = eq(replay_wb_common, UInt<1>(0))
    node wb_rocc_val = and(T_189990, T_189991)
    node T_189992 = and(wb_reg_valid, wb_ctrl.rocc)
    node T_189993 = eq(rocc.cmd.ready, UInt<1>(0))
    node T_189994 = and(T_189992, T_189993)
    node replay_wb = or(replay_wb_common, T_189994)
    node wb_xcpt = or(wb_reg_xcpt, csr.csr_xcpt)
    node T_189995 = or(replay_wb, wb_xcpt)
    node T_189996 = or(T_189995, csr.eret)
    take_pc_wb := T_189996
    when wb_rocc_val : 
      node T_189997 = eq(rocc.cmd.ready, UInt<1>(0))
      wb_reg_rocc_pending := T_189997
    when wb_reg_xcpt : wb_reg_rocc_pending := UInt<1>(0)
    node T_189998 = bit(dmem.resp.bits.tag, 0)
    node T_189999 = bit(T_189998, 0)
    node dmem_resp_xpu = eq(T_189999, UInt<1>(0))
    node T_190000 = bit(dmem.resp.bits.tag, 0)
    node dmem_resp_fpu = bit(T_190000, 0)
    node dmem_resp_waddr = dshr(dmem.resp.bits.tag, UInt<1>(1))
    node dmem_resp_valid = and(dmem.resp.valid, dmem.resp.bits.has_data)
    node dmem_resp_replay = and(dmem.resp.bits.replay, dmem.resp.bits.has_data)
    node T_190001 = and(wb_reg_valid, wb_ctrl.wxd)
    node T_190002 = eq(T_190001, UInt<1>(0))
    div.resp.ready := T_190002
    wire ll_wdata : UInt<64>
    ll_wdata := div.resp.bits.data
    wire ll_waddr : UInt<5>
    ll_waddr := div.resp.bits.tag
    node T_190003 = and(div.resp.ready, div.resp.valid)
    wire ll_wen : UInt<1>
    ll_wen := T_190003
    
    node T_190004 = and(dmem_resp_replay, dmem_resp_xpu)
    when T_190004 : 
      div.resp.ready := UInt<1>(0)
      ll_waddr := dmem_resp_waddr
      ll_wen := UInt<1>(1)
    node T_190005 = eq(replay_wb, UInt<1>(0))
    node T_190006 = and(wb_reg_valid, T_190005)
    node T_190007 = eq(csr.csr_xcpt, UInt<1>(0))
    node wb_valid = and(T_190006, T_190007)
    node wb_wen = and(wb_valid, wb_ctrl.wxd)
    node rf_wen = or(wb_wen, ll_wen)
    wire rf_waddr : UInt<5>
    rf_waddr := wb_waddr
    when ll_wen : rf_waddr := ll_waddr
    node T_190008 = and(dmem_resp_valid, dmem_resp_xpu)
    node T_190009 = neq(wb_ctrl.csr, UInt<3>(0))
    wire T_190010 : UInt
    T_190010 := wb_reg_wdata
    when T_190009 : T_190010 := csr.rw.rdata
    wire T_190011 : UInt
    T_190011 := T_190010
    when ll_wen : T_190011 := ll_wdata
    wire rf_wdata : UInt
    rf_wdata := T_190011
    when T_190008 : rf_wdata := dmem.resp.bits.data_subword
    when rf_wen : 
      node T_190012 = neq(rf_waddr, UInt<1>(0))
      when T_190012 : 
        node T_190013 = not(rf_waddr)
        accessor T_190014 = T_189576[T_190013]
        T_190014 := rf_wdata
        
        node T_190015 = eq(rf_waddr, id_raddr1)
        when T_190015 : T_189577 := rf_wdata
        
        node T_190016 = eq(rf_waddr, id_raddr2)
        when T_190016 : T_189580 := rf_wdata
    csr.exception := wb_reg_xcpt
    csr.cause := wb_reg_cause
    csr.retire := wb_valid
    csr.host <> host
    fpu.fcsr_rm := csr.fcsr_rm
    csr.fcsr_flags := fpu.fcsr_flags
    csr.rocc <> rocc
    csr.pc := wb_reg_pc
    csr.uarch_counters[0] := UInt<1>(0)
    csr.uarch_counters[1] := UInt<1>(0)
    csr.uarch_counters[2] := UInt<1>(0)
    csr.uarch_counters[3] := UInt<1>(0)
    csr.uarch_counters[4] := UInt<1>(0)
    csr.uarch_counters[5] := UInt<1>(0)
    csr.uarch_counters[6] := UInt<1>(0)
    csr.uarch_counters[7] := UInt<1>(0)
    csr.uarch_counters[8] := UInt<1>(0)
    csr.uarch_counters[9] := UInt<1>(0)
    csr.uarch_counters[10] := UInt<1>(0)
    csr.uarch_counters[11] := UInt<1>(0)
    csr.uarch_counters[12] := UInt<1>(0)
    csr.uarch_counters[13] := UInt<1>(0)
    csr.uarch_counters[14] := UInt<1>(0)
    csr.uarch_counters[15] := UInt<1>(0)
    ptw.ptbr := csr.ptbr
    ptw.invalidate := csr.fatc
    ptw.status := csr.status
    node T_190017 = bits(wb_reg_inst, 31, 20)
    csr.rw.addr := T_190017
    wire T_190018 : UInt<3>
    T_190018 := UInt<3>(0)
    when wb_reg_valid : T_190018 := wb_ctrl.csr
    csr.rw.cmd := T_190018
    csr.rw.wdata := wb_reg_wdata
    node T_190019 = neq(id_raddr1, UInt<1>(0))
    node T_190020 = and(id_ctrl.rxs1, T_190019)
    node T_190021 = neq(id_raddr2, UInt<1>(0))
    node T_190022 = and(id_ctrl.rxs2, T_190021)
    node T_190023 = neq(id_waddr, UInt<1>(0))
    node T_190024 = and(id_ctrl.wxd, T_190023)
    reg T_190025 : UInt<32>
    onreset T_190025 := UInt<32>(0)
    node T_190026 = dshl(UInt<1>(1), ll_waddr)
    wire T_190027 : UInt<1>
    T_190027 := UInt<1>(0)
    when ll_wen : T_190027 := T_190026
    node T_190028 = not(T_190027)
    node T_190029 = and(T_190025, T_190028)
    node T_190030 = or(UInt<1>(0), ll_wen)
    when T_190030 : T_190025 := T_190029
    node T_190031 = dshr(T_190029, id_raddr1)
    node T_190032 = bit(T_190031, 0)
    node T_190033 = and(T_190020, T_190032)
    node T_190034 = dshr(T_190029, id_raddr2)
    node T_190035 = bit(T_190034, 0)
    node T_190036 = and(T_190022, T_190035)
    node T_190037 = dshr(T_190029, id_waddr)
    node T_190038 = bit(T_190037, 0)
    node T_190039 = and(T_190024, T_190038)
    node T_190040 = or(T_190033, T_190036)
    node id_sboard_hazard = or(T_190040, T_190039)
    node T_190041 = and(wb_set_sboard, wb_wen)
    node T_190042 = dshl(UInt<1>(1), wb_waddr)
    wire T_190043 : UInt<1>
    T_190043 := UInt<1>(0)
    when T_190041 : T_190043 := T_190042
    node T_190044 = or(T_190029, T_190043)
    node T_190045 = or(T_190030, T_190041)
    when T_190045 : T_190025 := T_190044
    node T_190046 = neq(ex_ctrl.csr, UInt<3>(0))
    node T_190047 = or(T_190046, ex_ctrl.jalr)
    node T_190048 = or(T_190047, ex_ctrl.mem__)
    node T_190049 = or(T_190048, ex_ctrl.div)
    node T_190050 = or(T_190049, ex_ctrl.fp)
    node ex_cannot_bypass = or(T_190050, ex_ctrl.rocc)
    node T_190051 = eq(id_raddr1, ex_waddr)
    node T_190052 = and(T_190020, T_190051)
    node T_190053 = eq(id_raddr2, ex_waddr)
    node T_190054 = and(T_190022, T_190053)
    node T_190055 = eq(id_waddr, ex_waddr)
    node T_190056 = and(T_190024, T_190055)
    node T_190057 = or(T_190052, T_190054)
    node T_190058 = or(T_190057, T_190056)
    node data_hazard_ex = and(ex_ctrl.wxd, T_190058)
    node T_190059 = eq(id_raddr1, ex_waddr)
    node T_190060 = and(fpu.dec.ren1, T_190059)
    node T_190061 = eq(id_raddr2, ex_waddr)
    node T_190062 = and(fpu.dec.ren2, T_190061)
    node T_190063 = eq(id_raddr3, ex_waddr)
    node T_190064 = and(fpu.dec.ren3, T_190063)
    node T_190065 = eq(id_waddr, ex_waddr)
    node T_190066 = and(fpu.dec.wen, T_190065)
    node T_190067 = or(T_190060, T_190062)
    node T_190068 = or(T_190067, T_190064)
    node T_190069 = or(T_190068, T_190066)
    node fp_data_hazard_ex = and(ex_ctrl.wfd, T_190069)
    node T_190070 = and(data_hazard_ex, ex_cannot_bypass)
    node T_190071 = or(T_190070, fp_data_hazard_ex)
    node id_ex_hazard = and(ex_reg_valid, T_190071)
    node mem_mem_cmd_bh = and(UInt<1>(1), mem_reg_slow_bypass)
    node T_190072 = neq(mem_ctrl.csr, UInt<3>(0))
    node T_190073 = and(mem_ctrl.mem__, mem_mem_cmd_bh)
    node T_190074 = or(T_190072, T_190073)
    node T_190075 = or(T_190074, mem_ctrl.div)
    node T_190076 = or(T_190075, mem_ctrl.fp)
    node mem_cannot_bypass = or(T_190076, mem_ctrl.rocc)
    node T_190077 = eq(id_raddr1, mem_waddr)
    node T_190078 = and(T_190020, T_190077)
    node T_190079 = eq(id_raddr2, mem_waddr)
    node T_190080 = and(T_190022, T_190079)
    node T_190081 = eq(id_waddr, mem_waddr)
    node T_190082 = and(T_190024, T_190081)
    node T_190083 = or(T_190078, T_190080)
    node T_190084 = or(T_190083, T_190082)
    node data_hazard_mem = and(mem_ctrl.wxd, T_190084)
    node T_190085 = eq(id_raddr1, mem_waddr)
    node T_190086 = and(fpu.dec.ren1, T_190085)
    node T_190087 = eq(id_raddr2, mem_waddr)
    node T_190088 = and(fpu.dec.ren2, T_190087)
    node T_190089 = eq(id_raddr3, mem_waddr)
    node T_190090 = and(fpu.dec.ren3, T_190089)
    node T_190091 = eq(id_waddr, mem_waddr)
    node T_190092 = and(fpu.dec.wen, T_190091)
    node T_190093 = or(T_190086, T_190088)
    node T_190094 = or(T_190093, T_190090)
    node T_190095 = or(T_190094, T_190092)
    node fp_data_hazard_mem = and(mem_ctrl.wfd, T_190095)
    node T_190096 = and(data_hazard_mem, mem_cannot_bypass)
    node T_190097 = or(T_190096, fp_data_hazard_mem)
    node id_mem_hazard = and(mem_reg_valid, T_190097)
    node T_190098 = and(mem_reg_valid, data_hazard_mem)
    node T_190099 = and(T_190098, mem_ctrl.mem__)
    id_load_use := T_190099
    node T_190100 = eq(id_raddr1, wb_waddr)
    node T_190101 = and(T_190020, T_190100)
    node T_190102 = eq(id_raddr2, wb_waddr)
    node T_190103 = and(T_190022, T_190102)
    node T_190104 = eq(id_waddr, wb_waddr)
    node T_190105 = and(T_190024, T_190104)
    node T_190106 = or(T_190101, T_190103)
    node T_190107 = or(T_190106, T_190105)
    node data_hazard_wb = and(wb_ctrl.wxd, T_190107)
    node T_190108 = eq(id_raddr1, wb_waddr)
    node T_190109 = and(fpu.dec.ren1, T_190108)
    node T_190110 = eq(id_raddr2, wb_waddr)
    node T_190111 = and(fpu.dec.ren2, T_190110)
    node T_190112 = eq(id_raddr3, wb_waddr)
    node T_190113 = and(fpu.dec.ren3, T_190112)
    node T_190114 = eq(id_waddr, wb_waddr)
    node T_190115 = and(fpu.dec.wen, T_190114)
    node T_190116 = or(T_190109, T_190111)
    node T_190117 = or(T_190116, T_190113)
    node T_190118 = or(T_190117, T_190115)
    node fp_data_hazard_wb = and(wb_ctrl.wfd, T_190118)
    node T_190119 = and(data_hazard_wb, wb_set_sboard)
    node T_190120 = or(T_190119, fp_data_hazard_wb)
    node id_wb_hazard = and(wb_reg_valid, T_190120)
    reg T_190121 : UInt<32>
    onreset T_190121 := UInt<32>(0)
    node T_190122 = and(wb_dcache_miss, wb_ctrl.wfd)
    node T_190123 = or(T_190122, fpu.sboard_set)
    node T_190124 = and(T_190123, wb_valid)
    node T_190125 = dshl(UInt<1>(1), wb_waddr)
    wire T_190126 : UInt<1>
    T_190126 := UInt<1>(0)
    when T_190124 : T_190126 := T_190125
    node T_190127 = or(T_190121, T_190126)
    node T_190128 = or(UInt<1>(0), T_190124)
    when T_190128 : T_190121 := T_190127
    node T_190129 = and(dmem_resp_replay, dmem_resp_fpu)
    node T_190130 = dshl(UInt<1>(1), dmem_resp_waddr)
    wire T_190131 : UInt<1>
    T_190131 := UInt<1>(0)
    when T_190129 : T_190131 := T_190130
    node T_190132 = not(T_190131)
    node T_190133 = and(T_190127, T_190132)
    node T_190134 = or(T_190128, T_190129)
    when T_190134 : T_190121 := T_190133
    node T_190135 = dshl(UInt<1>(1), fpu.sboard_clra)
    wire T_190136 : UInt<1>
    T_190136 := UInt<1>(0)
    when fpu.sboard_clr : T_190136 := T_190135
    node T_190137 = not(T_190136)
    node T_190138 = and(T_190133, T_190137)
    node T_190139 = or(T_190134, fpu.sboard_clr)
    when T_190139 : T_190121 := T_190138
    node T_190140 = eq(fpu.fcsr_rdy, UInt<1>(0))
    node T_190141 = and(id_csr_en, T_190140)
    node T_190142 = dshr(T_190121, id_raddr1)
    node T_190143 = bit(T_190142, 0)
    node T_190144 = and(fpu.dec.ren1, T_190143)
    node T_190145 = dshr(T_190121, id_raddr2)
    node T_190146 = bit(T_190145, 0)
    node T_190147 = and(fpu.dec.ren2, T_190146)
    node T_190148 = dshr(T_190121, id_raddr3)
    node T_190149 = bit(T_190148, 0)
    node T_190150 = and(fpu.dec.ren3, T_190149)
    node T_190151 = dshr(T_190121, id_waddr)
    node T_190152 = bit(T_190151, 0)
    node T_190153 = and(fpu.dec.wen, T_190152)
    node T_190154 = or(T_190144, T_190147)
    node T_190155 = or(T_190154, T_190150)
    node T_190156 = or(T_190155, T_190153)
    node id_stall_fpu = or(T_190141, T_190156)
    node T_190157 = or(id_ex_hazard, id_mem_hazard)
    node T_190158 = or(T_190157, id_wb_hazard)
    node T_190159 = or(T_190158, id_sboard_hazard)
    node T_190160 = and(id_ctrl.fp, id_stall_fpu)
    node T_190161 = or(T_190159, T_190160)
    node T_190162 = eq(dmem.req.ready, UInt<1>(0))
    node T_190163 = and(id_ctrl.mem__, T_190162)
    node T_190164 = or(T_190161, T_190163)
    node T_190165 = and(UInt<1>(0), wb_reg_rocc_pending)
    node T_190166 = and(T_190165, id_ctrl.rocc)
    node T_190167 = eq(rocc.cmd.ready, UInt<1>(0))
    node T_190168 = and(T_190166, T_190167)
    node T_190169 = or(T_190164, T_190168)
    node T_190170 = or(T_190169, id_do_fence)
    node ctrl_stalld = or(T_190170, csr.csr_stall)
    node T_190171 = eq(imem.resp.valid, UInt<1>(0))
    node T_190172 = or(T_190171, take_pc_mem_wb)
    node T_190173 = or(T_190172, ctrl_stalld)
    node T_190174 = or(T_190173, csr.interrupt)
    ctrl_killd := T_190174
    imem.req.valid := take_pc_mem_wb
    node T_190175 = or(wb_xcpt, csr.eret)
    wire T_190176 : UInt
    T_190176 := mem_npc
    when replay_wb : T_190176 := wb_reg_pc
    wire T_190177 : UInt
    T_190177 := T_190176
    when T_190175 : T_190177 := csr.evec
    imem.req.bits.pc := T_190177
    node T_190178 = and(wb_reg_valid, wb_ctrl.fence_i)
    imem.invalidate := T_190178
    node T_190179 = eq(ctrl_stalld, UInt<1>(0))
    node T_190180 = or(T_190179, csr.interrupt)
    imem.resp.ready := T_190180
    node T_190181 = eq(mem_npc_misaligned, UInt<1>(0))
    node T_190182 = and(mem_reg_valid, T_190181)
    node T_190183 = and(T_190182, mem_wrong_npc)
    node T_190184 = and(mem_ctrl.branch, mem_br_taken)
    node T_190185 = or(T_190184, mem_ctrl.jalr)
    node T_190186 = or(T_190185, mem_ctrl.jal)
    node T_190187 = and(T_190183, T_190186)
    node T_190188 = eq(take_pc_wb, UInt<1>(0))
    node T_190189 = and(T_190187, T_190188)
    imem.btb_update.valid := T_190189
    node T_190190 = or(mem_ctrl.jal, mem_ctrl.jalr)
    imem.btb_update.bits.isJump := T_190190
    node T_190191 = bits(mem_reg_inst, 19, 15)
    node T_190192 = and(T_190191, UInt<5>(25))
    node T_190193 = eq(UInt<1>(1), T_190192)
    node T_190194 = and(mem_ctrl.jalr, T_190193)
    imem.btb_update.bits.isReturn := T_190194
    imem.btb_update.bits.pc := mem_reg_pc
    imem.btb_update.bits.target := imem.req.bits.pc
    imem.btb_update.bits.br_pc := mem_reg_pc
    imem.btb_update.bits.prediction.valid := mem_reg_btb_hit
    imem.btb_update.bits.prediction.bits := mem_reg_btb_resp
    node T_190195 = and(mem_reg_valid, mem_ctrl.branch)
    node T_190196 = eq(take_pc_wb, UInt<1>(0))
    node T_190197 = and(T_190195, T_190196)
    imem.bht_update.valid := T_190197
    imem.bht_update.bits.pc := mem_reg_pc
    imem.bht_update.bits.taken := mem_br_taken
    imem.bht_update.bits.mispredict := mem_wrong_npc
    imem.bht_update.bits.prediction := imem.btb_update.bits.prediction
    node T_190198 = and(mem_reg_valid, imem.btb_update.bits.isJump)
    node T_190199 = eq(mem_npc_misaligned, UInt<1>(0))
    node T_190200 = and(T_190198, T_190199)
    node T_190201 = eq(take_pc_wb, UInt<1>(0))
    node T_190202 = and(T_190200, T_190201)
    imem.ras_update.valid := T_190202
    imem.ras_update.bits.returnAddr := mem_int_wdata
    node T_190203 = bit(mem_waddr, 0)
    node T_190204 = and(mem_ctrl.wxd, T_190203)
    imem.ras_update.bits.isCall := T_190204
    imem.ras_update.bits.isReturn := imem.btb_update.bits.isReturn
    imem.ras_update.bits.prediction := imem.btb_update.bits.prediction
    node T_190205 = eq(ctrl_killd, UInt<1>(0))
    node T_190206 = and(T_190205, id_ctrl.fp)
    fpu.valid := T_190206
    fpu.killx := ctrl_killx
    fpu.killm := killm_common
    fpu.inst__ := imem.resp.bits.data[0]
    fpu.fromint_data := T_189657
    node T_190207 = and(dmem_resp_valid, dmem_resp_fpu)
    fpu.dmem_resp_val := T_190207
    fpu.dmem_resp_data := dmem.resp.bits.data
    fpu.dmem_resp_type := dmem.resp.bits.typ
    fpu.dmem_resp_tag := dmem_resp_waddr
    node T_190208 = and(ex_reg_valid, ex_ctrl.mem__)
    dmem.req.valid := T_190208
    node T_190209 = or(killm_common, mem_xcpt)
    dmem.req.bits.kill := T_190209
    dmem.req.bits.cmd := ex_ctrl.mem_cmd
    dmem.req.bits.typ := ex_ctrl.mem_type
    dmem.req.bits.phys := UInt<1>(0)
    node T_190210 = shr(T_189657, 38)
    node T_190211 = bits(alu.adder_out, 39, 38)
    node T_190212 = eq(T_190210, UInt<1>(0))
    node T_190213 = eq(T_190210, UInt<1>(1))
    node T_190214 = or(T_190212, T_190213)
    node T_190215 = neq(T_190211, UInt<1>(0))
    node T_190216 = eq(T_190210, SInt<1>(-1))
    node T_190217 = eq(T_190210, SInt<2>(-2))
    node T_190218 = or(T_190216, T_190217)
    node T_190219 = eq(T_190211, SInt<1>(-1))
    node T_190220 = bit(T_190211, 0)
    wire T_190221 : UInt<1>
    T_190221 := T_190220
    when T_190218 : T_190221 := T_190219
    wire T_190222 : UInt<1>
    T_190222 := T_190221
    when T_190214 : T_190222 := T_190215
    node T_190223 = bits(alu.adder_out, 38, 0)
    node T_190224 = cat(T_190222, T_190223)
    dmem.req.bits.addr := T_190224
    node T_190225 = cat(ex_waddr, ex_ctrl.fp)
    dmem.req.bits.tag := T_190225
    wire T_190226 : UInt
    T_190226 := mem_reg_rs2
    when mem_ctrl.fp : T_190226 := fpu.store_data
    dmem.req.bits.data := T_190226
    dmem.invalidate_lr := wb_xcpt
    rocc.cmd.valid := wb_rocc_val
    node T_190227 = eq(csr.status.xs, UInt<1>(0))
    node T_190228 = eq(T_190227, UInt<1>(0))
    node T_190229 = and(wb_xcpt, T_190228)
    rocc.exception := T_190229
    node T_190230 = eq(csr.status.prv, UInt<1>(0))
    node T_190231 = eq(T_190230, UInt<1>(0))
    rocc.s := T_190231
    wire T_190232 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}
    node T_190233 = bits(wb_reg_inst, 6, 0)
    T_190232.opcode := T_190233
    node T_190234 = bits(wb_reg_inst, 11, 7)
    T_190232.rd := T_190234
    node T_190235 = bits(wb_reg_inst, 12, 12)
    T_190232.xs2 := T_190235
    node T_190236 = bits(wb_reg_inst, 13, 13)
    T_190232.xs1 := T_190236
    node T_190237 = bits(wb_reg_inst, 14, 14)
    T_190232.xd := T_190237
    node T_190238 = bits(wb_reg_inst, 19, 15)
    T_190232.rs1 := T_190238
    node T_190239 = bits(wb_reg_inst, 24, 20)
    T_190232.rs2 := T_190239
    node T_190240 = bits(wb_reg_inst, 31, 25)
    T_190232.funct := T_190240
    rocc.cmd.bits.inst__ := T_190232
    rocc.cmd.bits.rs1 := wb_reg_wdata
    rocc.cmd.bits.rs2 := wb_reg_rs2
    node T_190241 = bits(csr.time, 32, 0)
    wire T_190242 : UInt<1>
    T_190242 := UInt<1>(0)
    when rf_wen : T_190242 := rf_waddr
    node T_190243 = bits(wb_reg_inst, 19, 15)
    reg T_190244 : UInt
    T_190244 := T_189657
    reg T_190245 : UInt
    T_190245 := T_190244
    node T_190246 = bits(wb_reg_inst, 24, 20)
    reg T_190247 : UInt
    T_190247 := T_189660
    reg T_190248 : UInt
    T_190248 := T_190247
  module HellaCacheArbiter : 
    input requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2]
    output mem__ : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}
    
    wire requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_subword : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<8>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2]
    requestor[0] := T_190249
    requestor[1] := T_190250
    reg T_190251 : UInt<1>
    T_190251 := requestor[0].req.valid
    reg T_190252 : UInt<1>
    T_190252 := requestor[1].req.valid
    node T_190253 = or(requestor[0].req.valid, requestor[1].req.valid)
    mem__.req.valid := T_190253
    requestor[0].req.ready := mem__.req.ready
    node T_190254 = eq(requestor[0].req.valid, UInt<1>(0))
    node T_190255 = and(requestor[0].req.ready, T_190254)
    requestor[1].req.ready := T_190255
    mem__.req.bits := requestor[1].req.bits
    node T_190256 = cat(requestor[1].req.bits.tag, UInt<1>(1))
    mem__.req.bits.tag := T_190256
    when requestor[0].req.valid : 
      mem__.req.bits.cmd := requestor[0].req.bits.cmd
      mem__.req.bits.typ := requestor[0].req.bits.typ
      mem__.req.bits.addr := requestor[0].req.bits.addr
      mem__.req.bits.phys := requestor[0].req.bits.phys
      node T_190257 = cat(requestor[0].req.bits.tag, UInt<1>(0))
      mem__.req.bits.tag := T_190257
    when T_190251 : 
      mem__.req.bits.kill := requestor[0].req.bits.kill
      mem__.req.bits.data := requestor[0].req.bits.data
    node T_190258 = bits(mem__.resp.bits.tag, 0, 0)
    node T_190259 = eq(T_190258, UInt<1>(0))
    node T_190260 = and(mem__.resp.valid, T_190259)
    requestor[0].resp.valid := T_190260
    requestor[0].xcpt := mem__.xcpt
    requestor[0].ordered := mem__.ordered
    requestor[0].resp.bits := mem__.resp.bits
    node T_190261 = dshr(mem__.resp.bits.tag, UInt<1>(1))
    requestor[0].resp.bits.tag := T_190261
    node T_190262 = and(mem__.resp.bits.nack, T_190259)
    requestor[0].resp.bits.nack := T_190262
    node T_190263 = and(mem__.resp.bits.replay, T_190259)
    requestor[0].resp.bits.replay := T_190263
    node T_190264 = bits(mem__.replay_next.bits, 0, 0)
    node T_190265 = eq(T_190264, UInt<1>(0))
    node T_190266 = and(mem__.replay_next.valid, T_190265)
    requestor[0].replay_next.valid := T_190266
    node T_190267 = dshr(mem__.replay_next.bits, UInt<1>(1))
    requestor[0].replay_next.bits := T_190267
    node T_190268 = bits(mem__.resp.bits.tag, 0, 0)
    node T_190269 = eq(T_190268, UInt<1>(1))
    node T_190270 = and(mem__.resp.valid, T_190269)
    requestor[1].resp.valid := T_190270
    requestor[1].xcpt := mem__.xcpt
    requestor[1].ordered := mem__.ordered
    requestor[1].resp.bits := mem__.resp.bits
    node T_190271 = dshr(mem__.resp.bits.tag, UInt<1>(1))
    requestor[1].resp.bits.tag := T_190271
    node T_190272 = and(mem__.resp.bits.nack, T_190269)
    requestor[1].resp.bits.nack := T_190272
    node T_190273 = and(mem__.resp.bits.replay, T_190269)
    requestor[1].resp.bits.replay := T_190273
    node T_190274 = bits(mem__.replay_next.bits, 0, 0)
    node T_190275 = eq(T_190274, UInt<1>(1))
    node T_190276 = and(mem__.replay_next.valid, T_190275)
    requestor[1].replay_next.valid := T_190276
    node T_190277 = dshr(mem__.replay_next.bits, UInt<1>(1))
    requestor[1].replay_next.bits := T_190277
  module FPUDecoder : 
    input inst__ : UInt<32>
    output sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}
    
    node T_190278 = and(inst__, UInt<32>(4))
    node T_190279 = eq(T_190278, UInt<32>(4))
    node T_190280 = and(inst__, UInt<32>(134217744))
    node T_190281 = eq(T_190280, UInt<32>(134217744))
    node T_190282 = or(UInt<1>(0), T_190279)
    node T_190283 = or(T_190282, T_190281)
    node T_190284 = and(inst__, UInt<32>(8))
    node T_190285 = eq(T_190284, UInt<32>(8))
    node T_190286 = and(inst__, UInt<32>(268435472))
    node T_190287 = eq(T_190286, UInt<32>(268435472))
    node T_190288 = or(UInt<1>(0), T_190285)
    node T_190289 = or(T_190288, T_190287)
    node T_190290 = and(inst__, UInt<32>(64))
    node T_190291 = eq(T_190290, UInt<32>(0))
    node T_190292 = and(inst__, UInt<32>(536870912))
    node T_190293 = eq(T_190292, UInt<32>(536870912))
    node T_190294 = or(UInt<1>(0), T_190291)
    node T_190295 = or(T_190294, T_190293)
    node T_190296 = and(inst__, UInt<32>(1073741824))
    node T_190297 = eq(T_190296, UInt<32>(1073741824))
    node T_190298 = or(UInt<1>(0), T_190291)
    node T_190299 = or(T_190298, T_190297)
    node T_190300 = and(inst__, UInt<32>(16))
    node T_190301 = eq(T_190300, UInt<32>(0))
    node T_190302 = or(UInt<1>(0), T_190301)
    node T_190303 = cat(T_190289, T_190283)
    node T_190304 = cat(T_190295, T_190303)
    node T_190305 = cat(T_190299, T_190304)
    node T_190306 = cat(T_190302, T_190305)
    node T_190307 = or(UInt<1>(0), T_190291)
    node T_190308 = and(inst__, UInt<32>(2147483680))
    node T_190309 = eq(T_190308, UInt<32>(0))
    node T_190310 = and(inst__, UInt<32>(48))
    node T_190311 = eq(T_190310, UInt<32>(0))
    node T_190312 = and(inst__, UInt<32>(268435488))
    node T_190313 = eq(T_190312, UInt<32>(268435456))
    node T_190314 = or(UInt<1>(0), T_190309)
    node T_190315 = or(T_190314, T_190311)
    node T_190316 = or(T_190315, T_190313)
    node T_190317 = and(inst__, UInt<32>(2147483652))
    node T_190318 = eq(T_190317, UInt<32>(0))
    node T_190319 = and(inst__, UInt<32>(268435460))
    node T_190320 = eq(T_190319, UInt<32>(0))
    node T_190321 = and(inst__, UInt<32>(80))
    node T_190322 = eq(T_190321, UInt<32>(64))
    node T_190323 = or(UInt<1>(0), T_190318)
    node T_190324 = or(T_190323, T_190320)
    node T_190325 = or(T_190324, T_190322)
    node T_190326 = and(inst__, UInt<32>(1073741828))
    node T_190327 = eq(T_190326, UInt<32>(0))
    node T_190328 = and(inst__, UInt<32>(32))
    node T_190329 = eq(T_190328, UInt<32>(32))
    node T_190330 = or(UInt<1>(0), T_190327)
    node T_190331 = or(T_190330, T_190329)
    node T_190332 = or(T_190331, T_190322)
    node T_190333 = or(UInt<1>(0), T_190322)
    node T_190334 = and(inst__, UInt<32>(1342177296))
    node T_190335 = eq(T_190334, UInt<32>(1342177296))
    node T_190336 = or(UInt<1>(0), T_190291)
    node T_190337 = or(T_190336, T_190335)
    node T_190338 = and(inst__, UInt<32>(805306384))
    node T_190339 = eq(T_190338, UInt<32>(16))
    node T_190340 = or(UInt<1>(0), T_190339)
    node T_190341 = and(inst__, UInt<32>(4160))
    node T_190342 = eq(T_190341, UInt<32>(0))
    node T_190343 = and(inst__, UInt<32>(33554496))
    node T_190344 = eq(T_190343, UInt<32>(64))
    node T_190345 = or(UInt<1>(0), T_190342)
    node T_190346 = or(T_190345, T_190344)
    node T_190347 = and(inst__, UInt<32>(2415919120))
    node T_190348 = eq(T_190347, UInt<32>(2415919120))
    node T_190349 = or(UInt<1>(0), T_190348)
    node T_190350 = and(inst__, UInt<32>(2415919120))
    node T_190351 = eq(T_190350, UInt<32>(2147483664))
    node T_190352 = or(UInt<1>(0), T_190329)
    node T_190353 = or(T_190352, T_190351)
    node T_190354 = and(inst__, UInt<32>(2684354576))
    node T_190355 = eq(T_190354, UInt<32>(536870928))
    node T_190356 = and(inst__, UInt<32>(3489660944))
    node T_190357 = eq(T_190356, UInt<32>(1073741840))
    node T_190358 = or(UInt<1>(0), T_190355)
    node T_190359 = or(T_190358, T_190357)
    node T_190360 = and(inst__, UInt<32>(1879048196))
    node T_190361 = eq(T_190360, UInt<32>(0))
    node T_190362 = and(inst__, UInt<32>(1744830468))
    node T_190363 = eq(T_190362, UInt<32>(0))
    node T_190364 = or(UInt<1>(0), T_190361)
    node T_190365 = or(T_190364, T_190363)
    node T_190366 = or(T_190365, T_190322)
    node T_190367 = and(inst__, UInt<32>(1476395024))
    node T_190368 = eq(T_190367, UInt<32>(402653200))
    node T_190369 = or(UInt<1>(0), T_190368)
    node T_190370 = and(inst__, UInt<32>(3489660944))
    node T_190371 = eq(T_190370, UInt<32>(1342177296))
    node T_190372 = or(UInt<1>(0), T_190371)
    node T_190373 = and(inst__, UInt<32>(536870916))
    node T_190374 = eq(T_190373, UInt<32>(0))
    node T_190375 = and(inst__, UInt<32>(1073750016))
    node T_190376 = eq(T_190375, UInt<32>(1073741824))
    node T_190377 = or(UInt<1>(0), T_190374)
    node T_190378 = or(T_190377, T_190322)
    node T_190379 = or(T_190378, T_190376)
    node T_190380 = and(inst__, UInt<32>(134225920))
    node T_190381 = eq(T_190380, UInt<32>(134217728))
    node T_190382 = and(inst__, UInt<32>(3221225476))
    node T_190383 = eq(T_190382, UInt<32>(2147483648))
    node T_190384 = or(UInt<1>(0), T_190374)
    node T_190385 = or(T_190384, T_190322)
    node T_190386 = or(T_190385, T_190381)
    node T_190387 = or(T_190386, T_190383)
    wire T_190388 : UInt<5>[17]
    T_190388[0] := sigs.cmd
    T_190388[1] := sigs.ldst
    T_190388[2] := sigs.wen
    T_190388[3] := sigs.ren1
    T_190388[4] := sigs.ren2
    T_190388[5] := sigs.ren3
    T_190388[6] := sigs.swap12
    T_190388[7] := sigs.swap23
    T_190388[8] := sigs.single
    T_190388[9] := sigs.fromint
    T_190388[10] := sigs.toint
    T_190388[11] := sigs.fastpipe
    T_190388[12] := sigs.fma
    T_190388[13] := sigs.div
    T_190388[14] := sigs.sqrt
    T_190388[15] := sigs.round
    T_190388[16] := sigs.wflags
    T_190388[0] := T_190306
    T_190388[1] := T_190307
    T_190388[2] := T_190316
    T_190388[3] := T_190325
    T_190388[4] := T_190332
    T_190388[5] := T_190333
    T_190388[6] := T_190337
    T_190388[7] := T_190340
    T_190388[8] := T_190346
    T_190388[9] := T_190349
    T_190388[10] := T_190353
    T_190388[11] := T_190359
    T_190388[12] := T_190366
    T_190388[13] := T_190369
    T_190388[14] := T_190372
    T_190388[15] := T_190379
    T_190388[16] := T_190387
  module mulAddSubRecodedFloatN : 
    input op : UInt<2>
    input a : UInt<33>
    input b : UInt<33>
    input c : UInt<33>
    input roundingMode : UInt<2>
    output out : UInt<33>
    output exceptionFlags : UInt<5>
    
    node signA = bit(a, 32)
    node expA = bits(a, 31, 23)
    node fractA = bits(a, 22, 0)
    node T_190389 = bits(expA, 8, 6)
    node isZeroA = eq(T_190389, UInt<1>(0))
    node T_190390 = bits(expA, 8, 7)
    node isSpecialA = eq(T_190390, UInt<2>(3))
    node T_190391 = bit(expA, 6)
    node T_190392 = eq(T_190391, UInt<1>(0))
    node isInfA = and(isSpecialA, T_190392)
    node T_190393 = bit(expA, 6)
    node isNaNA = and(isSpecialA, T_190393)
    node T_190394 = bit(fractA, 22)
    node T_190395 = eq(T_190394, UInt<1>(0))
    node isSigNaNA = and(isNaNA, T_190395)
    node T_190396 = eq(isZeroA, UInt<1>(0))
    node sigA = cat(T_190396, fractA)
    node signB = bit(b, 32)
    node expB = bits(b, 31, 23)
    node fractB = bits(b, 22, 0)
    node T_190397 = bits(expB, 8, 6)
    node isZeroB = eq(T_190397, UInt<1>(0))
    node T_190398 = bits(expB, 8, 7)
    node isSpecialB = eq(T_190398, UInt<2>(3))
    node T_190399 = bit(expB, 6)
    node T_190400 = eq(T_190399, UInt<1>(0))
    node isInfB = and(isSpecialB, T_190400)
    node T_190401 = bit(expB, 6)
    node isNaNB = and(isSpecialB, T_190401)
    node T_190402 = bit(fractB, 22)
    node T_190403 = eq(T_190402, UInt<1>(0))
    node isSigNaNB = and(isNaNB, T_190403)
    node T_190404 = eq(isZeroB, UInt<1>(0))
    node sigB = cat(T_190404, fractB)
    node T_190405 = bit(c, 32)
    node T_190406 = bit(op, 0)
    node opSignC = xor(T_190405, T_190406)
    node expC = bits(c, 31, 23)
    node fractC = bits(c, 22, 0)
    node T_190407 = bits(expC, 8, 6)
    node isZeroC = eq(T_190407, UInt<1>(0))
    node T_190408 = bits(expC, 8, 7)
    node isSpecialC = eq(T_190408, UInt<2>(3))
    node T_190409 = bit(expC, 6)
    node T_190410 = eq(T_190409, UInt<1>(0))
    node isInfC = and(isSpecialC, T_190410)
    node T_190411 = bit(expC, 6)
    node isNaNC = and(isSpecialC, T_190411)
    node T_190412 = bit(fractC, 22)
    node T_190413 = eq(T_190412, UInt<1>(0))
    node isSigNaNC = and(isNaNC, T_190413)
    node T_190414 = eq(isZeroC, UInt<1>(0))
    node sigC = cat(T_190414, fractC)
    node roundingMode_nearest_even = eq(roundingMode, UInt<2>(0))
    node roundingMode_minMag = eq(roundingMode, UInt<2>(1))
    node roundingMode_min = eq(roundingMode, UInt<2>(2))
    node roundingMode_max = eq(roundingMode, UInt<2>(3))
    node T_190415 = xor(signA, signB)
    node T_190416 = bit(op, 1)
    node signProd = xor(T_190415, T_190416)
    node isZeroProd = or(isZeroA, isZeroB)
    node T_190417 = bit(expB, 8)
    node T_190418 = eq(T_190417, UInt<1>(0))
    node T_190419 = subw(UInt<3>(0), UInt<2>(3))
    node T_190420 = bits(expB, 7, 0)
    node T_190421 = cat(T_190419, T_190420)
    node T_190422 = addw(T_190421, expA)
    node sExpAlignedProd = addw(T_190422, UInt<5>(27))
    node doSubMags = xor(signProd, opSignC)
    node sNatCAlignDist = subw(sExpAlignedProd, expC)
    node T_190423 = bit(sNatCAlignDist, 10)
    node CAlignDist_floor = or(isZeroProd, T_190423)
    node T_190424 = bits(sNatCAlignDist, 9, 0)
    node T_190425 = eq(T_190424, UInt<1>(0))
    node CAlignDist_0 = or(CAlignDist_floor, T_190425)
    node T_190426 = eq(isZeroC, UInt<1>(0))
    node T_190427 = bits(sNatCAlignDist, 9, 0)
    node T_190428 = lt(T_190427, UInt<5>(25))
    node T_190429 = or(CAlignDist_floor, T_190428)
    node isCDominant = and(T_190426, T_190429)
    node T_190430 = bits(sNatCAlignDist, 9, 0)
    node T_190431 = lt(T_190430, UInt<7>(74))
    wire T_190432 : UInt<7>
    T_190432 := UInt<7>(74)
    when T_190431 : T_190432 := sNatCAlignDist
    wire T_190433 : UInt<7>
    T_190433 := T_190432
    when CAlignDist_floor : T_190433 := UInt<1>(0)
    node CAlignDist = bits(T_190433, 6, 0)
    wire sExpSum : UInt<11>
    sExpSum := sExpAlignedProd
    when CAlignDist_floor : sExpSum := expC
    node T_190434 = dshr(SInt<129>(-340282366920938463463374607431768211456), CAlignDist)
    node T_190435 = bits(T_190434, 77, 54)
    node T_190436 = bits(T_190435, 15, 0)
    node T_190437 = dshl(UInt<8>(255), UInt<4>(8))
    node T_190438 = xor(UInt<16>(65535), T_190437)
    node T_190439 = dshr(T_190436, UInt<4>(8))
    node T_190440 = and(T_190439, T_190438)
    node T_190441 = bits(T_190436, 7, 0)
    node T_190442 = dshl(T_190441, UInt<4>(8))
    node T_190443 = not(T_190438)
    node T_190444 = and(T_190442, T_190443)
    node T_190445 = or(T_190440, T_190444)
    node T_190446 = bits(T_190438, 11, 0)
    node T_190447 = dshl(T_190446, UInt<3>(4))
    node T_190448 = xor(T_190438, T_190447)
    node T_190449 = dshr(T_190445, UInt<3>(4))
    node T_190450 = and(T_190449, T_190448)
    node T_190451 = bits(T_190445, 11, 0)
    node T_190452 = dshl(T_190451, UInt<3>(4))
    node T_190453 = not(T_190448)
    node T_190454 = and(T_190452, T_190453)
    node T_190455 = or(T_190450, T_190454)
    node T_190456 = bits(T_190448, 13, 0)
    node T_190457 = dshl(T_190456, UInt<2>(2))
    node T_190458 = xor(T_190448, T_190457)
    node T_190459 = dshr(T_190455, UInt<2>(2))
    node T_190460 = and(T_190459, T_190458)
    node T_190461 = bits(T_190455, 13, 0)
    node T_190462 = dshl(T_190461, UInt<2>(2))
    node T_190463 = not(T_190458)
    node T_190464 = and(T_190462, T_190463)
    node T_190465 = or(T_190460, T_190464)
    node T_190466 = bits(T_190458, 14, 0)
    node T_190467 = dshl(T_190466, UInt<1>(1))
    node T_190468 = xor(T_190458, T_190467)
    node T_190469 = dshr(T_190465, UInt<1>(1))
    node T_190470 = and(T_190469, T_190468)
    node T_190471 = bits(T_190465, 14, 0)
    node T_190472 = dshl(T_190471, UInt<1>(1))
    node T_190473 = not(T_190468)
    node T_190474 = and(T_190472, T_190473)
    node T_190475 = or(T_190470, T_190474)
    node T_190476 = bits(T_190435, 23, 16)
    node T_190477 = dshl(UInt<4>(15), UInt<3>(4))
    node T_190478 = xor(UInt<8>(255), T_190477)
    node T_190479 = dshr(T_190476, UInt<3>(4))
    node T_190480 = and(T_190479, T_190478)
    node T_190481 = bits(T_190476, 3, 0)
    node T_190482 = dshl(T_190481, UInt<3>(4))
    node T_190483 = not(T_190478)
    node T_190484 = and(T_190482, T_190483)
    node T_190485 = or(T_190480, T_190484)
    node T_190486 = bits(T_190478, 5, 0)
    node T_190487 = dshl(T_190486, UInt<2>(2))
    node T_190488 = xor(T_190478, T_190487)
    node T_190489 = dshr(T_190485, UInt<2>(2))
    node T_190490 = and(T_190489, T_190488)
    node T_190491 = bits(T_190485, 5, 0)
    node T_190492 = dshl(T_190491, UInt<2>(2))
    node T_190493 = not(T_190488)
    node T_190494 = and(T_190492, T_190493)
    node T_190495 = or(T_190490, T_190494)
    node T_190496 = bits(T_190488, 6, 0)
    node T_190497 = dshl(T_190496, UInt<1>(1))
    node T_190498 = xor(T_190488, T_190497)
    node T_190499 = dshr(T_190495, UInt<1>(1))
    node T_190500 = and(T_190499, T_190498)
    node T_190501 = bits(T_190495, 6, 0)
    node T_190502 = dshl(T_190501, UInt<1>(1))
    node T_190503 = not(T_190498)
    node T_190504 = and(T_190502, T_190503)
    node T_190505 = or(T_190500, T_190504)
    node CExtraMask = cat(T_190475, T_190505)
    node T_190506 = not(sigC)
    wire negSigC : UInt<24>
    negSigC := sigC
    when doSubMags : negSigC := T_190506
    node T_190507 = subw(UInt<50>(0), UInt<6>(50))
    node T_190508 = cat(negSigC, T_190507)
    node T_190509 = cat(doSubMags, T_190508)
    node T_190510 = asSInt(T_190509)
    node T_190511 = dshr(T_190510, CAlignDist)
    node T_190512 = and(sigC, CExtraMask)
    node T_190513 = neq(T_190512, UInt<1>(0))
    node T_190514 = xor(T_190513, doSubMags)
    node T_190515 = asUInt(T_190511)
    node T_190516 = cat(T_190515, T_190514)
    node alignedNegSigC = bits(T_190516, 74, 0)
    node T_190517 = mul(sigA, sigB)
    node T_190518 = dshl(T_190517, UInt<1>(1))
    node sigSum = addw(T_190518, alignedNegSigC)
    node T_190519 = bits(sigSum, 50, 1)
    node T_190520 = xor(UInt<50>(0), T_190519)
    node T_190521 = or(UInt<50>(0), T_190519)
    node T_190522 = dshl(T_190521, UInt<1>(1))
    node T_190523 = xor(T_190520, T_190522)
    node T_190524 = bit(T_190523, 49)
    node T_190525 = bit(T_190523, 48)
    node T_190526 = bit(T_190523, 47)
    node T_190527 = bit(T_190523, 46)
    node T_190528 = bit(T_190523, 45)
    node T_190529 = bit(T_190523, 44)
    node T_190530 = bit(T_190523, 43)
    node T_190531 = bit(T_190523, 42)
    node T_190532 = bit(T_190523, 41)
    node T_190533 = bit(T_190523, 40)
    node T_190534 = bit(T_190523, 39)
    node T_190535 = bit(T_190523, 38)
    node T_190536 = bit(T_190523, 37)
    node T_190537 = bit(T_190523, 36)
    node T_190538 = bit(T_190523, 35)
    node T_190539 = bit(T_190523, 34)
    node T_190540 = bit(T_190523, 33)
    node T_190541 = bit(T_190523, 32)
    node T_190542 = bit(T_190523, 31)
    node T_190543 = bit(T_190523, 30)
    node T_190544 = bit(T_190523, 29)
    node T_190545 = bit(T_190523, 28)
    node T_190546 = bit(T_190523, 27)
    node T_190547 = bit(T_190523, 26)
    node T_190548 = bit(T_190523, 25)
    node T_190549 = bit(T_190523, 24)
    node T_190550 = bit(T_190523, 23)
    node T_190551 = bit(T_190523, 22)
    node T_190552 = bit(T_190523, 21)
    node T_190553 = bit(T_190523, 20)
    node T_190554 = bit(T_190523, 19)
    node T_190555 = bit(T_190523, 18)
    node T_190556 = bit(T_190523, 17)
    node T_190557 = bit(T_190523, 16)
    node T_190558 = bit(T_190523, 15)
    node T_190559 = bit(T_190523, 14)
    node T_190560 = bit(T_190523, 13)
    node T_190561 = bit(T_190523, 12)
    node T_190562 = bit(T_190523, 11)
    node T_190563 = bit(T_190523, 10)
    node T_190564 = bit(T_190523, 9)
    node T_190565 = bit(T_190523, 8)
    node T_190566 = bit(T_190523, 7)
    node T_190567 = bit(T_190523, 6)
    node T_190568 = bit(T_190523, 5)
    node T_190569 = bit(T_190523, 4)
    node T_190570 = bit(T_190523, 3)
    node T_190571 = bit(T_190523, 2)
    node T_190572 = bit(T_190523, 1)
    node T_190573 = bit(T_190523, 0)
    wire T_190574 : UInt<7>
    T_190574 := UInt<7>(73)
    when T_190572 : T_190574 := UInt<7>(72)
    wire T_190575 : UInt<7>
    T_190575 := T_190574
    when T_190571 : T_190575 := UInt<7>(71)
    wire T_190576 : UInt<7>
    T_190576 := T_190575
    when T_190570 : T_190576 := UInt<7>(70)
    wire T_190577 : UInt<7>
    T_190577 := T_190576
    when T_190569 : T_190577 := UInt<7>(69)
    wire T_190578 : UInt<7>
    T_190578 := T_190577
    when T_190568 : T_190578 := UInt<7>(68)
    wire T_190579 : UInt<7>
    T_190579 := T_190578
    when T_190567 : T_190579 := UInt<7>(67)
    wire T_190580 : UInt<7>
    T_190580 := T_190579
    when T_190566 : T_190580 := UInt<7>(66)
    wire T_190581 : UInt<7>
    T_190581 := T_190580
    when T_190565 : T_190581 := UInt<7>(65)
    wire T_190582 : UInt<7>
    T_190582 := T_190581
    when T_190564 : T_190582 := UInt<7>(64)
    wire T_190583 : UInt<7>
    T_190583 := T_190582
    when T_190563 : T_190583 := UInt<7>(63)
    wire T_190584 : UInt<7>
    T_190584 := T_190583
    when T_190562 : T_190584 := UInt<7>(62)
    wire T_190585 : UInt<7>
    T_190585 := T_190584
    when T_190561 : T_190585 := UInt<7>(61)
    wire T_190586 : UInt<7>
    T_190586 := T_190585
    when T_190560 : T_190586 := UInt<7>(60)
    wire T_190587 : UInt<7>
    T_190587 := T_190586
    when T_190559 : T_190587 := UInt<7>(59)
    wire T_190588 : UInt<7>
    T_190588 := T_190587
    when T_190558 : T_190588 := UInt<7>(58)
    wire T_190589 : UInt<7>
    T_190589 := T_190588
    when T_190557 : T_190589 := UInt<7>(57)
    wire T_190590 : UInt<7>
    T_190590 := T_190589
    when T_190556 : T_190590 := UInt<7>(56)
    wire T_190591 : UInt<7>
    T_190591 := T_190590
    when T_190555 : T_190591 := UInt<7>(55)
    wire T_190592 : UInt<7>
    T_190592 := T_190591
    when T_190554 : T_190592 := UInt<7>(54)
    wire T_190593 : UInt<7>
    T_190593 := T_190592
    when T_190553 : T_190593 := UInt<7>(53)
    wire T_190594 : UInt<7>
    T_190594 := T_190593
    when T_190552 : T_190594 := UInt<7>(52)
    wire T_190595 : UInt<7>
    T_190595 := T_190594
    when T_190551 : T_190595 := UInt<7>(51)
    wire T_190596 : UInt<7>
    T_190596 := T_190595
    when T_190550 : T_190596 := UInt<7>(50)
    wire T_190597 : UInt<7>
    T_190597 := T_190596
    when T_190549 : T_190597 := UInt<7>(49)
    wire T_190598 : UInt<7>
    T_190598 := T_190597
    when T_190548 : T_190598 := UInt<7>(48)
    wire T_190599 : UInt<7>
    T_190599 := T_190598
    when T_190547 : T_190599 := UInt<7>(47)
    wire T_190600 : UInt<7>
    T_190600 := T_190599
    when T_190546 : T_190600 := UInt<7>(46)
    wire T_190601 : UInt<7>
    T_190601 := T_190600
    when T_190545 : T_190601 := UInt<7>(45)
    wire T_190602 : UInt<7>
    T_190602 := T_190601
    when T_190544 : T_190602 := UInt<7>(44)
    wire T_190603 : UInt<7>
    T_190603 := T_190602
    when T_190543 : T_190603 := UInt<7>(43)
    wire T_190604 : UInt<7>
    T_190604 := T_190603
    when T_190542 : T_190604 := UInt<7>(42)
    wire T_190605 : UInt<7>
    T_190605 := T_190604
    when T_190541 : T_190605 := UInt<7>(41)
    wire T_190606 : UInt<7>
    T_190606 := T_190605
    when T_190540 : T_190606 := UInt<7>(40)
    wire T_190607 : UInt<7>
    T_190607 := T_190606
    when T_190539 : T_190607 := UInt<7>(39)
    wire T_190608 : UInt<7>
    T_190608 := T_190607
    when T_190538 : T_190608 := UInt<7>(38)
    wire T_190609 : UInt<7>
    T_190609 := T_190608
    when T_190537 : T_190609 := UInt<7>(37)
    wire T_190610 : UInt<7>
    T_190610 := T_190609
    when T_190536 : T_190610 := UInt<7>(36)
    wire T_190611 : UInt<7>
    T_190611 := T_190610
    when T_190535 : T_190611 := UInt<7>(35)
    wire T_190612 : UInt<7>
    T_190612 := T_190611
    when T_190534 : T_190612 := UInt<7>(34)
    wire T_190613 : UInt<7>
    T_190613 := T_190612
    when T_190533 : T_190613 := UInt<7>(33)
    wire T_190614 : UInt<7>
    T_190614 := T_190613
    when T_190532 : T_190614 := UInt<7>(32)
    wire T_190615 : UInt<7>
    T_190615 := T_190614
    when T_190531 : T_190615 := UInt<7>(31)
    wire T_190616 : UInt<7>
    T_190616 := T_190615
    when T_190530 : T_190616 := UInt<7>(30)
    wire T_190617 : UInt<7>
    T_190617 := T_190616
    when T_190529 : T_190617 := UInt<7>(29)
    wire T_190618 : UInt<7>
    T_190618 := T_190617
    when T_190528 : T_190618 := UInt<7>(28)
    wire T_190619 : UInt<7>
    T_190619 := T_190618
    when T_190527 : T_190619 := UInt<7>(27)
    wire T_190620 : UInt<7>
    T_190620 := T_190619
    when T_190526 : T_190620 := UInt<7>(26)
    wire T_190621 : UInt<7>
    T_190621 := T_190620
    when T_190525 : T_190621 := UInt<7>(25)
    wire estNormPos_dist : UInt<7>
    estNormPos_dist := T_190621
    when T_190524 : estNormPos_dist := UInt<7>(24)
    node T_190622 = bits(sigSum, 33, 18)
    node T_190623 = neq(T_190622, UInt<1>(0))
    node T_190624 = bits(sigSum, 17, 0)
    node T_190625 = neq(T_190624, UInt<1>(0))
    node firstReduceSigSum = cat(T_190623, T_190625)
    node notSigSum = not(sigSum)
    node T_190626 = bits(notSigSum, 33, 18)
    node T_190627 = neq(T_190626, UInt<1>(0))
    node T_190628 = bits(notSigSum, 17, 0)
    node T_190629 = neq(T_190628, UInt<1>(0))
    node firstReduceNotSigSum = cat(T_190627, T_190629)
    node T_190630 = or(CAlignDist_0, doSubMags)
    node T_190631 = subw(CAlignDist, UInt<1>(1))
    node T_190632 = bits(T_190631, 4, 0)
    wire CDom_estNormDist : UInt<5>
    CDom_estNormDist := T_190632
    when T_190630 : CDom_estNormDist := CAlignDist
    node T_190633 = not(doSubMags)
    node T_190634 = bit(CDom_estNormDist, 4)
    node T_190635 = not(T_190634)
    node T_190636 = and(T_190633, T_190635)
    node T_190637 = asSInt(T_190636)
    node T_190638 = bits(sigSum, 74, 34)
    node T_190639 = neq(firstReduceSigSum, UInt<1>(0))
    node T_190640 = cat(T_190638, T_190639)
    node T_190641 = asSInt(T_190640)
    node T_190642 = and(T_190637, T_190641)
    node T_190643 = not(doSubMags)
    node T_190644 = bit(CDom_estNormDist, 4)
    node T_190645 = and(T_190643, T_190644)
    node T_190646 = asSInt(T_190645)
    node T_190647 = bits(sigSum, 58, 18)
    node T_190648 = bit(firstReduceSigSum, 0)
    node T_190649 = cat(T_190647, T_190648)
    node T_190650 = asSInt(T_190649)
    node T_190651 = and(T_190646, T_190650)
    node T_190652 = or(T_190642, T_190651)
    node T_190653 = bit(CDom_estNormDist, 4)
    node T_190654 = not(T_190653)
    node T_190655 = and(doSubMags, T_190654)
    node T_190656 = asSInt(T_190655)
    node T_190657 = bits(notSigSum, 74, 34)
    node T_190658 = neq(firstReduceNotSigSum, UInt<1>(0))
    node T_190659 = cat(T_190657, T_190658)
    node T_190660 = asSInt(T_190659)
    node T_190661 = and(T_190656, T_190660)
    node T_190662 = or(T_190652, T_190661)
    node T_190663 = bit(CDom_estNormDist, 4)
    node T_190664 = and(doSubMags, T_190663)
    node T_190665 = asSInt(T_190664)
    node T_190666 = bits(notSigSum, 58, 18)
    node T_190667 = bit(firstReduceNotSigSum, 0)
    node T_190668 = cat(T_190666, T_190667)
    node T_190669 = asSInt(T_190668)
    node T_190670 = and(T_190665, T_190669)
    node T_190671 = or(T_190662, T_190670)
    node CDom_firstNormAbsSigSum = asUInt(T_190671)
    node T_190672 = bits(sigSum, 50, 18)
    node T_190673 = bit(firstReduceNotSigSum, 0)
    node T_190674 = not(T_190673)
    node T_190675 = bit(firstReduceSigSum, 0)
    wire T_190676 : UInt<1>
    T_190676 := T_190675
    when doSubMags : T_190676 := T_190674
    node T_190677 = cat(T_190672, T_190676)
    node T_190678 = bits(sigSum, 42, 1)
    node T_190679 = bit(estNormPos_dist, 5)
    node T_190680 = bit(estNormPos_dist, 4)
    node T_190681 = bits(sigSum, 26, 1)
    node T_190682 = subw(UInt<16>(0), UInt<5>(16))
    node T_190683 = cat(T_190681, T_190682)
    wire T_190684 : UInt<42>
    T_190684 := T_190678
    when T_190680 : T_190684 := T_190683
    node T_190685 = bit(estNormPos_dist, 4)
    node T_190686 = bits(sigSum, 10, 1)
    node T_190687 = subw(UInt<32>(0), UInt<6>(32))
    node T_190688 = cat(T_190686, T_190687)
    wire T_190689 : UInt<42>
    T_190689 := T_190688
    when T_190685 : T_190689 := T_190677
    wire notCDom_pos_firstNormAbsSigSum : UInt<42>
    notCDom_pos_firstNormAbsSigSum := T_190689
    when T_190679 : notCDom_pos_firstNormAbsSigSum := T_190684
    node T_190690 = bits(notSigSum, 49, 18)
    node T_190691 = bit(firstReduceNotSigSum, 0)
    node T_190692 = cat(T_190690, T_190691)
    node T_190693 = bits(notSigSum, 42, 1)
    node T_190694 = bit(estNormPos_dist, 5)
    node T_190695 = bit(estNormPos_dist, 4)
    node T_190696 = bits(notSigSum, 27, 1)
    node T_190697 = dshl(T_190696, UInt<5>(16))
    wire T_190698 : UInt<42>
    T_190698 := T_190693
    when T_190695 : T_190698 := T_190697
    node T_190699 = bit(estNormPos_dist, 4)
    node T_190700 = bits(notSigSum, 11, 1)
    node T_190701 = dshl(T_190700, UInt<6>(32))
    wire T_190702 : UInt<75>
    T_190702 := T_190701
    when T_190699 : T_190702 := T_190692
    wire notCDom_neg_cFirstNormAbsSigSum : UInt<75>
    notCDom_neg_cFirstNormAbsSigSum := T_190702
    when T_190694 : notCDom_neg_cFirstNormAbsSigSum := T_190698
    node notCDom_signSigSum = bit(sigSum, 51)
    node T_190703 = not(isZeroC)
    node T_190704 = and(doSubMags, T_190703)
    wire doNegSignSum : UInt<1>
    doNegSignSum := notCDom_signSigSum
    when isCDominant : doNegSignSum := T_190704
    wire T_190705 : UInt<7>
    T_190705 := estNormPos_dist
    when notCDom_signSigSum : T_190705 := estNormPos_dist
    wire estNormDist : UInt<7>
    estNormDist := T_190705
    when isCDominant : estNormDist := CDom_estNormDist
    wire T_190706 : UInt<75>
    T_190706 := notCDom_neg_cFirstNormAbsSigSum
    when isCDominant : T_190706 := CDom_firstNormAbsSigSum
    wire T_190707 : UInt<42>
    T_190707 := notCDom_pos_firstNormAbsSigSum
    when isCDominant : T_190707 := CDom_firstNormAbsSigSum
    wire cFirstNormAbsSigSum : UInt<42>
    cFirstNormAbsSigSum := T_190707
    when notCDom_signSigSum : cFirstNormAbsSigSum := T_190706
    node T_190708 = not(isCDominant)
    node T_190709 = not(notCDom_signSigSum)
    node T_190710 = and(T_190708, T_190709)
    node doIncrSig = and(T_190710, doSubMags)
    node estNormDist_5 = bits(estNormDist, 3, 0)
    node normTo2ShiftDist = not(estNormDist_5)
    node T_190711 = dshr(SInt<17>(-65536), normTo2ShiftDist)
    node T_190712 = bits(T_190711, 15, 1)
    node T_190713 = bits(T_190712, 7, 0)
    node T_190714 = dshl(UInt<4>(15), UInt<3>(4))
    node T_190715 = xor(UInt<8>(255), T_190714)
    node T_190716 = dshr(T_190713, UInt<3>(4))
    node T_190717 = and(T_190716, T_190715)
    node T_190718 = bits(T_190713, 3, 0)
    node T_190719 = dshl(T_190718, UInt<3>(4))
    node T_190720 = not(T_190715)
    node T_190721 = and(T_190719, T_190720)
    node T_190722 = or(T_190717, T_190721)
    node T_190723 = bits(T_190715, 5, 0)
    node T_190724 = dshl(T_190723, UInt<2>(2))
    node T_190725 = xor(T_190715, T_190724)
    node T_190726 = dshr(T_190722, UInt<2>(2))
    node T_190727 = and(T_190726, T_190725)
    node T_190728 = bits(T_190722, 5, 0)
    node T_190729 = dshl(T_190728, UInt<2>(2))
    node T_190730 = not(T_190725)
    node T_190731 = and(T_190729, T_190730)
    node T_190732 = or(T_190727, T_190731)
    node T_190733 = bits(T_190725, 6, 0)
    node T_190734 = dshl(T_190733, UInt<1>(1))
    node T_190735 = xor(T_190725, T_190734)
    node T_190736 = dshr(T_190732, UInt<1>(1))
    node T_190737 = and(T_190736, T_190735)
    node T_190738 = bits(T_190732, 6, 0)
    node T_190739 = dshl(T_190738, UInt<1>(1))
    node T_190740 = not(T_190735)
    node T_190741 = and(T_190739, T_190740)
    node T_190742 = or(T_190737, T_190741)
    node T_190743 = bits(T_190712, 14, 8)
    node T_190744 = bits(T_190743, 3, 0)
    node T_190745 = bits(T_190744, 1, 0)
    node T_190746 = bits(T_190745, 0, 0)
    node T_190747 = bits(T_190745, 1, 1)
    node T_190748 = cat(T_190746, T_190747)
    node T_190749 = bits(T_190744, 3, 2)
    node T_190750 = bits(T_190749, 0, 0)
    node T_190751 = bits(T_190749, 1, 1)
    node T_190752 = cat(T_190750, T_190751)
    node T_190753 = cat(T_190748, T_190752)
    node T_190754 = bits(T_190743, 6, 4)
    node T_190755 = bits(T_190754, 1, 0)
    node T_190756 = bits(T_190755, 0, 0)
    node T_190757 = bits(T_190755, 1, 1)
    node T_190758 = cat(T_190756, T_190757)
    node T_190759 = bits(T_190754, 2, 2)
    node T_190760 = cat(T_190758, T_190759)
    node T_190761 = cat(T_190753, T_190760)
    node T_190762 = cat(T_190742, T_190761)
    node absSigSumExtraMask = cat(T_190762, UInt<1>(1))
    node T_190763 = bits(cFirstNormAbsSigSum, 42, 1)
    node T_190764 = dshr(T_190763, normTo2ShiftDist)
    node T_190765 = bits(cFirstNormAbsSigSum, 15, 0)
    node T_190766 = not(T_190765)
    node T_190767 = and(T_190766, absSigSumExtraMask)
    node T_190768 = eq(T_190767, UInt<1>(0))
    node T_190769 = bits(cFirstNormAbsSigSum, 15, 0)
    node T_190770 = and(T_190769, absSigSumExtraMask)
    node T_190771 = neq(T_190770, UInt<1>(0))
    wire T_190772 : UInt<1>
    T_190772 := T_190771
    when doIncrSig : T_190772 := T_190768
    node T_190773 = cat(T_190764, T_190772)
    node sigX3 = bits(T_190773, 27, 0)
    node T_190774 = bits(sigX3, 27, 26)
    node sigX3Shift1 = eq(T_190774, UInt<1>(0))
    node sExpX3 = subw(sExpSum, estNormDist)
    node T_190775 = bits(sigX3, 27, 25)
    node isZeroY = eq(T_190775, UInt<1>(0))
    node T_190776 = not(isZeroY)
    node T_190777 = xor(signProd, doNegSignSum)
    node signY = and(T_190776, T_190777)
    node sExpX3_13 = bits(sExpX3, 9, 0)
    node T_190778 = bit(sExpX3, 10)
    node T_190779 = subw(UInt<27>(0), UInt<5>(27))
    node T_190780 = not(sExpX3_13)
    node T_190781 = dshr(SInt<1025>(-179769313486231590772930519078902473361797697894230657273430081157732675805500963132708477322407536021120113879871393357658789768814416622492847430639474124377767893424865485276302219601246094119453082952085005768838150682342462881473913110540827237163350510684586298239947245938479716304835356329624224137216), T_190780)
    node T_190782 = bits(T_190781, 131, 107)
    node T_190783 = bits(T_190782, 15, 0)
    node T_190784 = dshl(UInt<8>(255), UInt<4>(8))
    node T_190785 = xor(UInt<16>(65535), T_190784)
    node T_190786 = dshr(T_190783, UInt<4>(8))
    node T_190787 = and(T_190786, T_190785)
    node T_190788 = bits(T_190783, 7, 0)
    node T_190789 = dshl(T_190788, UInt<4>(8))
    node T_190790 = not(T_190785)
    node T_190791 = and(T_190789, T_190790)
    node T_190792 = or(T_190787, T_190791)
    node T_190793 = bits(T_190785, 11, 0)
    node T_190794 = dshl(T_190793, UInt<3>(4))
    node T_190795 = xor(T_190785, T_190794)
    node T_190796 = dshr(T_190792, UInt<3>(4))
    node T_190797 = and(T_190796, T_190795)
    node T_190798 = bits(T_190792, 11, 0)
    node T_190799 = dshl(T_190798, UInt<3>(4))
    node T_190800 = not(T_190795)
    node T_190801 = and(T_190799, T_190800)
    node T_190802 = or(T_190797, T_190801)
    node T_190803 = bits(T_190795, 13, 0)
    node T_190804 = dshl(T_190803, UInt<2>(2))
    node T_190805 = xor(T_190795, T_190804)
    node T_190806 = dshr(T_190802, UInt<2>(2))
    node T_190807 = and(T_190806, T_190805)
    node T_190808 = bits(T_190802, 13, 0)
    node T_190809 = dshl(T_190808, UInt<2>(2))
    node T_190810 = not(T_190805)
    node T_190811 = and(T_190809, T_190810)
    node T_190812 = or(T_190807, T_190811)
    node T_190813 = bits(T_190805, 14, 0)
    node T_190814 = dshl(T_190813, UInt<1>(1))
    node T_190815 = xor(T_190805, T_190814)
    node T_190816 = dshr(T_190812, UInt<1>(1))
    node T_190817 = and(T_190816, T_190815)
    node T_190818 = bits(T_190812, 14, 0)
    node T_190819 = dshl(T_190818, UInt<1>(1))
    node T_190820 = not(T_190815)
    node T_190821 = and(T_190819, T_190820)
    node T_190822 = or(T_190817, T_190821)
    node T_190823 = bits(T_190782, 24, 16)
    node T_190824 = bits(T_190823, 7, 0)
    node T_190825 = dshl(UInt<4>(15), UInt<3>(4))
    node T_190826 = xor(UInt<8>(255), T_190825)
    node T_190827 = dshr(T_190824, UInt<3>(4))
    node T_190828 = and(T_190827, T_190826)
    node T_190829 = bits(T_190824, 3, 0)
    node T_190830 = dshl(T_190829, UInt<3>(4))
    node T_190831 = not(T_190826)
    node T_190832 = and(T_190830, T_190831)
    node T_190833 = or(T_190828, T_190832)
    node T_190834 = bits(T_190826, 5, 0)
    node T_190835 = dshl(T_190834, UInt<2>(2))
    node T_190836 = xor(T_190826, T_190835)
    node T_190837 = dshr(T_190833, UInt<2>(2))
    node T_190838 = and(T_190837, T_190836)
    node T_190839 = bits(T_190833, 5, 0)
    node T_190840 = dshl(T_190839, UInt<2>(2))
    node T_190841 = not(T_190836)
    node T_190842 = and(T_190840, T_190841)
    node T_190843 = or(T_190838, T_190842)
    node T_190844 = bits(T_190836, 6, 0)
    node T_190845 = dshl(T_190844, UInt<1>(1))
    node T_190846 = xor(T_190836, T_190845)
    node T_190847 = dshr(T_190843, UInt<1>(1))
    node T_190848 = and(T_190847, T_190846)
    node T_190849 = bits(T_190843, 6, 0)
    node T_190850 = dshl(T_190849, UInt<1>(1))
    node T_190851 = not(T_190846)
    node T_190852 = and(T_190850, T_190851)
    node T_190853 = or(T_190848, T_190852)
    node T_190854 = bits(T_190823, 8, 8)
    node T_190855 = cat(T_190853, T_190854)
    node T_190856 = cat(T_190822, T_190855)
    node T_190857 = bit(sigX3, 26)
    node T_190858 = or(T_190856, T_190857)
    node T_190859 = cat(T_190858, UInt<2>(3))
    node roundMask = or(T_190779, T_190859)
    node T_190860 = dshr(roundMask, UInt<1>(1))
    node T_190861 = not(T_190860)
    node roundPosMask = and(T_190861, roundMask)
    node T_190862 = and(sigX3, roundPosMask)
    node roundPosBit = neq(T_190862, UInt<1>(0))
    node T_190863 = dshr(roundMask, UInt<1>(1))
    node T_190864 = and(sigX3, T_190863)
    node anyRoundExtra = neq(T_190864, UInt<1>(0))
    node T_190865 = not(sigX3)
    node T_190866 = dshr(roundMask, UInt<1>(1))
    node T_190867 = and(T_190865, T_190866)
    node allRoundExtra = eq(T_190867, UInt<1>(0))
    node anyRound = or(roundPosBit, anyRoundExtra)
    node allRound = and(roundPosBit, allRoundExtra)
    wire roundDirectUp : UInt<1>
    roundDirectUp := roundingMode_max
    when signY : roundDirectUp := roundingMode_min
    node T_190868 = not(doIncrSig)
    node T_190869 = and(T_190868, roundingMode_nearest_even)
    node T_190870 = and(T_190869, roundPosBit)
    node T_190871 = and(T_190870, anyRoundExtra)
    node T_190872 = not(doIncrSig)
    node T_190873 = and(T_190872, roundDirectUp)
    node T_190874 = and(T_190873, anyRound)
    node T_190875 = or(T_190871, T_190874)
    node T_190876 = and(doIncrSig, allRound)
    node T_190877 = or(T_190875, T_190876)
    node T_190878 = and(doIncrSig, roundingMode_nearest_even)
    node T_190879 = and(T_190878, roundPosBit)
    node T_190880 = or(T_190877, T_190879)
    node T_190881 = and(doIncrSig, roundDirectUp)
    node roundUp = or(T_190880, T_190881)
    node T_190882 = not(roundPosBit)
    node T_190883 = and(roundingMode_nearest_even, T_190882)
    node T_190884 = and(T_190883, allRoundExtra)
    node T_190885 = and(roundingMode_nearest_even, roundPosBit)
    node T_190886 = not(anyRoundExtra)
    node T_190887 = and(T_190885, T_190886)
    wire roundEven : UInt<1>
    roundEven := T_190887
    when doIncrSig : roundEven := T_190884
    node T_190888 = not(allRound)
    wire roundInexact : UInt<1>
    roundInexact := anyRound
    when doIncrSig : roundInexact := T_190888
    node T_190889 = or(sigX3, roundMask)
    node T_190890 = dshr(T_190889, UInt<2>(2))
    node T_190891 = addw(T_190890, UInt<1>(1))
    node roundUp_sigY3 = bits(T_190891, 25, 0)
    node T_190892 = not(roundUp)
    node T_190893 = not(roundEven)
    node T_190894 = and(T_190892, T_190893)
    node T_190895 = not(roundMask)
    node T_190896 = and(sigX3, T_190895)
    node T_190897 = dshr(T_190896, UInt<2>(2))
    wire T_190898 : UInt<1>
    T_190898 := UInt<1>(0)
    when T_190894 : T_190898 := T_190897
    wire T_190899 : UInt<1>
    T_190899 := UInt<1>(0)
    when roundUp : T_190899 := roundUp_sigY3
    node T_190900 = or(T_190898, T_190899)
    node T_190901 = dshr(roundMask, UInt<1>(1))
    node T_190902 = not(T_190901)
    node T_190903 = and(roundUp_sigY3, T_190902)
    wire T_190904 : UInt<1>
    T_190904 := UInt<1>(0)
    when roundEven : T_190904 := T_190903
    node sigY3 = or(T_190900, T_190904)
    node T_190905 = bit(sigY3, 25)
    node T_190906 = addw(sExpX3, UInt<1>(1))
    wire T_190907 : UInt<1>
    T_190907 := UInt<1>(0)
    when T_190905 : T_190907 := T_190906
    node T_190908 = bit(sigY3, 24)
    wire T_190909 : UInt<1>
    T_190909 := UInt<1>(0)
    when T_190908 : T_190909 := sExpX3
    node T_190910 = or(T_190907, T_190909)
    node T_190911 = bits(sigY3, 25, 24)
    node T_190912 = eq(T_190911, UInt<1>(0))
    node T_190913 = subw(sExpX3, UInt<1>(1))
    wire T_190914 : UInt<1>
    T_190914 := UInt<1>(0)
    when T_190912 : T_190914 := T_190913
    node sExpY = or(T_190910, T_190914)
    node expY = bits(sExpY, 8, 0)
    node T_190915 = bits(sigY3, 22, 0)
    node T_190916 = bits(sigY3, 23, 1)
    wire fractY : UInt<23>
    fractY := T_190916
    when sigX3Shift1 : fractY := T_190915
    node T_190917 = bits(sExpY, 9, 7)
    node overflowY = eq(T_190917, UInt<2>(3))
    node T_190918 = bit(sExpY, 9)
    node T_190919 = bits(sExpY, 8, 0)
    node T_190920 = lt(T_190919, UInt<7>(107))
    node totalUnderflowY = or(T_190918, T_190920)
    node T_190921 = bit(sExpX3, 10)
    wire T_190922 : UInt<8>
    T_190922 := UInt<8>(129)
    when sigX3Shift1 : T_190922 := UInt<8>(130)
    node T_190923 = leq(sExpX3_13, T_190922)
    node T_190924 = or(T_190921, T_190923)
    node underflowY = and(roundInexact, T_190924)
    node T_190925 = and(roundingMode_min, signY)
    node T_190926 = or(roundingMode_nearest_even, T_190925)
    node T_190927 = not(signY)
    node T_190928 = and(roundingMode_max, T_190927)
    node overflowY_roundMagUp = or(T_190926, T_190928)
    node mulSpecial = or(isSpecialA, isSpecialB)
    node addSpecial = or(mulSpecial, isSpecialC)
    node notSpecial_addZeros = and(isZeroProd, isZeroC)
    node T_190929 = not(addSpecial)
    node T_190930 = not(notSpecial_addZeros)
    node commonCase = and(T_190929, T_190930)
    node T_190931 = and(isInfA, isZeroB)
    node T_190932 = and(isZeroA, isInfB)
    node T_190933 = or(T_190931, T_190932)
    node T_190934 = not(isNaNA)
    node T_190935 = not(isNaNB)
    node T_190936 = and(T_190934, T_190935)
    node T_190937 = or(isInfA, isInfB)
    node T_190938 = and(T_190936, T_190937)
    node T_190939 = and(T_190938, isInfC)
    node T_190940 = and(T_190939, doSubMags)
    node notSigNaN_invalid = or(T_190933, T_190940)
    node T_190941 = or(isSigNaNA, isSigNaNB)
    node T_190942 = or(T_190941, isSigNaNC)
    node invalid = or(T_190942, notSigNaN_invalid)
    node overflow = and(commonCase, overflowY)
    node underflow = and(commonCase, underflowY)
    node T_190943 = and(commonCase, roundInexact)
    node inexact = or(overflow, T_190943)
    node T_190944 = or(notSpecial_addZeros, isZeroY)
    node notSpecial_isZeroOut = or(T_190944, totalUnderflowY)
    node T_190945 = not(overflowY_roundMagUp)
    node isSatOut = and(overflow, T_190945)
    node T_190946 = or(isInfA, isInfB)
    node T_190947 = or(T_190946, isInfC)
    node T_190948 = and(overflow, overflowY_roundMagUp)
    node notNaN_isInfOut = or(T_190947, T_190948)
    node T_190949 = or(isNaNA, isNaNB)
    node T_190950 = or(T_190949, isNaNC)
    node isNaNOut = or(T_190950, notSigNaN_invalid)
    node T_190951 = eq(doSubMags, UInt<1>(0))
    node T_190952 = and(T_190951, opSignC)
    node T_190953 = and(isNaNOut, UInt<1>(1))
    node T_190954 = or(T_190952, T_190953)
    node T_190955 = eq(isSpecialC, UInt<1>(0))
    node T_190956 = and(mulSpecial, T_190955)
    node T_190957 = and(T_190956, signProd)
    node T_190958 = or(T_190954, T_190957)
    node T_190959 = eq(mulSpecial, UInt<1>(0))
    node T_190960 = and(T_190959, isSpecialC)
    node T_190961 = and(T_190960, opSignC)
    node T_190962 = or(T_190958, T_190961)
    node T_190963 = eq(mulSpecial, UInt<1>(0))
    node T_190964 = and(T_190963, notSpecial_addZeros)
    node T_190965 = and(T_190964, doSubMags)
    node T_190966 = and(T_190965, UInt<1>(0))
    node T_190967 = or(T_190962, T_190966)
    node T_190968 = and(commonCase, signY)
    node signOut = or(T_190967, T_190968)
    wire T_190969 : UInt<9>
    T_190969 := UInt<9>(0)
    when notSpecial_isZeroOut : T_190969 := UInt<9>(448)
    node T_190970 = not(T_190969)
    node T_190971 = and(expY, T_190970)
    wire T_190972 : UInt<9>
    T_190972 := UInt<9>(0)
    when isSatOut : T_190972 := UInt<8>(128)
    node T_190973 = not(T_190972)
    node T_190974 = and(T_190971, T_190973)
    wire T_190975 : UInt<9>
    T_190975 := UInt<9>(0)
    when notNaN_isInfOut : T_190975 := UInt<7>(64)
    node T_190976 = not(T_190975)
    node T_190977 = and(T_190974, T_190976)
    wire T_190978 : UInt<9>
    T_190978 := UInt<9>(0)
    when isSatOut : T_190978 := UInt<9>(383)
    node T_190979 = or(T_190977, T_190978)
    wire T_190980 : UInt<9>
    T_190980 := UInt<9>(0)
    when notNaN_isInfOut : T_190980 := UInt<9>(384)
    node T_190981 = or(T_190979, T_190980)
    wire T_190982 : UInt<9>
    T_190982 := UInt<9>(0)
    when isNaNOut : T_190982 := UInt<9>(448)
    node expOut = or(T_190981, T_190982)
    node T_190983 = or(isNaNOut, isSatOut)
    node T_190984 = subw(UInt<23>(0), UInt<5>(23))
    node fractOut = or(fractY, T_190984)
    node T_190985 = cat(expOut, fractOut)
    node T_190986 = cat(signOut, T_190985)
    out := T_190986
    node T_190987 = cat(invalid, UInt<1>(0))
    node T_190988 = cat(underflow, inexact)
    node T_190989 = cat(overflow, T_190988)
    node T_190990 = cat(T_190987, T_190989)
    exceptionFlags := T_190990
  module FPUFMAPipe : 
    input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    
    node one = shl(UInt<1>(1), 31)
    node T_190991 = bit(in.bits.in1, 32)
    node T_190992 = bit(in.bits.in2, 32)
    node T_190993 = xor(T_190991, T_190992)
    node zero = shl(T_190993, 32)
    reg valid : UInt<1>
    valid := in.valid
    reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    when in.valid : 
      in := in.bits
      node T_190994 = bit(in.bits.cmd, 1)
      node T_190995 = or(in.bits.ren3, in.bits.swap23)
      node T_190996 = and(T_190994, T_190995)
      node T_190997 = bit(in.bits.cmd, 0)
      node T_190998 = cat(T_190996, T_190997)
      in.cmd := T_190998
      when in.bits.swap23 : in.in2 := one
      node T_190999 = or(in.bits.ren3, in.bits.swap23)
      
      node T_191000 = eq(T_190999, UInt<1>(0))
      when T_191000 : in.in3 := zero
    inst fma of mulAddSubRecodedFloatN
    fma.op := in.cmd
    fma.roundingMode := in.rm
    fma.a := in.in1
    fma.b := in.in2
    fma.c := in.in3
    wire res : {data : UInt<65>, exc : UInt<5>}
    res.data := fma.out
    res.exc := fma.exceptionFlags
    reg T_191001 : UInt<1>
    onreset T_191001 := UInt<1>(0)
    T_191001 := valid
    reg T_191002 : {data : UInt<65>, exc : UInt<5>}
    when valid : T_191002 := res
    T_191003.valid <> T_191001
    T_191003.bits <> T_191002
    out := T_191003
  module mulAddSubRecodedFloatN_160940 : 
    input op : UInt<2>
    input a : UInt<65>
    input b : UInt<65>
    input c : UInt<65>
    input roundingMode : UInt<2>
    output out : UInt<65>
    output exceptionFlags : UInt<5>
    
    node signA = bit(a, 64)
    node expA = bits(a, 63, 52)
    node fractA = bits(a, 51, 0)
    node T_191004 = bits(expA, 11, 9)
    node isZeroA = eq(T_191004, UInt<1>(0))
    node T_191005 = bits(expA, 11, 10)
    node isSpecialA = eq(T_191005, UInt<2>(3))
    node T_191006 = bit(expA, 9)
    node T_191007 = eq(T_191006, UInt<1>(0))
    node isInfA = and(isSpecialA, T_191007)
    node T_191008 = bit(expA, 9)
    node isNaNA = and(isSpecialA, T_191008)
    node T_191009 = bit(fractA, 51)
    node T_191010 = eq(T_191009, UInt<1>(0))
    node isSigNaNA = and(isNaNA, T_191010)
    node T_191011 = eq(isZeroA, UInt<1>(0))
    node sigA = cat(T_191011, fractA)
    node signB = bit(b, 64)
    node expB = bits(b, 63, 52)
    node fractB = bits(b, 51, 0)
    node T_191012 = bits(expB, 11, 9)
    node isZeroB = eq(T_191012, UInt<1>(0))
    node T_191013 = bits(expB, 11, 10)
    node isSpecialB = eq(T_191013, UInt<2>(3))
    node T_191014 = bit(expB, 9)
    node T_191015 = eq(T_191014, UInt<1>(0))
    node isInfB = and(isSpecialB, T_191015)
    node T_191016 = bit(expB, 9)
    node isNaNB = and(isSpecialB, T_191016)
    node T_191017 = bit(fractB, 51)
    node T_191018 = eq(T_191017, UInt<1>(0))
    node isSigNaNB = and(isNaNB, T_191018)
    node T_191019 = eq(isZeroB, UInt<1>(0))
    node sigB = cat(T_191019, fractB)
    node T_191020 = bit(c, 64)
    node T_191021 = bit(op, 0)
    node opSignC = xor(T_191020, T_191021)
    node expC = bits(c, 63, 52)
    node fractC = bits(c, 51, 0)
    node T_191022 = bits(expC, 11, 9)
    node isZeroC = eq(T_191022, UInt<1>(0))
    node T_191023 = bits(expC, 11, 10)
    node isSpecialC = eq(T_191023, UInt<2>(3))
    node T_191024 = bit(expC, 9)
    node T_191025 = eq(T_191024, UInt<1>(0))
    node isInfC = and(isSpecialC, T_191025)
    node T_191026 = bit(expC, 9)
    node isNaNC = and(isSpecialC, T_191026)
    node T_191027 = bit(fractC, 51)
    node T_191028 = eq(T_191027, UInt<1>(0))
    node isSigNaNC = and(isNaNC, T_191028)
    node T_191029 = eq(isZeroC, UInt<1>(0))
    node sigC = cat(T_191029, fractC)
    node roundingMode_nearest_even = eq(roundingMode, UInt<2>(0))
    node roundingMode_minMag = eq(roundingMode, UInt<2>(1))
    node roundingMode_min = eq(roundingMode, UInt<2>(2))
    node roundingMode_max = eq(roundingMode, UInt<2>(3))
    node T_191030 = xor(signA, signB)
    node T_191031 = bit(op, 1)
    node signProd = xor(T_191030, T_191031)
    node isZeroProd = or(isZeroA, isZeroB)
    node T_191032 = bit(expB, 11)
    node T_191033 = eq(T_191032, UInt<1>(0))
    node T_191034 = subw(UInt<3>(0), UInt<2>(3))
    node T_191035 = bits(expB, 10, 0)
    node T_191036 = cat(T_191034, T_191035)
    node T_191037 = addw(T_191036, expA)
    node sExpAlignedProd = addw(T_191037, UInt<6>(56))
    node doSubMags = xor(signProd, opSignC)
    node sNatCAlignDist = subw(sExpAlignedProd, expC)
    node T_191038 = bit(sNatCAlignDist, 13)
    node CAlignDist_floor = or(isZeroProd, T_191038)
    node T_191039 = bits(sNatCAlignDist, 12, 0)
    node T_191040 = eq(T_191039, UInt<1>(0))
    node CAlignDist_0 = or(CAlignDist_floor, T_191040)
    node T_191041 = eq(isZeroC, UInt<1>(0))
    node T_191042 = bits(sNatCAlignDist, 12, 0)
    node T_191043 = lt(T_191042, UInt<6>(54))
    node T_191044 = or(CAlignDist_floor, T_191043)
    node isCDominant = and(T_191041, T_191044)
    node T_191045 = bits(sNatCAlignDist, 12, 0)
    node T_191046 = lt(T_191045, UInt<8>(161))
    wire T_191047 : UInt<8>
    T_191047 := UInt<8>(161)
    when T_191046 : T_191047 := sNatCAlignDist
    wire T_191048 : UInt<8>
    T_191048 := T_191047
    when CAlignDist_floor : T_191048 := UInt<1>(0)
    node CAlignDist = bits(T_191048, 7, 0)
    wire sExpSum : UInt<14>
    sExpSum := sExpAlignedProd
    when CAlignDist_floor : sExpSum := expC
    node T_191049 = dshr(SInt<257>(-115792089237316195423570985008687907853269984665640564039457584007913129639936), CAlignDist)
    node T_191050 = bits(T_191049, 147, 95)
    node T_191051 = bits(T_191050, 31, 0)
    node T_191052 = dshl(UInt<16>(65535), UInt<5>(16))
    node T_191053 = xor(UInt<32>(4294967295), T_191052)
    node T_191054 = dshr(T_191051, UInt<5>(16))
    node T_191055 = and(T_191054, T_191053)
    node T_191056 = bits(T_191051, 15, 0)
    node T_191057 = dshl(T_191056, UInt<5>(16))
    node T_191058 = not(T_191053)
    node T_191059 = and(T_191057, T_191058)
    node T_191060 = or(T_191055, T_191059)
    node T_191061 = bits(T_191053, 23, 0)
    node T_191062 = dshl(T_191061, UInt<4>(8))
    node T_191063 = xor(T_191053, T_191062)
    node T_191064 = dshr(T_191060, UInt<4>(8))
    node T_191065 = and(T_191064, T_191063)
    node T_191066 = bits(T_191060, 23, 0)
    node T_191067 = dshl(T_191066, UInt<4>(8))
    node T_191068 = not(T_191063)
    node T_191069 = and(T_191067, T_191068)
    node T_191070 = or(T_191065, T_191069)
    node T_191071 = bits(T_191063, 27, 0)
    node T_191072 = dshl(T_191071, UInt<3>(4))
    node T_191073 = xor(T_191063, T_191072)
    node T_191074 = dshr(T_191070, UInt<3>(4))
    node T_191075 = and(T_191074, T_191073)
    node T_191076 = bits(T_191070, 27, 0)
    node T_191077 = dshl(T_191076, UInt<3>(4))
    node T_191078 = not(T_191073)
    node T_191079 = and(T_191077, T_191078)
    node T_191080 = or(T_191075, T_191079)
    node T_191081 = bits(T_191073, 29, 0)
    node T_191082 = dshl(T_191081, UInt<2>(2))
    node T_191083 = xor(T_191073, T_191082)
    node T_191084 = dshr(T_191080, UInt<2>(2))
    node T_191085 = and(T_191084, T_191083)
    node T_191086 = bits(T_191080, 29, 0)
    node T_191087 = dshl(T_191086, UInt<2>(2))
    node T_191088 = not(T_191083)
    node T_191089 = and(T_191087, T_191088)
    node T_191090 = or(T_191085, T_191089)
    node T_191091 = bits(T_191083, 30, 0)
    node T_191092 = dshl(T_191091, UInt<1>(1))
    node T_191093 = xor(T_191083, T_191092)
    node T_191094 = dshr(T_191090, UInt<1>(1))
    node T_191095 = and(T_191094, T_191093)
    node T_191096 = bits(T_191090, 30, 0)
    node T_191097 = dshl(T_191096, UInt<1>(1))
    node T_191098 = not(T_191093)
    node T_191099 = and(T_191097, T_191098)
    node T_191100 = or(T_191095, T_191099)
    node T_191101 = bits(T_191050, 52, 32)
    node T_191102 = bits(T_191101, 15, 0)
    node T_191103 = dshl(UInt<8>(255), UInt<4>(8))
    node T_191104 = xor(UInt<16>(65535), T_191103)
    node T_191105 = dshr(T_191102, UInt<4>(8))
    node T_191106 = and(T_191105, T_191104)
    node T_191107 = bits(T_191102, 7, 0)
    node T_191108 = dshl(T_191107, UInt<4>(8))
    node T_191109 = not(T_191104)
    node T_191110 = and(T_191108, T_191109)
    node T_191111 = or(T_191106, T_191110)
    node T_191112 = bits(T_191104, 11, 0)
    node T_191113 = dshl(T_191112, UInt<3>(4))
    node T_191114 = xor(T_191104, T_191113)
    node T_191115 = dshr(T_191111, UInt<3>(4))
    node T_191116 = and(T_191115, T_191114)
    node T_191117 = bits(T_191111, 11, 0)
    node T_191118 = dshl(T_191117, UInt<3>(4))
    node T_191119 = not(T_191114)
    node T_191120 = and(T_191118, T_191119)
    node T_191121 = or(T_191116, T_191120)
    node T_191122 = bits(T_191114, 13, 0)
    node T_191123 = dshl(T_191122, UInt<2>(2))
    node T_191124 = xor(T_191114, T_191123)
    node T_191125 = dshr(T_191121, UInt<2>(2))
    node T_191126 = and(T_191125, T_191124)
    node T_191127 = bits(T_191121, 13, 0)
    node T_191128 = dshl(T_191127, UInt<2>(2))
    node T_191129 = not(T_191124)
    node T_191130 = and(T_191128, T_191129)
    node T_191131 = or(T_191126, T_191130)
    node T_191132 = bits(T_191124, 14, 0)
    node T_191133 = dshl(T_191132, UInt<1>(1))
    node T_191134 = xor(T_191124, T_191133)
    node T_191135 = dshr(T_191131, UInt<1>(1))
    node T_191136 = and(T_191135, T_191134)
    node T_191137 = bits(T_191131, 14, 0)
    node T_191138 = dshl(T_191137, UInt<1>(1))
    node T_191139 = not(T_191134)
    node T_191140 = and(T_191138, T_191139)
    node T_191141 = or(T_191136, T_191140)
    node T_191142 = bits(T_191101, 20, 16)
    node T_191143 = bits(T_191142, 3, 0)
    node T_191144 = bits(T_191143, 1, 0)
    node T_191145 = bits(T_191144, 0, 0)
    node T_191146 = bits(T_191144, 1, 1)
    node T_191147 = cat(T_191145, T_191146)
    node T_191148 = bits(T_191143, 3, 2)
    node T_191149 = bits(T_191148, 0, 0)
    node T_191150 = bits(T_191148, 1, 1)
    node T_191151 = cat(T_191149, T_191150)
    node T_191152 = cat(T_191147, T_191151)
    node T_191153 = bits(T_191142, 4, 4)
    node T_191154 = cat(T_191152, T_191153)
    node T_191155 = cat(T_191141, T_191154)
    node CExtraMask = cat(T_191100, T_191155)
    node T_191156 = not(sigC)
    wire negSigC : UInt<53>
    negSigC := sigC
    when doSubMags : negSigC := T_191156
    node T_191157 = subw(UInt<108>(0), UInt<7>(108))
    node T_191158 = cat(negSigC, T_191157)
    node T_191159 = cat(doSubMags, T_191158)
    node T_191160 = asSInt(T_191159)
    node T_191161 = dshr(T_191160, CAlignDist)
    node T_191162 = and(sigC, CExtraMask)
    node T_191163 = neq(T_191162, UInt<1>(0))
    node T_191164 = xor(T_191163, doSubMags)
    node T_191165 = asUInt(T_191161)
    node T_191166 = cat(T_191165, T_191164)
    node alignedNegSigC = bits(T_191166, 161, 0)
    node T_191167 = mul(sigA, sigB)
    node T_191168 = dshl(T_191167, UInt<1>(1))
    node sigSum = addw(T_191168, alignedNegSigC)
    node T_191169 = bits(sigSum, 108, 1)
    node T_191170 = xor(UInt<108>(0), T_191169)
    node T_191171 = or(UInt<108>(0), T_191169)
    node T_191172 = dshl(T_191171, UInt<1>(1))
    node T_191173 = xor(T_191170, T_191172)
    node T_191174 = bit(T_191173, 107)
    node T_191175 = bit(T_191173, 106)
    node T_191176 = bit(T_191173, 105)
    node T_191177 = bit(T_191173, 104)
    node T_191178 = bit(T_191173, 103)
    node T_191179 = bit(T_191173, 102)
    node T_191180 = bit(T_191173, 101)
    node T_191181 = bit(T_191173, 100)
    node T_191182 = bit(T_191173, 99)
    node T_191183 = bit(T_191173, 98)
    node T_191184 = bit(T_191173, 97)
    node T_191185 = bit(T_191173, 96)
    node T_191186 = bit(T_191173, 95)
    node T_191187 = bit(T_191173, 94)
    node T_191188 = bit(T_191173, 93)
    node T_191189 = bit(T_191173, 92)
    node T_191190 = bit(T_191173, 91)
    node T_191191 = bit(T_191173, 90)
    node T_191192 = bit(T_191173, 89)
    node T_191193 = bit(T_191173, 88)
    node T_191194 = bit(T_191173, 87)
    node T_191195 = bit(T_191173, 86)
    node T_191196 = bit(T_191173, 85)
    node T_191197 = bit(T_191173, 84)
    node T_191198 = bit(T_191173, 83)
    node T_191199 = bit(T_191173, 82)
    node T_191200 = bit(T_191173, 81)
    node T_191201 = bit(T_191173, 80)
    node T_191202 = bit(T_191173, 79)
    node T_191203 = bit(T_191173, 78)
    node T_191204 = bit(T_191173, 77)
    node T_191205 = bit(T_191173, 76)
    node T_191206 = bit(T_191173, 75)
    node T_191207 = bit(T_191173, 74)
    node T_191208 = bit(T_191173, 73)
    node T_191209 = bit(T_191173, 72)
    node T_191210 = bit(T_191173, 71)
    node T_191211 = bit(T_191173, 70)
    node T_191212 = bit(T_191173, 69)
    node T_191213 = bit(T_191173, 68)
    node T_191214 = bit(T_191173, 67)
    node T_191215 = bit(T_191173, 66)
    node T_191216 = bit(T_191173, 65)
    node T_191217 = bit(T_191173, 64)
    node T_191218 = bit(T_191173, 63)
    node T_191219 = bit(T_191173, 62)
    node T_191220 = bit(T_191173, 61)
    node T_191221 = bit(T_191173, 60)
    node T_191222 = bit(T_191173, 59)
    node T_191223 = bit(T_191173, 58)
    node T_191224 = bit(T_191173, 57)
    node T_191225 = bit(T_191173, 56)
    node T_191226 = bit(T_191173, 55)
    node T_191227 = bit(T_191173, 54)
    node T_191228 = bit(T_191173, 53)
    node T_191229 = bit(T_191173, 52)
    node T_191230 = bit(T_191173, 51)
    node T_191231 = bit(T_191173, 50)
    node T_191232 = bit(T_191173, 49)
    node T_191233 = bit(T_191173, 48)
    node T_191234 = bit(T_191173, 47)
    node T_191235 = bit(T_191173, 46)
    node T_191236 = bit(T_191173, 45)
    node T_191237 = bit(T_191173, 44)
    node T_191238 = bit(T_191173, 43)
    node T_191239 = bit(T_191173, 42)
    node T_191240 = bit(T_191173, 41)
    node T_191241 = bit(T_191173, 40)
    node T_191242 = bit(T_191173, 39)
    node T_191243 = bit(T_191173, 38)
    node T_191244 = bit(T_191173, 37)
    node T_191245 = bit(T_191173, 36)
    node T_191246 = bit(T_191173, 35)
    node T_191247 = bit(T_191173, 34)
    node T_191248 = bit(T_191173, 33)
    node T_191249 = bit(T_191173, 32)
    node T_191250 = bit(T_191173, 31)
    node T_191251 = bit(T_191173, 30)
    node T_191252 = bit(T_191173, 29)
    node T_191253 = bit(T_191173, 28)
    node T_191254 = bit(T_191173, 27)
    node T_191255 = bit(T_191173, 26)
    node T_191256 = bit(T_191173, 25)
    node T_191257 = bit(T_191173, 24)
    node T_191258 = bit(T_191173, 23)
    node T_191259 = bit(T_191173, 22)
    node T_191260 = bit(T_191173, 21)
    node T_191261 = bit(T_191173, 20)
    node T_191262 = bit(T_191173, 19)
    node T_191263 = bit(T_191173, 18)
    node T_191264 = bit(T_191173, 17)
    node T_191265 = bit(T_191173, 16)
    node T_191266 = bit(T_191173, 15)
    node T_191267 = bit(T_191173, 14)
    node T_191268 = bit(T_191173, 13)
    node T_191269 = bit(T_191173, 12)
    node T_191270 = bit(T_191173, 11)
    node T_191271 = bit(T_191173, 10)
    node T_191272 = bit(T_191173, 9)
    node T_191273 = bit(T_191173, 8)
    node T_191274 = bit(T_191173, 7)
    node T_191275 = bit(T_191173, 6)
    node T_191276 = bit(T_191173, 5)
    node T_191277 = bit(T_191173, 4)
    node T_191278 = bit(T_191173, 3)
    node T_191279 = bit(T_191173, 2)
    node T_191280 = bit(T_191173, 1)
    node T_191281 = bit(T_191173, 0)
    wire T_191282 : UInt<8>
    T_191282 := UInt<8>(160)
    when T_191280 : T_191282 := UInt<8>(159)
    wire T_191283 : UInt<8>
    T_191283 := T_191282
    when T_191279 : T_191283 := UInt<8>(158)
    wire T_191284 : UInt<8>
    T_191284 := T_191283
    when T_191278 : T_191284 := UInt<8>(157)
    wire T_191285 : UInt<8>
    T_191285 := T_191284
    when T_191277 : T_191285 := UInt<8>(156)
    wire T_191286 : UInt<8>
    T_191286 := T_191285
    when T_191276 : T_191286 := UInt<8>(155)
    wire T_191287 : UInt<8>
    T_191287 := T_191286
    when T_191275 : T_191287 := UInt<8>(154)
    wire T_191288 : UInt<8>
    T_191288 := T_191287
    when T_191274 : T_191288 := UInt<8>(153)
    wire T_191289 : UInt<8>
    T_191289 := T_191288
    when T_191273 : T_191289 := UInt<8>(152)
    wire T_191290 : UInt<8>
    T_191290 := T_191289
    when T_191272 : T_191290 := UInt<8>(151)
    wire T_191291 : UInt<8>
    T_191291 := T_191290
    when T_191271 : T_191291 := UInt<8>(150)
    wire T_191292 : UInt<8>
    T_191292 := T_191291
    when T_191270 : T_191292 := UInt<8>(149)
    wire T_191293 : UInt<8>
    T_191293 := T_191292
    when T_191269 : T_191293 := UInt<8>(148)
    wire T_191294 : UInt<8>
    T_191294 := T_191293
    when T_191268 : T_191294 := UInt<8>(147)
    wire T_191295 : UInt<8>
    T_191295 := T_191294
    when T_191267 : T_191295 := UInt<8>(146)
    wire T_191296 : UInt<8>
    T_191296 := T_191295
    when T_191266 : T_191296 := UInt<8>(145)
    wire T_191297 : UInt<8>
    T_191297 := T_191296
    when T_191265 : T_191297 := UInt<8>(144)
    wire T_191298 : UInt<8>
    T_191298 := T_191297
    when T_191264 : T_191298 := UInt<8>(143)
    wire T_191299 : UInt<8>
    T_191299 := T_191298
    when T_191263 : T_191299 := UInt<8>(142)
    wire T_191300 : UInt<8>
    T_191300 := T_191299
    when T_191262 : T_191300 := UInt<8>(141)
    wire T_191301 : UInt<8>
    T_191301 := T_191300
    when T_191261 : T_191301 := UInt<8>(140)
    wire T_191302 : UInt<8>
    T_191302 := T_191301
    when T_191260 : T_191302 := UInt<8>(139)
    wire T_191303 : UInt<8>
    T_191303 := T_191302
    when T_191259 : T_191303 := UInt<8>(138)
    wire T_191304 : UInt<8>
    T_191304 := T_191303
    when T_191258 : T_191304 := UInt<8>(137)
    wire T_191305 : UInt<8>
    T_191305 := T_191304
    when T_191257 : T_191305 := UInt<8>(136)
    wire T_191306 : UInt<8>
    T_191306 := T_191305
    when T_191256 : T_191306 := UInt<8>(135)
    wire T_191307 : UInt<8>
    T_191307 := T_191306
    when T_191255 : T_191307 := UInt<8>(134)
    wire T_191308 : UInt<8>
    T_191308 := T_191307
    when T_191254 : T_191308 := UInt<8>(133)
    wire T_191309 : UInt<8>
    T_191309 := T_191308
    when T_191253 : T_191309 := UInt<8>(132)
    wire T_191310 : UInt<8>
    T_191310 := T_191309
    when T_191252 : T_191310 := UInt<8>(131)
    wire T_191311 : UInt<8>
    T_191311 := T_191310
    when T_191251 : T_191311 := UInt<8>(130)
    wire T_191312 : UInt<8>
    T_191312 := T_191311
    when T_191250 : T_191312 := UInt<8>(129)
    wire T_191313 : UInt<8>
    T_191313 := T_191312
    when T_191249 : T_191313 := UInt<8>(128)
    wire T_191314 : UInt<8>
    T_191314 := T_191313
    when T_191248 : T_191314 := UInt<8>(127)
    wire T_191315 : UInt<8>
    T_191315 := T_191314
    when T_191247 : T_191315 := UInt<8>(126)
    wire T_191316 : UInt<8>
    T_191316 := T_191315
    when T_191246 : T_191316 := UInt<8>(125)
    wire T_191317 : UInt<8>
    T_191317 := T_191316
    when T_191245 : T_191317 := UInt<8>(124)
    wire T_191318 : UInt<8>
    T_191318 := T_191317
    when T_191244 : T_191318 := UInt<8>(123)
    wire T_191319 : UInt<8>
    T_191319 := T_191318
    when T_191243 : T_191319 := UInt<8>(122)
    wire T_191320 : UInt<8>
    T_191320 := T_191319
    when T_191242 : T_191320 := UInt<8>(121)
    wire T_191321 : UInt<8>
    T_191321 := T_191320
    when T_191241 : T_191321 := UInt<8>(120)
    wire T_191322 : UInt<8>
    T_191322 := T_191321
    when T_191240 : T_191322 := UInt<8>(119)
    wire T_191323 : UInt<8>
    T_191323 := T_191322
    when T_191239 : T_191323 := UInt<8>(118)
    wire T_191324 : UInt<8>
    T_191324 := T_191323
    when T_191238 : T_191324 := UInt<8>(117)
    wire T_191325 : UInt<8>
    T_191325 := T_191324
    when T_191237 : T_191325 := UInt<8>(116)
    wire T_191326 : UInt<8>
    T_191326 := T_191325
    when T_191236 : T_191326 := UInt<8>(115)
    wire T_191327 : UInt<8>
    T_191327 := T_191326
    when T_191235 : T_191327 := UInt<8>(114)
    wire T_191328 : UInt<8>
    T_191328 := T_191327
    when T_191234 : T_191328 := UInt<8>(113)
    wire T_191329 : UInt<8>
    T_191329 := T_191328
    when T_191233 : T_191329 := UInt<8>(112)
    wire T_191330 : UInt<8>
    T_191330 := T_191329
    when T_191232 : T_191330 := UInt<8>(111)
    wire T_191331 : UInt<8>
    T_191331 := T_191330
    when T_191231 : T_191331 := UInt<8>(110)
    wire T_191332 : UInt<8>
    T_191332 := T_191331
    when T_191230 : T_191332 := UInt<8>(109)
    wire T_191333 : UInt<8>
    T_191333 := T_191332
    when T_191229 : T_191333 := UInt<8>(108)
    wire T_191334 : UInt<8>
    T_191334 := T_191333
    when T_191228 : T_191334 := UInt<8>(107)
    wire T_191335 : UInt<8>
    T_191335 := T_191334
    when T_191227 : T_191335 := UInt<8>(106)
    wire T_191336 : UInt<8>
    T_191336 := T_191335
    when T_191226 : T_191336 := UInt<8>(105)
    wire T_191337 : UInt<8>
    T_191337 := T_191336
    when T_191225 : T_191337 := UInt<8>(104)
    wire T_191338 : UInt<8>
    T_191338 := T_191337
    when T_191224 : T_191338 := UInt<8>(103)
    wire T_191339 : UInt<8>
    T_191339 := T_191338
    when T_191223 : T_191339 := UInt<8>(102)
    wire T_191340 : UInt<8>
    T_191340 := T_191339
    when T_191222 : T_191340 := UInt<8>(101)
    wire T_191341 : UInt<8>
    T_191341 := T_191340
    when T_191221 : T_191341 := UInt<8>(100)
    wire T_191342 : UInt<8>
    T_191342 := T_191341
    when T_191220 : T_191342 := UInt<8>(99)
    wire T_191343 : UInt<8>
    T_191343 := T_191342
    when T_191219 : T_191343 := UInt<8>(98)
    wire T_191344 : UInt<8>
    T_191344 := T_191343
    when T_191218 : T_191344 := UInt<8>(97)
    wire T_191345 : UInt<8>
    T_191345 := T_191344
    when T_191217 : T_191345 := UInt<8>(96)
    wire T_191346 : UInt<8>
    T_191346 := T_191345
    when T_191216 : T_191346 := UInt<8>(95)
    wire T_191347 : UInt<8>
    T_191347 := T_191346
    when T_191215 : T_191347 := UInt<8>(94)
    wire T_191348 : UInt<8>
    T_191348 := T_191347
    when T_191214 : T_191348 := UInt<8>(93)
    wire T_191349 : UInt<8>
    T_191349 := T_191348
    when T_191213 : T_191349 := UInt<8>(92)
    wire T_191350 : UInt<8>
    T_191350 := T_191349
    when T_191212 : T_191350 := UInt<8>(91)
    wire T_191351 : UInt<8>
    T_191351 := T_191350
    when T_191211 : T_191351 := UInt<8>(90)
    wire T_191352 : UInt<8>
    T_191352 := T_191351
    when T_191210 : T_191352 := UInt<8>(89)
    wire T_191353 : UInt<8>
    T_191353 := T_191352
    when T_191209 : T_191353 := UInt<8>(88)
    wire T_191354 : UInt<8>
    T_191354 := T_191353
    when T_191208 : T_191354 := UInt<8>(87)
    wire T_191355 : UInt<8>
    T_191355 := T_191354
    when T_191207 : T_191355 := UInt<8>(86)
    wire T_191356 : UInt<8>
    T_191356 := T_191355
    when T_191206 : T_191356 := UInt<8>(85)
    wire T_191357 : UInt<8>
    T_191357 := T_191356
    when T_191205 : T_191357 := UInt<8>(84)
    wire T_191358 : UInt<8>
    T_191358 := T_191357
    when T_191204 : T_191358 := UInt<8>(83)
    wire T_191359 : UInt<8>
    T_191359 := T_191358
    when T_191203 : T_191359 := UInt<8>(82)
    wire T_191360 : UInt<8>
    T_191360 := T_191359
    when T_191202 : T_191360 := UInt<8>(81)
    wire T_191361 : UInt<8>
    T_191361 := T_191360
    when T_191201 : T_191361 := UInt<8>(80)
    wire T_191362 : UInt<8>
    T_191362 := T_191361
    when T_191200 : T_191362 := UInt<8>(79)
    wire T_191363 : UInt<8>
    T_191363 := T_191362
    when T_191199 : T_191363 := UInt<8>(78)
    wire T_191364 : UInt<8>
    T_191364 := T_191363
    when T_191198 : T_191364 := UInt<8>(77)
    wire T_191365 : UInt<8>
    T_191365 := T_191364
    when T_191197 : T_191365 := UInt<8>(76)
    wire T_191366 : UInt<8>
    T_191366 := T_191365
    when T_191196 : T_191366 := UInt<8>(75)
    wire T_191367 : UInt<8>
    T_191367 := T_191366
    when T_191195 : T_191367 := UInt<8>(74)
    wire T_191368 : UInt<8>
    T_191368 := T_191367
    when T_191194 : T_191368 := UInt<8>(73)
    wire T_191369 : UInt<8>
    T_191369 := T_191368
    when T_191193 : T_191369 := UInt<8>(72)
    wire T_191370 : UInt<8>
    T_191370 := T_191369
    when T_191192 : T_191370 := UInt<8>(71)
    wire T_191371 : UInt<8>
    T_191371 := T_191370
    when T_191191 : T_191371 := UInt<8>(70)
    wire T_191372 : UInt<8>
    T_191372 := T_191371
    when T_191190 : T_191372 := UInt<8>(69)
    wire T_191373 : UInt<8>
    T_191373 := T_191372
    when T_191189 : T_191373 := UInt<8>(68)
    wire T_191374 : UInt<8>
    T_191374 := T_191373
    when T_191188 : T_191374 := UInt<8>(67)
    wire T_191375 : UInt<8>
    T_191375 := T_191374
    when T_191187 : T_191375 := UInt<8>(66)
    wire T_191376 : UInt<8>
    T_191376 := T_191375
    when T_191186 : T_191376 := UInt<8>(65)
    wire T_191377 : UInt<8>
    T_191377 := T_191376
    when T_191185 : T_191377 := UInt<8>(64)
    wire T_191378 : UInt<8>
    T_191378 := T_191377
    when T_191184 : T_191378 := UInt<8>(63)
    wire T_191379 : UInt<8>
    T_191379 := T_191378
    when T_191183 : T_191379 := UInt<8>(62)
    wire T_191380 : UInt<8>
    T_191380 := T_191379
    when T_191182 : T_191380 := UInt<8>(61)
    wire T_191381 : UInt<8>
    T_191381 := T_191380
    when T_191181 : T_191381 := UInt<8>(60)
    wire T_191382 : UInt<8>
    T_191382 := T_191381
    when T_191180 : T_191382 := UInt<8>(59)
    wire T_191383 : UInt<8>
    T_191383 := T_191382
    when T_191179 : T_191383 := UInt<8>(58)
    wire T_191384 : UInt<8>
    T_191384 := T_191383
    when T_191178 : T_191384 := UInt<8>(57)
    wire T_191385 : UInt<8>
    T_191385 := T_191384
    when T_191177 : T_191385 := UInt<8>(56)
    wire T_191386 : UInt<8>
    T_191386 := T_191385
    when T_191176 : T_191386 := UInt<8>(55)
    wire T_191387 : UInt<8>
    T_191387 := T_191386
    when T_191175 : T_191387 := UInt<8>(54)
    wire estNormPos_dist : UInt<8>
    estNormPos_dist := T_191387
    when T_191174 : estNormPos_dist := UInt<8>(53)
    node T_191388 = bits(sigSum, 75, 44)
    node T_191389 = neq(T_191388, UInt<1>(0))
    node T_191390 = bits(sigSum, 43, 0)
    node T_191391 = neq(T_191390, UInt<1>(0))
    node firstReduceSigSum = cat(T_191389, T_191391)
    node notSigSum = not(sigSum)
    node T_191392 = bits(notSigSum, 75, 44)
    node T_191393 = neq(T_191392, UInt<1>(0))
    node T_191394 = bits(notSigSum, 43, 0)
    node T_191395 = neq(T_191394, UInt<1>(0))
    node firstReduceNotSigSum = cat(T_191393, T_191395)
    node T_191396 = or(CAlignDist_0, doSubMags)
    node T_191397 = subw(CAlignDist, UInt<1>(1))
    node T_191398 = bits(T_191397, 5, 0)
    wire CDom_estNormDist : UInt<6>
    CDom_estNormDist := T_191398
    when T_191396 : CDom_estNormDist := CAlignDist
    node T_191399 = not(doSubMags)
    node T_191400 = bit(CDom_estNormDist, 5)
    node T_191401 = not(T_191400)
    node T_191402 = and(T_191399, T_191401)
    node T_191403 = asSInt(T_191402)
    node T_191404 = bits(sigSum, 161, 76)
    node T_191405 = neq(firstReduceSigSum, UInt<1>(0))
    node T_191406 = cat(T_191404, T_191405)
    node T_191407 = asSInt(T_191406)
    node T_191408 = and(T_191403, T_191407)
    node T_191409 = not(doSubMags)
    node T_191410 = bit(CDom_estNormDist, 5)
    node T_191411 = and(T_191409, T_191410)
    node T_191412 = asSInt(T_191411)
    node T_191413 = bits(sigSum, 129, 44)
    node T_191414 = bit(firstReduceSigSum, 0)
    node T_191415 = cat(T_191413, T_191414)
    node T_191416 = asSInt(T_191415)
    node T_191417 = and(T_191412, T_191416)
    node T_191418 = or(T_191408, T_191417)
    node T_191419 = bit(CDom_estNormDist, 5)
    node T_191420 = not(T_191419)
    node T_191421 = and(doSubMags, T_191420)
    node T_191422 = asSInt(T_191421)
    node T_191423 = bits(notSigSum, 161, 76)
    node T_191424 = neq(firstReduceNotSigSum, UInt<1>(0))
    node T_191425 = cat(T_191423, T_191424)
    node T_191426 = asSInt(T_191425)
    node T_191427 = and(T_191422, T_191426)
    node T_191428 = or(T_191418, T_191427)
    node T_191429 = bit(CDom_estNormDist, 5)
    node T_191430 = and(doSubMags, T_191429)
    node T_191431 = asSInt(T_191430)
    node T_191432 = bits(notSigSum, 129, 44)
    node T_191433 = bit(firstReduceNotSigSum, 0)
    node T_191434 = cat(T_191432, T_191433)
    node T_191435 = asSInt(T_191434)
    node T_191436 = and(T_191431, T_191435)
    node T_191437 = or(T_191428, T_191436)
    node CDom_firstNormAbsSigSum = asUInt(T_191437)
    node T_191438 = bits(sigSum, 108, 44)
    node T_191439 = bit(firstReduceNotSigSum, 0)
    node T_191440 = not(T_191439)
    node T_191441 = bit(firstReduceSigSum, 0)
    wire T_191442 : UInt<1>
    T_191442 := T_191441
    when doSubMags : T_191442 := T_191440
    node T_191443 = cat(T_191438, T_191442)
    node T_191444 = bits(sigSum, 97, 1)
    node T_191445 = bit(estNormPos_dist, 4)
    node T_191446 = bits(sigSum, 1, 1)
    node T_191447 = subw(UInt<86>(0), UInt<7>(86))
    node T_191448 = cat(T_191446, T_191447)
    wire T_191449 : UInt<87>
    T_191449 := T_191448
    when T_191445 : T_191449 := T_191443
    node T_191450 = bits(sigSum, 97, 12)
    node T_191451 = bits(notSigSum, 11, 1)
    node T_191452 = eq(T_191451, UInt<1>(0))
    node T_191453 = bits(sigSum, 11, 1)
    node T_191454 = neq(T_191453, UInt<1>(0))
    wire T_191455 : UInt<1>
    T_191455 := T_191454
    when doSubMags : T_191455 := T_191452
    node T_191456 = cat(T_191450, T_191455)
    node T_191457 = bit(estNormPos_dist, 6)
    node T_191458 = bit(estNormPos_dist, 5)
    node T_191459 = bits(sigSum, 65, 1)
    node T_191460 = subw(UInt<22>(0), UInt<5>(22))
    node T_191461 = cat(T_191459, T_191460)
    wire T_191462 : UInt<87>
    T_191462 := T_191456
    when T_191458 : T_191462 := T_191461
    node T_191463 = bit(estNormPos_dist, 5)
    node T_191464 = bits(sigSum, 33, 1)
    node T_191465 = subw(UInt<54>(0), UInt<6>(54))
    node T_191466 = cat(T_191464, T_191465)
    wire T_191467 : UInt<87>
    T_191467 := T_191466
    when T_191463 : T_191467 := T_191449
    wire notCDom_pos_firstNormAbsSigSum : UInt<87>
    notCDom_pos_firstNormAbsSigSum := T_191467
    when T_191457 : notCDom_pos_firstNormAbsSigSum := T_191462
    node T_191468 = bits(notSigSum, 107, 44)
    node T_191469 = bit(firstReduceNotSigSum, 0)
    node T_191470 = cat(T_191468, T_191469)
    node T_191471 = bits(notSigSum, 97, 1)
    node T_191472 = bit(estNormPos_dist, 4)
    node T_191473 = bits(notSigSum, 2, 1)
    node T_191474 = dshl(T_191473, UInt<7>(86))
    wire T_191475 : UInt<130>
    T_191475 := T_191474
    when T_191472 : T_191475 := T_191470
    node T_191476 = bits(notSigSum, 98, 12)
    node T_191477 = bits(notSigSum, 11, 1)
    node T_191478 = neq(T_191477, UInt<1>(0))
    node T_191479 = cat(T_191476, T_191478)
    node T_191480 = bit(estNormPos_dist, 6)
    node T_191481 = bit(estNormPos_dist, 5)
    node T_191482 = bits(notSigSum, 66, 1)
    node T_191483 = dshl(T_191482, UInt<5>(22))
    wire T_191484 : UInt<88>
    T_191484 := T_191479
    when T_191481 : T_191484 := T_191483
    node T_191485 = bit(estNormPos_dist, 5)
    node T_191486 = bits(notSigSum, 34, 1)
    node T_191487 = dshl(T_191486, UInt<6>(54))
    wire T_191488 : UInt<98>
    T_191488 := T_191487
    when T_191485 : T_191488 := T_191475
    wire notCDom_neg_cFirstNormAbsSigSum : UInt<98>
    notCDom_neg_cFirstNormAbsSigSum := T_191488
    when T_191480 : notCDom_neg_cFirstNormAbsSigSum := T_191484
    node notCDom_signSigSum = bit(sigSum, 109)
    node T_191489 = not(isZeroC)
    node T_191490 = and(doSubMags, T_191489)
    wire doNegSignSum : UInt<1>
    doNegSignSum := notCDom_signSigSum
    when isCDominant : doNegSignSum := T_191490
    wire T_191491 : UInt<8>
    T_191491 := estNormPos_dist
    when notCDom_signSigSum : T_191491 := estNormPos_dist
    wire estNormDist : UInt<8>
    estNormDist := T_191491
    when isCDominant : estNormDist := CDom_estNormDist
    wire T_191492 : UInt<98>
    T_191492 := notCDom_neg_cFirstNormAbsSigSum
    when isCDominant : T_191492 := CDom_firstNormAbsSigSum
    wire T_191493 : UInt<87>
    T_191493 := notCDom_pos_firstNormAbsSigSum
    when isCDominant : T_191493 := CDom_firstNormAbsSigSum
    wire cFirstNormAbsSigSum : UInt<87>
    cFirstNormAbsSigSum := T_191493
    when notCDom_signSigSum : cFirstNormAbsSigSum := T_191492
    node T_191494 = not(isCDominant)
    node T_191495 = not(notCDom_signSigSum)
    node T_191496 = and(T_191494, T_191495)
    node doIncrSig = and(T_191496, doSubMags)
    node estNormDist_5 = bits(estNormDist, 4, 0)
    node normTo2ShiftDist = not(estNormDist_5)
    node T_191497 = dshr(SInt<33>(-4294967296), normTo2ShiftDist)
    node T_191498 = bits(T_191497, 31, 1)
    node T_191499 = bits(T_191498, 15, 0)
    node T_191500 = dshl(UInt<8>(255), UInt<4>(8))
    node T_191501 = xor(UInt<16>(65535), T_191500)
    node T_191502 = dshr(T_191499, UInt<4>(8))
    node T_191503 = and(T_191502, T_191501)
    node T_191504 = bits(T_191499, 7, 0)
    node T_191505 = dshl(T_191504, UInt<4>(8))
    node T_191506 = not(T_191501)
    node T_191507 = and(T_191505, T_191506)
    node T_191508 = or(T_191503, T_191507)
    node T_191509 = bits(T_191501, 11, 0)
    node T_191510 = dshl(T_191509, UInt<3>(4))
    node T_191511 = xor(T_191501, T_191510)
    node T_191512 = dshr(T_191508, UInt<3>(4))
    node T_191513 = and(T_191512, T_191511)
    node T_191514 = bits(T_191508, 11, 0)
    node T_191515 = dshl(T_191514, UInt<3>(4))
    node T_191516 = not(T_191511)
    node T_191517 = and(T_191515, T_191516)
    node T_191518 = or(T_191513, T_191517)
    node T_191519 = bits(T_191511, 13, 0)
    node T_191520 = dshl(T_191519, UInt<2>(2))
    node T_191521 = xor(T_191511, T_191520)
    node T_191522 = dshr(T_191518, UInt<2>(2))
    node T_191523 = and(T_191522, T_191521)
    node T_191524 = bits(T_191518, 13, 0)
    node T_191525 = dshl(T_191524, UInt<2>(2))
    node T_191526 = not(T_191521)
    node T_191527 = and(T_191525, T_191526)
    node T_191528 = or(T_191523, T_191527)
    node T_191529 = bits(T_191521, 14, 0)
    node T_191530 = dshl(T_191529, UInt<1>(1))
    node T_191531 = xor(T_191521, T_191530)
    node T_191532 = dshr(T_191528, UInt<1>(1))
    node T_191533 = and(T_191532, T_191531)
    node T_191534 = bits(T_191528, 14, 0)
    node T_191535 = dshl(T_191534, UInt<1>(1))
    node T_191536 = not(T_191531)
    node T_191537 = and(T_191535, T_191536)
    node T_191538 = or(T_191533, T_191537)
    node T_191539 = bits(T_191498, 30, 16)
    node T_191540 = bits(T_191539, 7, 0)
    node T_191541 = dshl(UInt<4>(15), UInt<3>(4))
    node T_191542 = xor(UInt<8>(255), T_191541)
    node T_191543 = dshr(T_191540, UInt<3>(4))
    node T_191544 = and(T_191543, T_191542)
    node T_191545 = bits(T_191540, 3, 0)
    node T_191546 = dshl(T_191545, UInt<3>(4))
    node T_191547 = not(T_191542)
    node T_191548 = and(T_191546, T_191547)
    node T_191549 = or(T_191544, T_191548)
    node T_191550 = bits(T_191542, 5, 0)
    node T_191551 = dshl(T_191550, UInt<2>(2))
    node T_191552 = xor(T_191542, T_191551)
    node T_191553 = dshr(T_191549, UInt<2>(2))
    node T_191554 = and(T_191553, T_191552)
    node T_191555 = bits(T_191549, 5, 0)
    node T_191556 = dshl(T_191555, UInt<2>(2))
    node T_191557 = not(T_191552)
    node T_191558 = and(T_191556, T_191557)
    node T_191559 = or(T_191554, T_191558)
    node T_191560 = bits(T_191552, 6, 0)
    node T_191561 = dshl(T_191560, UInt<1>(1))
    node T_191562 = xor(T_191552, T_191561)
    node T_191563 = dshr(T_191559, UInt<1>(1))
    node T_191564 = and(T_191563, T_191562)
    node T_191565 = bits(T_191559, 6, 0)
    node T_191566 = dshl(T_191565, UInt<1>(1))
    node T_191567 = not(T_191562)
    node T_191568 = and(T_191566, T_191567)
    node T_191569 = or(T_191564, T_191568)
    node T_191570 = bits(T_191539, 14, 8)
    node T_191571 = bits(T_191570, 3, 0)
    node T_191572 = bits(T_191571, 1, 0)
    node T_191573 = bits(T_191572, 0, 0)
    node T_191574 = bits(T_191572, 1, 1)
    node T_191575 = cat(T_191573, T_191574)
    node T_191576 = bits(T_191571, 3, 2)
    node T_191577 = bits(T_191576, 0, 0)
    node T_191578 = bits(T_191576, 1, 1)
    node T_191579 = cat(T_191577, T_191578)
    node T_191580 = cat(T_191575, T_191579)
    node T_191581 = bits(T_191570, 6, 4)
    node T_191582 = bits(T_191581, 1, 0)
    node T_191583 = bits(T_191582, 0, 0)
    node T_191584 = bits(T_191582, 1, 1)
    node T_191585 = cat(T_191583, T_191584)
    node T_191586 = bits(T_191581, 2, 2)
    node T_191587 = cat(T_191585, T_191586)
    node T_191588 = cat(T_191580, T_191587)
    node T_191589 = cat(T_191569, T_191588)
    node T_191590 = cat(T_191538, T_191589)
    node absSigSumExtraMask = cat(T_191590, UInt<1>(1))
    node T_191591 = bits(cFirstNormAbsSigSum, 87, 1)
    node T_191592 = dshr(T_191591, normTo2ShiftDist)
    node T_191593 = bits(cFirstNormAbsSigSum, 31, 0)
    node T_191594 = not(T_191593)
    node T_191595 = and(T_191594, absSigSumExtraMask)
    node T_191596 = eq(T_191595, UInt<1>(0))
    node T_191597 = bits(cFirstNormAbsSigSum, 31, 0)
    node T_191598 = and(T_191597, absSigSumExtraMask)
    node T_191599 = neq(T_191598, UInt<1>(0))
    wire T_191600 : UInt<1>
    T_191600 := T_191599
    when doIncrSig : T_191600 := T_191596
    node T_191601 = cat(T_191592, T_191600)
    node sigX3 = bits(T_191601, 56, 0)
    node T_191602 = bits(sigX3, 56, 55)
    node sigX3Shift1 = eq(T_191602, UInt<1>(0))
    node sExpX3 = subw(sExpSum, estNormDist)
    node T_191603 = bits(sigX3, 56, 54)
    node isZeroY = eq(T_191603, UInt<1>(0))
    node T_191604 = not(isZeroY)
    node T_191605 = xor(signProd, doNegSignSum)
    node signY = and(T_191604, T_191605)
    node sExpX3_13 = bits(sExpX3, 12, 0)
    node T_191606 = bit(sExpX3, 13)
    node T_191607 = subw(UInt<56>(0), UInt<6>(56))
    node T_191608 = not(sExpX3_13)
    node T_191609 = dshr(SInt<8193>(-1090748135619415929462984244733782862448264161996232692431832786189721331849119295216264234525201987223957291796157025273109870820177184063610979765077554799078906298842192989538609825228048205159696851613591638196771886542609324560121290553901886301017900252535799917200010079600026535836800905297805880952350501630195475653911005312364560014847426035293551245843928918752768696279344088055617515694349945406677825140814900616105920256438504578013326493565836047242407382442812245131517757519164899226365743722432277368075027627883045206501792761700945699168497257879683851737049996900961120515655050115561271491492515342105748966629547032786321505730828430221664970324396138635251626409516168005427623435996308921691446181187406395310665404885739434832877428167407495370993511868756359970390117021823616749458620969857006263612082706715408157066575137281027022310927564910276759160520878304632411049364568754920967322982459184763427383790272448438018526977764941072715611580434690827459339991961414242741410599117426060556483763756314527611362658628383368621157993638020878537675545336789915694234433955666315070087213535470255670312004130725495834508357439653828936077080978550578912967907352780054935621561090795845172954115972927479877527738560008204118558930004777748727761853813510493840581861598652211605960308356405941821189714037868726219481498727603653616298856174822413033485438785324024751419417183012281078209729303537372804574372095228703622776363945290869806258422355148507571039619387449629866808188769662815778153079393179093143648340761738581819563002994422790754955061288818308430079648693232179158765918035565216157115402992120276155607873107937477466841528362987708699450152031231862594203085693838944657061346236704234026821102958954951197087076546186622796294536451620756509351018906023773821539532776208676978589731966330308893304665169436185078350641568336944530051437491311298834367265238595404904273455928723949525227184617404367854754610474377019768025576605881038077270707717942221977090385438585844095492116099852538903974655703943973086090930596963360767529964938414598185705963754561497355827813623833288906309004288017321424808663962671333528009232758350873059614118723781422101460198615747386855096896089189180441339558524822867541113212638793675567650340362970031930023397828465318547238244232028015189689660418822976000815437610652254270163595650875433851147123214227266605403581781469090806576468950587661997186505665475715792896), T_191608)
    node T_191610 = bits(T_191609, 1027, 974)
    node T_191611 = bits(T_191610, 31, 0)
    node T_191612 = dshl(UInt<16>(65535), UInt<5>(16))
    node T_191613 = xor(UInt<32>(4294967295), T_191612)
    node T_191614 = dshr(T_191611, UInt<5>(16))
    node T_191615 = and(T_191614, T_191613)
    node T_191616 = bits(T_191611, 15, 0)
    node T_191617 = dshl(T_191616, UInt<5>(16))
    node T_191618 = not(T_191613)
    node T_191619 = and(T_191617, T_191618)
    node T_191620 = or(T_191615, T_191619)
    node T_191621 = bits(T_191613, 23, 0)
    node T_191622 = dshl(T_191621, UInt<4>(8))
    node T_191623 = xor(T_191613, T_191622)
    node T_191624 = dshr(T_191620, UInt<4>(8))
    node T_191625 = and(T_191624, T_191623)
    node T_191626 = bits(T_191620, 23, 0)
    node T_191627 = dshl(T_191626, UInt<4>(8))
    node T_191628 = not(T_191623)
    node T_191629 = and(T_191627, T_191628)
    node T_191630 = or(T_191625, T_191629)
    node T_191631 = bits(T_191623, 27, 0)
    node T_191632 = dshl(T_191631, UInt<3>(4))
    node T_191633 = xor(T_191623, T_191632)
    node T_191634 = dshr(T_191630, UInt<3>(4))
    node T_191635 = and(T_191634, T_191633)
    node T_191636 = bits(T_191630, 27, 0)
    node T_191637 = dshl(T_191636, UInt<3>(4))
    node T_191638 = not(T_191633)
    node T_191639 = and(T_191637, T_191638)
    node T_191640 = or(T_191635, T_191639)
    node T_191641 = bits(T_191633, 29, 0)
    node T_191642 = dshl(T_191641, UInt<2>(2))
    node T_191643 = xor(T_191633, T_191642)
    node T_191644 = dshr(T_191640, UInt<2>(2))
    node T_191645 = and(T_191644, T_191643)
    node T_191646 = bits(T_191640, 29, 0)
    node T_191647 = dshl(T_191646, UInt<2>(2))
    node T_191648 = not(T_191643)
    node T_191649 = and(T_191647, T_191648)
    node T_191650 = or(T_191645, T_191649)
    node T_191651 = bits(T_191643, 30, 0)
    node T_191652 = dshl(T_191651, UInt<1>(1))
    node T_191653 = xor(T_191643, T_191652)
    node T_191654 = dshr(T_191650, UInt<1>(1))
    node T_191655 = and(T_191654, T_191653)
    node T_191656 = bits(T_191650, 30, 0)
    node T_191657 = dshl(T_191656, UInt<1>(1))
    node T_191658 = not(T_191653)
    node T_191659 = and(T_191657, T_191658)
    node T_191660 = or(T_191655, T_191659)
    node T_191661 = bits(T_191610, 53, 32)
    node T_191662 = bits(T_191661, 15, 0)
    node T_191663 = dshl(UInt<8>(255), UInt<4>(8))
    node T_191664 = xor(UInt<16>(65535), T_191663)
    node T_191665 = dshr(T_191662, UInt<4>(8))
    node T_191666 = and(T_191665, T_191664)
    node T_191667 = bits(T_191662, 7, 0)
    node T_191668 = dshl(T_191667, UInt<4>(8))
    node T_191669 = not(T_191664)
    node T_191670 = and(T_191668, T_191669)
    node T_191671 = or(T_191666, T_191670)
    node T_191672 = bits(T_191664, 11, 0)
    node T_191673 = dshl(T_191672, UInt<3>(4))
    node T_191674 = xor(T_191664, T_191673)
    node T_191675 = dshr(T_191671, UInt<3>(4))
    node T_191676 = and(T_191675, T_191674)
    node T_191677 = bits(T_191671, 11, 0)
    node T_191678 = dshl(T_191677, UInt<3>(4))
    node T_191679 = not(T_191674)
    node T_191680 = and(T_191678, T_191679)
    node T_191681 = or(T_191676, T_191680)
    node T_191682 = bits(T_191674, 13, 0)
    node T_191683 = dshl(T_191682, UInt<2>(2))
    node T_191684 = xor(T_191674, T_191683)
    node T_191685 = dshr(T_191681, UInt<2>(2))
    node T_191686 = and(T_191685, T_191684)
    node T_191687 = bits(T_191681, 13, 0)
    node T_191688 = dshl(T_191687, UInt<2>(2))
    node T_191689 = not(T_191684)
    node T_191690 = and(T_191688, T_191689)
    node T_191691 = or(T_191686, T_191690)
    node T_191692 = bits(T_191684, 14, 0)
    node T_191693 = dshl(T_191692, UInt<1>(1))
    node T_191694 = xor(T_191684, T_191693)
    node T_191695 = dshr(T_191691, UInt<1>(1))
    node T_191696 = and(T_191695, T_191694)
    node T_191697 = bits(T_191691, 14, 0)
    node T_191698 = dshl(T_191697, UInt<1>(1))
    node T_191699 = not(T_191694)
    node T_191700 = and(T_191698, T_191699)
    node T_191701 = or(T_191696, T_191700)
    node T_191702 = bits(T_191661, 21, 16)
    node T_191703 = bits(T_191702, 3, 0)
    node T_191704 = bits(T_191703, 1, 0)
    node T_191705 = bits(T_191704, 0, 0)
    node T_191706 = bits(T_191704, 1, 1)
    node T_191707 = cat(T_191705, T_191706)
    node T_191708 = bits(T_191703, 3, 2)
    node T_191709 = bits(T_191708, 0, 0)
    node T_191710 = bits(T_191708, 1, 1)
    node T_191711 = cat(T_191709, T_191710)
    node T_191712 = cat(T_191707, T_191711)
    node T_191713 = bits(T_191702, 5, 4)
    node T_191714 = bits(T_191713, 0, 0)
    node T_191715 = bits(T_191713, 1, 1)
    node T_191716 = cat(T_191714, T_191715)
    node T_191717 = cat(T_191712, T_191716)
    node T_191718 = cat(T_191701, T_191717)
    node T_191719 = cat(T_191660, T_191718)
    node T_191720 = bit(sigX3, 55)
    node T_191721 = or(T_191719, T_191720)
    node T_191722 = cat(T_191721, UInt<2>(3))
    node roundMask = or(T_191607, T_191722)
    node T_191723 = dshr(roundMask, UInt<1>(1))
    node T_191724 = not(T_191723)
    node roundPosMask = and(T_191724, roundMask)
    node T_191725 = and(sigX3, roundPosMask)
    node roundPosBit = neq(T_191725, UInt<1>(0))
    node T_191726 = dshr(roundMask, UInt<1>(1))
    node T_191727 = and(sigX3, T_191726)
    node anyRoundExtra = neq(T_191727, UInt<1>(0))
    node T_191728 = not(sigX3)
    node T_191729 = dshr(roundMask, UInt<1>(1))
    node T_191730 = and(T_191728, T_191729)
    node allRoundExtra = eq(T_191730, UInt<1>(0))
    node anyRound = or(roundPosBit, anyRoundExtra)
    node allRound = and(roundPosBit, allRoundExtra)
    wire roundDirectUp : UInt<1>
    roundDirectUp := roundingMode_max
    when signY : roundDirectUp := roundingMode_min
    node T_191731 = not(doIncrSig)
    node T_191732 = and(T_191731, roundingMode_nearest_even)
    node T_191733 = and(T_191732, roundPosBit)
    node T_191734 = and(T_191733, anyRoundExtra)
    node T_191735 = not(doIncrSig)
    node T_191736 = and(T_191735, roundDirectUp)
    node T_191737 = and(T_191736, anyRound)
    node T_191738 = or(T_191734, T_191737)
    node T_191739 = and(doIncrSig, allRound)
    node T_191740 = or(T_191738, T_191739)
    node T_191741 = and(doIncrSig, roundingMode_nearest_even)
    node T_191742 = and(T_191741, roundPosBit)
    node T_191743 = or(T_191740, T_191742)
    node T_191744 = and(doIncrSig, roundDirectUp)
    node roundUp = or(T_191743, T_191744)
    node T_191745 = not(roundPosBit)
    node T_191746 = and(roundingMode_nearest_even, T_191745)
    node T_191747 = and(T_191746, allRoundExtra)
    node T_191748 = and(roundingMode_nearest_even, roundPosBit)
    node T_191749 = not(anyRoundExtra)
    node T_191750 = and(T_191748, T_191749)
    wire roundEven : UInt<1>
    roundEven := T_191750
    when doIncrSig : roundEven := T_191747
    node T_191751 = not(allRound)
    wire roundInexact : UInt<1>
    roundInexact := anyRound
    when doIncrSig : roundInexact := T_191751
    node T_191752 = or(sigX3, roundMask)
    node T_191753 = dshr(T_191752, UInt<2>(2))
    node T_191754 = addw(T_191753, UInt<1>(1))
    node roundUp_sigY3 = bits(T_191754, 54, 0)
    node T_191755 = not(roundUp)
    node T_191756 = not(roundEven)
    node T_191757 = and(T_191755, T_191756)
    node T_191758 = not(roundMask)
    node T_191759 = and(sigX3, T_191758)
    node T_191760 = dshr(T_191759, UInt<2>(2))
    wire T_191761 : UInt<1>
    T_191761 := UInt<1>(0)
    when T_191757 : T_191761 := T_191760
    wire T_191762 : UInt<1>
    T_191762 := UInt<1>(0)
    when roundUp : T_191762 := roundUp_sigY3
    node T_191763 = or(T_191761, T_191762)
    node T_191764 = dshr(roundMask, UInt<1>(1))
    node T_191765 = not(T_191764)
    node T_191766 = and(roundUp_sigY3, T_191765)
    wire T_191767 : UInt<1>
    T_191767 := UInt<1>(0)
    when roundEven : T_191767 := T_191766
    node sigY3 = or(T_191763, T_191767)
    node T_191768 = bit(sigY3, 54)
    node T_191769 = addw(sExpX3, UInt<1>(1))
    wire T_191770 : UInt<1>
    T_191770 := UInt<1>(0)
    when T_191768 : T_191770 := T_191769
    node T_191771 = bit(sigY3, 53)
    wire T_191772 : UInt<1>
    T_191772 := UInt<1>(0)
    when T_191771 : T_191772 := sExpX3
    node T_191773 = or(T_191770, T_191772)
    node T_191774 = bits(sigY3, 54, 53)
    node T_191775 = eq(T_191774, UInt<1>(0))
    node T_191776 = subw(sExpX3, UInt<1>(1))
    wire T_191777 : UInt<1>
    T_191777 := UInt<1>(0)
    when T_191775 : T_191777 := T_191776
    node sExpY = or(T_191773, T_191777)
    node expY = bits(sExpY, 11, 0)
    node T_191778 = bits(sigY3, 51, 0)
    node T_191779 = bits(sigY3, 52, 1)
    wire fractY : UInt<52>
    fractY := T_191779
    when sigX3Shift1 : fractY := T_191778
    node T_191780 = bits(sExpY, 12, 10)
    node overflowY = eq(T_191780, UInt<2>(3))
    node T_191781 = bit(sExpY, 12)
    node T_191782 = bits(sExpY, 11, 0)
    node T_191783 = lt(T_191782, UInt<10>(974))
    node totalUnderflowY = or(T_191781, T_191783)
    node T_191784 = bit(sExpX3, 13)
    wire T_191785 : UInt<11>
    T_191785 := UInt<11>(1025)
    when sigX3Shift1 : T_191785 := UInt<11>(1026)
    node T_191786 = leq(sExpX3_13, T_191785)
    node T_191787 = or(T_191784, T_191786)
    node underflowY = and(roundInexact, T_191787)
    node T_191788 = and(roundingMode_min, signY)
    node T_191789 = or(roundingMode_nearest_even, T_191788)
    node T_191790 = not(signY)
    node T_191791 = and(roundingMode_max, T_191790)
    node overflowY_roundMagUp = or(T_191789, T_191791)
    node mulSpecial = or(isSpecialA, isSpecialB)
    node addSpecial = or(mulSpecial, isSpecialC)
    node notSpecial_addZeros = and(isZeroProd, isZeroC)
    node T_191792 = not(addSpecial)
    node T_191793 = not(notSpecial_addZeros)
    node commonCase = and(T_191792, T_191793)
    node T_191794 = and(isInfA, isZeroB)
    node T_191795 = and(isZeroA, isInfB)
    node T_191796 = or(T_191794, T_191795)
    node T_191797 = not(isNaNA)
    node T_191798 = not(isNaNB)
    node T_191799 = and(T_191797, T_191798)
    node T_191800 = or(isInfA, isInfB)
    node T_191801 = and(T_191799, T_191800)
    node T_191802 = and(T_191801, isInfC)
    node T_191803 = and(T_191802, doSubMags)
    node notSigNaN_invalid = or(T_191796, T_191803)
    node T_191804 = or(isSigNaNA, isSigNaNB)
    node T_191805 = or(T_191804, isSigNaNC)
    node invalid = or(T_191805, notSigNaN_invalid)
    node overflow = and(commonCase, overflowY)
    node underflow = and(commonCase, underflowY)
    node T_191806 = and(commonCase, roundInexact)
    node inexact = or(overflow, T_191806)
    node T_191807 = or(notSpecial_addZeros, isZeroY)
    node notSpecial_isZeroOut = or(T_191807, totalUnderflowY)
    node T_191808 = not(overflowY_roundMagUp)
    node isSatOut = and(overflow, T_191808)
    node T_191809 = or(isInfA, isInfB)
    node T_191810 = or(T_191809, isInfC)
    node T_191811 = and(overflow, overflowY_roundMagUp)
    node notNaN_isInfOut = or(T_191810, T_191811)
    node T_191812 = or(isNaNA, isNaNB)
    node T_191813 = or(T_191812, isNaNC)
    node isNaNOut = or(T_191813, notSigNaN_invalid)
    node T_191814 = eq(doSubMags, UInt<1>(0))
    node T_191815 = and(T_191814, opSignC)
    node T_191816 = and(isNaNOut, UInt<1>(1))
    node T_191817 = or(T_191815, T_191816)
    node T_191818 = eq(isSpecialC, UInt<1>(0))
    node T_191819 = and(mulSpecial, T_191818)
    node T_191820 = and(T_191819, signProd)
    node T_191821 = or(T_191817, T_191820)
    node T_191822 = eq(mulSpecial, UInt<1>(0))
    node T_191823 = and(T_191822, isSpecialC)
    node T_191824 = and(T_191823, opSignC)
    node T_191825 = or(T_191821, T_191824)
    node T_191826 = eq(mulSpecial, UInt<1>(0))
    node T_191827 = and(T_191826, notSpecial_addZeros)
    node T_191828 = and(T_191827, doSubMags)
    node T_191829 = and(T_191828, UInt<1>(0))
    node T_191830 = or(T_191825, T_191829)
    node T_191831 = and(commonCase, signY)
    node signOut = or(T_191830, T_191831)
    wire T_191832 : UInt<12>
    T_191832 := UInt<12>(0)
    when notSpecial_isZeroOut : T_191832 := UInt<12>(3584)
    node T_191833 = not(T_191832)
    node T_191834 = and(expY, T_191833)
    wire T_191835 : UInt<12>
    T_191835 := UInt<12>(0)
    when isSatOut : T_191835 := UInt<11>(1024)
    node T_191836 = not(T_191835)
    node T_191837 = and(T_191834, T_191836)
    wire T_191838 : UInt<12>
    T_191838 := UInt<12>(0)
    when notNaN_isInfOut : T_191838 := UInt<10>(512)
    node T_191839 = not(T_191838)
    node T_191840 = and(T_191837, T_191839)
    wire T_191841 : UInt<12>
    T_191841 := UInt<12>(0)
    when isSatOut : T_191841 := UInt<12>(3071)
    node T_191842 = or(T_191840, T_191841)
    wire T_191843 : UInt<12>
    T_191843 := UInt<12>(0)
    when notNaN_isInfOut : T_191843 := UInt<12>(3072)
    node T_191844 = or(T_191842, T_191843)
    wire T_191845 : UInt<12>
    T_191845 := UInt<12>(0)
    when isNaNOut : T_191845 := UInt<12>(3584)
    node expOut = or(T_191844, T_191845)
    node T_191846 = or(isNaNOut, isSatOut)
    node T_191847 = subw(UInt<52>(0), UInt<6>(52))
    node fractOut = or(fractY, T_191847)
    node T_191848 = cat(expOut, fractOut)
    node T_191849 = cat(signOut, T_191848)
    out := T_191849
    node T_191850 = cat(invalid, UInt<1>(0))
    node T_191851 = cat(underflow, inexact)
    node T_191852 = cat(overflow, T_191851)
    node T_191853 = cat(T_191850, T_191852)
    exceptionFlags := T_191853
  module FPUFMAPipe_160964 : 
    input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    
    node one = shl(UInt<1>(1), 63)
    node T_191854 = bit(in.bits.in1, 64)
    node T_191855 = bit(in.bits.in2, 64)
    node T_191856 = xor(T_191854, T_191855)
    node zero = shl(T_191856, 64)
    reg valid : UInt<1>
    valid := in.valid
    reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    when in.valid : 
      in := in.bits
      node T_191857 = bit(in.bits.cmd, 1)
      node T_191858 = or(in.bits.ren3, in.bits.swap23)
      node T_191859 = and(T_191857, T_191858)
      node T_191860 = bit(in.bits.cmd, 0)
      node T_191861 = cat(T_191859, T_191860)
      in.cmd := T_191861
      when in.bits.swap23 : in.in2 := one
      node T_191862 = or(in.bits.ren3, in.bits.swap23)
      
      node T_191863 = eq(T_191862, UInt<1>(0))
      when T_191863 : in.in3 := zero
    inst fma of mulAddSubRecodedFloatN_160940
    fma.op := in.cmd
    fma.roundingMode := in.rm
    fma.a := in.in1
    fma.b := in.in2
    fma.c := in.in3
    wire res : {data : UInt<65>, exc : UInt<5>}
    res.data := fma.out
    res.exc := fma.exceptionFlags
    reg T_191864 : UInt<1>
    onreset T_191864 := UInt<1>(0)
    T_191864 := valid
    reg T_191865 : {data : UInt<65>, exc : UInt<5>}
    when valid : T_191865 := res
    reg T_191866 : UInt<1>
    onreset T_191866 := UInt<1>(0)
    T_191866 := T_191864
    reg T_191867 : {data : UInt<65>, exc : UInt<5>}
    when T_191864 : T_191867 := T_191865
    T_191868.valid <> T_191866
    T_191868.bits <> T_191867
    out := T_191868
  module recodedFloatNCompare : 
    input a : UInt<65>
    input b : UInt<65>
    output a_eq_b : UInt<1>
    output a_lt_b : UInt<1>
    output a_eq_b_invalid : UInt<1>
    output a_lt_b_invalid : UInt<1>
    
    node signA = bit(a, 64)
    node expA = bits(a, 63, 52)
    node sigA = bits(a, 51, 0)
    node codeA = bits(expA, 11, 9)
    node T_191869 = eq(codeA, UInt<1>(0))
    node T_191870 = eq(T_191869, UInt<1>(0))
    node isZeroA = eq(T_191870, UInt<1>(0))
    node isNaNA = eq(codeA, UInt<1>(-1))
    node T_191871 = bit(sigA, 51)
    node T_191872 = eq(T_191871, UInt<1>(0))
    node isSignalingNaNA = and(isNaNA, T_191872)
    node signB = bit(b, 64)
    node expB = bits(b, 63, 52)
    node sigB = bits(b, 51, 0)
    node codeB = bits(expB, 11, 9)
    node T_191873 = eq(codeB, UInt<1>(0))
    node T_191874 = eq(T_191873, UInt<1>(0))
    node isZeroB = eq(T_191874, UInt<1>(0))
    node isNaNB = eq(codeB, UInt<1>(-1))
    node T_191875 = bit(sigB, 51)
    node T_191876 = eq(T_191875, UInt<1>(0))
    node isSignalingNaNB = and(isNaNB, T_191876)
    node signEqual = eq(signA, signB)
    node expEqual = eq(expA, expB)
    node T_191877 = eq(sigA, sigB)
    node magEqual = and(expEqual, T_191877)
    node T_191878 = lt(expA, expB)
    node T_191879 = lt(sigA, sigB)
    node T_191880 = and(expEqual, T_191879)
    node magLess = or(T_191878, T_191880)
    node T_191881 = or(isSignalingNaNA, isSignalingNaNB)
    a_eq_b_invalid := T_191881
    node T_191882 = or(isNaNA, isNaNB)
    a_lt_b_invalid := T_191882
    node T_191883 = eq(isNaNA, UInt<1>(0))
    node T_191884 = and(T_191883, magEqual)
    node T_191885 = or(isZeroA, signEqual)
    node T_191886 = and(T_191884, T_191885)
    a_eq_b := T_191886
    node T_191887 = eq(a_lt_b_invalid, UInt<1>(0))
    node T_191888 = eq(magLess, UInt<1>(0))
    node T_191889 = and(signA, T_191888)
    node T_191890 = eq(magEqual, UInt<1>(0))
    node T_191891 = and(T_191889, T_191890)
    node T_191892 = and(isZeroA, isZeroB)
    node T_191893 = eq(T_191892, UInt<1>(0))
    wire T_191894 : UInt<1>
    T_191894 := magLess
    when signA : T_191894 := T_191893
    wire T_191895 : UInt<1>
    T_191895 := T_191894
    when signB : T_191895 := T_191891
    node T_191896 = and(T_191887, T_191895)
    a_lt_b := T_191896
  module FPToInt : 
    input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    output as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    output out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}
    
    reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    reg valid : UInt<1>
    valid := in.valid
    when in.valid : 
      in := in.bits
      
      
      node T_191897 = eq(in.bits.ldst, UInt<1>(0))
      node T_191898 = and(in.bits.single, T_191897)
      node T_191899 = and(in.bits.cmd, UInt<4>(12))
      node T_191900 = eq(UInt<4>(12), T_191899)
      node T_191901 = eq(T_191900, UInt<1>(0))
      node T_191902 = and(T_191898, T_191901)
      when T_191902 : 
        node T_191903 = bit(in.bits.in1, 32)
        node T_191904 = bits(in.bits.in1, 22, 0)
        node T_191905 = bits(in.bits.in1, 31, 23)
        node T_191906 = bits(in.bits.in1, 31, 29)
        node T_191907 = bits(in.bits.in1, 30, 23)
        node T_191908 = eq(T_191906, UInt<1>(-1))
        node T_191909 = bit(T_191904, 22)
        node T_191910 = eq(T_191909, UInt<1>(0))
        node T_191911 = and(T_191908, T_191910)
        node T_191912 = lt(T_191906, UInt<1>(1))
        node T_191913 = lt(T_191906, UInt<3>(4))
        node T_191914 = cat(UInt<3>(7), T_191907)
        node T_191915 = lt(T_191906, UInt<3>(6))
        node T_191916 = cat(UInt<4>(8), T_191907)
        node T_191917 = lt(T_191906, UInt<3>(7))
        wire T_191918 : UInt<12>
        T_191918 := UInt<12>(3584)
        when T_191917 : T_191918 := UInt<12>(3072)
        wire T_191919 : UInt<12>
        T_191919 := T_191918
        when T_191915 : T_191919 := T_191916
        wire T_191920 : UInt<12>
        T_191920 := T_191919
        when T_191913 : T_191920 := T_191914
        wire T_191921 : UInt<12>
        T_191921 := T_191920
        when T_191912 : T_191921 := T_191907
        node T_191922 = subw(UInt<52>(0), UInt<6>(52))
        node T_191923 = dshl(T_191904, UInt<5>(29))
        node T_191924 = or(T_191922, T_191923)
        node T_191925 = cat(T_191921, T_191924)
        node T_191926 = cat(T_191903, T_191925)
        node T_191927 = dshl(T_191911, UInt<3>(4))
        in.in1 := T_191926
        node T_191928 = bit(in.bits.in2, 32)
        node T_191929 = bits(in.bits.in2, 22, 0)
        node T_191930 = bits(in.bits.in2, 31, 23)
        node T_191931 = bits(in.bits.in2, 31, 29)
        node T_191932 = bits(in.bits.in2, 30, 23)
        node T_191933 = eq(T_191931, UInt<1>(-1))
        node T_191934 = bit(T_191929, 22)
        node T_191935 = eq(T_191934, UInt<1>(0))
        node T_191936 = and(T_191933, T_191935)
        node T_191937 = lt(T_191931, UInt<1>(1))
        node T_191938 = lt(T_191931, UInt<3>(4))
        node T_191939 = cat(UInt<3>(7), T_191932)
        node T_191940 = lt(T_191931, UInt<3>(6))
        node T_191941 = cat(UInt<4>(8), T_191932)
        node T_191942 = lt(T_191931, UInt<3>(7))
        wire T_191943 : UInt<12>
        T_191943 := UInt<12>(3584)
        when T_191942 : T_191943 := UInt<12>(3072)
        wire T_191944 : UInt<12>
        T_191944 := T_191943
        when T_191940 : T_191944 := T_191941
        wire T_191945 : UInt<12>
        T_191945 := T_191944
        when T_191938 : T_191945 := T_191939
        wire T_191946 : UInt<12>
        T_191946 := T_191945
        when T_191937 : T_191946 := T_191932
        node T_191947 = subw(UInt<52>(0), UInt<6>(52))
        node T_191948 = dshl(T_191929, UInt<5>(29))
        node T_191949 = or(T_191947, T_191948)
        node T_191950 = cat(T_191946, T_191949)
        node T_191951 = cat(T_191928, T_191950)
        node T_191952 = dshl(T_191936, UInt<3>(4))
        in.in2 := T_191951
    node T_191953 = bit(in.in1, 32)
    node T_191954 = bits(in.in1, 31, 23)
    node T_191955 = bits(in.in1, 22, 0)
    node T_191956 = bits(T_191954, 6, 0)
    node T_191957 = lt(T_191956, UInt<2>(2))
    node T_191958 = bits(T_191954, 8, 6)
    node T_191959 = eq(T_191958, UInt<1>(1))
    node T_191960 = bits(T_191954, 8, 7)
    node T_191961 = eq(T_191960, UInt<1>(1))
    node T_191962 = and(T_191961, T_191957)
    node T_191963 = or(T_191959, T_191962)
    node T_191964 = bits(T_191954, 8, 7)
    node T_191965 = eq(T_191964, UInt<1>(1))
    node T_191966 = eq(T_191957, UInt<1>(0))
    node T_191967 = and(T_191965, T_191966)
    node T_191968 = bits(T_191954, 8, 7)
    node T_191969 = eq(T_191968, UInt<2>(2))
    node T_191970 = or(T_191967, T_191969)
    node T_191971 = bits(T_191954, 8, 7)
    node T_191972 = eq(T_191971, UInt<2>(3))
    node T_191973 = bit(T_191954, 6)
    node T_191974 = and(T_191972, T_191973)
    node T_191975 = bits(T_191954, 4, 0)
    node T_191976 = subw(UInt<2>(2), T_191975)
    node T_191977 = cat(UInt<1>(1), T_191955)
    node T_191978 = dshr(T_191977, T_191976)
    node T_191979 = bits(T_191978, 22, 0)
    node T_191980 = bits(T_191954, 7, 0)
    node T_191981 = subw(T_191980, UInt<8>(129))
    node T_191982 = subw(UInt<8>(0), UInt<4>(8))
    wire T_191983 : UInt<8>
    T_191983 := T_191982
    when T_191970 : T_191983 := T_191981
    node T_191984 = or(T_191970, T_191974)
    wire T_191985 : UInt<1>
    T_191985 := UInt<1>(0)
    when T_191963 : T_191985 := T_191979
    wire T_191986 : UInt<1>
    T_191986 := T_191985
    when T_191984 : T_191986 := T_191955
    node T_191987 = cat(T_191983, T_191986)
    node unrec_s = cat(T_191953, T_191987)
    node T_191988 = bit(in.in1, 64)
    node T_191989 = bits(in.in1, 63, 52)
    node T_191990 = bits(in.in1, 51, 0)
    node T_191991 = bits(T_191989, 9, 0)
    node T_191992 = lt(T_191991, UInt<2>(2))
    node T_191993 = bits(T_191989, 11, 9)
    node T_191994 = eq(T_191993, UInt<1>(1))
    node T_191995 = bits(T_191989, 11, 10)
    node T_191996 = eq(T_191995, UInt<1>(1))
    node T_191997 = and(T_191996, T_191992)
    node T_191998 = or(T_191994, T_191997)
    node T_191999 = bits(T_191989, 11, 10)
    node T_192000 = eq(T_191999, UInt<1>(1))
    node T_192001 = eq(T_191992, UInt<1>(0))
    node T_192002 = and(T_192000, T_192001)
    node T_192003 = bits(T_191989, 11, 10)
    node T_192004 = eq(T_192003, UInt<2>(2))
    node T_192005 = or(T_192002, T_192004)
    node T_192006 = bits(T_191989, 11, 10)
    node T_192007 = eq(T_192006, UInt<2>(3))
    node T_192008 = bit(T_191989, 9)
    node T_192009 = and(T_192007, T_192008)
    node T_192010 = bits(T_191989, 5, 0)
    node T_192011 = subw(UInt<2>(2), T_192010)
    node T_192012 = cat(UInt<1>(1), T_191990)
    node T_192013 = dshr(T_192012, T_192011)
    node T_192014 = bits(T_192013, 51, 0)
    node T_192015 = bits(T_191989, 10, 0)
    node T_192016 = subw(T_192015, UInt<11>(1025))
    node T_192017 = subw(UInt<11>(0), UInt<4>(11))
    wire T_192018 : UInt<11>
    T_192018 := T_192017
    when T_192005 : T_192018 := T_192016
    node T_192019 = or(T_192005, T_192009)
    wire T_192020 : UInt<1>
    T_192020 := UInt<1>(0)
    when T_191998 : T_192020 := T_192014
    wire T_192021 : UInt<1>
    T_192021 := T_192020
    when T_192019 : T_192021 := T_191990
    node T_192022 = cat(T_192018, T_192021)
    node unrec_d = cat(T_191988, T_192022)
    node T_192023 = bit(unrec_s, 31)
    node T_192024 = subw(UInt<32>(0), UInt<6>(32))
    node T_192025 = cat(T_192024, unrec_s)
    wire unrec_out : UInt<13>
    unrec_out := unrec_d
    when in.single : unrec_out := T_192025
    node T_192026 = bit(in.in1, 32)
    node T_192027 = bits(in.in1, 31, 23)
    node T_192028 = bits(in.in1, 22, 0)
    node T_192029 = bits(T_192027, 8, 6)
    node T_192030 = bits(T_192029, 2, 1)
    node T_192031 = eq(T_192030, UInt<2>(3))
    node T_192032 = bits(T_192027, 6, 0)
    node T_192033 = lt(T_192032, UInt<2>(2))
    node T_192034 = eq(T_192029, UInt<1>(1))
    node T_192035 = eq(T_192030, UInt<1>(1))
    node T_192036 = and(T_192035, T_192033)
    node T_192037 = or(T_192034, T_192036)
    node T_192038 = eq(T_192030, UInt<1>(1))
    node T_192039 = eq(T_192033, UInt<1>(0))
    node T_192040 = and(T_192038, T_192039)
    node T_192041 = eq(T_192030, UInt<2>(2))
    node T_192042 = or(T_192040, T_192041)
    node T_192043 = eq(T_192029, UInt<1>(0))
    node T_192044 = bit(T_192027, 6)
    node T_192045 = eq(T_192044, UInt<1>(0))
    node T_192046 = and(T_192031, T_192045)
    node T_192047 = eq(T_192029, UInt<1>(-1))
    node T_192048 = bit(T_192028, 22)
    node T_192049 = eq(T_192048, UInt<1>(0))
    node T_192050 = and(T_192047, T_192049)
    node T_192051 = bit(T_192028, 22)
    node T_192052 = and(T_192047, T_192051)
    node T_192053 = eq(T_192026, UInt<1>(0))
    node T_192054 = and(T_192046, T_192053)
    node T_192055 = eq(T_192026, UInt<1>(0))
    node T_192056 = and(T_192042, T_192055)
    node T_192057 = eq(T_192026, UInt<1>(0))
    node T_192058 = and(T_192037, T_192057)
    node T_192059 = eq(T_192026, UInt<1>(0))
    node T_192060 = and(T_192043, T_192059)
    node T_192061 = and(T_192043, T_192026)
    node T_192062 = and(T_192037, T_192026)
    node T_192063 = and(T_192042, T_192026)
    node T_192064 = and(T_192046, T_192026)
    node T_192065 = cat(T_192052, T_192050)
    node T_192066 = cat(T_192056, T_192058)
    node T_192067 = cat(T_192054, T_192066)
    node T_192068 = cat(T_192065, T_192067)
    node T_192069 = cat(T_192060, T_192061)
    node T_192070 = cat(T_192063, T_192064)
    node T_192071 = cat(T_192062, T_192070)
    node T_192072 = cat(T_192069, T_192071)
    node classify_s = cat(T_192068, T_192072)
    node T_192073 = bit(in.in1, 64)
    node T_192074 = bits(in.in1, 63, 52)
    node T_192075 = bits(in.in1, 51, 0)
    node T_192076 = bits(T_192074, 11, 9)
    node T_192077 = bits(T_192076, 2, 1)
    node T_192078 = eq(T_192077, UInt<2>(3))
    node T_192079 = bits(T_192074, 9, 0)
    node T_192080 = lt(T_192079, UInt<2>(2))
    node T_192081 = eq(T_192076, UInt<1>(1))
    node T_192082 = eq(T_192077, UInt<1>(1))
    node T_192083 = and(T_192082, T_192080)
    node T_192084 = or(T_192081, T_192083)
    node T_192085 = eq(T_192077, UInt<1>(1))
    node T_192086 = eq(T_192080, UInt<1>(0))
    node T_192087 = and(T_192085, T_192086)
    node T_192088 = eq(T_192077, UInt<2>(2))
    node T_192089 = or(T_192087, T_192088)
    node T_192090 = eq(T_192076, UInt<1>(0))
    node T_192091 = bit(T_192074, 9)
    node T_192092 = eq(T_192091, UInt<1>(0))
    node T_192093 = and(T_192078, T_192092)
    node T_192094 = eq(T_192076, UInt<1>(-1))
    node T_192095 = bit(T_192075, 51)
    node T_192096 = eq(T_192095, UInt<1>(0))
    node T_192097 = and(T_192094, T_192096)
    node T_192098 = bit(T_192075, 51)
    node T_192099 = and(T_192094, T_192098)
    node T_192100 = eq(T_192073, UInt<1>(0))
    node T_192101 = and(T_192093, T_192100)
    node T_192102 = eq(T_192073, UInt<1>(0))
    node T_192103 = and(T_192089, T_192102)
    node T_192104 = eq(T_192073, UInt<1>(0))
    node T_192105 = and(T_192084, T_192104)
    node T_192106 = eq(T_192073, UInt<1>(0))
    node T_192107 = and(T_192090, T_192106)
    node T_192108 = and(T_192090, T_192073)
    node T_192109 = and(T_192084, T_192073)
    node T_192110 = and(T_192089, T_192073)
    node T_192111 = and(T_192093, T_192073)
    node T_192112 = cat(T_192099, T_192097)
    node T_192113 = cat(T_192103, T_192105)
    node T_192114 = cat(T_192101, T_192113)
    node T_192115 = cat(T_192112, T_192114)
    node T_192116 = cat(T_192107, T_192108)
    node T_192117 = cat(T_192110, T_192111)
    node T_192118 = cat(T_192109, T_192117)
    node T_192119 = cat(T_192116, T_192118)
    node classify_d = cat(T_192115, T_192119)
    wire classify_out : UInt<10>
    classify_out := classify_d
    when in.single : classify_out := classify_s
    inst dcmp of recodedFloatNCompare
    dcmp.a := in.in1
    dcmp.b := in.in2
    node T_192120 = not(in.rm)
    node T_192121 = cat(dcmp.a_lt_b, dcmp.a_eq_b)
    node T_192122 = and(T_192120, T_192121)
    node T_192123 = eq(T_192122, UInt<1>(0))
    node dcmp_out = eq(T_192123, UInt<1>(0))
    node T_192124 = not(in.rm)
    node T_192125 = cat(dcmp.a_lt_b_invalid, dcmp.a_eq_b_invalid)
    node T_192126 = and(T_192124, T_192125)
    node T_192127 = eq(T_192126, UInt<1>(0))
    node T_192128 = eq(T_192127, UInt<1>(0))
    node dcmp_exc = dshl(T_192128, UInt<3>(4))
    node T_192129 = xor(in.typ, UInt<1>(1))
    node T_192130 = bit(in.in1, 64)
    node T_192131 = bits(in.in1, 63, 52)
    node T_192132 = bits(in.in1, 51, 0)
    node T_192133 = bits(T_192131, 10, 0)
    node T_192134 = eq(T_192133, UInt<1>(-1))
    node T_192135 = eq(T_192134, UInt<1>(0))
    node T_192136 = bit(T_192131, 11)
    node T_192137 = eq(T_192136, UInt<1>(0))
    node T_192138 = bits(T_192131, 11, 9)
    node T_192139 = eq(T_192138, UInt<1>(0))
    node T_192140 = bits(T_192131, 11, 10)
    node T_192141 = eq(T_192140, UInt<1>(-1))
    node T_192142 = bits(T_192131, 5, 0)
    wire T_192143 : UInt<6>
    T_192143 := T_192142
    when T_192137 : T_192143 := UInt<1>(0)
    node T_192144 = eq(T_192137, UInt<1>(0))
    node T_192145 = cat(T_192144, T_192132)
    node T_192146 = dshl(T_192145, T_192143)
    node T_192147 = bits(T_192146, 115, 52)
    node T_192148 = bits(T_192146, 52, 51)
    node T_192149 = bits(T_192146, 50, 0)
    node T_192150 = eq(T_192149, UInt<1>(0))
    node T_192151 = eq(T_192150, UInt<1>(0))
    node T_192152 = cat(T_192148, T_192151)
    node T_192153 = bits(T_192152, 1, 0)
    node T_192154 = eq(T_192153, UInt<1>(0))
    node T_192155 = eq(T_192154, UInt<1>(0))
    node T_192156 = eq(T_192135, UInt<1>(0))
    node T_192157 = and(T_192156, T_192155)
    node T_192158 = bits(T_192152, 2, 1)
    node T_192159 = eq(T_192158, UInt<1>(-1))
    node T_192160 = bits(T_192152, 1, 0)
    node T_192161 = eq(T_192160, UInt<1>(-1))
    node T_192162 = or(T_192159, T_192161)
    wire T_192163 : UInt<1>
    T_192163 := T_192162
    when T_192137 : T_192163 := T_192157
    node T_192164 = eq(T_192139, UInt<1>(0))
    wire T_192165 : UInt<1>
    T_192165 := T_192155
    when T_192137 : T_192165 := T_192164
    node T_192166 = eq(in.rm, UInt<2>(0))
    node T_192167 = eq(in.rm, UInt<2>(2))
    node T_192168 = and(T_192130, T_192165)
    node T_192169 = eq(in.rm, UInt<2>(3))
    node T_192170 = eq(T_192130, UInt<1>(0))
    node T_192171 = and(T_192170, T_192165)
    wire T_192172 : UInt<1>
    T_192172 := UInt<1>(0)
    when T_192169 : T_192172 := T_192171
    wire T_192173 : UInt<1>
    T_192173 := T_192172
    when T_192167 : T_192173 := T_192168
    wire T_192174 : UInt<1>
    T_192174 := T_192173
    when T_192166 : T_192174 := T_192163
    node T_192175 = not(T_192147)
    wire T_192176 : UInt<64>
    T_192176 := T_192147
    when T_192130 : T_192176 := T_192175
    node T_192177 = xor(T_192174, T_192130)
    node T_192178 = addw(T_192176, UInt<1>(1))
    wire T_192179 : UInt<64>
    T_192179 := T_192176
    when T_192177 : T_192179 := T_192178
    node T_192180 = asSInt(T_192179)
    node T_192181 = eq(T_192147, UInt<1>(-1))
    node T_192182 = and(T_192174, T_192181)
    node T_192183 = eq(T_192130, UInt<1>(0))
    node T_192184 = and(T_192183, T_192182)
    node T_192185 = eq(T_192130, UInt<1>(0))
    node T_192186 = or(T_192185, T_192174)
    node T_192187 = eq(T_192147, UInt<1>(0))
    node T_192188 = eq(T_192187, UInt<1>(0))
    node T_192189 = or(T_192186, T_192188)
    node T_192190 = bits(T_192131, 10, 0)
    node T_192191 = eq(T_192129, UInt<2>(0))
    node T_192192 = and(T_192130, T_192174)
    node T_192193 = eq(T_192190, UInt<5>(31))
    node T_192194 = geq(T_192190, UInt<6>(32))
    wire T_192195 : UInt<1>
    T_192195 := T_192194
    when T_192193 : T_192195 := T_192182
    node T_192196 = or(T_192130, T_192195)
    wire T_192197 : UInt<1>
    T_192197 := T_192196
    when T_192137 : T_192197 := T_192192
    node T_192198 = eq(T_192129, UInt<2>(1))
    node T_192199 = eq(T_192190, UInt<5>(30))
    node T_192200 = eq(T_192190, UInt<5>(31))
    node T_192201 = geq(T_192190, UInt<6>(32))
    wire T_192202 : UInt<1>
    T_192202 := T_192201
    when T_192200 : T_192202 := T_192189
    wire T_192203 : UInt<1>
    T_192203 := T_192202
    when T_192199 : T_192203 := T_192184
    wire T_192204 : UInt<1>
    T_192204 := T_192203
    when T_192137 : T_192204 := UInt<1>(0)
    node T_192205 = eq(T_192129, UInt<2>(2))
    node T_192206 = and(T_192130, T_192174)
    node T_192207 = eq(T_192190, UInt<6>(63))
    node T_192208 = geq(T_192190, UInt<7>(64))
    wire T_192209 : UInt<1>
    T_192209 := T_192208
    when T_192207 : T_192209 := T_192182
    node T_192210 = or(T_192130, T_192209)
    wire T_192211 : UInt<1>
    T_192211 := T_192210
    when T_192137 : T_192211 := T_192206
    node T_192212 = eq(T_192190, UInt<6>(62))
    node T_192213 = eq(T_192190, UInt<6>(63))
    node T_192214 = geq(T_192190, UInt<7>(64))
    wire T_192215 : UInt<1>
    T_192215 := T_192214
    when T_192213 : T_192215 := T_192189
    wire T_192216 : UInt<1>
    T_192216 := T_192215
    when T_192212 : T_192216 := T_192184
    wire T_192217 : UInt<1>
    T_192217 := T_192216
    when T_192137 : T_192217 := UInt<1>(0)
    wire T_192218 : UInt<1>
    T_192218 := T_192217
    when T_192205 : T_192218 := T_192211
    wire T_192219 : UInt<1>
    T_192219 := T_192218
    when T_192198 : T_192219 := T_192204
    wire T_192220 : UInt<1>
    T_192220 := T_192219
    when T_192191 : T_192220 := T_192197
    node T_192221 = or(T_192141, T_192220)
    node T_192222 = eq(T_192129, UInt<2>(3))
    node T_192223 = and(T_192222, T_192130)
    node T_192224 = eq(T_192129, UInt<2>(1))
    node T_192225 = and(T_192224, T_192130)
    node T_192226 = eq(T_192129, UInt<2>(3))
    node T_192227 = eq(T_192130, UInt<1>(0))
    node T_192228 = and(T_192226, T_192227)
    node T_192229 = eq(T_192129, UInt<2>(1))
    node T_192230 = eq(T_192130, UInt<1>(0))
    node T_192231 = and(T_192229, T_192230)
    wire T_192232 : SInt<1>
    T_192232 := SInt<1>(-1)
    when T_192231 : T_192232 := SInt<32>(2147483647)
    wire T_192233 : SInt<1>
    T_192233 := T_192232
    when T_192228 : T_192233 := SInt<64>(9223372036854775807)
    wire T_192234 : SInt<1>
    T_192234 := T_192233
    when T_192225 : T_192234 := SInt<32>(-2147483648)
    wire T_192235 : SInt<1>
    T_192235 := T_192234
    when T_192223 : T_192235 := SInt<64>(-9223372036854775808)
    node T_192236 = eq(T_192221, UInt<1>(0))
    node T_192237 = and(T_192155, T_192236)
    wire T_192238 : SInt<64>
    T_192238 := T_192180
    when T_192221 : T_192238 := T_192235
    node T_192239 = cat(UInt<3>(0), T_192237)
    node T_192240 = cat(T_192221, T_192239)
    node T_192241 = bit(in.rm, 0)
    wire T_192242 : UInt<13>
    T_192242 := unrec_out
    when T_192241 : T_192242 := classify_out
    out.bits.toint := T_192242
    out.bits.store := unrec_out
    out.bits.exc := UInt<1>(0)
    
    
    node T_192243 = and(in.cmd, UInt<4>(12))
    node T_192244 = eq(UInt<3>(4), T_192243)
    when T_192244 : 
      out.bits.toint := dcmp_out
      out.bits.exc := dcmp_exc
    
    
    node T_192245 = and(in.cmd, UInt<4>(12))
    node T_192246 = eq(UInt<4>(8), T_192245)
    when T_192246 : 
      node T_192247 = bit(in.typ, 1)
      node T_192248 = bits(T_192238, 31, 0)
      node T_192249 = asSInt(T_192248)
      wire T_192250 : SInt<32>
      T_192250 := T_192249
      when T_192247 : T_192250 := T_192238
      out.bits.toint := T_192250
      out.bits.exc := T_192240
    out.valid := valid
    out.bits.lt := dcmp.a_lt_b
    as_double := in
  module IntToFP : 
    input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    
    reg T_192251 : UInt<1>
    onreset T_192251 := UInt<1>(0)
    T_192251 := in.valid
    reg T_192252 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    when in.valid : T_192252 := in.bits
    in.valid <> T_192251
    in.bits <> T_192252
    wire mux : {data : UInt<65>, exc : UInt<5>}
    mux.exc := UInt<1>(0)
    node T_192253 = bit(in.bits.in1, 63)
    node T_192254 = bits(in.bits.in1, 62, 52)
    node T_192255 = bits(in.bits.in1, 51, 0)
    node T_192256 = eq(T_192254, UInt<1>(0))
    node T_192257 = eq(T_192255, UInt<1>(0))
    node T_192258 = and(T_192256, T_192257)
    node T_192259 = eq(T_192257, UInt<1>(0))
    node T_192260 = and(T_192256, T_192259)
    node T_192261 = shl(T_192255, 12)
    node T_192262 = bit(T_192261, 63)
    node T_192263 = bit(T_192261, 62)
    node T_192264 = bit(T_192261, 61)
    node T_192265 = bit(T_192261, 60)
    node T_192266 = bit(T_192261, 59)
    node T_192267 = bit(T_192261, 58)
    node T_192268 = bit(T_192261, 57)
    node T_192269 = bit(T_192261, 56)
    node T_192270 = bit(T_192261, 55)
    node T_192271 = bit(T_192261, 54)
    node T_192272 = bit(T_192261, 53)
    node T_192273 = bit(T_192261, 52)
    node T_192274 = bit(T_192261, 51)
    node T_192275 = bit(T_192261, 50)
    node T_192276 = bit(T_192261, 49)
    node T_192277 = bit(T_192261, 48)
    node T_192278 = bit(T_192261, 47)
    node T_192279 = bit(T_192261, 46)
    node T_192280 = bit(T_192261, 45)
    node T_192281 = bit(T_192261, 44)
    node T_192282 = bit(T_192261, 43)
    node T_192283 = bit(T_192261, 42)
    node T_192284 = bit(T_192261, 41)
    node T_192285 = bit(T_192261, 40)
    node T_192286 = bit(T_192261, 39)
    node T_192287 = bit(T_192261, 38)
    node T_192288 = bit(T_192261, 37)
    node T_192289 = bit(T_192261, 36)
    node T_192290 = bit(T_192261, 35)
    node T_192291 = bit(T_192261, 34)
    node T_192292 = bit(T_192261, 33)
    node T_192293 = bit(T_192261, 32)
    node T_192294 = bit(T_192261, 31)
    node T_192295 = bit(T_192261, 30)
    node T_192296 = bit(T_192261, 29)
    node T_192297 = bit(T_192261, 28)
    node T_192298 = bit(T_192261, 27)
    node T_192299 = bit(T_192261, 26)
    node T_192300 = bit(T_192261, 25)
    node T_192301 = bit(T_192261, 24)
    node T_192302 = bit(T_192261, 23)
    node T_192303 = bit(T_192261, 22)
    node T_192304 = bit(T_192261, 21)
    node T_192305 = bit(T_192261, 20)
    node T_192306 = bit(T_192261, 19)
    node T_192307 = bit(T_192261, 18)
    node T_192308 = bit(T_192261, 17)
    node T_192309 = bit(T_192261, 16)
    node T_192310 = bit(T_192261, 15)
    node T_192311 = bit(T_192261, 14)
    node T_192312 = bit(T_192261, 13)
    node T_192313 = bit(T_192261, 12)
    node T_192314 = bit(T_192261, 11)
    node T_192315 = bit(T_192261, 10)
    node T_192316 = bit(T_192261, 9)
    node T_192317 = bit(T_192261, 8)
    node T_192318 = bit(T_192261, 7)
    node T_192319 = bit(T_192261, 6)
    node T_192320 = bit(T_192261, 5)
    node T_192321 = bit(T_192261, 4)
    node T_192322 = bit(T_192261, 3)
    node T_192323 = bit(T_192261, 2)
    node T_192324 = bit(T_192261, 1)
    wire T_192325 : UInt<1>
    T_192325 := T_192324
    when T_192323 : T_192325 := UInt<2>(2)
    wire T_192326 : UInt<1>
    T_192326 := T_192325
    when T_192322 : T_192326 := UInt<2>(3)
    wire T_192327 : UInt<1>
    T_192327 := T_192326
    when T_192321 : T_192327 := UInt<3>(4)
    wire T_192328 : UInt<1>
    T_192328 := T_192327
    when T_192320 : T_192328 := UInt<3>(5)
    wire T_192329 : UInt<1>
    T_192329 := T_192328
    when T_192319 : T_192329 := UInt<3>(6)
    wire T_192330 : UInt<1>
    T_192330 := T_192329
    when T_192318 : T_192330 := UInt<3>(7)
    wire T_192331 : UInt<1>
    T_192331 := T_192330
    when T_192317 : T_192331 := UInt<4>(8)
    wire T_192332 : UInt<1>
    T_192332 := T_192331
    when T_192316 : T_192332 := UInt<4>(9)
    wire T_192333 : UInt<1>
    T_192333 := T_192332
    when T_192315 : T_192333 := UInt<4>(10)
    wire T_192334 : UInt<1>
    T_192334 := T_192333
    when T_192314 : T_192334 := UInt<4>(11)
    wire T_192335 : UInt<1>
    T_192335 := T_192334
    when T_192313 : T_192335 := UInt<4>(12)
    wire T_192336 : UInt<1>
    T_192336 := T_192335
    when T_192312 : T_192336 := UInt<4>(13)
    wire T_192337 : UInt<1>
    T_192337 := T_192336
    when T_192311 : T_192337 := UInt<4>(14)
    wire T_192338 : UInt<1>
    T_192338 := T_192337
    when T_192310 : T_192338 := UInt<4>(15)
    wire T_192339 : UInt<1>
    T_192339 := T_192338
    when T_192309 : T_192339 := UInt<5>(16)
    wire T_192340 : UInt<1>
    T_192340 := T_192339
    when T_192308 : T_192340 := UInt<5>(17)
    wire T_192341 : UInt<1>
    T_192341 := T_192340
    when T_192307 : T_192341 := UInt<5>(18)
    wire T_192342 : UInt<1>
    T_192342 := T_192341
    when T_192306 : T_192342 := UInt<5>(19)
    wire T_192343 : UInt<1>
    T_192343 := T_192342
    when T_192305 : T_192343 := UInt<5>(20)
    wire T_192344 : UInt<1>
    T_192344 := T_192343
    when T_192304 : T_192344 := UInt<5>(21)
    wire T_192345 : UInt<1>
    T_192345 := T_192344
    when T_192303 : T_192345 := UInt<5>(22)
    wire T_192346 : UInt<1>
    T_192346 := T_192345
    when T_192302 : T_192346 := UInt<5>(23)
    wire T_192347 : UInt<1>
    T_192347 := T_192346
    when T_192301 : T_192347 := UInt<5>(24)
    wire T_192348 : UInt<1>
    T_192348 := T_192347
    when T_192300 : T_192348 := UInt<5>(25)
    wire T_192349 : UInt<1>
    T_192349 := T_192348
    when T_192299 : T_192349 := UInt<5>(26)
    wire T_192350 : UInt<1>
    T_192350 := T_192349
    when T_192298 : T_192350 := UInt<5>(27)
    wire T_192351 : UInt<1>
    T_192351 := T_192350
    when T_192297 : T_192351 := UInt<5>(28)
    wire T_192352 : UInt<1>
    T_192352 := T_192351
    when T_192296 : T_192352 := UInt<5>(29)
    wire T_192353 : UInt<1>
    T_192353 := T_192352
    when T_192295 : T_192353 := UInt<5>(30)
    wire T_192354 : UInt<1>
    T_192354 := T_192353
    when T_192294 : T_192354 := UInt<5>(31)
    wire T_192355 : UInt<1>
    T_192355 := T_192354
    when T_192293 : T_192355 := UInt<6>(32)
    wire T_192356 : UInt<1>
    T_192356 := T_192355
    when T_192292 : T_192356 := UInt<6>(33)
    wire T_192357 : UInt<1>
    T_192357 := T_192356
    when T_192291 : T_192357 := UInt<6>(34)
    wire T_192358 : UInt<1>
    T_192358 := T_192357
    when T_192290 : T_192358 := UInt<6>(35)
    wire T_192359 : UInt<1>
    T_192359 := T_192358
    when T_192289 : T_192359 := UInt<6>(36)
    wire T_192360 : UInt<1>
    T_192360 := T_192359
    when T_192288 : T_192360 := UInt<6>(37)
    wire T_192361 : UInt<1>
    T_192361 := T_192360
    when T_192287 : T_192361 := UInt<6>(38)
    wire T_192362 : UInt<1>
    T_192362 := T_192361
    when T_192286 : T_192362 := UInt<6>(39)
    wire T_192363 : UInt<1>
    T_192363 := T_192362
    when T_192285 : T_192363 := UInt<6>(40)
    wire T_192364 : UInt<1>
    T_192364 := T_192363
    when T_192284 : T_192364 := UInt<6>(41)
    wire T_192365 : UInt<1>
    T_192365 := T_192364
    when T_192283 : T_192365 := UInt<6>(42)
    wire T_192366 : UInt<1>
    T_192366 := T_192365
    when T_192282 : T_192366 := UInt<6>(43)
    wire T_192367 : UInt<1>
    T_192367 := T_192366
    when T_192281 : T_192367 := UInt<6>(44)
    wire T_192368 : UInt<1>
    T_192368 := T_192367
    when T_192280 : T_192368 := UInt<6>(45)
    wire T_192369 : UInt<1>
    T_192369 := T_192368
    when T_192279 : T_192369 := UInt<6>(46)
    wire T_192370 : UInt<1>
    T_192370 := T_192369
    when T_192278 : T_192370 := UInt<6>(47)
    wire T_192371 : UInt<1>
    T_192371 := T_192370
    when T_192277 : T_192371 := UInt<6>(48)
    wire T_192372 : UInt<1>
    T_192372 := T_192371
    when T_192276 : T_192372 := UInt<6>(49)
    wire T_192373 : UInt<1>
    T_192373 := T_192372
    when T_192275 : T_192373 := UInt<6>(50)
    wire T_192374 : UInt<1>
    T_192374 := T_192373
    when T_192274 : T_192374 := UInt<6>(51)
    wire T_192375 : UInt<1>
    T_192375 := T_192374
    when T_192273 : T_192375 := UInt<6>(52)
    wire T_192376 : UInt<1>
    T_192376 := T_192375
    when T_192272 : T_192376 := UInt<6>(53)
    wire T_192377 : UInt<1>
    T_192377 := T_192376
    when T_192271 : T_192377 := UInt<6>(54)
    wire T_192378 : UInt<1>
    T_192378 := T_192377
    when T_192270 : T_192378 := UInt<6>(55)
    wire T_192379 : UInt<1>
    T_192379 := T_192378
    when T_192269 : T_192379 := UInt<6>(56)
    wire T_192380 : UInt<1>
    T_192380 := T_192379
    when T_192268 : T_192380 := UInt<6>(57)
    wire T_192381 : UInt<1>
    T_192381 := T_192380
    when T_192267 : T_192381 := UInt<6>(58)
    wire T_192382 : UInt<1>
    T_192382 := T_192381
    when T_192266 : T_192382 := UInt<6>(59)
    wire T_192383 : UInt<1>
    T_192383 := T_192382
    when T_192265 : T_192383 := UInt<6>(60)
    wire T_192384 : UInt<1>
    T_192384 := T_192383
    when T_192264 : T_192384 := UInt<6>(61)
    wire T_192385 : UInt<1>
    T_192385 := T_192384
    when T_192263 : T_192385 := UInt<6>(62)
    wire T_192386 : UInt<1>
    T_192386 := T_192385
    when T_192262 : T_192386 := UInt<6>(63)
    node T_192387 = not(T_192386)
    node T_192388 = dshl(T_192261, T_192387)
    node T_192389 = subw(UInt<6>(0), UInt<3>(6))
    node T_192390 = not(T_192387)
    node T_192391 = cat(T_192389, T_192390)
    node T_192392 = bits(T_192388, 62, 11)
    wire T_192393 : UInt<7>
    T_192393 := T_192391
    when T_192257 : T_192393 := UInt<1>(0)
    wire T_192394 : UInt<11>
    T_192394 := T_192254
    when T_192256 : T_192394 := T_192393
    wire T_192395 : UInt<1>
    T_192395 := UInt<1>(1)
    when T_192260 : T_192395 := UInt<2>(2)
    node T_192396 = or(UInt<11>(1024), T_192395)
    wire T_192397 : UInt<11>
    T_192397 := T_192396
    when T_192258 : T_192397 := UInt<1>(0)
    node T_192398 = addw(T_192394, T_192397)
    node T_192399 = bits(T_192398, 11, 10)
    node T_192400 = eq(T_192399, UInt<1>(-1))
    node T_192401 = eq(T_192257, UInt<1>(0))
    node T_192402 = and(T_192400, T_192401)
    node T_192403 = dshl(T_192402, UInt<4>(9))
    node T_192404 = or(T_192398, T_192403)
    wire T_192405 : UInt<52>
    T_192405 := T_192255
    when T_192256 : T_192405 := T_192392
    node T_192406 = cat(T_192404, T_192405)
    node T_192407 = cat(T_192253, T_192406)
    mux.data := T_192407
    when in.bits.single : 
      node T_192408 = bit(in.bits.in1, 31)
      node T_192409 = bits(in.bits.in1, 30, 23)
      node T_192410 = bits(in.bits.in1, 22, 0)
      node T_192411 = eq(T_192409, UInt<1>(0))
      node T_192412 = eq(T_192410, UInt<1>(0))
      node T_192413 = and(T_192411, T_192412)
      node T_192414 = eq(T_192412, UInt<1>(0))
      node T_192415 = and(T_192411, T_192414)
      node T_192416 = shl(T_192410, 9)
      node T_192417 = bit(T_192416, 31)
      node T_192418 = bit(T_192416, 30)
      node T_192419 = bit(T_192416, 29)
      node T_192420 = bit(T_192416, 28)
      node T_192421 = bit(T_192416, 27)
      node T_192422 = bit(T_192416, 26)
      node T_192423 = bit(T_192416, 25)
      node T_192424 = bit(T_192416, 24)
      node T_192425 = bit(T_192416, 23)
      node T_192426 = bit(T_192416, 22)
      node T_192427 = bit(T_192416, 21)
      node T_192428 = bit(T_192416, 20)
      node T_192429 = bit(T_192416, 19)
      node T_192430 = bit(T_192416, 18)
      node T_192431 = bit(T_192416, 17)
      node T_192432 = bit(T_192416, 16)
      node T_192433 = bit(T_192416, 15)
      node T_192434 = bit(T_192416, 14)
      node T_192435 = bit(T_192416, 13)
      node T_192436 = bit(T_192416, 12)
      node T_192437 = bit(T_192416, 11)
      node T_192438 = bit(T_192416, 10)
      node T_192439 = bit(T_192416, 9)
      node T_192440 = bit(T_192416, 8)
      node T_192441 = bit(T_192416, 7)
      node T_192442 = bit(T_192416, 6)
      node T_192443 = bit(T_192416, 5)
      node T_192444 = bit(T_192416, 4)
      node T_192445 = bit(T_192416, 3)
      node T_192446 = bit(T_192416, 2)
      node T_192447 = bit(T_192416, 1)
      wire T_192448 : UInt<1>
      T_192448 := T_192447
      when T_192446 : T_192448 := UInt<2>(2)
      wire T_192449 : UInt<1>
      T_192449 := T_192448
      when T_192445 : T_192449 := UInt<2>(3)
      wire T_192450 : UInt<1>
      T_192450 := T_192449
      when T_192444 : T_192450 := UInt<3>(4)
      wire T_192451 : UInt<1>
      T_192451 := T_192450
      when T_192443 : T_192451 := UInt<3>(5)
      wire T_192452 : UInt<1>
      T_192452 := T_192451
      when T_192442 : T_192452 := UInt<3>(6)
      wire T_192453 : UInt<1>
      T_192453 := T_192452
      when T_192441 : T_192453 := UInt<3>(7)
      wire T_192454 : UInt<1>
      T_192454 := T_192453
      when T_192440 : T_192454 := UInt<4>(8)
      wire T_192455 : UInt<1>
      T_192455 := T_192454
      when T_192439 : T_192455 := UInt<4>(9)
      wire T_192456 : UInt<1>
      T_192456 := T_192455
      when T_192438 : T_192456 := UInt<4>(10)
      wire T_192457 : UInt<1>
      T_192457 := T_192456
      when T_192437 : T_192457 := UInt<4>(11)
      wire T_192458 : UInt<1>
      T_192458 := T_192457
      when T_192436 : T_192458 := UInt<4>(12)
      wire T_192459 : UInt<1>
      T_192459 := T_192458
      when T_192435 : T_192459 := UInt<4>(13)
      wire T_192460 : UInt<1>
      T_192460 := T_192459
      when T_192434 : T_192460 := UInt<4>(14)
      wire T_192461 : UInt<1>
      T_192461 := T_192460
      when T_192433 : T_192461 := UInt<4>(15)
      wire T_192462 : UInt<1>
      T_192462 := T_192461
      when T_192432 : T_192462 := UInt<5>(16)
      wire T_192463 : UInt<1>
      T_192463 := T_192462
      when T_192431 : T_192463 := UInt<5>(17)
      wire T_192464 : UInt<1>
      T_192464 := T_192463
      when T_192430 : T_192464 := UInt<5>(18)
      wire T_192465 : UInt<1>
      T_192465 := T_192464
      when T_192429 : T_192465 := UInt<5>(19)
      wire T_192466 : UInt<1>
      T_192466 := T_192465
      when T_192428 : T_192466 := UInt<5>(20)
      wire T_192467 : UInt<1>
      T_192467 := T_192466
      when T_192427 : T_192467 := UInt<5>(21)
      wire T_192468 : UInt<1>
      T_192468 := T_192467
      when T_192426 : T_192468 := UInt<5>(22)
      wire T_192469 : UInt<1>
      T_192469 := T_192468
      when T_192425 : T_192469 := UInt<5>(23)
      wire T_192470 : UInt<1>
      T_192470 := T_192469
      when T_192424 : T_192470 := UInt<5>(24)
      wire T_192471 : UInt<1>
      T_192471 := T_192470
      when T_192423 : T_192471 := UInt<5>(25)
      wire T_192472 : UInt<1>
      T_192472 := T_192471
      when T_192422 : T_192472 := UInt<5>(26)
      wire T_192473 : UInt<1>
      T_192473 := T_192472
      when T_192421 : T_192473 := UInt<5>(27)
      wire T_192474 : UInt<1>
      T_192474 := T_192473
      when T_192420 : T_192474 := UInt<5>(28)
      wire T_192475 : UInt<1>
      T_192475 := T_192474
      when T_192419 : T_192475 := UInt<5>(29)
      wire T_192476 : UInt<1>
      T_192476 := T_192475
      when T_192418 : T_192476 := UInt<5>(30)
      wire T_192477 : UInt<1>
      T_192477 := T_192476
      when T_192417 : T_192477 := UInt<5>(31)
      node T_192478 = not(T_192477)
      node T_192479 = dshl(T_192416, T_192478)
      node T_192480 = subw(UInt<4>(0), UInt<3>(4))
      node T_192481 = not(T_192478)
      node T_192482 = cat(T_192480, T_192481)
      node T_192483 = bits(T_192479, 30, 8)
      wire T_192484 : UInt<5>
      T_192484 := T_192482
      when T_192412 : T_192484 := UInt<1>(0)
      wire T_192485 : UInt<8>
      T_192485 := T_192409
      when T_192411 : T_192485 := T_192484
      wire T_192486 : UInt<1>
      T_192486 := UInt<1>(1)
      when T_192415 : T_192486 := UInt<2>(2)
      node T_192487 = or(UInt<8>(128), T_192486)
      wire T_192488 : UInt<8>
      T_192488 := T_192487
      when T_192413 : T_192488 := UInt<1>(0)
      node T_192489 = addw(T_192485, T_192488)
      node T_192490 = bits(T_192489, 8, 7)
      node T_192491 = eq(T_192490, UInt<1>(-1))
      node T_192492 = eq(T_192412, UInt<1>(0))
      node T_192493 = and(T_192491, T_192492)
      node T_192494 = dshl(T_192493, UInt<3>(6))
      node T_192495 = or(T_192489, T_192494)
      wire T_192496 : UInt<23>
      T_192496 := T_192410
      when T_192411 : T_192496 := T_192483
      node T_192497 = cat(T_192495, T_192496)
      node T_192498 = cat(T_192408, T_192497)
      node T_192499 = asUInt(SInt<32>(-1))
      node T_192500 = cat(T_192499, T_192498)
      mux.data := T_192500
    
    
    node T_192501 = and(in.bits.cmd, UInt<3>(4))
    node T_192502 = eq(UInt<1>(0), T_192501)
    when T_192502 : when in.bits.single : 
        node T_192624 = bits(in.bits.in1, 63, 0)
        node T_192625 = xor(in.bits.typ, UInt<1>(1))
        node T_192626 = eq(T_192625, UInt<2>(1))
        node T_192627 = bit(T_192624, 31)
        node T_192628 = eq(T_192625, UInt<2>(3))
        node T_192629 = bit(T_192624, 63)
        wire T_192630 : UInt<1>
        T_192630 := UInt<1>(0)
        when T_192628 : T_192630 := T_192629
        wire T_192631 : UInt<1>
        T_192631 := T_192630
        when T_192626 : T_192631 := T_192627
        node T_192632 = subw(UInt<1>(0), T_192624)
        wire T_192633 : UInt<64>
        T_192633 := T_192624
        when T_192631 : T_192633 := T_192632
        node T_192634 = eq(T_192625, UInt<2>(3))
        node T_192635 = eq(T_192625, UInt<2>(2))
        node T_192636 = or(T_192634, T_192635)
        node T_192637 = bits(T_192633, 31, 0)
        wire T_192638 : UInt<32>
        T_192638 := T_192637
        when T_192636 : T_192638 := T_192633
        node T_192639 = bit(T_192638, 31)
        node T_192640 = bit(T_192638, 30)
        node T_192641 = bit(T_192638, 29)
        node T_192642 = bit(T_192638, 28)
        node T_192643 = bit(T_192638, 27)
        node T_192644 = bit(T_192638, 26)
        node T_192645 = bit(T_192638, 25)
        node T_192646 = bit(T_192638, 24)
        node T_192647 = bit(T_192638, 23)
        node T_192648 = bit(T_192638, 22)
        node T_192649 = bit(T_192638, 21)
        node T_192650 = bit(T_192638, 20)
        node T_192651 = bit(T_192638, 19)
        node T_192652 = bit(T_192638, 18)
        node T_192653 = bit(T_192638, 17)
        node T_192654 = bit(T_192638, 16)
        node T_192655 = bit(T_192638, 15)
        node T_192656 = bit(T_192638, 14)
        node T_192657 = bit(T_192638, 13)
        node T_192658 = bit(T_192638, 12)
        node T_192659 = bit(T_192638, 11)
        node T_192660 = bit(T_192638, 10)
        node T_192661 = bit(T_192638, 9)
        node T_192662 = bit(T_192638, 8)
        node T_192663 = bit(T_192638, 7)
        node T_192664 = bit(T_192638, 6)
        node T_192665 = bit(T_192638, 5)
        node T_192666 = bit(T_192638, 4)
        node T_192667 = bit(T_192638, 3)
        node T_192668 = bit(T_192638, 2)
        node T_192669 = bit(T_192638, 1)
        wire T_192670 : UInt<1>
        T_192670 := T_192669
        when T_192668 : T_192670 := UInt<2>(2)
        wire T_192671 : UInt<1>
        T_192671 := T_192670
        when T_192667 : T_192671 := UInt<2>(3)
        wire T_192672 : UInt<1>
        T_192672 := T_192671
        when T_192666 : T_192672 := UInt<3>(4)
        wire T_192673 : UInt<1>
        T_192673 := T_192672
        when T_192665 : T_192673 := UInt<3>(5)
        wire T_192674 : UInt<1>
        T_192674 := T_192673
        when T_192664 : T_192674 := UInt<3>(6)
        wire T_192675 : UInt<1>
        T_192675 := T_192674
        when T_192663 : T_192675 := UInt<3>(7)
        wire T_192676 : UInt<1>
        T_192676 := T_192675
        when T_192662 : T_192676 := UInt<4>(8)
        wire T_192677 : UInt<1>
        T_192677 := T_192676
        when T_192661 : T_192677 := UInt<4>(9)
        wire T_192678 : UInt<1>
        T_192678 := T_192677
        when T_192660 : T_192678 := UInt<4>(10)
        wire T_192679 : UInt<1>
        T_192679 := T_192678
        when T_192659 : T_192679 := UInt<4>(11)
        wire T_192680 : UInt<1>
        T_192680 := T_192679
        when T_192658 : T_192680 := UInt<4>(12)
        wire T_192681 : UInt<1>
        T_192681 := T_192680
        when T_192657 : T_192681 := UInt<4>(13)
        wire T_192682 : UInt<1>
        T_192682 := T_192681
        when T_192656 : T_192682 := UInt<4>(14)
        wire T_192683 : UInt<1>
        T_192683 := T_192682
        when T_192655 : T_192683 := UInt<4>(15)
        wire T_192684 : UInt<1>
        T_192684 := T_192683
        when T_192654 : T_192684 := UInt<5>(16)
        wire T_192685 : UInt<1>
        T_192685 := T_192684
        when T_192653 : T_192685 := UInt<5>(17)
        wire T_192686 : UInt<1>
        T_192686 := T_192685
        when T_192652 : T_192686 := UInt<5>(18)
        wire T_192687 : UInt<1>
        T_192687 := T_192686
        when T_192651 : T_192687 := UInt<5>(19)
        wire T_192688 : UInt<1>
        T_192688 := T_192687
        when T_192650 : T_192688 := UInt<5>(20)
        wire T_192689 : UInt<1>
        T_192689 := T_192688
        when T_192649 : T_192689 := UInt<5>(21)
        wire T_192690 : UInt<1>
        T_192690 := T_192689
        when T_192648 : T_192690 := UInt<5>(22)
        wire T_192691 : UInt<1>
        T_192691 := T_192690
        when T_192647 : T_192691 := UInt<5>(23)
        wire T_192692 : UInt<1>
        T_192692 := T_192691
        when T_192646 : T_192692 := UInt<5>(24)
        wire T_192693 : UInt<1>
        T_192693 := T_192692
        when T_192645 : T_192693 := UInt<5>(25)
        wire T_192694 : UInt<1>
        T_192694 := T_192693
        when T_192644 : T_192694 := UInt<5>(26)
        wire T_192695 : UInt<1>
        T_192695 := T_192694
        when T_192643 : T_192695 := UInt<5>(27)
        wire T_192696 : UInt<1>
        T_192696 := T_192695
        when T_192642 : T_192696 := UInt<5>(28)
        wire T_192697 : UInt<1>
        T_192697 := T_192696
        when T_192641 : T_192697 := UInt<5>(29)
        wire T_192698 : UInt<1>
        T_192698 := T_192697
        when T_192640 : T_192698 := UInt<5>(30)
        wire T_192699 : UInt<1>
        T_192699 := T_192698
        when T_192639 : T_192699 := UInt<5>(31)
        node T_192700 = not(T_192699)
        node T_192701 = dshl(T_192638, T_192700)
        node T_192702 = bits(T_192701, 40, 39)
        node T_192703 = bits(T_192701, 38, 0)
        node T_192704 = eq(T_192703, UInt<1>(0))
        node T_192705 = eq(T_192704, UInt<1>(0))
        node T_192706 = cat(T_192702, T_192705)
        node T_192707 = bits(T_192706, 1, 0)
        node T_192708 = eq(T_192707, UInt<1>(0))
        node T_192709 = eq(T_192708, UInt<1>(0))
        node T_192710 = eq(in.bits.rm, UInt<2>(0))
        node T_192711 = bits(T_192706, 2, 1)
        node T_192712 = eq(T_192711, UInt<1>(-1))
        node T_192713 = bits(T_192706, 1, 0)
        node T_192714 = eq(T_192713, UInt<1>(-1))
        node T_192715 = or(T_192712, T_192714)
        node T_192716 = eq(in.bits.rm, UInt<2>(2))
        node T_192717 = and(T_192631, T_192709)
        node T_192718 = eq(in.bits.rm, UInt<2>(3))
        node T_192719 = eq(T_192631, UInt<1>(0))
        node T_192720 = and(T_192719, T_192709)
        wire T_192721 : UInt<1>
        T_192721 := UInt<1>(0)
        when T_192718 : T_192721 := T_192720
        wire T_192722 : UInt<1>
        T_192722 := T_192721
        when T_192716 : T_192722 := T_192717
        wire T_192723 : UInt<1>
        T_192723 := T_192722
        when T_192710 : T_192723 := T_192715
        node T_192724 = bits(T_192701, 63, 40)
        node T_192725 = cat(UInt<1>(0), T_192724)
        node T_192726 = addw(T_192725, UInt<1>(1))
        wire T_192727 : UInt<25>
        T_192727 := T_192725
        when T_192723 : T_192727 := T_192726
        node T_192728 = not(T_192700)
        node T_192729 = cat(UInt<1>(0), T_192728)
        node T_192730 = cat(UInt<1>(0), T_192729)
        node T_192731 = bit(T_192727, 24)
        node T_192732 = addw(T_192730, T_192731)
        node T_192733 = bit(T_192701, 63)
        node T_192734 = bits(T_192732, 7, 0)
        wire T_192735 : UInt<8>
        T_192735 := T_192734
        when UInt<1>(0) : T_192735 := UInt<8>(128)
        node T_192736 = cat(T_192733, T_192735)
        node T_192737 = or(UInt<1>(0), UInt<1>(0))
        node T_192738 = or(T_192709, T_192737)
        node T_192739 = bits(T_192727, 22, 0)
        node T_192740 = cat(T_192736, T_192739)
        node T_192741 = cat(T_192631, T_192740)
        node T_192742 = cat(UInt<2>(0), T_192737)
        node T_192743 = cat(UInt<1>(0), T_192738)
        node T_192744 = cat(T_192742, T_192743)
        node T_192745 = asUInt(SInt<32>(-1))
        node T_192746 = cat(T_192745, T_192741)
        mux.data := T_192746
        mux.exc := T_192744
      else : 
        
        node T_192503 = bits(in.bits.in1, 63, 0)
        node T_192504 = xor(in.bits.typ, UInt<1>(1))
        node T_192505 = eq(T_192504, UInt<2>(1))
        node T_192506 = bit(T_192503, 31)
        node T_192507 = eq(T_192504, UInt<2>(3))
        node T_192508 = bit(T_192503, 63)
        wire T_192509 : UInt<1>
        T_192509 := UInt<1>(0)
        when T_192507 : T_192509 := T_192508
        wire T_192510 : UInt<1>
        T_192510 := T_192509
        when T_192505 : T_192510 := T_192506
        node T_192511 = subw(UInt<1>(0), T_192503)
        wire T_192512 : UInt<64>
        T_192512 := T_192503
        when T_192510 : T_192512 := T_192511
        node T_192513 = eq(T_192504, UInt<2>(3))
        node T_192514 = eq(T_192504, UInt<2>(2))
        node T_192515 = or(T_192513, T_192514)
        node T_192516 = bits(T_192512, 31, 0)
        wire T_192517 : UInt<32>
        T_192517 := T_192516
        when T_192515 : T_192517 := T_192512
        node T_192518 = bit(T_192517, 31)
        node T_192519 = bit(T_192517, 30)
        node T_192520 = bit(T_192517, 29)
        node T_192521 = bit(T_192517, 28)
        node T_192522 = bit(T_192517, 27)
        node T_192523 = bit(T_192517, 26)
        node T_192524 = bit(T_192517, 25)
        node T_192525 = bit(T_192517, 24)
        node T_192526 = bit(T_192517, 23)
        node T_192527 = bit(T_192517, 22)
        node T_192528 = bit(T_192517, 21)
        node T_192529 = bit(T_192517, 20)
        node T_192530 = bit(T_192517, 19)
        node T_192531 = bit(T_192517, 18)
        node T_192532 = bit(T_192517, 17)
        node T_192533 = bit(T_192517, 16)
        node T_192534 = bit(T_192517, 15)
        node T_192535 = bit(T_192517, 14)
        node T_192536 = bit(T_192517, 13)
        node T_192537 = bit(T_192517, 12)
        node T_192538 = bit(T_192517, 11)
        node T_192539 = bit(T_192517, 10)
        node T_192540 = bit(T_192517, 9)
        node T_192541 = bit(T_192517, 8)
        node T_192542 = bit(T_192517, 7)
        node T_192543 = bit(T_192517, 6)
        node T_192544 = bit(T_192517, 5)
        node T_192545 = bit(T_192517, 4)
        node T_192546 = bit(T_192517, 3)
        node T_192547 = bit(T_192517, 2)
        node T_192548 = bit(T_192517, 1)
        wire T_192549 : UInt<1>
        T_192549 := T_192548
        when T_192547 : T_192549 := UInt<2>(2)
        wire T_192550 : UInt<1>
        T_192550 := T_192549
        when T_192546 : T_192550 := UInt<2>(3)
        wire T_192551 : UInt<1>
        T_192551 := T_192550
        when T_192545 : T_192551 := UInt<3>(4)
        wire T_192552 : UInt<1>
        T_192552 := T_192551
        when T_192544 : T_192552 := UInt<3>(5)
        wire T_192553 : UInt<1>
        T_192553 := T_192552
        when T_192543 : T_192553 := UInt<3>(6)
        wire T_192554 : UInt<1>
        T_192554 := T_192553
        when T_192542 : T_192554 := UInt<3>(7)
        wire T_192555 : UInt<1>
        T_192555 := T_192554
        when T_192541 : T_192555 := UInt<4>(8)
        wire T_192556 : UInt<1>
        T_192556 := T_192555
        when T_192540 : T_192556 := UInt<4>(9)
        wire T_192557 : UInt<1>
        T_192557 := T_192556
        when T_192539 : T_192557 := UInt<4>(10)
        wire T_192558 : UInt<1>
        T_192558 := T_192557
        when T_192538 : T_192558 := UInt<4>(11)
        wire T_192559 : UInt<1>
        T_192559 := T_192558
        when T_192537 : T_192559 := UInt<4>(12)
        wire T_192560 : UInt<1>
        T_192560 := T_192559
        when T_192536 : T_192560 := UInt<4>(13)
        wire T_192561 : UInt<1>
        T_192561 := T_192560
        when T_192535 : T_192561 := UInt<4>(14)
        wire T_192562 : UInt<1>
        T_192562 := T_192561
        when T_192534 : T_192562 := UInt<4>(15)
        wire T_192563 : UInt<1>
        T_192563 := T_192562
        when T_192533 : T_192563 := UInt<5>(16)
        wire T_192564 : UInt<1>
        T_192564 := T_192563
        when T_192532 : T_192564 := UInt<5>(17)
        wire T_192565 : UInt<1>
        T_192565 := T_192564
        when T_192531 : T_192565 := UInt<5>(18)
        wire T_192566 : UInt<1>
        T_192566 := T_192565
        when T_192530 : T_192566 := UInt<5>(19)
        wire T_192567 : UInt<1>
        T_192567 := T_192566
        when T_192529 : T_192567 := UInt<5>(20)
        wire T_192568 : UInt<1>
        T_192568 := T_192567
        when T_192528 : T_192568 := UInt<5>(21)
        wire T_192569 : UInt<1>
        T_192569 := T_192568
        when T_192527 : T_192569 := UInt<5>(22)
        wire T_192570 : UInt<1>
        T_192570 := T_192569
        when T_192526 : T_192570 := UInt<5>(23)
        wire T_192571 : UInt<1>
        T_192571 := T_192570
        when T_192525 : T_192571 := UInt<5>(24)
        wire T_192572 : UInt<1>
        T_192572 := T_192571
        when T_192524 : T_192572 := UInt<5>(25)
        wire T_192573 : UInt<1>
        T_192573 := T_192572
        when T_192523 : T_192573 := UInt<5>(26)
        wire T_192574 : UInt<1>
        T_192574 := T_192573
        when T_192522 : T_192574 := UInt<5>(27)
        wire T_192575 : UInt<1>
        T_192575 := T_192574
        when T_192521 : T_192575 := UInt<5>(28)
        wire T_192576 : UInt<1>
        T_192576 := T_192575
        when T_192520 : T_192576 := UInt<5>(29)
        wire T_192577 : UInt<1>
        T_192577 := T_192576
        when T_192519 : T_192577 := UInt<5>(30)
        wire T_192578 : UInt<1>
        T_192578 := T_192577
        when T_192518 : T_192578 := UInt<5>(31)
        node T_192579 = not(T_192578)
        node T_192580 = dshl(T_192517, T_192579)
        node T_192581 = bits(T_192580, 11, 10)
        node T_192582 = bits(T_192580, 9, 0)
        node T_192583 = eq(T_192582, UInt<1>(0))
        node T_192584 = eq(T_192583, UInt<1>(0))
        node T_192585 = cat(T_192581, T_192584)
        node T_192586 = bits(T_192585, 1, 0)
        node T_192587 = eq(T_192586, UInt<1>(0))
        node T_192588 = eq(T_192587, UInt<1>(0))
        node T_192589 = eq(in.bits.rm, UInt<2>(0))
        node T_192590 = bits(T_192585, 2, 1)
        node T_192591 = eq(T_192590, UInt<1>(-1))
        node T_192592 = bits(T_192585, 1, 0)
        node T_192593 = eq(T_192592, UInt<1>(-1))
        node T_192594 = or(T_192591, T_192593)
        node T_192595 = eq(in.bits.rm, UInt<2>(2))
        node T_192596 = and(T_192510, T_192588)
        node T_192597 = eq(in.bits.rm, UInt<2>(3))
        node T_192598 = eq(T_192510, UInt<1>(0))
        node T_192599 = and(T_192598, T_192588)
        wire T_192600 : UInt<1>
        T_192600 := UInt<1>(0)
        when T_192597 : T_192600 := T_192599
        wire T_192601 : UInt<1>
        T_192601 := T_192600
        when T_192595 : T_192601 := T_192596
        wire T_192602 : UInt<1>
        T_192602 := T_192601
        when T_192589 : T_192602 := T_192594
        node T_192603 = bits(T_192580, 63, 11)
        node T_192604 = cat(UInt<1>(0), T_192603)
        node T_192605 = addw(T_192604, UInt<1>(1))
        wire T_192606 : UInt<54>
        T_192606 := T_192604
        when T_192602 : T_192606 := T_192605
        node T_192607 = not(T_192579)
        node T_192608 = cat(UInt<4>(0), T_192607)
        node T_192609 = cat(UInt<1>(0), T_192608)
        node T_192610 = bit(T_192606, 53)
        node T_192611 = addw(T_192609, T_192610)
        node T_192612 = bit(T_192580, 63)
        node T_192613 = bits(T_192611, 10, 0)
        wire T_192614 : UInt<11>
        T_192614 := T_192613
        when UInt<1>(0) : T_192614 := UInt<11>(1024)
        node T_192615 = cat(T_192612, T_192614)
        node T_192616 = or(UInt<1>(0), UInt<1>(0))
        node T_192617 = or(T_192588, T_192616)
        node T_192618 = bits(T_192606, 51, 0)
        node T_192619 = cat(T_192615, T_192618)
        node T_192620 = cat(T_192510, T_192619)
        node T_192621 = cat(UInt<2>(0), T_192616)
        node T_192622 = cat(UInt<1>(0), T_192617)
        node T_192623 = cat(T_192621, T_192622)
        mux.data := T_192620
        mux.exc := T_192623
    reg T_192747 : UInt<1>
    onreset T_192747 := UInt<1>(0)
    T_192747 := in.valid
    reg T_192748 : {data : UInt<65>, exc : UInt<5>}
    when in.valid : T_192748 := mux
    reg T_192749 : UInt<1>
    onreset T_192749 := UInt<1>(0)
    T_192749 := T_192747
    reg T_192750 : {data : UInt<65>, exc : UInt<5>}
    when T_192747 : T_192750 := T_192748
    T_192751.valid <> T_192749
    T_192751.bits <> T_192750
    out <> T_192751
  module FPToFP : 
    input in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
    output out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}
    input lt : UInt<1>
    
    reg T_192752 : UInt<1>
    onreset T_192752 := UInt<1>(0)
    T_192752 := in.valid
    reg T_192753 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    when in.valid : T_192753 := in.bits
    in.valid <> T_192752
    in.bits <> T_192753
    node T_192754 = and(in.bits.cmd, UInt<3>(5))
    node isSgnj = eq(UInt<3>(4), T_192754)
    node T_192755 = and(in.bits.single, isSgnj)
    node T_192756 = bit(in.bits.rm, 1)
    node T_192757 = eq(T_192755, UInt<1>(0))
    node T_192758 = or(T_192756, T_192757)
    node T_192759 = bit(in.bits.in1, 32)
    node T_192760 = bit(in.bits.rm, 0)
    wire T_192761 : UInt<1>
    T_192761 := T_192760
    when T_192758 : T_192761 := T_192759
    node T_192762 = bit(in.bits.in2, 32)
    node T_192763 = and(T_192755, T_192762)
    node sign_s = xor(T_192761, T_192763)
    node T_192764 = eq(in.bits.single, UInt<1>(0))
    node T_192765 = and(T_192764, isSgnj)
    node T_192766 = bit(in.bits.rm, 1)
    node T_192767 = eq(T_192765, UInt<1>(0))
    node T_192768 = or(T_192766, T_192767)
    node T_192769 = bit(in.bits.in1, 64)
    node T_192770 = bit(in.bits.rm, 0)
    wire T_192771 : UInt<1>
    T_192771 := T_192770
    when T_192768 : T_192771 := T_192769
    node T_192772 = bit(in.bits.in2, 64)
    node T_192773 = and(T_192765, T_192772)
    node sign_d = xor(T_192771, T_192773)
    node T_192774 = bits(in.bits.in1, 63, 33)
    node T_192775 = bits(in.bits.in1, 31, 0)
    node T_192776 = cat(sign_d, T_192774)
    node T_192777 = cat(sign_s, T_192775)
    node fsgnj = cat(T_192776, T_192777)
    node T_192778 = bit(in.bits.in1, 32)
    node T_192779 = bits(in.bits.in1, 22, 0)
    node T_192780 = bits(in.bits.in1, 31, 23)
    node T_192781 = bits(in.bits.in1, 31, 29)
    node T_192782 = bits(in.bits.in1, 30, 23)
    node T_192783 = eq(T_192781, UInt<1>(-1))
    node T_192784 = bit(T_192779, 22)
    node T_192785 = eq(T_192784, UInt<1>(0))
    node T_192786 = and(T_192783, T_192785)
    node T_192787 = lt(T_192781, UInt<1>(1))
    node T_192788 = lt(T_192781, UInt<3>(4))
    node T_192789 = cat(UInt<3>(7), T_192782)
    node T_192790 = lt(T_192781, UInt<3>(6))
    node T_192791 = cat(UInt<4>(8), T_192782)
    node T_192792 = lt(T_192781, UInt<3>(7))
    wire T_192793 : UInt<12>
    T_192793 := UInt<12>(3584)
    when T_192792 : T_192793 := UInt<12>(3072)
    wire T_192794 : UInt<12>
    T_192794 := T_192793
    when T_192790 : T_192794 := T_192791
    wire T_192795 : UInt<12>
    T_192795 := T_192794
    when T_192788 : T_192795 := T_192789
    wire T_192796 : UInt<12>
    T_192796 := T_192795
    when T_192787 : T_192796 := T_192782
    node T_192797 = subw(UInt<52>(0), UInt<6>(52))
    node T_192798 = dshl(T_192779, UInt<5>(29))
    node T_192799 = or(T_192797, T_192798)
    node T_192800 = cat(T_192796, T_192799)
    node T_192801 = cat(T_192778, T_192800)
    node T_192802 = dshl(T_192786, UInt<3>(4))
    node T_192803 = bit(in.bits.in1, 64)
    node T_192804 = bits(in.bits.in1, 51, 0)
    node T_192805 = bits(in.bits.in1, 63, 52)
    node T_192806 = bits(in.bits.in1, 63, 61)
    node T_192807 = bits(in.bits.in1, 62, 52)
    node T_192808 = eq(T_192806, UInt<1>(-1))
    node T_192809 = bit(T_192804, 51)
    node T_192810 = eq(T_192809, UInt<1>(0))
    node T_192811 = and(T_192808, T_192810)
    node T_192812 = eq(T_192806, UInt<1>(0))
    node T_192813 = eq(T_192812, UInt<1>(0))
    node T_192814 = eq(T_192813, UInt<1>(0))
    node T_192815 = bits(T_192806, 2, 1)
    node T_192816 = eq(T_192815, UInt<1>(-1))
    node T_192817 = or(T_192814, T_192816)
    node T_192818 = geq(T_192805, UInt<11>(1898))
    node T_192819 = leq(T_192805, UInt<11>(1921))
    node T_192820 = and(T_192818, T_192819)
    node T_192821 = lt(T_192805, UInt<11>(1898))
    node T_192822 = eq(T_192817, UInt<1>(0))
    node T_192823 = and(T_192821, T_192822)
    node T_192824 = gt(T_192805, UInt<12>(2175))
    node T_192825 = eq(T_192817, UInt<1>(0))
    node T_192826 = and(T_192824, T_192825)
    node T_192827 = addw(UInt<11>(1921), UInt<1>(1))
    node T_192828 = subw(T_192827, T_192805)
    wire T_192829 : UInt<1>
    T_192829 := UInt<1>(0)
    when T_192820 : T_192829 := T_192828
    node T_192830 = bits(T_192829, 4, 0)
    node T_192831 = bits(T_192804, 51, 28)
    node T_192832 = cat(T_192831, UInt<24>(0))
    node T_192833 = cat(UInt<1>(1), T_192832)
    node T_192834 = dshr(T_192833, T_192830)
    node T_192835 = bits(T_192834, 23, 0)
    node T_192836 = neq(T_192835, UInt<1>(0))
    node T_192837 = bits(T_192804, 27, 0)
    node T_192838 = neq(T_192837, UInt<1>(0))
    node T_192839 = or(T_192836, T_192838)
    node T_192840 = bits(T_192834, 25, 24)
    node T_192841 = cat(T_192840, T_192839)
    node T_192842 = bits(T_192841, 1, 0)
    node T_192843 = neq(T_192842, UInt<1>(0))
    node T_192844 = eq(T_192817, UInt<1>(0))
    node T_192845 = and(T_192843, T_192844)
    node T_192846 = eq(in.bits.rm, UInt<2>(0))
    node T_192847 = bits(T_192841, 1, 0)
    node T_192848 = eq(T_192847, UInt<1>(-1))
    node T_192849 = bits(T_192841, 2, 1)
    node T_192850 = eq(T_192849, UInt<1>(-1))
    node T_192851 = or(T_192848, T_192850)
    node T_192852 = eq(in.bits.rm, UInt<2>(2))
    node T_192853 = and(T_192803, T_192845)
    node T_192854 = eq(in.bits.rm, UInt<2>(3))
    node T_192855 = eq(T_192803, UInt<1>(0))
    node T_192856 = and(T_192855, T_192845)
    wire T_192857 : UInt<1>
    T_192857 := UInt<1>(0)
    when T_192854 : T_192857 := T_192856
    wire T_192858 : UInt<1>
    T_192858 := T_192857
    when T_192852 : T_192858 := T_192853
    wire T_192859 : UInt<1>
    T_192859 := T_192858
    when T_192846 : T_192859 := T_192851
    node T_192860 = dshl(UInt<25>(33554431), T_192830)
    node T_192861 = bits(T_192860, 24, 0)
    node T_192862 = bits(T_192804, 51, 29)
    node T_192863 = cat(UInt<2>(1), T_192862)
    node T_192864 = not(T_192861)
    node T_192865 = or(T_192863, T_192864)
    node T_192866 = addw(T_192865, UInt<1>(1))
    wire T_192867 : UInt<25>
    T_192867 := T_192865
    when T_192859 : T_192867 := T_192866
    node T_192868 = bits(T_192805, 8, 0)
    node T_192869 = addw(T_192868, UInt<9>(256))
    node T_192870 = bit(T_192867, 24)
    node T_192871 = addw(T_192869, UInt<1>(1))
    wire T_192872 : UInt<9>
    T_192872 := T_192869
    when T_192870 : T_192872 := T_192871
    node T_192873 = eq(in.bits.rm, UInt<2>(2))
    node T_192874 = and(T_192873, T_192803)
    node T_192875 = eq(in.bits.rm, UInt<2>(3))
    node T_192876 = eq(T_192803, UInt<1>(0))
    node T_192877 = and(T_192875, T_192876)
    node T_192878 = or(T_192874, T_192877)
    node T_192879 = eq(in.bits.rm, UInt<2>(0))
    node T_192880 = or(T_192878, T_192879)
    node T_192881 = eq(T_192880, UInt<1>(0))
    node T_192882 = subw(UInt<23>(0), UInt<5>(23))
    wire T_192883 : UInt<9>
    T_192883 := UInt<9>(383)
    when T_192880 : T_192883 := UInt<9>(384)
    wire T_192884 : UInt<1>
    T_192884 := UInt<1>(0)
    when T_192878 : T_192884 := UInt<7>(107)
    node T_192885 = dshl(T_192806, UInt<3>(6))
    wire T_192886 : UInt<9>
    T_192886 := T_192872
    when T_192823 : T_192886 := T_192884
    wire T_192887 : UInt<9>
    T_192887 := T_192886
    when T_192826 : T_192887 := T_192883
    wire T_192888 : UInt<9>
    T_192888 := T_192887
    when T_192817 : T_192888 := T_192885
    node T_192889 = subw(UInt<23>(0), UInt<5>(23))
    node T_192890 = bits(T_192867, 22, 0)
    wire T_192891 : UInt<23>
    T_192891 := T_192890
    when T_192823 : T_192891 := UInt<1>(0)
    wire T_192892 : UInt<23>
    T_192892 := T_192891
    when T_192826 : T_192892 := T_192882
    wire T_192893 : UInt<23>
    T_192893 := T_192892
    when T_192817 : T_192893 := T_192889
    node T_192894 = cat(T_192888, T_192893)
    node T_192895 = cat(T_192803, T_192894)
    node T_192896 = and(T_192820, T_192845)
    node T_192897 = or(T_192823, T_192896)
    node T_192898 = eq(T_192805, UInt<12>(2175))
    node T_192899 = bit(T_192867, 24)
    node T_192900 = and(T_192898, T_192899)
    node T_192901 = or(T_192826, T_192900)
    node T_192902 = or(T_192845, T_192826)
    node T_192903 = or(T_192902, T_192823)
    node T_192904 = cat(T_192811, UInt<1>(0))
    node T_192905 = cat(T_192897, T_192903)
    node T_192906 = cat(T_192901, T_192905)
    node T_192907 = cat(T_192904, T_192906)
    node T_192908 = bits(in.bits.in1, 31, 29)
    node T_192909 = eq(T_192908, UInt<1>(-1))
    node T_192910 = bits(in.bits.in1, 63, 61)
    node T_192911 = eq(T_192910, UInt<1>(-1))
    wire isnan1 : UInt<1>
    isnan1 := T_192911
    when in.bits.single : isnan1 := T_192909
    node T_192912 = bits(in.bits.in2, 31, 29)
    node T_192913 = eq(T_192912, UInt<1>(-1))
    node T_192914 = bits(in.bits.in2, 63, 61)
    node T_192915 = eq(T_192914, UInt<1>(-1))
    wire isnan2 : UInt<1>
    isnan2 := T_192915
    when in.bits.single : isnan2 := T_192913
    node T_192916 = bit(in.bits.in1, 22)
    node T_192917 = bit(in.bits.in1, 51)
    wire T_192918 : UInt<1>
    T_192918 := T_192917
    when in.bits.single : T_192918 := T_192916
    node T_192919 = not(T_192918)
    node issnan1 = and(isnan1, T_192919)
    node T_192920 = bit(in.bits.in2, 22)
    node T_192921 = bit(in.bits.in2, 51)
    wire T_192922 : UInt<1>
    T_192922 := T_192921
    when in.bits.single : T_192922 := T_192920
    node T_192923 = not(T_192922)
    node issnan2 = and(isnan2, T_192923)
    node T_192924 = or(issnan1, issnan2)
    node minmax_exc = cat(T_192924, UInt<4>(0))
    node isMax = bit(in.bits.rm, 0)
    node T_192925 = neq(isMax, lt)
    node T_192926 = eq(isnan1, UInt<1>(0))
    node T_192927 = and(T_192925, T_192926)
    node isLHS = or(isnan2, T_192927)
    wire mux : {data : UInt<65>, exc : UInt<5>}
    mux.exc := minmax_exc
    mux.data := in.bits.in2
    when isSgnj : mux.exc := UInt<1>(0)
    
    node T_192928 = or(isSgnj, isLHS)
    when T_192928 : mux.data := fsgnj
    
    
    node T_192929 = and(in.bits.cmd, UInt<3>(4))
    node T_192930 = eq(UInt<1>(0), T_192929)
    when T_192930 : when in.bits.single : 
        node T_192931 = asUInt(SInt<32>(-1))
        node T_192932 = cat(T_192931, T_192895)
        mux.data := T_192932
        mux.exc := T_192907
      else : 
        
        mux.data := T_192801
        mux.exc := T_192802
    reg T_192933 : UInt<1>
    onreset T_192933 := UInt<1>(0)
    T_192933 := in.valid
    reg T_192934 : {data : UInt<65>, exc : UInt<5>}
    when in.valid : T_192934 := mux
    T_192935.valid <> T_192933
    T_192935.bits <> T_192934
    out <> T_192935
  module divSqrtRecodedFloat64_mulAddZ31 : 
    output inReady_div : UInt<1>
    output inReady_sqrt : UInt<1>
    input inValid : UInt<1>
    input sqrtOp : UInt<1>
    input a : UInt<65>
    input b : UInt<65>
    input roundingMode : UInt<2>
    output outValid_div : UInt<1>
    output outValid_sqrt : UInt<1>
    output out : UInt<65>
    output exceptionFlags : UInt<5>
    output usingMulAdd : UInt<4>
    output latchMulAddA_0 : UInt<1>
    output mulAddA_0 : UInt<54>
    output latchMulAddB_0 : UInt<1>
    output mulAddB_0 : UInt<54>
    output mulAddC_2 : UInt<105>
    input mulAddResult_3 : UInt<105>
    
    reg valid_PA : UInt<1>
    onreset valid_PA := UInt<1>(0)
    reg sqrtOp_PA : UInt<1>
    reg sign_PA : UInt<1>
    reg specialCodeB_PA : UInt<3>
    reg fractB_51_PA : UInt<1>
    reg roundingMode_PA : UInt<2>
    reg specialCodeA_PA : UInt<3>
    reg fractA_51_PA : UInt<1>
    reg exp_PA : UInt<14>
    reg fractB_other_PA : UInt<51>
    reg fractA_other_PA : UInt<51>
    reg valid_PB : UInt<1>
    onreset valid_PB := UInt<1>(0)
    reg sqrtOp_PB : UInt<1>
    reg sign_PB : UInt<1>
    reg specialCodeA_PB : UInt<3>
    reg fractA_51_PB : UInt<1>
    reg specialCodeB_PB : UInt<3>
    reg fractB_51_PB : UInt<1>
    reg roundingMode_PB : UInt<2>
    reg exp_PB : UInt<14>
    reg fractA_0_PB : UInt<1>
    reg fractB_other_PB : UInt<51>
    reg valid_PC : UInt<1>
    onreset valid_PC := UInt<1>(0)
    reg sqrtOp_PC : UInt<1>
    reg sign_PC : UInt<1>
    reg specialCodeA_PC : UInt<3>
    reg fractA_51_PC : UInt<1>
    reg specialCodeB_PC : UInt<3>
    reg fractB_51_PC : UInt<1>
    reg roundingMode_PC : UInt<2>
    reg exp_PC : UInt<14>
    reg fractA_0_PC : UInt<1>
    reg fractB_other_PC : UInt<51>
    reg cycleNum_A : UInt<3>
    onreset cycleNum_A := UInt<3>(0)
    reg cycleNum_B : UInt<4>
    onreset cycleNum_B := UInt<4>(0)
    reg cycleNum_C : UInt<3>
    onreset cycleNum_C := UInt<3>(0)
    reg cycleNum_E : UInt<3>
    onreset cycleNum_E := UInt<3>(0)
    reg fractR0_A : UInt<9>
    reg hiSqrR0_A_sqrt : UInt<10>
    reg partNegSigma0_A : UInt<21>
    reg nextMulAdd9A_A : UInt<9>
    reg nextMulAdd9B_A : UInt<9>
    reg ER1_B_sqrt : UInt<17>
    reg ESqrR1_B_sqrt : UInt<32>
    reg sigX1_B : UInt<58>
    reg sqrSigma1_C : UInt<33>
    reg sigXN_C : UInt<58>
    reg u_C_sqrt : UInt<31>
    reg E_E_div : UInt<1>
    reg sigT_E : UInt<53>
    reg extraT_E : UInt<1>
    reg isNegRemT_E : UInt<1>
    reg trueEqX_E1 : UInt<1>
    wire ready_PA : UInt<1>
    wire ready_PB : UInt<1>
    wire ready_PC : UInt<1>
    wire leaving_PA : UInt<1>
    wire leaving_PB : UInt<1>
    wire leaving_PC : UInt<1>
    wire cyc_B10_sqrt : UInt<1>
    wire cyc_B9_sqrt : UInt<1>
    wire cyc_B8_sqrt : UInt<1>
    wire cyc_B7_sqrt : UInt<1>
    wire cyc_B6 : UInt<1>
    wire cyc_B5 : UInt<1>
    wire cyc_B4 : UInt<1>
    wire cyc_B3 : UInt<1>
    wire cyc_B2 : UInt<1>
    wire cyc_B1 : UInt<1>
    wire cyc_B6_div : UInt<1>
    wire cyc_B5_div : UInt<1>
    wire cyc_B4_div : UInt<1>
    wire cyc_B3_div : UInt<1>
    wire cyc_B2_div : UInt<1>
    wire cyc_B1_div : UInt<1>
    wire cyc_B6_sqrt : UInt<1>
    wire cyc_B5_sqrt : UInt<1>
    wire cyc_B4_sqrt : UInt<1>
    wire cyc_B3_sqrt : UInt<1>
    wire cyc_B2_sqrt : UInt<1>
    wire cyc_B1_sqrt : UInt<1>
    wire cyc_C5 : UInt<1>
    wire cyc_C4 : UInt<1>
    wire cyc_C3 : UInt<1>
    wire cyc_C2 : UInt<1>
    wire cyc_C1 : UInt<1>
    wire cyc_E4 : UInt<1>
    wire cyc_E3 : UInt<1>
    wire cyc_E2 : UInt<1>
    wire cyc_E1 : UInt<1>
    wire zSigma1_B4 : UInt
    wire sigXNU_B3_CX : UInt
    wire zComplSigT_C1_sqrt : UInt
    wire zComplSigT_C1 : UInt
    node T_192936 = not(cyc_B6_sqrt)
    node T_192937 = and(ready_PA, T_192936)
    node T_192938 = not(cyc_B5_sqrt)
    node T_192939 = and(T_192937, T_192938)
    node T_192940 = not(cyc_B4_sqrt)
    node T_192941 = and(T_192939, T_192940)
    node T_192942 = not(cyc_B3)
    node T_192943 = and(T_192941, T_192942)
    node T_192944 = not(cyc_B2)
    node T_192945 = and(T_192943, T_192944)
    node T_192946 = not(cyc_B1_sqrt)
    node T_192947 = and(T_192945, T_192946)
    node T_192948 = not(cyc_C5)
    node T_192949 = and(T_192947, T_192948)
    node T_192950 = not(cyc_C4)
    node T_192951 = and(T_192949, T_192950)
    inReady_div := T_192951
    node T_192952 = not(cyc_B6_sqrt)
    node T_192953 = and(ready_PA, T_192952)
    node T_192954 = not(cyc_B5_sqrt)
    node T_192955 = and(T_192953, T_192954)
    node T_192956 = not(cyc_B4_sqrt)
    node T_192957 = and(T_192955, T_192956)
    node T_192958 = not(cyc_B2_div)
    node T_192959 = and(T_192957, T_192958)
    node T_192960 = not(cyc_B1_sqrt)
    node T_192961 = and(T_192959, T_192960)
    inReady_sqrt := T_192961
    node T_192962 = and(inReady_div, inValid)
    node T_192963 = not(sqrtOp)
    node cyc_S_div = and(T_192962, T_192963)
    node T_192964 = and(inReady_sqrt, inValid)
    node cyc_S_sqrt = and(T_192964, sqrtOp)
    node cyc_S = or(cyc_S_div, cyc_S_sqrt)
    node signA_S = bit(a, 64)
    node expA_S = bits(a, 63, 52)
    node fractA_S = bits(a, 51, 0)
    node specialCodeA_S = bits(expA_S, 11, 9)
    node isZeroA_S = eq(specialCodeA_S, UInt<3>(0))
    node T_192965 = bits(specialCodeA_S, 2, 1)
    node isSpecialA_S = eq(T_192965, UInt<2>(3))
    node signB_S = bit(b, 64)
    node expB_S = bits(b, 63, 52)
    node fractB_S = bits(b, 51, 0)
    node specialCodeB_S = bits(expB_S, 11, 9)
    node isZeroB_S = eq(specialCodeB_S, UInt<3>(0))
    node T_192966 = bits(specialCodeB_S, 2, 1)
    node isSpecialB_S = eq(T_192966, UInt<2>(3))
    node T_192967 = xor(signA_S, signB_S)
    wire sign_S : UInt<1>
    sign_S := T_192967
    when sqrtOp : sign_S := signB_S
    node T_192968 = not(isSpecialA_S)
    node T_192969 = not(isSpecialB_S)
    node T_192970 = and(T_192968, T_192969)
    node T_192971 = not(isZeroA_S)
    node T_192972 = and(T_192970, T_192971)
    node T_192973 = not(isZeroB_S)
    node normalCase_S_div = and(T_192972, T_192973)
    node T_192974 = not(isSpecialB_S)
    node T_192975 = not(isZeroB_S)
    node T_192976 = and(T_192974, T_192975)
    node T_192977 = not(signB_S)
    node normalCase_S_sqrt = and(T_192976, T_192977)
    wire normalCase_S : UInt<1>
    normalCase_S := normalCase_S_div
    when sqrtOp : normalCase_S := normalCase_S_sqrt
    node cyc_A4_div = and(cyc_S_div, normalCase_S_div)
    node cyc_A7_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt)
    node entering_PA_normalCase = or(cyc_A4_div, cyc_A7_sqrt)
    node T_192978 = not(ready_PB)
    node T_192979 = or(valid_PA, T_192978)
    node T_192980 = and(cyc_S, T_192979)
    node entering_PA = or(entering_PA_normalCase, T_192980)
    node T_192981 = not(normalCase_S)
    node T_192982 = and(cyc_S, T_192981)
    node T_192983 = not(valid_PA)
    node T_192984 = and(T_192982, T_192983)
    node T_192985 = not(valid_PB)
    node T_192986 = not(ready_PC)
    node T_192987 = and(T_192985, T_192986)
    node T_192988 = or(leaving_PB, T_192987)
    node entering_PB_S = and(T_192984, T_192988)
    node T_192989 = not(normalCase_S)
    node T_192990 = and(cyc_S, T_192989)
    node T_192991 = not(valid_PA)
    node T_192992 = and(T_192990, T_192991)
    node T_192993 = not(valid_PB)
    node T_192994 = and(T_192992, T_192993)
    node entering_PC_S = and(T_192994, ready_PC)
    
    node T_192995 = or(entering_PA, leaving_PA)
    when T_192995 : valid_PA := entering_PA
    when entering_PA : 
      sqrtOp_PA := sqrtOp
      sign_PA := sign_S
      specialCodeB_PA := specialCodeB_S
      node T_192996 = bit(fractB_S, 51)
      fractB_51_PA := T_192996
      roundingMode_PA := roundingMode
    
    
    node T_192997 = not(sqrtOp)
    node T_192998 = and(entering_PA, T_192997)
    when T_192998 : 
      specialCodeA_PA := specialCodeA_S
      node T_192999 = bit(fractA_S, 51)
      fractA_51_PA := T_192999
    when entering_PA_normalCase : 
      node T_193000 = bit(expB_S, 11)
      node T_193001 = subw(UInt<3>(0), UInt<2>(3))
      node T_193002 = bits(expB_S, 10, 0)
      node T_193003 = not(T_193002)
      node T_193004 = cat(T_193001, T_193003)
      node T_193005 = addw(expA_S, T_193004)
      wire T_193006 : UInt<14>
      T_193006 := T_193005
      when sqrtOp : T_193006 := expB_S
      exp_PA := T_193006
      node T_193007 = bits(fractB_S, 50, 0)
      fractB_other_PA := T_193007
    when cyc_A4_div : 
      node T_193008 = bits(fractA_S, 50, 0)
      fractA_other_PA := T_193008
    node isZeroA_PA = eq(specialCodeA_PA, UInt<3>(0))
    node T_193009 = bits(specialCodeA_PA, 2, 1)
    node isSpecialA_PA = eq(T_193009, UInt<2>(3))
    node T_193010 = cat(fractA_51_PA, fractA_other_PA)
    node sigA_PA = cat(UInt<1>(1), T_193010)
    node isZeroB_PA = eq(specialCodeB_PA, UInt<3>(0))
    node T_193011 = bits(specialCodeB_PA, 2, 1)
    node isSpecialB_PA = eq(T_193011, UInt<2>(3))
    node T_193012 = cat(fractB_51_PA, fractB_other_PA)
    node sigB_PA = cat(UInt<1>(1), T_193012)
    node T_193013 = not(isSpecialB_PA)
    node T_193014 = not(isZeroB_PA)
    node T_193015 = and(T_193013, T_193014)
    node T_193016 = not(sign_PA)
    node T_193017 = and(T_193015, T_193016)
    node T_193018 = not(isSpecialA_PA)
    node T_193019 = not(isSpecialB_PA)
    node T_193020 = and(T_193018, T_193019)
    node T_193021 = not(isZeroA_PA)
    node T_193022 = and(T_193020, T_193021)
    node T_193023 = not(isZeroB_PA)
    node T_193024 = and(T_193022, T_193023)
    wire normalCase_PA : UInt<1>
    normalCase_PA := T_193024
    when sqrtOp_PA : normalCase_PA := T_193017
    node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt)
    wire valid_leaving_PA : UInt<1>
    valid_leaving_PA := ready_PB
    when normalCase_PA : valid_leaving_PA := valid_normalCase_leaving_PA
    node T_193025 = and(valid_PA, valid_leaving_PA)
    leaving_PA := T_193025
    node T_193026 = not(valid_PA)
    node T_193027 = or(T_193026, valid_leaving_PA)
    ready_PA := T_193027
    node T_193028 = and(valid_PA, normalCase_PA)
    node entering_PB_normalCase = and(T_193028, valid_normalCase_leaving_PA)
    node entering_PB = or(entering_PB_S, leaving_PA)
    
    node T_193029 = or(entering_PB, leaving_PB)
    when T_193029 : valid_PB := entering_PB
    when entering_PB : 
      wire T_193030 : UInt<1>
      T_193030 := sqrtOp
      when valid_PA : T_193030 := sqrtOp_PA
      sqrtOp_PB := T_193030
      wire T_193031 : UInt<1>
      T_193031 := sign_S
      when valid_PA : T_193031 := sign_PA
      sign_PB := T_193031
      wire T_193032 : UInt<3>
      T_193032 := specialCodeA_S
      when valid_PA : T_193032 := specialCodeA_PA
      specialCodeA_PB := T_193032
      node T_193033 = bit(fractA_S, 51)
      wire T_193034 : UInt<1>
      T_193034 := T_193033
      when valid_PA : T_193034 := fractA_51_PA
      fractA_51_PB := T_193034
      wire T_193035 : UInt<3>
      T_193035 := specialCodeB_S
      when valid_PA : T_193035 := specialCodeB_PA
      specialCodeB_PB := T_193035
      node T_193036 = bit(fractB_S, 51)
      wire T_193037 : UInt<1>
      T_193037 := T_193036
      when valid_PA : T_193037 := fractB_51_PA
      fractB_51_PB := T_193037
      wire T_193038 : UInt<2>
      T_193038 := roundingMode
      when valid_PA : T_193038 := roundingMode_PA
      roundingMode_PB := T_193038
    when entering_PB_normalCase : 
      exp_PB := exp_PA
      node T_193039 = bit(fractA_other_PA, 0)
      fractA_0_PB := T_193039
      fractB_other_PB := fractB_other_PA
    node isZeroA_PB = eq(specialCodeA_PB, UInt<3>(0))
    node T_193040 = bits(specialCodeA_PB, 2, 1)
    node isSpecialA_PB = eq(T_193040, UInt<2>(3))
    node isZeroB_PB = eq(specialCodeB_PB, UInt<3>(0))
    node T_193041 = bits(specialCodeB_PB, 2, 1)
    node isSpecialB_PB = eq(T_193041, UInt<2>(3))
    node T_193042 = not(isSpecialB_PB)
    node T_193043 = not(isZeroB_PB)
    node T_193044 = and(T_193042, T_193043)
    node T_193045 = not(sign_PB)
    node T_193046 = and(T_193044, T_193045)
    node T_193047 = not(isSpecialA_PB)
    node T_193048 = not(isSpecialB_PB)
    node T_193049 = and(T_193047, T_193048)
    node T_193050 = not(isZeroA_PB)
    node T_193051 = and(T_193049, T_193050)
    node T_193052 = not(isZeroB_PB)
    node T_193053 = and(T_193051, T_193052)
    wire normalCase_PB : UInt<1>
    normalCase_PB := T_193053
    when sqrtOp_PB : normalCase_PB := T_193046
    wire valid_leaving_PB : UInt<1>
    valid_leaving_PB := ready_PC
    when normalCase_PB : valid_leaving_PB := cyc_C3
    node T_193054 = and(valid_PB, valid_leaving_PB)
    leaving_PB := T_193054
    node T_193055 = not(valid_PB)
    node T_193056 = or(T_193055, valid_leaving_PB)
    ready_PB := T_193056
    node T_193057 = and(valid_PB, normalCase_PB)
    node entering_PC_normalCase = and(T_193057, cyc_C3)
    node entering_PC = or(entering_PC_S, leaving_PB)
    
    node T_193058 = or(entering_PC, leaving_PC)
    when T_193058 : valid_PC := entering_PC
    when entering_PC : 
      wire T_193059 : UInt<1>
      T_193059 := sqrtOp
      when valid_PB : T_193059 := sqrtOp_PB
      sqrtOp_PC := T_193059
      wire T_193060 : UInt<1>
      T_193060 := sign_S
      when valid_PB : T_193060 := sign_PB
      sign_PC := T_193060
      wire T_193061 : UInt<3>
      T_193061 := specialCodeA_S
      when valid_PB : T_193061 := specialCodeA_PB
      specialCodeA_PC := T_193061
      node T_193062 = bit(fractA_S, 51)
      wire T_193063 : UInt<1>
      T_193063 := T_193062
      when valid_PB : T_193063 := fractA_51_PB
      fractA_51_PC := T_193063
      wire T_193064 : UInt<3>
      T_193064 := specialCodeB_S
      when valid_PB : T_193064 := specialCodeB_PB
      specialCodeB_PC := T_193064
      node T_193065 = bit(fractB_S, 51)
      wire T_193066 : UInt<1>
      T_193066 := T_193065
      when valid_PB : T_193066 := fractB_51_PB
      fractB_51_PC := T_193066
      wire T_193067 : UInt<2>
      T_193067 := roundingMode
      when valid_PB : T_193067 := roundingMode_PB
      roundingMode_PC := T_193067
    when entering_PC_normalCase : 
      exp_PC := exp_PB
      fractA_0_PC := fractA_0_PB
      fractB_other_PC := fractB_other_PB
    node isZeroA_PC = eq(specialCodeA_PC, UInt<3>(0))
    node T_193068 = bits(specialCodeA_PC, 2, 1)
    node isSpecialA_PC = eq(T_193068, UInt<2>(3))
    node T_193069 = bit(specialCodeA_PC, 0)
    node T_193070 = not(T_193069)
    node isInfA_PC = and(isSpecialA_PC, T_193070)
    node T_193071 = bit(specialCodeA_PC, 0)
    node isNaNA_PC = and(isSpecialA_PC, T_193071)
    node T_193072 = not(fractA_51_PC)
    node isSigNaNA_PC = and(isNaNA_PC, T_193072)
    node isZeroB_PC = eq(specialCodeB_PC, UInt<3>(0))
    node T_193073 = bits(specialCodeB_PC, 2, 1)
    node isSpecialB_PC = eq(T_193073, UInt<2>(3))
    node T_193074 = bit(specialCodeB_PC, 0)
    node T_193075 = not(T_193074)
    node isInfB_PC = and(isSpecialB_PC, T_193075)
    node T_193076 = bit(specialCodeB_PC, 0)
    node isNaNB_PC = and(isSpecialB_PC, T_193076)
    node T_193077 = not(fractB_51_PC)
    node isSigNaNB_PC = and(isNaNB_PC, T_193077)
    node T_193078 = cat(fractB_51_PC, fractB_other_PC)
    node sigB_PC = cat(UInt<1>(1), T_193078)
    node T_193079 = not(isSpecialB_PC)
    node T_193080 = not(isZeroB_PC)
    node T_193081 = and(T_193079, T_193080)
    node T_193082 = not(sign_PC)
    node T_193083 = and(T_193081, T_193082)
    node T_193084 = not(isSpecialA_PC)
    node T_193085 = not(isSpecialB_PC)
    node T_193086 = and(T_193084, T_193085)
    node T_193087 = not(isZeroA_PC)
    node T_193088 = and(T_193086, T_193087)
    node T_193089 = not(isZeroB_PC)
    node T_193090 = and(T_193088, T_193089)
    wire normalCase_PC : UInt<1>
    normalCase_PC := T_193090
    when sqrtOp_PC : normalCase_PC := T_193083
    node expP2_PC = addw(exp_PC, UInt<2>(2))
    node T_193091 = bit(exp_PC, 0)
    node T_193092 = bits(expP2_PC, 13, 1)
    node T_193093 = cat(T_193092, UInt<1>(0))
    node T_193094 = bits(exp_PC, 13, 1)
    node T_193095 = cat(T_193094, UInt<1>(1))
    wire expP1_PC : UInt<14>
    expP1_PC := T_193095
    when T_193091 : expP1_PC := T_193093
    node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>(0))
    node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>(1))
    node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>(2))
    node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>(3))
    wire roundMagUp_PC : UInt<1>
    roundMagUp_PC := roundingMode_max_PC
    when sign_PC : roundMagUp_PC := roundingMode_min_PC
    node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC)
    node T_193096 = not(roundMagUp_PC)
    node T_193097 = not(roundingMode_near_even_PC)
    node roundMagDown_PC = and(T_193096, T_193097)
    node T_193098 = not(normalCase_PC)
    node valid_leaving_PC = or(T_193098, cyc_E1)
    node T_193099 = and(valid_PC, valid_leaving_PC)
    leaving_PC := T_193099
    node T_193100 = not(valid_PC)
    node T_193101 = or(T_193100, valid_leaving_PC)
    ready_PC := T_193101
    node T_193102 = not(sqrtOp_PC)
    node T_193103 = and(leaving_PC, T_193102)
    outValid_div := T_193103
    node T_193104 = and(leaving_PC, sqrtOp_PC)
    outValid_sqrt := T_193104
    
    
    node T_193105 = neq(cycleNum_A, UInt<1>(0))
    node T_193106 = or(entering_PA_normalCase, T_193105)
    when T_193106 : 
      wire T_193107 : UInt<1>
      T_193107 := UInt<1>(0)
      when cyc_A4_div : T_193107 := UInt<2>(3)
      wire T_193108 : UInt<1>
      T_193108 := UInt<1>(0)
      when cyc_A7_sqrt : T_193108 := UInt<3>(6)
      node T_193109 = or(T_193107, T_193108)
      node T_193110 = not(entering_PA_normalCase)
      node T_193111 = subw(cycleNum_A, UInt<1>(1))
      wire T_193112 : UInt<1>
      T_193112 := UInt<1>(0)
      when T_193110 : T_193112 := T_193111
      node T_193113 = or(T_193109, T_193112)
      cycleNum_A := T_193113
    node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>(6))
    node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>(5))
    node cyc_A4_sqrt = eq(cycleNum_A, UInt<3>(4))
    node cyc_A4 = or(cyc_A4_sqrt, cyc_A4_div)
    node cyc_A3 = eq(cycleNum_A, UInt<2>(3))
    node cyc_A2 = eq(cycleNum_A, UInt<2>(2))
    node cyc_A1 = eq(cycleNum_A, UInt<1>(1))
    node T_193114 = not(sqrtOp_PA)
    node cyc_A3_div = and(cyc_A3, T_193114)
    node T_193115 = not(sqrtOp_PA)
    node cyc_A2_div = and(cyc_A2, T_193115)
    node T_193116 = not(sqrtOp_PA)
    node cyc_A1_div = and(cyc_A1, T_193116)
    node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA)
    node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA)
    node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA)
    
    
    node T_193117 = neq(cycleNum_B, UInt<1>(0))
    node T_193118 = or(cyc_A1, T_193117)
    when T_193118 : 
      wire T_193119 : UInt<3>
      T_193119 := UInt<3>(6)
      when sqrtOp_PA : T_193119 := UInt<4>(10)
      node T_193120 = subw(cycleNum_B, UInt<1>(1))
      wire T_193121 : UInt<4>
      T_193121 := T_193120
      when cyc_A1 : T_193121 := T_193119
      cycleNum_B := T_193121
    node T_193122 = eq(cycleNum_B, UInt<4>(10))
    cyc_B10_sqrt := T_193122
    node T_193123 = eq(cycleNum_B, UInt<4>(9))
    cyc_B9_sqrt := T_193123
    node T_193124 = eq(cycleNum_B, UInt<4>(8))
    cyc_B8_sqrt := T_193124
    node T_193125 = eq(cycleNum_B, UInt<3>(7))
    cyc_B7_sqrt := T_193125
    node T_193126 = eq(cycleNum_B, UInt<3>(6))
    cyc_B6 := T_193126
    node T_193127 = eq(cycleNum_B, UInt<3>(5))
    cyc_B5 := T_193127
    node T_193128 = eq(cycleNum_B, UInt<3>(4))
    cyc_B4 := T_193128
    node T_193129 = eq(cycleNum_B, UInt<2>(3))
    cyc_B3 := T_193129
    node T_193130 = eq(cycleNum_B, UInt<2>(2))
    cyc_B2 := T_193130
    node T_193131 = eq(cycleNum_B, UInt<1>(1))
    cyc_B1 := T_193131
    node T_193132 = and(cyc_B6, valid_PA)
    node T_193133 = not(sqrtOp_PA)
    node T_193134 = and(T_193132, T_193133)
    cyc_B6_div := T_193134
    node T_193135 = and(cyc_B5, valid_PA)
    node T_193136 = not(sqrtOp_PA)
    node T_193137 = and(T_193135, T_193136)
    cyc_B5_div := T_193137
    node T_193138 = and(cyc_B4, valid_PA)
    node T_193139 = not(sqrtOp_PA)
    node T_193140 = and(T_193138, T_193139)
    cyc_B4_div := T_193140
    node T_193141 = not(sqrtOp_PB)
    node T_193142 = and(cyc_B3, T_193141)
    cyc_B3_div := T_193142
    node T_193143 = not(sqrtOp_PB)
    node T_193144 = and(cyc_B2, T_193143)
    cyc_B2_div := T_193144
    node T_193145 = not(sqrtOp_PB)
    node T_193146 = and(cyc_B1, T_193145)
    cyc_B1_div := T_193146
    node T_193147 = and(cyc_B6, valid_PB)
    node T_193148 = and(T_193147, sqrtOp_PB)
    cyc_B6_sqrt := T_193148
    node T_193149 = and(cyc_B5, valid_PB)
    node T_193150 = and(T_193149, sqrtOp_PB)
    cyc_B5_sqrt := T_193150
    node T_193151 = and(cyc_B4, valid_PB)
    node T_193152 = and(T_193151, sqrtOp_PB)
    cyc_B4_sqrt := T_193152
    node T_193153 = and(cyc_B3, sqrtOp_PB)
    cyc_B3_sqrt := T_193153
    node T_193154 = and(cyc_B2, sqrtOp_PB)
    cyc_B2_sqrt := T_193154
    node T_193155 = and(cyc_B1, sqrtOp_PB)
    cyc_B1_sqrt := T_193155
    
    
    node T_193156 = neq(cycleNum_C, UInt<1>(0))
    node T_193157 = or(cyc_B1, T_193156)
    when T_193157 : 
      wire T_193158 : UInt<3>
      T_193158 := UInt<3>(5)
      when sqrtOp_PB : T_193158 := UInt<3>(6)
      node T_193159 = subw(cycleNum_C, UInt<1>(1))
      wire T_193160 : UInt<3>
      T_193160 := T_193159
      when cyc_B1 : T_193160 := T_193158
      cycleNum_C := T_193160
    node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>(6))
    node T_193161 = eq(cycleNum_C, UInt<3>(5))
    cyc_C5 := T_193161
    node T_193162 = eq(cycleNum_C, UInt<3>(4))
    cyc_C4 := T_193162
    node T_193163 = eq(cycleNum_C, UInt<2>(3))
    cyc_C3 := T_193163
    node T_193164 = eq(cycleNum_C, UInt<2>(2))
    cyc_C2 := T_193164
    node T_193165 = eq(cycleNum_C, UInt<1>(1))
    cyc_C1 := T_193165
    node T_193166 = not(sqrtOp_PB)
    node cyc_C5_div = and(cyc_C5, T_193166)
    node T_193167 = not(sqrtOp_PB)
    node cyc_C4_div = and(cyc_C4, T_193167)
    node T_193168 = not(sqrtOp_PB)
    node cyc_C3_div = and(cyc_C3, T_193168)
    node T_193169 = not(sqrtOp_PC)
    node cyc_C2_div = and(cyc_C2, T_193169)
    node T_193170 = not(sqrtOp_PC)
    node cyc_C1_div = and(cyc_C1, T_193170)
    node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB)
    node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB)
    node cyc_C3_sqrt = and(cyc_C3, sqrtOp_PB)
    node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC)
    node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC)
    
    
    node T_193171 = neq(cycleNum_E, UInt<1>(0))
    node T_193172 = or(cyc_C1, T_193171)
    when T_193172 : 
      node T_193173 = subw(cycleNum_E, UInt<1>(1))
      wire T_193174 : UInt<3>
      T_193174 := T_193173
      when cyc_C1 : T_193174 := UInt<3>(4)
      cycleNum_E := T_193174
    node T_193175 = eq(cycleNum_E, UInt<3>(4))
    cyc_E4 := T_193175
    node T_193176 = eq(cycleNum_E, UInt<2>(3))
    cyc_E3 := T_193176
    node T_193177 = eq(cycleNum_E, UInt<2>(2))
    cyc_E2 := T_193177
    node T_193178 = eq(cycleNum_E, UInt<1>(1))
    cyc_E1 := T_193178
    node T_193179 = not(sqrtOp_PC)
    node cyc_E4_div = and(cyc_E4, T_193179)
    node T_193180 = not(sqrtOp_PC)
    node cyc_E3_div = and(cyc_E3, T_193180)
    node T_193181 = not(sqrtOp_PC)
    node cyc_E2_div = and(cyc_E2, T_193181)
    node T_193182 = not(sqrtOp_PC)
    node cyc_E1_div = and(cyc_E1, T_193182)
    node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC)
    node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC)
    node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC)
    node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC)
    wire zFractB_A4_div : UInt<1>
    zFractB_A4_div := UInt<1>(0)
    when cyc_A4_div : zFractB_A4_div := fractB_S
    node T_193183 = bits(fractB_S, 51, 49)
    node T_193184 = eq(T_193183, UInt<1>(0))
    node zLinPiece_0_A4_div = and(cyc_A4_div, T_193184)
    node T_193185 = bits(fractB_S, 51, 49)
    node T_193186 = eq(T_193185, UInt<1>(1))
    node zLinPiece_1_A4_div = and(cyc_A4_div, T_193186)
    node T_193187 = bits(fractB_S, 51, 49)
    node T_193188 = eq(T_193187, UInt<2>(2))
    node zLinPiece_2_A4_div = and(cyc_A4_div, T_193188)
    node T_193189 = bits(fractB_S, 51, 49)
    node T_193190 = eq(T_193189, UInt<2>(3))
    node zLinPiece_3_A4_div = and(cyc_A4_div, T_193190)
    node T_193191 = bits(fractB_S, 51, 49)
    node T_193192 = eq(T_193191, UInt<3>(4))
    node zLinPiece_4_A4_div = and(cyc_A4_div, T_193192)
    node T_193193 = bits(fractB_S, 51, 49)
    node T_193194 = eq(T_193193, UInt<3>(5))
    node zLinPiece_5_A4_div = and(cyc_A4_div, T_193194)
    node T_193195 = bits(fractB_S, 51, 49)
    node T_193196 = eq(T_193195, UInt<3>(6))
    node zLinPiece_6_A4_div = and(cyc_A4_div, T_193196)
    node T_193197 = bits(fractB_S, 51, 49)
    node T_193198 = eq(T_193197, UInt<3>(7))
    node zLinPiece_7_A4_div = and(cyc_A4_div, T_193198)
    wire T_193199 : UInt<1>
    T_193199 := UInt<1>(0)
    when zLinPiece_0_A4_div : T_193199 := UInt<9>(455)
    wire T_193200 : UInt<1>
    T_193200 := UInt<1>(0)
    when zLinPiece_1_A4_div : T_193200 := UInt<9>(364)
    node T_193201 = or(T_193199, T_193200)
    wire T_193202 : UInt<1>
    T_193202 := UInt<1>(0)
    when zLinPiece_2_A4_div : T_193202 := UInt<9>(298)
    node T_193203 = or(T_193201, T_193202)
    wire T_193204 : UInt<1>
    T_193204 := UInt<1>(0)
    when zLinPiece_3_A4_div : T_193204 := UInt<9>(248)
    node T_193205 = or(T_193203, T_193204)
    wire T_193206 : UInt<1>
    T_193206 := UInt<1>(0)
    when zLinPiece_4_A4_div : T_193206 := UInt<9>(210)
    node T_193207 = or(T_193205, T_193206)
    wire T_193208 : UInt<1>
    T_193208 := UInt<1>(0)
    when zLinPiece_5_A4_div : T_193208 := UInt<9>(180)
    node T_193209 = or(T_193207, T_193208)
    wire T_193210 : UInt<1>
    T_193210 := UInt<1>(0)
    when zLinPiece_6_A4_div : T_193210 := UInt<9>(156)
    node T_193211 = or(T_193209, T_193210)
    wire T_193212 : UInt<1>
    T_193212 := UInt<1>(0)
    when zLinPiece_7_A4_div : T_193212 := UInt<9>(137)
    node zK1_A4_div = or(T_193211, T_193212)
    node T_193213 = not(UInt<12>(4067))
    wire T_193214 : UInt<1>
    T_193214 := UInt<1>(0)
    when zLinPiece_0_A4_div : T_193214 := T_193213
    node T_193215 = not(UInt<12>(3165))
    wire T_193216 : UInt<1>
    T_193216 := UInt<1>(0)
    when zLinPiece_1_A4_div : T_193216 := T_193215
    node T_193217 = or(T_193214, T_193216)
    node T_193218 = not(UInt<12>(2442))
    wire T_193219 : UInt<1>
    T_193219 := UInt<1>(0)
    when zLinPiece_2_A4_div : T_193219 := T_193218
    node T_193220 = or(T_193217, T_193219)
    node T_193221 = not(UInt<12>(1849))
    wire T_193222 : UInt<1>
    T_193222 := UInt<1>(0)
    when zLinPiece_3_A4_div : T_193222 := T_193221
    node T_193223 = or(T_193220, T_193222)
    node T_193224 = not(UInt<12>(1355))
    wire T_193225 : UInt<1>
    T_193225 := UInt<1>(0)
    when zLinPiece_4_A4_div : T_193225 := T_193224
    node T_193226 = or(T_193223, T_193225)
    node T_193227 = not(UInt<12>(937))
    wire T_193228 : UInt<1>
    T_193228 := UInt<1>(0)
    when zLinPiece_5_A4_div : T_193228 := T_193227
    node T_193229 = or(T_193226, T_193228)
    node T_193230 = not(UInt<12>(578))
    wire T_193231 : UInt<1>
    T_193231 := UInt<1>(0)
    when zLinPiece_6_A4_div : T_193231 := T_193230
    node T_193232 = or(T_193229, T_193231)
    node T_193233 = not(UInt<12>(267))
    wire T_193234 : UInt<1>
    T_193234 := UInt<1>(0)
    when zLinPiece_7_A4_div : T_193234 := T_193233
    node zComplFractK0_A4_div = or(T_193232, T_193234)
    wire zFractB_A7_sqrt : UInt<1>
    zFractB_A7_sqrt := UInt<1>(0)
    when cyc_A7_sqrt : zFractB_A7_sqrt := fractB_S
    node T_193235 = bit(expB_S, 0)
    node T_193236 = not(T_193235)
    node T_193237 = and(cyc_A7_sqrt, T_193236)
    node T_193238 = bit(fractB_S, 51)
    node T_193239 = not(T_193238)
    node zQuadPiece_0_A7_sqrt = and(T_193237, T_193239)
    node T_193240 = bit(expB_S, 0)
    node T_193241 = not(T_193240)
    node T_193242 = and(cyc_A7_sqrt, T_193241)
    node T_193243 = bit(fractB_S, 51)
    node zQuadPiece_1_A7_sqrt = and(T_193242, T_193243)
    node T_193244 = bit(expB_S, 0)
    node T_193245 = and(cyc_A7_sqrt, T_193244)
    node T_193246 = bit(fractB_S, 51)
    node T_193247 = not(T_193246)
    node zQuadPiece_2_A7_sqrt = and(T_193245, T_193247)
    node T_193248 = bit(expB_S, 0)
    node T_193249 = and(cyc_A7_sqrt, T_193248)
    node T_193250 = bit(fractB_S, 51)
    node zQuadPiece_3_A7_sqrt = and(T_193249, T_193250)
    wire T_193251 : UInt<1>
    T_193251 := UInt<1>(0)
    when zQuadPiece_0_A7_sqrt : T_193251 := UInt<9>(456)
    wire T_193252 : UInt<1>
    T_193252 := UInt<1>(0)
    when zQuadPiece_1_A7_sqrt : T_193252 := UInt<9>(193)
    node T_193253 = or(T_193251, T_193252)
    wire T_193254 : UInt<1>
    T_193254 := UInt<1>(0)
    when zQuadPiece_2_A7_sqrt : T_193254 := UInt<9>(323)
    node T_193255 = or(T_193253, T_193254)
    wire T_193256 : UInt<1>
    T_193256 := UInt<1>(0)
    when zQuadPiece_3_A7_sqrt : T_193256 := UInt<9>(137)
    node zK2_A7_sqrt = or(T_193255, T_193256)
    node T_193257 = not(UInt<10>(976))
    wire T_193258 : UInt<1>
    T_193258 := UInt<1>(0)
    when zQuadPiece_0_A7_sqrt : T_193258 := T_193257
    node T_193259 = not(UInt<10>(544))
    wire T_193260 : UInt<1>
    T_193260 := UInt<1>(0)
    when zQuadPiece_1_A7_sqrt : T_193260 := T_193259
    node T_193261 = or(T_193258, T_193260)
    node T_193262 = not(UInt<10>(690))
    wire T_193263 : UInt<1>
    T_193263 := UInt<1>(0)
    when zQuadPiece_2_A7_sqrt : T_193263 := T_193262
    node T_193264 = or(T_193261, T_193263)
    node T_193265 = not(UInt<10>(385))
    wire T_193266 : UInt<1>
    T_193266 := UInt<1>(0)
    when zQuadPiece_3_A7_sqrt : T_193266 := T_193265
    node zComplK1_A7_sqrt = or(T_193264, T_193266)
    node T_193267 = bit(exp_PA, 0)
    node T_193268 = not(T_193267)
    node T_193269 = and(cyc_A6_sqrt, T_193268)
    node T_193270 = bit(sigB_PA, 51)
    node T_193271 = not(T_193270)
    node zQuadPiece_0_A6_sqrt = and(T_193269, T_193271)
    node T_193272 = bit(exp_PA, 0)
    node T_193273 = not(T_193272)
    node T_193274 = and(cyc_A6_sqrt, T_193273)
    node T_193275 = bit(sigB_PA, 51)
    node zQuadPiece_1_A6_sqrt = and(T_193274, T_193275)
    node T_193276 = bit(exp_PA, 0)
    node T_193277 = and(cyc_A6_sqrt, T_193276)
    node T_193278 = bit(sigB_PA, 51)
    node T_193279 = not(T_193278)
    node zQuadPiece_2_A6_sqrt = and(T_193277, T_193279)
    node T_193280 = bit(exp_PA, 0)
    node T_193281 = and(cyc_A6_sqrt, T_193280)
    node T_193282 = bit(sigB_PA, 51)
    node zQuadPiece_3_A6_sqrt = and(T_193281, T_193282)
    node T_193283 = not(UInt<13>(8165))
    wire T_193284 : UInt<1>
    T_193284 := UInt<1>(0)
    when zQuadPiece_0_A6_sqrt : T_193284 := T_193283
    node T_193285 = not(UInt<13>(5173))
    wire T_193286 : UInt<1>
    T_193286 := UInt<1>(0)
    when zQuadPiece_1_A6_sqrt : T_193286 := T_193285
    node T_193287 = or(T_193284, T_193286)
    node T_193288 = not(UInt<13>(3372))
    wire T_193289 : UInt<1>
    T_193289 := UInt<1>(0)
    when zQuadPiece_2_A6_sqrt : T_193289 := T_193288
    node T_193290 = or(T_193287, T_193289)
    node T_193291 = not(UInt<13>(1256))
    wire T_193292 : UInt<1>
    T_193292 := UInt<1>(0)
    when zQuadPiece_3_A6_sqrt : T_193292 := T_193291
    node zComplFractK0_A6_sqrt = or(T_193290, T_193292)
    node T_193293 = bits(zFractB_A4_div, 48, 40)
    node T_193294 = or(T_193293, zK2_A7_sqrt)
    node T_193295 = not(cyc_S)
    wire T_193296 : UInt<1>
    T_193296 := UInt<1>(0)
    when T_193295 : T_193296 := nextMulAdd9A_A
    node mulAdd9A_A = or(T_193294, T_193296)
    node T_193297 = bits(zFractB_A7_sqrt, 50, 42)
    node T_193298 = or(zK1_A4_div, T_193297)
    node T_193299 = not(cyc_S)
    wire T_193300 : UInt<1>
    T_193300 := UInt<1>(0)
    when T_193299 : T_193300 := nextMulAdd9B_A
    node mulAdd9B_A = or(T_193298, T_193300)
    node T_193301 = shl(zComplK1_A7_sqrt, 10)
    node T_193302 = subw(UInt<6>(0), UInt<3>(6))
    node T_193303 = cat(zComplFractK0_A6_sqrt, T_193302)
    node T_193304 = cat(cyc_A6_sqrt, T_193303)
    node T_193305 = or(T_193301, T_193304)
    node T_193306 = subw(UInt<8>(0), UInt<4>(8))
    node T_193307 = cat(zComplFractK0_A4_div, T_193306)
    node T_193308 = cat(cyc_A4_div, T_193307)
    node T_193309 = or(T_193305, T_193308)
    node T_193310 = shl(fractR0_A, 10)
    node T_193311 = addw(UInt<20>(262144), T_193310)
    wire T_193312 : UInt<1>
    T_193312 := UInt<1>(0)
    when cyc_A5_sqrt : T_193312 := T_193311
    node T_193313 = or(T_193309, T_193312)
    node T_193314 = bit(hiSqrR0_A_sqrt, 9)
    node T_193315 = not(T_193314)
    node T_193316 = and(cyc_A4_sqrt, T_193315)
    wire T_193317 : UInt<1>
    T_193317 := UInt<1>(0)
    when T_193316 : T_193317 := UInt<11>(1024)
    node T_193318 = or(T_193313, T_193317)
    node T_193319 = bit(hiSqrR0_A_sqrt, 9)
    node T_193320 = and(cyc_A4_sqrt, T_193319)
    node T_193321 = or(T_193320, cyc_A3_div)
    node T_193322 = bits(sigB_PA, 46, 26)
    node T_193323 = addw(T_193322, UInt<11>(1024))
    wire T_193324 : UInt<1>
    T_193324 := UInt<1>(0)
    when T_193321 : T_193324 := T_193323
    node T_193325 = or(T_193318, T_193324)
    node T_193326 = or(cyc_A3_sqrt, cyc_A2)
    wire T_193327 : UInt<1>
    T_193327 := UInt<1>(0)
    when T_193326 : T_193327 := partNegSigma0_A
    node T_193328 = or(T_193325, T_193327)
    node T_193329 = shl(fractR0_A, 16)
    wire T_193330 : UInt<1>
    T_193330 := UInt<1>(0)
    when cyc_A1_sqrt : T_193330 := T_193329
    node T_193331 = or(T_193328, T_193330)
    node T_193332 = shl(fractR0_A, 15)
    wire T_193333 : UInt<1>
    T_193333 := UInt<1>(0)
    when cyc_A1_div : T_193333 := T_193332
    node mulAdd9C_A = or(T_193331, T_193333)
    node T_193334 = mul(mulAdd9A_A, mulAdd9B_A)
    node T_193335 = bits(mulAdd9C_A, 17, 0)
    node T_193336 = cat(UInt<1>(0), T_193335)
    node loMulAdd9Out_A = addw(T_193334, T_193336)
    node T_193337 = bit(loMulAdd9Out_A, 18)
    node T_193338 = bits(mulAdd9C_A, 24, 18)
    node T_193339 = addw(T_193338, UInt<1>(1))
    node T_193340 = bits(mulAdd9C_A, 24, 18)
    wire T_193341 : UInt<7>
    T_193341 := T_193340
    when T_193337 : T_193341 := T_193339
    node T_193342 = bits(loMulAdd9Out_A, 17, 0)
    node mulAdd9Out_A = cat(T_193341, T_193342)
    node T_193343 = bit(mulAdd9Out_A, 19)
    node T_193344 = and(cyc_A6_sqrt, T_193343)
    node T_193345 = not(mulAdd9Out_A)
    node T_193346 = shr(T_193345, 10)
    wire T_193347 : UInt<1>
    T_193347 := UInt<1>(0)
    when T_193344 : T_193347 := T_193346
    node zFractR0_A6_sqrt = bits(T_193347, 8, 0)
    node T_193348 = bit(exp_PA, 0)
    node T_193349 = shl(mulAdd9Out_A, 1)
    wire sqrR0_A5_sqrt : UInt<25>
    sqrR0_A5_sqrt := mulAdd9Out_A
    when T_193348 : sqrR0_A5_sqrt := T_193349
    node T_193350 = bit(mulAdd9Out_A, 20)
    node T_193351 = and(cyc_A4_div, T_193350)
    node T_193352 = not(mulAdd9Out_A)
    node T_193353 = shr(T_193352, 11)
    wire T_193354 : UInt<1>
    T_193354 := UInt<1>(0)
    when T_193351 : T_193354 := T_193353
    node zFractR0_A4_div = bits(T_193354, 8, 0)
    node T_193355 = bit(mulAdd9Out_A, 11)
    node T_193356 = and(cyc_A2, T_193355)
    node T_193357 = not(mulAdd9Out_A)
    node T_193358 = shr(T_193357, 2)
    wire T_193359 : UInt<1>
    T_193359 := UInt<1>(0)
    when T_193356 : T_193359 := T_193358
    node zSigma0_A2 = bits(T_193359, 8, 0)
    node T_193360 = shr(mulAdd9Out_A, 10)
    node T_193361 = shr(mulAdd9Out_A, 9)
    wire T_193362 : UInt<16>
    T_193362 := T_193361
    when sqrtOp_PA : T_193362 := T_193360
    node fractR1_A1 = bits(T_193362, 14, 0)
    node r1_A1 = cat(UInt<1>(1), fractR1_A1)
    node T_193363 = bit(exp_PA, 0)
    node T_193364 = shl(r1_A1, 1)
    wire ER1_A1_sqrt : UInt<16>
    ER1_A1_sqrt := r1_A1
    when T_193363 : ER1_A1_sqrt := T_193364
    
    node T_193365 = or(cyc_A6_sqrt, cyc_A4_div)
    when T_193365 : 
      node T_193366 = or(zFractR0_A6_sqrt, zFractR0_A4_div)
      fractR0_A := T_193366
    when cyc_A5_sqrt : 
      node T_193367 = shr(sqrR0_A5_sqrt, 10)
      hiSqrR0_A_sqrt := T_193367
    
    node T_193368 = or(cyc_A4_sqrt, cyc_A3)
    when T_193368 : 
      node T_193369 = shr(mulAdd9Out_A, 9)
      wire T_193370 : UInt<16>
      T_193370 := T_193369
      when cyc_A4_sqrt : T_193370 := mulAdd9Out_A
      node T_193371 = bits(T_193370, 20, 0)
      partNegSigma0_A := T_193371
    
    
    node T_193372 = or(cyc_A7_sqrt, cyc_A6_sqrt)
    node T_193373 = or(T_193372, cyc_A5_sqrt)
    node T_193374 = or(T_193373, cyc_A4)
    node T_193375 = or(T_193374, cyc_A3)
    node T_193376 = or(T_193375, cyc_A2)
    when T_193376 : 
      node T_193377 = not(mulAdd9Out_A)
      node T_193378 = shr(T_193377, 11)
      wire T_193379 : UInt<1>
      T_193379 := UInt<1>(0)
      when cyc_A7_sqrt : T_193379 := T_193378
      node T_193380 = or(T_193379, zFractR0_A6_sqrt)
      node T_193381 = bits(sigB_PA, 43, 35)
      wire T_193382 : UInt<1>
      T_193382 := UInt<1>(0)
      when cyc_A4_sqrt : T_193382 := T_193381
      node T_193383 = or(T_193380, T_193382)
      node T_193384 = bits(zFractB_A4_div, 43, 35)
      node T_193385 = or(T_193383, T_193384)
      node T_193386 = or(cyc_A5_sqrt, cyc_A3)
      node T_193387 = bits(sigB_PA, 52, 44)
      wire T_193388 : UInt<1>
      T_193388 := UInt<1>(0)
      when T_193386 : T_193388 := T_193387
      node T_193389 = or(T_193385, T_193388)
      node T_193390 = or(T_193389, zSigma0_A2)
      nextMulAdd9A_A := T_193390
    
    
    node T_193391 = or(cyc_A7_sqrt, cyc_A6_sqrt)
    node T_193392 = or(T_193391, cyc_A5_sqrt)
    node T_193393 = or(T_193392, cyc_A4)
    node T_193394 = or(T_193393, cyc_A2)
    when T_193394 : 
      node T_193395 = bits(zFractB_A7_sqrt, 50, 42)
      node T_193396 = or(T_193395, zFractR0_A6_sqrt)
      node T_193397 = bits(sqrR0_A5_sqrt, 9, 1)
      wire T_193398 : UInt<1>
      T_193398 := UInt<1>(0)
      when cyc_A5_sqrt : T_193398 := T_193397
      node T_193399 = or(T_193396, T_193398)
      node T_193400 = or(T_193399, zFractR0_A4_div)
      node T_193401 = bits(hiSqrR0_A_sqrt, 8, 0)
      wire T_193402 : UInt<1>
      T_193402 := UInt<1>(0)
      when cyc_A4_sqrt : T_193402 := T_193401
      node T_193403 = or(T_193400, T_193402)
      node T_193404 = bits(fractR0_A, 8, 1)
      node T_193405 = cat(UInt<1>(1), T_193404)
      wire T_193406 : UInt<1>
      T_193406 := UInt<1>(0)
      when cyc_A2 : T_193406 := T_193405
      node T_193407 = or(T_193403, T_193406)
      nextMulAdd9B_A := T_193407
    when cyc_A1_sqrt : ER1_B_sqrt := ER1_A1_sqrt
    node T_193408 = or(cyc_A1, cyc_B7_sqrt)
    node T_193409 = or(T_193408, cyc_B6_div)
    node T_193410 = or(T_193409, cyc_B4)
    node T_193411 = or(T_193410, cyc_B3)
    node T_193412 = or(T_193411, cyc_C6_sqrt)
    node T_193413 = or(T_193412, cyc_C4)
    node T_193414 = or(T_193413, cyc_C1)
    latchMulAddA_0 := T_193414
    node T_193415 = shl(ER1_A1_sqrt, 36)
    wire T_193416 : UInt<1>
    T_193416 := UInt<1>(0)
    when cyc_A1_sqrt : T_193416 := T_193415
    node T_193417 = or(cyc_B7_sqrt, cyc_A1_div)
    wire T_193418 : UInt<1>
    T_193418 := UInt<1>(0)
    when T_193417 : T_193418 := sigB_PA
    node T_193419 = or(T_193416, T_193418)
    wire T_193420 : UInt<1>
    T_193420 := UInt<1>(0)
    when cyc_B6_div : T_193420 := sigA_PA
    node T_193421 = or(T_193419, T_193420)
    node T_193422 = bits(zSigma1_B4, 45, 12)
    node T_193423 = or(T_193421, T_193422)
    node T_193424 = or(cyc_B3, cyc_C6_sqrt)
    node T_193425 = bits(sigXNU_B3_CX, 57, 12)
    wire T_193426 : UInt<1>
    T_193426 := UInt<1>(0)
    when T_193424 : T_193426 := T_193425
    node T_193427 = or(T_193423, T_193426)
    node T_193428 = bits(sigXN_C, 57, 25)
    node T_193429 = shl(T_193428, 13)
    wire T_193430 : UInt<1>
    T_193430 := UInt<1>(0)
    when cyc_C4_div : T_193430 := T_193429
    node T_193431 = or(T_193427, T_193430)
    node T_193432 = shl(u_C_sqrt, 15)
    wire T_193433 : UInt<1>
    T_193433 := UInt<1>(0)
    when cyc_C4_sqrt : T_193433 := T_193432
    node T_193434 = or(T_193431, T_193433)
    wire T_193435 : UInt<1>
    T_193435 := UInt<1>(0)
    when cyc_C1_div : T_193435 := sigB_PC
    node T_193436 = or(T_193434, T_193435)
    node T_193437 = or(T_193436, zComplSigT_C1_sqrt)
    mulAddA_0 := T_193437
    node T_193438 = or(cyc_A1, cyc_B7_sqrt)
    node T_193439 = or(T_193438, cyc_B6_sqrt)
    node T_193440 = or(T_193439, cyc_B4)
    node T_193441 = or(T_193440, cyc_C6_sqrt)
    node T_193442 = or(T_193441, cyc_C4)
    node T_193443 = or(T_193442, cyc_C1)
    latchMulAddB_0 := T_193443
    node T_193444 = shl(r1_A1, 36)
    wire T_193445 : UInt<1>
    T_193445 := UInt<1>(0)
    when cyc_A1 : T_193445 := T_193444
    node T_193446 = shl(ESqrR1_B_sqrt, 19)
    wire T_193447 : UInt<1>
    T_193447 := UInt<1>(0)
    when cyc_B7_sqrt : T_193447 := T_193446
    node T_193448 = or(T_193445, T_193447)
    node T_193449 = shl(ER1_B_sqrt, 36)
    wire T_193450 : UInt<1>
    T_193450 := UInt<1>(0)
    when cyc_B6_sqrt : T_193450 := T_193449
    node T_193451 = or(T_193448, T_193450)
    node T_193452 = or(T_193451, zSigma1_B4)
    node T_193453 = bits(sqrSigma1_C, 30, 1)
    wire T_193454 : UInt<1>
    T_193454 := UInt<1>(0)
    when cyc_C6_sqrt : T_193454 := T_193453
    node T_193455 = or(T_193452, T_193454)
    wire T_193456 : UInt<1>
    T_193456 := UInt<1>(0)
    when cyc_C4 : T_193456 := sqrSigma1_C
    node T_193457 = or(T_193455, T_193456)
    node T_193458 = or(T_193457, zComplSigT_C1)
    mulAddB_0 := T_193458
    node T_193459 = or(cyc_A4, cyc_A3_div)
    node T_193460 = or(T_193459, cyc_A1_div)
    node T_193461 = or(T_193460, cyc_B10_sqrt)
    node T_193462 = or(T_193461, cyc_B9_sqrt)
    node T_193463 = or(T_193462, cyc_B7_sqrt)
    node T_193464 = or(T_193463, cyc_B6)
    node T_193465 = or(T_193464, cyc_B5_sqrt)
    node T_193466 = or(T_193465, cyc_B3_sqrt)
    node T_193467 = or(T_193466, cyc_B2_div)
    node T_193468 = or(T_193467, cyc_B1_sqrt)
    node T_193469 = or(T_193468, cyc_C4)
    node T_193470 = or(cyc_A3, cyc_A2_div)
    node T_193471 = or(T_193470, cyc_B9_sqrt)
    node T_193472 = or(T_193471, cyc_B8_sqrt)
    node T_193473 = or(T_193472, cyc_B6)
    node T_193474 = or(T_193473, cyc_B5)
    node T_193475 = or(T_193474, cyc_B4_sqrt)
    node T_193476 = or(T_193475, cyc_B2_sqrt)
    node T_193477 = or(T_193476, cyc_B1_div)
    node T_193478 = or(T_193477, cyc_C6_sqrt)
    node T_193479 = or(T_193478, cyc_C3)
    node T_193480 = or(cyc_A2, cyc_A1_div)
    node T_193481 = or(T_193480, cyc_B8_sqrt)
    node T_193482 = or(T_193481, cyc_B7_sqrt)
    node T_193483 = or(T_193482, cyc_B5)
    node T_193484 = or(T_193483, cyc_B4)
    node T_193485 = or(T_193484, cyc_B3_sqrt)
    node T_193486 = or(T_193485, cyc_B1_sqrt)
    node T_193487 = or(T_193486, cyc_C5)
    node T_193488 = or(T_193487, cyc_C2)
    node T_193489 = or(latchMulAddA_0, cyc_B6)
    node T_193490 = or(T_193489, cyc_B2_sqrt)
    node T_193491 = cat(T_193469, T_193479)
    node T_193492 = cat(T_193488, T_193490)
    node T_193493 = cat(T_193491, T_193492)
    usingMulAdd := T_193493
    node T_193494 = shl(sigX1_B, 47)
    wire T_193495 : UInt<1>
    T_193495 := UInt<1>(0)
    when cyc_B1 : T_193495 := T_193494
    node T_193496 = shl(sigX1_B, 46)
    wire T_193497 : UInt<1>
    T_193497 := UInt<1>(0)
    when cyc_C6_sqrt : T_193497 := T_193496
    node T_193498 = or(T_193495, T_193497)
    node T_193499 = or(cyc_C4_sqrt, cyc_C2)
    node T_193500 = shl(sigXN_C, 47)
    wire T_193501 : UInt<1>
    T_193501 := UInt<1>(0)
    when T_193499 : T_193501 := T_193500
    node T_193502 = or(T_193498, T_193501)
    node T_193503 = not(E_E_div)
    node T_193504 = and(cyc_E3_div, T_193503)
    node T_193505 = shl(fractA_0_PC, 53)
    wire T_193506 : UInt<1>
    T_193506 := UInt<1>(0)
    when T_193504 : T_193506 := T_193505
    node T_193507 = or(T_193502, T_193506)
    node T_193508 = bit(exp_PC, 0)
    node T_193509 = bit(sigB_PC, 0)
    node T_193510 = cat(T_193509, UInt<1>(0))
    node T_193511 = bit(sigB_PC, 1)
    node T_193512 = bit(sigB_PC, 0)
    node T_193513 = xor(T_193511, T_193512)
    node T_193514 = bit(sigB_PC, 0)
    node T_193515 = cat(T_193513, T_193514)
    wire T_193516 : UInt<2>
    T_193516 := T_193515
    when T_193508 : T_193516 := T_193510
    node T_193517 = not(extraT_E)
    node T_193518 = cat(T_193517, UInt<1>(0))
    node T_193519 = xor(T_193516, T_193518)
    node T_193520 = shl(T_193519, 54)
    wire T_193521 : UInt<1>
    T_193521 := UInt<1>(0)
    when cyc_E3_sqrt : T_193521 := T_193520
    node T_193522 = or(T_193507, T_193521)
    mulAddC_2 := T_193522
    node ESqrR1_B8_sqrt = bits(mulAddResult_3, 103, 72)
    node T_193523 = bits(mulAddResult_3, 90, 45)
    node T_193524 = not(T_193523)
    wire T_193525 : UInt<1>
    T_193525 := UInt<1>(0)
    when cyc_B4 : T_193525 := T_193524
    zSigma1_B4 := T_193525
    node sqrSigma1_B1 = bits(mulAddResult_3, 79, 47)
    node T_193526 = bits(mulAddResult_3, 104, 47)
    sigXNU_B3_CX := T_193526
    node T_193527 = bit(mulAddResult_3, 104)
    node E_C1_div = not(T_193527)
    node T_193528 = not(E_C1_div)
    node T_193529 = and(cyc_C1_div, T_193528)
    node T_193530 = or(T_193529, cyc_C1_sqrt)
    node T_193531 = bits(mulAddResult_3, 104, 51)
    node T_193532 = not(T_193531)
    wire T_193533 : UInt<1>
    T_193533 := UInt<1>(0)
    when T_193530 : T_193533 := T_193532
    node T_193534 = and(cyc_C1_div, E_C1_div)
    node T_193535 = bits(mulAddResult_3, 102, 50)
    node T_193536 = not(T_193535)
    node T_193537 = cat(UInt<1>(0), T_193536)
    wire T_193538 : UInt<1>
    T_193538 := UInt<1>(0)
    when T_193534 : T_193538 := T_193537
    node T_193539 = or(T_193533, T_193538)
    zComplSigT_C1 := T_193539
    node T_193540 = bits(mulAddResult_3, 104, 51)
    node T_193541 = not(T_193540)
    wire T_193542 : UInt<1>
    T_193542 := UInt<1>(0)
    when cyc_C1_sqrt : T_193542 := T_193541
    zComplSigT_C1_sqrt := T_193542
    node sigT_C1 = not(zComplSigT_C1)
    node remT_E2 = bits(mulAddResult_3, 55, 0)
    when cyc_B8_sqrt : ESqrR1_B_sqrt := ESqrR1_B8_sqrt
    when cyc_B3 : sigX1_B := sigXNU_B3_CX
    when cyc_B1 : sqrSigma1_C := sqrSigma1_B1
    
    
    node T_193543 = or(cyc_C6_sqrt, cyc_C5_div)
    node T_193544 = or(T_193543, cyc_C3_sqrt)
    when T_193544 : sigXN_C := sigXNU_B3_CX
    when cyc_C5_sqrt : 
      node T_193545 = bits(sigXNU_B3_CX, 56, 26)
      u_C_sqrt := T_193545
    when cyc_C1 : 
      E_E_div := E_C1_div
      node T_193546 = bits(sigT_C1, 53, 1)
      sigT_E := T_193546
      node T_193547 = bit(sigT_C1, 0)
      extraT_E := T_193547
    when cyc_E2 : 
      node T_193548 = bit(remT_E2, 55)
      node T_193549 = bit(remT_E2, 53)
      wire T_193550 : UInt<1>
      T_193550 := T_193549
      when sqrtOp_PC : T_193550 := T_193548
      isNegRemT_E := T_193550
      node T_193551 = bits(remT_E2, 53, 0)
      node T_193552 = eq(T_193551, UInt<1>(0))
      node T_193553 = not(sqrtOp_PC)
      node T_193554 = bits(remT_E2, 55, 54)
      node T_193555 = eq(T_193554, UInt<1>(0))
      node T_193556 = or(T_193553, T_193555)
      node T_193557 = and(T_193552, T_193556)
      trueEqX_E1 := T_193557
    node T_193558 = not(sqrtOp_PC)
    node T_193559 = and(T_193558, E_E_div)
    wire T_193560 : UInt<1>
    T_193560 := UInt<1>(0)
    when T_193559 : T_193560 := exp_PC
    node T_193561 = not(sqrtOp_PC)
    node T_193562 = not(E_E_div)
    node T_193563 = and(T_193561, T_193562)
    wire T_193564 : UInt<1>
    T_193564 := UInt<1>(0)
    when T_193563 : T_193564 := expP1_PC
    node T_193565 = or(T_193560, T_193564)
    node T_193566 = shr(exp_PC, 1)
    node T_193567 = addw(T_193566, UInt<12>(1024))
    wire T_193568 : UInt<1>
    T_193568 := UInt<1>(0)
    when sqrtOp_PC : T_193568 := T_193567
    node sExpX_E = or(T_193565, T_193568)
    node posExpX_E = bits(sExpX_E, 12, 0)
    node T_193569 = bits(posExpX_E, 12, 6)
    node posExpX_0001111_E = eq(T_193569, UInt<7>(15))
    node T_193570 = bit(posExpX_E, 5)
    node T_193571 = not(T_193570)
    node posExpX_00011110_E = and(posExpX_0001111_E, T_193571)
    node T_193572 = bit(posExpX_E, 4)
    node T_193573 = not(T_193572)
    node posExpX_000111100_E = and(posExpX_00011110_E, T_193573)
    node T_193574 = bits(sExpX_E, 2, 0)
    node exp3X_lt_001_E = lt(T_193574, UInt<3>(1))
    node T_193575 = bits(sExpX_E, 2, 0)
    node exp3X_lt_010_E = lt(T_193575, UInt<3>(2))
    node T_193576 = bits(sExpX_E, 2, 0)
    node exp3X_lt_011_E = lt(T_193576, UInt<3>(3))
    node T_193577 = bits(sExpX_E, 2, 0)
    node exp3X_lt_100_E = lt(T_193577, UInt<3>(4))
    node T_193578 = bits(sExpX_E, 2, 0)
    node exp3X_lt_101_E = lt(T_193578, UInt<3>(5))
    node T_193579 = bits(sExpX_E, 2, 0)
    node exp3X_lt_110_E = lt(T_193579, UInt<3>(6))
    node T_193580 = bits(sExpX_E, 2, 0)
    node exp3X_lt_111_E = lt(T_193580, UInt<3>(7))
    node T_193581 = bits(sExpX_E, 4, 3)
    node exp5X_00_E = eq(T_193581, UInt<2>(0))
    node T_193582 = bits(sExpX_E, 4, 3)
    node exp5X_01_E = eq(T_193582, UInt<2>(1))
    node T_193583 = bits(sExpX_E, 4, 3)
    node exp5X_10_E = eq(T_193583, UInt<2>(2))
    node exp5X_lt_00001_E = and(exp5X_00_E, exp3X_lt_001_E)
    node exp5X_lt_00010_E = and(exp5X_00_E, exp3X_lt_010_E)
    node exp5X_lt_00011_E = and(exp5X_00_E, exp3X_lt_011_E)
    node exp5X_lt_00100_E = and(exp5X_00_E, exp3X_lt_100_E)
    node exp5X_lt_00101_E = and(exp5X_00_E, exp3X_lt_101_E)
    node exp5X_lt_00110_E = and(exp5X_00_E, exp3X_lt_110_E)
    node exp5X_lt_00111_E = and(exp5X_00_E, exp3X_lt_111_E)
    node T_193584 = and(exp5X_01_E, exp3X_lt_001_E)
    node exp5X_lt_01001_E = or(exp5X_00_E, T_193584)
    node T_193585 = and(exp5X_01_E, exp3X_lt_010_E)
    node exp5X_lt_01010_E = or(exp5X_00_E, T_193585)
    node T_193586 = and(exp5X_01_E, exp3X_lt_011_E)
    node exp5X_lt_01011_E = or(exp5X_00_E, T_193586)
    node T_193587 = and(exp5X_01_E, exp3X_lt_100_E)
    node exp5X_lt_01100_E = or(exp5X_00_E, T_193587)
    node T_193588 = and(exp5X_01_E, exp3X_lt_101_E)
    node exp5X_lt_01101_E = or(exp5X_00_E, T_193588)
    node T_193589 = and(exp5X_01_E, exp3X_lt_110_E)
    node exp5X_lt_01110_E = or(exp5X_00_E, T_193589)
    node T_193590 = and(exp5X_01_E, exp3X_lt_111_E)
    node exp5X_lt_01111_E = or(exp5X_00_E, T_193590)
    node T_193591 = bit(sExpX_E, 4)
    node exp5X_lt_10000_E = not(T_193591)
    node T_193592 = bit(sExpX_E, 4)
    node T_193593 = not(T_193592)
    node T_193594 = and(exp5X_10_E, exp3X_lt_001_E)
    node exp5X_lt_10001_E = or(T_193593, T_193594)
    node T_193595 = bit(sExpX_E, 4)
    node T_193596 = not(T_193595)
    node T_193597 = and(exp5X_10_E, exp3X_lt_010_E)
    node exp5X_lt_10010_E = or(T_193596, T_193597)
    node T_193598 = bit(sExpX_E, 4)
    node T_193599 = not(T_193598)
    node T_193600 = and(exp5X_10_E, exp3X_lt_011_E)
    node exp5X_lt_10011_E = or(T_193599, T_193600)
    node T_193601 = bit(sExpX_E, 4)
    node T_193602 = not(T_193601)
    node T_193603 = and(exp5X_10_E, exp3X_lt_100_E)
    node exp5X_lt_10100_E = or(T_193602, T_193603)
    node T_193604 = bit(sExpX_E, 4)
    node T_193605 = not(T_193604)
    node T_193606 = and(exp5X_10_E, exp3X_lt_101_E)
    node exp5X_lt_10101_E = or(T_193605, T_193606)
    node T_193607 = bit(sExpX_E, 4)
    node T_193608 = not(T_193607)
    node T_193609 = and(exp5X_10_E, exp3X_lt_110_E)
    node exp5X_lt_10110_E = or(T_193608, T_193609)
    node T_193610 = bit(sExpX_E, 4)
    node T_193611 = not(T_193610)
    node T_193612 = and(exp5X_10_E, exp3X_lt_111_E)
    node exp5X_lt_10111_E = or(T_193611, T_193612)
    node T_193613 = bits(sExpX_E, 4, 3)
    node exp5X_lt_11000_E = neq(T_193613, UInt<2>(3))
    node exp5X_lt_11001_E = or(exp5X_lt_11000_E, exp3X_lt_001_E)
    node exp5X_lt_11010_E = or(exp5X_lt_11000_E, exp3X_lt_010_E)
    node exp5X_lt_11011_E = or(exp5X_lt_11000_E, exp3X_lt_011_E)
    node exp5X_lt_11100_E = or(exp5X_lt_11000_E, exp3X_lt_100_E)
    node exp5X_lt_11101_E = or(exp5X_lt_11000_E, exp3X_lt_101_E)
    node exp5X_lt_11110_E = or(exp5X_lt_11000_E, exp3X_lt_110_E)
    node exp5X_lt_11111_E = or(exp5X_lt_11000_E, exp3X_lt_111_E)
    node T_193614 = bits(sExpX_E, 3, 0)
    node T_193615 = lt(T_193614, UInt<4>(14))
    node T_193616 = and(posExpX_000111100_E, T_193615)
    node T_193617 = bits(sExpX_E, 3, 0)
    node T_193618 = lt(T_193617, UInt<4>(15))
    node T_193619 = and(posExpX_000111100_E, T_193618)
    node T_193620 = and(posExpX_00011110_E, exp5X_lt_10001_E)
    node T_193621 = and(posExpX_00011110_E, exp5X_lt_10010_E)
    node T_193622 = and(posExpX_00011110_E, exp5X_lt_10011_E)
    node T_193623 = and(posExpX_00011110_E, exp5X_lt_10100_E)
    node T_193624 = and(posExpX_00011110_E, exp5X_lt_10101_E)
    node T_193625 = and(posExpX_00011110_E, exp5X_lt_10110_E)
    node T_193626 = and(posExpX_00011110_E, exp5X_lt_10111_E)
    node T_193627 = and(posExpX_00011110_E, exp5X_lt_11000_E)
    node T_193628 = and(posExpX_00011110_E, exp5X_lt_11001_E)
    node T_193629 = and(posExpX_00011110_E, exp5X_lt_11010_E)
    node T_193630 = and(posExpX_00011110_E, exp5X_lt_11011_E)
    node T_193631 = and(posExpX_00011110_E, exp5X_lt_11100_E)
    node T_193632 = and(posExpX_00011110_E, exp5X_lt_11101_E)
    node T_193633 = and(posExpX_00011110_E, exp5X_lt_11110_E)
    node T_193634 = and(posExpX_00011110_E, exp5X_lt_11111_E)
    node T_193635 = bit(sExpX_E, 5)
    node T_193636 = not(T_193635)
    node T_193637 = or(T_193636, exp5X_lt_00001_E)
    node T_193638 = and(posExpX_0001111_E, T_193637)
    node T_193639 = bit(sExpX_E, 5)
    node T_193640 = not(T_193639)
    node T_193641 = or(T_193640, exp5X_lt_00010_E)
    node T_193642 = and(posExpX_0001111_E, T_193641)
    node T_193643 = bit(sExpX_E, 5)
    node T_193644 = not(T_193643)
    node T_193645 = or(T_193644, exp5X_lt_00011_E)
    node T_193646 = and(posExpX_0001111_E, T_193645)
    node T_193647 = bit(sExpX_E, 5)
    node T_193648 = not(T_193647)
    node T_193649 = or(T_193648, exp5X_lt_00100_E)
    node T_193650 = and(posExpX_0001111_E, T_193649)
    node T_193651 = bit(sExpX_E, 5)
    node T_193652 = not(T_193651)
    node T_193653 = or(T_193652, exp5X_lt_00101_E)
    node T_193654 = and(posExpX_0001111_E, T_193653)
    node T_193655 = bit(sExpX_E, 5)
    node T_193656 = not(T_193655)
    node T_193657 = or(T_193656, exp5X_lt_00110_E)
    node T_193658 = and(posExpX_0001111_E, T_193657)
    node T_193659 = bit(sExpX_E, 5)
    node T_193660 = not(T_193659)
    node T_193661 = or(T_193660, exp5X_lt_00111_E)
    node T_193662 = and(posExpX_0001111_E, T_193661)
    node T_193663 = bit(sExpX_E, 5)
    node T_193664 = not(T_193663)
    node T_193665 = or(T_193664, exp5X_00_E)
    node T_193666 = and(posExpX_0001111_E, T_193665)
    node T_193667 = bit(sExpX_E, 5)
    node T_193668 = not(T_193667)
    node T_193669 = or(T_193668, exp5X_lt_01001_E)
    node T_193670 = and(posExpX_0001111_E, T_193669)
    node T_193671 = bit(sExpX_E, 5)
    node T_193672 = not(T_193671)
    node T_193673 = or(T_193672, exp5X_lt_01010_E)
    node T_193674 = and(posExpX_0001111_E, T_193673)
    node T_193675 = bit(sExpX_E, 5)
    node T_193676 = not(T_193675)
    node T_193677 = or(T_193676, exp5X_lt_01011_E)
    node T_193678 = and(posExpX_0001111_E, T_193677)
    node T_193679 = bit(sExpX_E, 5)
    node T_193680 = not(T_193679)
    node T_193681 = or(T_193680, exp5X_lt_01100_E)
    node T_193682 = and(posExpX_0001111_E, T_193681)
    node T_193683 = bit(sExpX_E, 5)
    node T_193684 = not(T_193683)
    node T_193685 = or(T_193684, exp5X_lt_01101_E)
    node T_193686 = and(posExpX_0001111_E, T_193685)
    node T_193687 = bit(sExpX_E, 5)
    node T_193688 = not(T_193687)
    node T_193689 = or(T_193688, exp5X_lt_01110_E)
    node T_193690 = and(posExpX_0001111_E, T_193689)
    node T_193691 = bit(sExpX_E, 5)
    node T_193692 = not(T_193691)
    node T_193693 = or(T_193692, exp5X_lt_01111_E)
    node T_193694 = and(posExpX_0001111_E, T_193693)
    node T_193695 = bit(sExpX_E, 5)
    node T_193696 = not(T_193695)
    node T_193697 = or(T_193696, exp5X_lt_10000_E)
    node T_193698 = and(posExpX_0001111_E, T_193697)
    node T_193699 = bit(sExpX_E, 5)
    node T_193700 = not(T_193699)
    node T_193701 = or(T_193700, exp5X_lt_10001_E)
    node T_193702 = and(posExpX_0001111_E, T_193701)
    node T_193703 = bit(sExpX_E, 5)
    node T_193704 = not(T_193703)
    node T_193705 = or(T_193704, exp5X_lt_10010_E)
    node T_193706 = and(posExpX_0001111_E, T_193705)
    node T_193707 = bit(sExpX_E, 5)
    node T_193708 = not(T_193707)
    node T_193709 = or(T_193708, exp5X_lt_10011_E)
    node T_193710 = and(posExpX_0001111_E, T_193709)
    node T_193711 = bit(sExpX_E, 5)
    node T_193712 = not(T_193711)
    node T_193713 = or(T_193712, exp5X_lt_10100_E)
    node T_193714 = and(posExpX_0001111_E, T_193713)
    node T_193715 = bit(sExpX_E, 5)
    node T_193716 = not(T_193715)
    node T_193717 = or(T_193716, exp5X_lt_10101_E)
    node T_193718 = and(posExpX_0001111_E, T_193717)
    node T_193719 = bit(sExpX_E, 5)
    node T_193720 = not(T_193719)
    node T_193721 = or(T_193720, exp5X_lt_10110_E)
    node T_193722 = and(posExpX_0001111_E, T_193721)
    node T_193723 = bit(sExpX_E, 5)
    node T_193724 = not(T_193723)
    node T_193725 = or(T_193724, exp5X_lt_10111_E)
    node T_193726 = and(posExpX_0001111_E, T_193725)
    node T_193727 = bit(sExpX_E, 5)
    node T_193728 = not(T_193727)
    node T_193729 = or(T_193728, exp5X_lt_11000_E)
    node T_193730 = and(posExpX_0001111_E, T_193729)
    node T_193731 = bit(sExpX_E, 5)
    node T_193732 = not(T_193731)
    node T_193733 = or(T_193732, exp5X_lt_11001_E)
    node T_193734 = and(posExpX_0001111_E, T_193733)
    node T_193735 = bit(sExpX_E, 5)
    node T_193736 = not(T_193735)
    node T_193737 = or(T_193736, exp5X_lt_11010_E)
    node T_193738 = and(posExpX_0001111_E, T_193737)
    node T_193739 = bit(sExpX_E, 5)
    node T_193740 = not(T_193739)
    node T_193741 = or(T_193740, exp5X_lt_11011_E)
    node T_193742 = and(posExpX_0001111_E, T_193741)
    node T_193743 = bit(sExpX_E, 5)
    node T_193744 = not(T_193743)
    node T_193745 = or(T_193744, exp5X_lt_11100_E)
    node T_193746 = and(posExpX_0001111_E, T_193745)
    node T_193747 = bit(sExpX_E, 5)
    node T_193748 = not(T_193747)
    node T_193749 = or(T_193748, exp5X_lt_11101_E)
    node T_193750 = and(posExpX_0001111_E, T_193749)
    node T_193751 = bit(sExpX_E, 5)
    node T_193752 = not(T_193751)
    node T_193753 = or(T_193752, exp5X_lt_11110_E)
    node T_193754 = and(posExpX_0001111_E, T_193753)
    node T_193755 = bit(sExpX_E, 5)
    node T_193756 = not(T_193755)
    node T_193757 = or(T_193756, exp5X_lt_11111_E)
    node T_193758 = and(posExpX_0001111_E, T_193757)
    node T_193759 = lt(posExpX_E, UInt<13>(1025))
    node T_193760 = lt(posExpX_E, UInt<13>(1026))
    node T_193761 = cat(T_193619, posExpX_000111100_E)
    node T_193762 = cat(T_193616, T_193761)
    node T_193763 = cat(T_193621, T_193622)
    node T_193764 = cat(T_193620, T_193763)
    node T_193765 = cat(T_193762, T_193764)
    node T_193766 = cat(T_193624, T_193625)
    node T_193767 = cat(T_193623, T_193766)
    node T_193768 = cat(T_193626, T_193627)
    node T_193769 = cat(T_193628, T_193629)
    node T_193770 = cat(T_193768, T_193769)
    node T_193771 = cat(T_193767, T_193770)
    node T_193772 = cat(T_193765, T_193771)
    node T_193773 = cat(T_193631, T_193632)
    node T_193774 = cat(T_193630, T_193773)
    node T_193775 = cat(T_193634, posExpX_00011110_E)
    node T_193776 = cat(T_193633, T_193775)
    node T_193777 = cat(T_193774, T_193776)
    node T_193778 = cat(T_193642, T_193646)
    node T_193779 = cat(T_193638, T_193778)
    node T_193780 = cat(T_193650, T_193654)
    node T_193781 = cat(T_193658, T_193662)
    node T_193782 = cat(T_193780, T_193781)
    node T_193783 = cat(T_193779, T_193782)
    node T_193784 = cat(T_193777, T_193783)
    node T_193785 = cat(T_193772, T_193784)
    node T_193786 = cat(T_193670, T_193674)
    node T_193787 = cat(T_193666, T_193786)
    node T_193788 = cat(T_193682, T_193686)
    node T_193789 = cat(T_193678, T_193788)
    node T_193790 = cat(T_193787, T_193789)
    node T_193791 = cat(T_193694, T_193698)
    node T_193792 = cat(T_193690, T_193791)
    node T_193793 = cat(T_193702, T_193706)
    node T_193794 = cat(T_193710, T_193714)
    node T_193795 = cat(T_193793, T_193794)
    node T_193796 = cat(T_193792, T_193795)
    node T_193797 = cat(T_193790, T_193796)
    node T_193798 = cat(T_193722, T_193726)
    node T_193799 = cat(T_193718, T_193798)
    node T_193800 = cat(T_193730, T_193734)
    node T_193801 = cat(T_193738, T_193742)
    node T_193802 = cat(T_193800, T_193801)
    node T_193803 = cat(T_193799, T_193802)
    node T_193804 = cat(T_193750, T_193754)
    node T_193805 = cat(T_193746, T_193804)
    node T_193806 = cat(T_193758, posExpX_0001111_E)
    node T_193807 = cat(T_193759, T_193760)
    node T_193808 = cat(T_193806, T_193807)
    node T_193809 = cat(T_193805, T_193808)
    node T_193810 = cat(T_193803, T_193809)
    node T_193811 = cat(T_193797, T_193810)
    node roundMask_E = cat(T_193785, T_193811)
    node T_193812 = cat(UInt<1>(0), roundMask_E)
    node T_193813 = not(T_193812)
    node T_193814 = cat(roundMask_E, UInt<1>(1))
    node incrPosMask_E = and(T_193813, T_193814)
    node T_193815 = shr(incrPosMask_E, 1)
    node T_193816 = and(sigT_E, T_193815)
    node hiRoundPosBitT_E = neq(T_193816, UInt<1>(0))
    node T_193817 = shr(roundMask_E, 1)
    node T_193818 = and(sigT_E, T_193817)
    node all0sHiRoundExtraT_E = eq(T_193818, UInt<1>(0))
    node T_193819 = not(sigT_E)
    node T_193820 = shr(roundMask_E, 1)
    node T_193821 = and(T_193819, T_193820)
    node all1sHiRoundExtraT_E = eq(T_193821, UInt<1>(0))
    node T_193822 = bit(roundMask_E, 0)
    node T_193823 = not(T_193822)
    node T_193824 = or(T_193823, hiRoundPosBitT_E)
    node all1sHiRoundT_E = and(T_193824, all1sHiRoundExtraT_E)
    node T_193825 = addw(UInt<54>(0), sigT_E)
    node sigAdjT_E = addw(T_193825, roundMagUp_PC)
    node T_193826 = not(roundMask_E)
    node T_193827 = cat(UInt<1>(1), T_193826)
    node sigY0_E = and(sigAdjT_E, T_193827)
    node T_193828 = cat(UInt<1>(0), roundMask_E)
    node T_193829 = or(sigAdjT_E, T_193828)
    node sigY1_E = addw(T_193829, UInt<1>(1))
    node T_193830 = not(isNegRemT_E)
    node T_193831 = not(trueEqX_E1)
    node T_193832 = and(T_193830, T_193831)
    wire trueLtX_E1 : UInt<1>
    trueLtX_E1 := isNegRemT_E
    when sqrtOp_PC : trueLtX_E1 := T_193832
    node T_193833 = bit(roundMask_E, 0)
    node T_193834 = not(trueLtX_E1)
    node T_193835 = and(T_193833, T_193834)
    node T_193836 = and(T_193835, all1sHiRoundExtraT_E)
    node T_193837 = and(T_193836, extraT_E)
    node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_193837)
    node T_193838 = not(trueEqX_E1)
    node T_193839 = not(extraT_E)
    node T_193840 = or(T_193838, T_193839)
    node T_193841 = not(all1sHiRoundExtraT_E)
    node anyRoundExtra_E1 = or(T_193840, T_193841)
    node T_193842 = and(roundingMode_near_even_PC, hiRoundPosBit_E1)
    node T_193843 = not(anyRoundExtra_E1)
    node T_193844 = and(T_193842, T_193843)
    wire roundEvenMask_E1 : UInt<1>
    roundEvenMask_E1 := UInt<1>(0)
    when T_193844 : roundEvenMask_E1 := incrPosMask_E
    node T_193845 = and(roundMagDown_PC, extraT_E)
    node T_193846 = not(trueLtX_E1)
    node T_193847 = and(T_193845, T_193846)
    node T_193848 = and(T_193847, all1sHiRoundT_E)
    node T_193849 = not(trueLtX_E1)
    node T_193850 = and(extraT_E, T_193849)
    node T_193851 = not(trueEqX_E1)
    node T_193852 = and(T_193850, T_193851)
    node T_193853 = not(all1sHiRoundT_E)
    node T_193854 = or(T_193852, T_193853)
    node T_193855 = and(roundMagUp_PC, T_193854)
    node T_193856 = or(T_193848, T_193855)
    node T_193857 = not(trueLtX_E1)
    node T_193858 = or(extraT_E, T_193857)
    node T_193859 = bit(roundMask_E, 0)
    node T_193860 = not(T_193859)
    node T_193861 = and(T_193858, T_193860)
    node T_193862 = or(hiRoundPosBitT_E, T_193861)
    node T_193863 = not(trueLtX_E1)
    node T_193864 = and(extraT_E, T_193863)
    node T_193865 = and(T_193864, all1sHiRoundExtraT_E)
    node T_193866 = or(T_193862, T_193865)
    node T_193867 = and(roundingMode_near_even_PC, T_193866)
    node T_193868 = or(T_193856, T_193867)
    wire T_193869 : UInt<54>
    T_193869 := sigY0_E
    when T_193868 : T_193869 := sigY1_E
    node T_193870 = not(roundEvenMask_E1)
    node sigY_E1 = and(T_193869, T_193870)
    node fractY_E1 = bits(sigY_E1, 51, 0)
    node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1)
    node T_193871 = bit(sigY_E1, 53)
    node T_193872 = not(T_193871)
    wire T_193873 : UInt<1>
    T_193873 := UInt<1>(0)
    when T_193872 : T_193873 := sExpX_E
    node T_193874 = bit(sigY_E1, 53)
    node T_193875 = not(sqrtOp_PC)
    node T_193876 = and(T_193874, T_193875)
    node T_193877 = and(T_193876, E_E_div)
    wire T_193878 : UInt<1>
    T_193878 := UInt<1>(0)
    when T_193877 : T_193878 := expP1_PC
    node T_193879 = or(T_193873, T_193878)
    node T_193880 = bit(sigY_E1, 53)
    node T_193881 = not(sqrtOp_PC)
    node T_193882 = and(T_193880, T_193881)
    node T_193883 = not(E_E_div)
    node T_193884 = and(T_193882, T_193883)
    wire T_193885 : UInt<1>
    T_193885 := UInt<1>(0)
    when T_193884 : T_193885 := expP2_PC
    node T_193886 = or(T_193879, T_193885)
    node T_193887 = bit(sigY_E1, 53)
    node T_193888 = and(T_193887, sqrtOp_PC)
    node T_193889 = shr(expP2_PC, 1)
    node T_193890 = addw(T_193889, UInt<12>(1024))
    wire T_193891 : UInt<1>
    T_193891 := UInt<1>(0)
    when T_193888 : T_193891 := T_193890
    node sExpY_E1 = or(T_193886, T_193891)
    node expY_E1 = bits(sExpY_E1, 11, 0)
    node T_193892 = bit(sExpY_E1, 13)
    node T_193893 = not(T_193892)
    node T_193894 = bits(sExpY_E1, 12, 10)
    node T_193895 = leq(UInt<3>(3), T_193894)
    node overflowY_E1 = and(T_193893, T_193895)
    node T_193896 = bit(sExpY_E1, 13)
    node T_193897 = bits(sExpY_E1, 12, 0)
    node T_193898 = lt(T_193897, UInt<13>(974))
    node totalUnderflowY_E1 = or(T_193896, T_193898)
    node T_193899 = leq(posExpX_E, UInt<13>(1025))
    node T_193900 = and(T_193899, inexactY_E1)
    node underflowY_E1 = or(totalUnderflowY_E1, T_193900)
    node T_193901 = not(isNaNB_PC)
    node T_193902 = not(isZeroB_PC)
    node T_193903 = and(T_193901, T_193902)
    node T_193904 = and(T_193903, sign_PC)
    node T_193905 = and(isZeroA_PC, isZeroB_PC)
    node T_193906 = and(isInfA_PC, isInfB_PC)
    node T_193907 = or(T_193905, T_193906)
    wire notSigNaN_invalid_PC : UInt<1>
    notSigNaN_invalid_PC := T_193907
    when sqrtOp_PC : notSigNaN_invalid_PC := T_193904
    node T_193908 = not(sqrtOp_PC)
    node T_193909 = and(T_193908, isSigNaNA_PC)
    node T_193910 = or(T_193909, isSigNaNB_PC)
    node invalid_PC = or(T_193910, notSigNaN_invalid_PC)
    node T_193911 = not(sqrtOp_PC)
    node T_193912 = not(isSpecialA_PC)
    node T_193913 = and(T_193911, T_193912)
    node T_193914 = not(isZeroA_PC)
    node T_193915 = and(T_193913, T_193914)
    node infinity_PC = and(T_193915, isZeroB_PC)
    node overflow_E1 = and(normalCase_PC, overflowY_E1)
    node underflow_E1 = and(normalCase_PC, underflowY_E1)
    node T_193916 = or(overflow_E1, underflow_E1)
    node T_193917 = and(normalCase_PC, inexactY_E1)
    node inexact_E1 = or(T_193916, T_193917)
    node T_193918 = or(isZeroA_PC, isInfB_PC)
    node T_193919 = not(roundMagUp_PC)
    node T_193920 = and(totalUnderflowY_E1, T_193919)
    node T_193921 = or(T_193918, T_193920)
    wire notSpecial_isZeroOut_E1 : UInt<1>
    notSpecial_isZeroOut_E1 := T_193921
    when sqrtOp_PC : notSpecial_isZeroOut_E1 := isZeroB_PC
    node T_193922 = and(normalCase_PC, totalUnderflowY_E1)
    node pegMinFiniteMagOut_E1 = and(T_193922, roundMagUp_PC)
    node T_193923 = not(overflowY_roundMagUp_PC)
    node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_193923)
    node T_193924 = or(isInfA_PC, isZeroB_PC)
    node T_193925 = and(overflow_E1, overflowY_roundMagUp_PC)
    node T_193926 = or(T_193924, T_193925)
    wire notNaN_isInfOut_E1 : UInt<1>
    notNaN_isInfOut_E1 := T_193926
    when sqrtOp_PC : notNaN_isInfOut_E1 := isInfB_PC
    node T_193927 = not(sqrtOp_PC)
    node T_193928 = and(T_193927, isNaNA_PC)
    node T_193929 = or(T_193928, isNaNB_PC)
    node isNaNOut_PC = or(T_193929, notSigNaN_invalid_PC)
    node T_193930 = and(isZeroB_PC, sign_PC)
    wire T_193931 : UInt<1>
    T_193931 := sign_PC
    when sqrtOp_PC : T_193931 := T_193930
    node signOut_PC = or(isNaNOut_PC, T_193931)
    node T_193932 = not(UInt<12>(511))
    wire T_193933 : UInt<1>
    T_193933 := UInt<1>(0)
    when notSpecial_isZeroOut_E1 : T_193933 := T_193932
    node T_193934 = not(T_193933)
    node T_193935 = and(expY_E1, T_193934)
    node T_193936 = not(UInt<12>(974))
    wire T_193937 : UInt<1>
    T_193937 := UInt<1>(0)
    when pegMinFiniteMagOut_E1 : T_193937 := T_193936
    node T_193938 = not(T_193937)
    node T_193939 = and(T_193935, T_193938)
    node T_193940 = not(UInt<12>(3071))
    wire T_193941 : UInt<1>
    T_193941 := UInt<1>(0)
    when pegMaxFiniteMagOut_E1 : T_193941 := T_193940
    node T_193942 = not(T_193941)
    node T_193943 = and(T_193939, T_193942)
    node T_193944 = not(UInt<12>(3583))
    wire T_193945 : UInt<1>
    T_193945 := UInt<1>(0)
    when notNaN_isInfOut_E1 : T_193945 := T_193944
    node T_193946 = not(T_193945)
    node T_193947 = and(T_193943, T_193946)
    wire T_193948 : UInt<1>
    T_193948 := UInt<1>(0)
    when pegMinFiniteMagOut_E1 : T_193948 := UInt<12>(974)
    node T_193949 = or(T_193947, T_193948)
    wire T_193950 : UInt<1>
    T_193950 := UInt<1>(0)
    when pegMaxFiniteMagOut_E1 : T_193950 := UInt<12>(3071)
    node T_193951 = or(T_193949, T_193950)
    wire T_193952 : UInt<1>
    T_193952 := UInt<1>(0)
    when notNaN_isInfOut_E1 : T_193952 := UInt<12>(3072)
    node T_193953 = or(T_193951, T_193952)
    wire T_193954 : UInt<1>
    T_193954 := UInt<1>(0)
    when isNaNOut_PC : T_193954 := UInt<12>(3584)
    node expOut_E1 = or(T_193953, T_193954)
    node T_193955 = and(totalUnderflowY_E1, roundMagUp_PC)
    wire T_193956 : UInt<52>
    T_193956 := fractY_E1
    when T_193955 : T_193956 := UInt<1>(0)
    node T_193957 = or(isNaNOut_PC, pegMaxFiniteMagOut_E1)
    wire T_193958 : UInt<1>
    T_193958 := UInt<1>(0)
    when T_193957 : T_193958 := UInt<52>(4503599627370495)
    node fractOut_E1 = or(T_193956, T_193958)
    node T_193959 = cat(expOut_E1, fractOut_E1)
    node T_193960 = cat(signOut_PC, T_193959)
    out := T_193960
    node T_193961 = cat(invalid_PC, infinity_PC)
    node T_193962 = cat(underflow_E1, inexact_E1)
    node T_193963 = cat(overflow_E1, T_193962)
    node T_193964 = cat(T_193961, T_193963)
    exceptionFlags := T_193964
  module mul54 : 
    input val_s0 : UInt<1>
    input latch_a_s0 : UInt<1>
    input a_s0 : UInt<54>
    input latch_b_s0 : UInt<1>
    input b_s0 : UInt<54>
    input c_s2 : UInt<105>
    output result_s3 : UInt<105>
    
    reg val_s1 : UInt<1>
    reg val_s2 : UInt<1>
    reg reg_a_s1 : UInt<54>
    reg reg_b_s1 : UInt<54>
    reg reg_a_s2 : UInt<54>
    reg reg_b_s2 : UInt<54>
    reg reg_result_s3 : UInt<105>
    val_s1 := val_s0
    val_s2 := val_s1
    when val_s0 : 
      when latch_a_s0 : reg_a_s1 := a_s0
      when latch_b_s0 : reg_b_s1 := b_s0
    when val_s1 : 
      reg_a_s2 := reg_a_s1
      reg_b_s2 := reg_b_s1
    when val_s2 : 
      node T_193965 = mul(reg_a_s2, reg_b_s2)
      node T_193966 = addw(T_193965, c_s2)
      reg_result_s3 := T_193966
    result_s3 := reg_result_s3
  module divSqrtRecodedFloat64 : 
    output inReady_div : UInt<1>
    output inReady_sqrt : UInt<1>
    input inValid : UInt<1>
    input sqrtOp : UInt<1>
    input a : UInt<65>
    input b : UInt<65>
    input roundingMode : UInt<2>
    output outValid_div : UInt<1>
    output outValid_sqrt : UInt<1>
    output out : UInt<65>
    output exceptionFlags : UInt<5>
    
    inst ds of divSqrtRecodedFloat64_mulAddZ31
    inReady_div := ds.inReady_div
    inReady_sqrt := ds.inReady_sqrt
    ds.inValid := inValid
    ds.sqrtOp := sqrtOp
    ds.a := a
    ds.b := b
    ds.roundingMode := roundingMode
    outValid_div := ds.outValid_div
    outValid_sqrt := ds.outValid_sqrt
    out := ds.out
    exceptionFlags := ds.exceptionFlags
    inst mul of mul54
    node T_193967 = bit(ds.usingMulAdd, 0)
    mul.val_s0 := T_193967
    mul.latch_a_s0 := ds.latchMulAddA_0
    mul.a_s0 := ds.mulAddA_0
    mul.latch_b_s0 := ds.latchMulAddB_0
    mul.b_s0 := ds.mulAddB_0
    mul.c_s2 := ds.mulAddC_2
    ds.mulAddResult_3 := mul.result_s3
  module FPU : 
    input inst__ : UInt<32>
    input fromint_data : UInt<64>
    input fcsr_rm : UInt<3>
    output fcsr_flags : {valid : UInt<1>, bits : UInt<5>}
    output store_data : UInt<64>
    output toint_data : UInt<64>
    input dmem_resp_val : UInt<1>
    input dmem_resp_type : UInt<3>
    input dmem_resp_tag : UInt<5>
    input dmem_resp_data : UInt<64>
    input valid : UInt<1>
    output fcsr_rdy : UInt<1>
    output nack_mem : UInt<1>
    output illegal_rm : UInt<1>
    input killx : UInt<1>
    input killm : UInt<1>
    output dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}
    output sboard_set : UInt<1>
    output sboard_clr : UInt<1>
    output sboard_clra : UInt<5>
    
    reg ex_reg_valid : UInt<1>
    onreset ex_reg_valid := UInt<1>(0)
    ex_reg_valid := valid
    reg ex_reg_inst : UInt<32>
    when valid : ex_reg_inst := inst__
    node T_193968 = eq(killx, UInt<1>(0))
    node T_193969 = and(ex_reg_valid, T_193968)
    reg mem_reg_valid : UInt<1>
    onreset mem_reg_valid := UInt<1>(0)
    mem_reg_valid := T_193969
    reg mem_reg_inst : UInt<32>
    when ex_reg_valid : mem_reg_inst := ex_reg_inst
    node killm = or(killm, nack_mem)
    node T_193970 = eq(killm, UInt<1>(0))
    node T_193971 = and(mem_reg_valid, T_193970)
    reg wb_reg_valid : UInt<1>
    onreset wb_reg_valid := UInt<1>(0)
    wb_reg_valid := T_193971
    inst fp_decoder of FPUDecoder
    fp_decoder.inst__ := inst__
    reg ex_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}
    when valid : ex_ctrl := fp_decoder.sigs
    reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}
    when ex_reg_valid : mem_ctrl := ex_ctrl
    reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}
    when mem_reg_valid : wb_ctrl := mem_ctrl
    reg load_wb : UInt<1>
    load_wb := dmem_resp_val
    node T_193972 = eq(dmem_resp_type, UInt<3>(2))
    node T_193973 = eq(dmem_resp_type, UInt<3>(6))
    node T_193974 = or(T_193972, T_193973)
    reg load_wb_single : UInt<1>
    when dmem_resp_val : load_wb_single := T_193974
    reg load_wb_data : UInt<64>
    when dmem_resp_val : load_wb_data := dmem_resp_data
    reg load_wb_tag : UInt<5>
    when dmem_resp_val : load_wb_tag := dmem_resp_tag
    node T_193975 = bit(load_wb_data, 31)
    node T_193976 = bits(load_wb_data, 30, 23)
    node T_193977 = bits(load_wb_data, 22, 0)
    node T_193978 = eq(T_193976, UInt<1>(0))
    node T_193979 = eq(T_193977, UInt<1>(0))
    node T_193980 = and(T_193978, T_193979)
    node T_193981 = eq(T_193979, UInt<1>(0))
    node T_193982 = and(T_193978, T_193981)
    node T_193983 = shl(T_193977, 9)
    node T_193984 = bit(T_193983, 31)
    node T_193985 = bit(T_193983, 30)
    node T_193986 = bit(T_193983, 29)
    node T_193987 = bit(T_193983, 28)
    node T_193988 = bit(T_193983, 27)
    node T_193989 = bit(T_193983, 26)
    node T_193990 = bit(T_193983, 25)
    node T_193991 = bit(T_193983, 24)
    node T_193992 = bit(T_193983, 23)
    node T_193993 = bit(T_193983, 22)
    node T_193994 = bit(T_193983, 21)
    node T_193995 = bit(T_193983, 20)
    node T_193996 = bit(T_193983, 19)
    node T_193997 = bit(T_193983, 18)
    node T_193998 = bit(T_193983, 17)
    node T_193999 = bit(T_193983, 16)
    node T_194000 = bit(T_193983, 15)
    node T_194001 = bit(T_193983, 14)
    node T_194002 = bit(T_193983, 13)
    node T_194003 = bit(T_193983, 12)
    node T_194004 = bit(T_193983, 11)
    node T_194005 = bit(T_193983, 10)
    node T_194006 = bit(T_193983, 9)
    node T_194007 = bit(T_193983, 8)
    node T_194008 = bit(T_193983, 7)
    node T_194009 = bit(T_193983, 6)
    node T_194010 = bit(T_193983, 5)
    node T_194011 = bit(T_193983, 4)
    node T_194012 = bit(T_193983, 3)
    node T_194013 = bit(T_193983, 2)
    node T_194014 = bit(T_193983, 1)
    wire T_194015 : UInt<1>
    T_194015 := T_194014
    when T_194013 : T_194015 := UInt<2>(2)
    wire T_194016 : UInt<1>
    T_194016 := T_194015
    when T_194012 : T_194016 := UInt<2>(3)
    wire T_194017 : UInt<1>
    T_194017 := T_194016
    when T_194011 : T_194017 := UInt<3>(4)
    wire T_194018 : UInt<1>
    T_194018 := T_194017
    when T_194010 : T_194018 := UInt<3>(5)
    wire T_194019 : UInt<1>
    T_194019 := T_194018
    when T_194009 : T_194019 := UInt<3>(6)
    wire T_194020 : UInt<1>
    T_194020 := T_194019
    when T_194008 : T_194020 := UInt<3>(7)
    wire T_194021 : UInt<1>
    T_194021 := T_194020
    when T_194007 : T_194021 := UInt<4>(8)
    wire T_194022 : UInt<1>
    T_194022 := T_194021
    when T_194006 : T_194022 := UInt<4>(9)
    wire T_194023 : UInt<1>
    T_194023 := T_194022
    when T_194005 : T_194023 := UInt<4>(10)
    wire T_194024 : UInt<1>
    T_194024 := T_194023
    when T_194004 : T_194024 := UInt<4>(11)
    wire T_194025 : UInt<1>
    T_194025 := T_194024
    when T_194003 : T_194025 := UInt<4>(12)
    wire T_194026 : UInt<1>
    T_194026 := T_194025
    when T_194002 : T_194026 := UInt<4>(13)
    wire T_194027 : UInt<1>
    T_194027 := T_194026
    when T_194001 : T_194027 := UInt<4>(14)
    wire T_194028 : UInt<1>
    T_194028 := T_194027
    when T_194000 : T_194028 := UInt<4>(15)
    wire T_194029 : UInt<1>
    T_194029 := T_194028
    when T_193999 : T_194029 := UInt<5>(16)
    wire T_194030 : UInt<1>
    T_194030 := T_194029
    when T_193998 : T_194030 := UInt<5>(17)
    wire T_194031 : UInt<1>
    T_194031 := T_194030
    when T_193997 : T_194031 := UInt<5>(18)
    wire T_194032 : UInt<1>
    T_194032 := T_194031
    when T_193996 : T_194032 := UInt<5>(19)
    wire T_194033 : UInt<1>
    T_194033 := T_194032
    when T_193995 : T_194033 := UInt<5>(20)
    wire T_194034 : UInt<1>
    T_194034 := T_194033
    when T_193994 : T_194034 := UInt<5>(21)
    wire T_194035 : UInt<1>
    T_194035 := T_194034
    when T_193993 : T_194035 := UInt<5>(22)
    wire T_194036 : UInt<1>
    T_194036 := T_194035
    when T_193992 : T_194036 := UInt<5>(23)
    wire T_194037 : UInt<1>
    T_194037 := T_194036
    when T_193991 : T_194037 := UInt<5>(24)
    wire T_194038 : UInt<1>
    T_194038 := T_194037
    when T_193990 : T_194038 := UInt<5>(25)
    wire T_194039 : UInt<1>
    T_194039 := T_194038
    when T_193989 : T_194039 := UInt<5>(26)
    wire T_194040 : UInt<1>
    T_194040 := T_194039
    when T_193988 : T_194040 := UInt<5>(27)
    wire T_194041 : UInt<1>
    T_194041 := T_194040
    when T_193987 : T_194041 := UInt<5>(28)
    wire T_194042 : UInt<1>
    T_194042 := T_194041
    when T_193986 : T_194042 := UInt<5>(29)
    wire T_194043 : UInt<1>
    T_194043 := T_194042
    when T_193985 : T_194043 := UInt<5>(30)
    wire T_194044 : UInt<1>
    T_194044 := T_194043
    when T_193984 : T_194044 := UInt<5>(31)
    node T_194045 = not(T_194044)
    node T_194046 = dshl(T_193983, T_194045)
    node T_194047 = subw(UInt<4>(0), UInt<3>(4))
    node T_194048 = not(T_194045)
    node T_194049 = cat(T_194047, T_194048)
    node T_194050 = bits(T_194046, 30, 8)
    wire T_194051 : UInt<5>
    T_194051 := T_194049
    when T_193979 : T_194051 := UInt<1>(0)
    wire T_194052 : UInt<8>
    T_194052 := T_193976
    when T_193978 : T_194052 := T_194051
    wire T_194053 : UInt<1>
    T_194053 := UInt<1>(1)
    when T_193982 : T_194053 := UInt<2>(2)
    node T_194054 = or(UInt<8>(128), T_194053)
    wire T_194055 : UInt<8>
    T_194055 := T_194054
    when T_193980 : T_194055 := UInt<1>(0)
    node T_194056 = addw(T_194052, T_194055)
    node T_194057 = bits(T_194056, 8, 7)
    node T_194058 = eq(T_194057, UInt<1>(-1))
    node T_194059 = eq(T_193979, UInt<1>(0))
    node T_194060 = and(T_194058, T_194059)
    node T_194061 = dshl(T_194060, UInt<3>(6))
    node T_194062 = or(T_194056, T_194061)
    wire T_194063 : UInt<23>
    T_194063 := T_193977
    when T_193978 : T_194063 := T_194050
    node T_194064 = cat(T_194062, T_194063)
    node rec_s = cat(T_193975, T_194064)
    node T_194065 = bit(load_wb_data, 63)
    node T_194066 = bits(load_wb_data, 62, 52)
    node T_194067 = bits(load_wb_data, 51, 0)
    node T_194068 = eq(T_194066, UInt<1>(0))
    node T_194069 = eq(T_194067, UInt<1>(0))
    node T_194070 = and(T_194068, T_194069)
    node T_194071 = eq(T_194069, UInt<1>(0))
    node T_194072 = and(T_194068, T_194071)
    node T_194073 = shl(T_194067, 12)
    node T_194074 = bit(T_194073, 63)
    node T_194075 = bit(T_194073, 62)
    node T_194076 = bit(T_194073, 61)
    node T_194077 = bit(T_194073, 60)
    node T_194078 = bit(T_194073, 59)
    node T_194079 = bit(T_194073, 58)
    node T_194080 = bit(T_194073, 57)
    node T_194081 = bit(T_194073, 56)
    node T_194082 = bit(T_194073, 55)
    node T_194083 = bit(T_194073, 54)
    node T_194084 = bit(T_194073, 53)
    node T_194085 = bit(T_194073, 52)
    node T_194086 = bit(T_194073, 51)
    node T_194087 = bit(T_194073, 50)
    node T_194088 = bit(T_194073, 49)
    node T_194089 = bit(T_194073, 48)
    node T_194090 = bit(T_194073, 47)
    node T_194091 = bit(T_194073, 46)
    node T_194092 = bit(T_194073, 45)
    node T_194093 = bit(T_194073, 44)
    node T_194094 = bit(T_194073, 43)
    node T_194095 = bit(T_194073, 42)
    node T_194096 = bit(T_194073, 41)
    node T_194097 = bit(T_194073, 40)
    node T_194098 = bit(T_194073, 39)
    node T_194099 = bit(T_194073, 38)
    node T_194100 = bit(T_194073, 37)
    node T_194101 = bit(T_194073, 36)
    node T_194102 = bit(T_194073, 35)
    node T_194103 = bit(T_194073, 34)
    node T_194104 = bit(T_194073, 33)
    node T_194105 = bit(T_194073, 32)
    node T_194106 = bit(T_194073, 31)
    node T_194107 = bit(T_194073, 30)
    node T_194108 = bit(T_194073, 29)
    node T_194109 = bit(T_194073, 28)
    node T_194110 = bit(T_194073, 27)
    node T_194111 = bit(T_194073, 26)
    node T_194112 = bit(T_194073, 25)
    node T_194113 = bit(T_194073, 24)
    node T_194114 = bit(T_194073, 23)
    node T_194115 = bit(T_194073, 22)
    node T_194116 = bit(T_194073, 21)
    node T_194117 = bit(T_194073, 20)
    node T_194118 = bit(T_194073, 19)
    node T_194119 = bit(T_194073, 18)
    node T_194120 = bit(T_194073, 17)
    node T_194121 = bit(T_194073, 16)
    node T_194122 = bit(T_194073, 15)
    node T_194123 = bit(T_194073, 14)
    node T_194124 = bit(T_194073, 13)
    node T_194125 = bit(T_194073, 12)
    node T_194126 = bit(T_194073, 11)
    node T_194127 = bit(T_194073, 10)
    node T_194128 = bit(T_194073, 9)
    node T_194129 = bit(T_194073, 8)
    node T_194130 = bit(T_194073, 7)
    node T_194131 = bit(T_194073, 6)
    node T_194132 = bit(T_194073, 5)
    node T_194133 = bit(T_194073, 4)
    node T_194134 = bit(T_194073, 3)
    node T_194135 = bit(T_194073, 2)
    node T_194136 = bit(T_194073, 1)
    wire T_194137 : UInt<1>
    T_194137 := T_194136
    when T_194135 : T_194137 := UInt<2>(2)
    wire T_194138 : UInt<1>
    T_194138 := T_194137
    when T_194134 : T_194138 := UInt<2>(3)
    wire T_194139 : UInt<1>
    T_194139 := T_194138
    when T_194133 : T_194139 := UInt<3>(4)
    wire T_194140 : UInt<1>
    T_194140 := T_194139
    when T_194132 : T_194140 := UInt<3>(5)
    wire T_194141 : UInt<1>
    T_194141 := T_194140
    when T_194131 : T_194141 := UInt<3>(6)
    wire T_194142 : UInt<1>
    T_194142 := T_194141
    when T_194130 : T_194142 := UInt<3>(7)
    wire T_194143 : UInt<1>
    T_194143 := T_194142
    when T_194129 : T_194143 := UInt<4>(8)
    wire T_194144 : UInt<1>
    T_194144 := T_194143
    when T_194128 : T_194144 := UInt<4>(9)
    wire T_194145 : UInt<1>
    T_194145 := T_194144
    when T_194127 : T_194145 := UInt<4>(10)
    wire T_194146 : UInt<1>
    T_194146 := T_194145
    when T_194126 : T_194146 := UInt<4>(11)
    wire T_194147 : UInt<1>
    T_194147 := T_194146
    when T_194125 : T_194147 := UInt<4>(12)
    wire T_194148 : UInt<1>
    T_194148 := T_194147
    when T_194124 : T_194148 := UInt<4>(13)
    wire T_194149 : UInt<1>
    T_194149 := T_194148
    when T_194123 : T_194149 := UInt<4>(14)
    wire T_194150 : UInt<1>
    T_194150 := T_194149
    when T_194122 : T_194150 := UInt<4>(15)
    wire T_194151 : UInt<1>
    T_194151 := T_194150
    when T_194121 : T_194151 := UInt<5>(16)
    wire T_194152 : UInt<1>
    T_194152 := T_194151
    when T_194120 : T_194152 := UInt<5>(17)
    wire T_194153 : UInt<1>
    T_194153 := T_194152
    when T_194119 : T_194153 := UInt<5>(18)
    wire T_194154 : UInt<1>
    T_194154 := T_194153
    when T_194118 : T_194154 := UInt<5>(19)
    wire T_194155 : UInt<1>
    T_194155 := T_194154
    when T_194117 : T_194155 := UInt<5>(20)
    wire T_194156 : UInt<1>
    T_194156 := T_194155
    when T_194116 : T_194156 := UInt<5>(21)
    wire T_194157 : UInt<1>
    T_194157 := T_194156
    when T_194115 : T_194157 := UInt<5>(22)
    wire T_194158 : UInt<1>
    T_194158 := T_194157
    when T_194114 : T_194158 := UInt<5>(23)
    wire T_194159 : UInt<1>
    T_194159 := T_194158
    when T_194113 : T_194159 := UInt<5>(24)
    wire T_194160 : UInt<1>
    T_194160 := T_194159
    when T_194112 : T_194160 := UInt<5>(25)
    wire T_194161 : UInt<1>
    T_194161 := T_194160
    when T_194111 : T_194161 := UInt<5>(26)
    wire T_194162 : UInt<1>
    T_194162 := T_194161
    when T_194110 : T_194162 := UInt<5>(27)
    wire T_194163 : UInt<1>
    T_194163 := T_194162
    when T_194109 : T_194163 := UInt<5>(28)
    wire T_194164 : UInt<1>
    T_194164 := T_194163
    when T_194108 : T_194164 := UInt<5>(29)
    wire T_194165 : UInt<1>
    T_194165 := T_194164
    when T_194107 : T_194165 := UInt<5>(30)
    wire T_194166 : UInt<1>
    T_194166 := T_194165
    when T_194106 : T_194166 := UInt<5>(31)
    wire T_194167 : UInt<1>
    T_194167 := T_194166
    when T_194105 : T_194167 := UInt<6>(32)
    wire T_194168 : UInt<1>
    T_194168 := T_194167
    when T_194104 : T_194168 := UInt<6>(33)
    wire T_194169 : UInt<1>
    T_194169 := T_194168
    when T_194103 : T_194169 := UInt<6>(34)
    wire T_194170 : UInt<1>
    T_194170 := T_194169
    when T_194102 : T_194170 := UInt<6>(35)
    wire T_194171 : UInt<1>
    T_194171 := T_194170
    when T_194101 : T_194171 := UInt<6>(36)
    wire T_194172 : UInt<1>
    T_194172 := T_194171
    when T_194100 : T_194172 := UInt<6>(37)
    wire T_194173 : UInt<1>
    T_194173 := T_194172
    when T_194099 : T_194173 := UInt<6>(38)
    wire T_194174 : UInt<1>
    T_194174 := T_194173
    when T_194098 : T_194174 := UInt<6>(39)
    wire T_194175 : UInt<1>
    T_194175 := T_194174
    when T_194097 : T_194175 := UInt<6>(40)
    wire T_194176 : UInt<1>
    T_194176 := T_194175
    when T_194096 : T_194176 := UInt<6>(41)
    wire T_194177 : UInt<1>
    T_194177 := T_194176
    when T_194095 : T_194177 := UInt<6>(42)
    wire T_194178 : UInt<1>
    T_194178 := T_194177
    when T_194094 : T_194178 := UInt<6>(43)
    wire T_194179 : UInt<1>
    T_194179 := T_194178
    when T_194093 : T_194179 := UInt<6>(44)
    wire T_194180 : UInt<1>
    T_194180 := T_194179
    when T_194092 : T_194180 := UInt<6>(45)
    wire T_194181 : UInt<1>
    T_194181 := T_194180
    when T_194091 : T_194181 := UInt<6>(46)
    wire T_194182 : UInt<1>
    T_194182 := T_194181
    when T_194090 : T_194182 := UInt<6>(47)
    wire T_194183 : UInt<1>
    T_194183 := T_194182
    when T_194089 : T_194183 := UInt<6>(48)
    wire T_194184 : UInt<1>
    T_194184 := T_194183
    when T_194088 : T_194184 := UInt<6>(49)
    wire T_194185 : UInt<1>
    T_194185 := T_194184
    when T_194087 : T_194185 := UInt<6>(50)
    wire T_194186 : UInt<1>
    T_194186 := T_194185
    when T_194086 : T_194186 := UInt<6>(51)
    wire T_194187 : UInt<1>
    T_194187 := T_194186
    when T_194085 : T_194187 := UInt<6>(52)
    wire T_194188 : UInt<1>
    T_194188 := T_194187
    when T_194084 : T_194188 := UInt<6>(53)
    wire T_194189 : UInt<1>
    T_194189 := T_194188
    when T_194083 : T_194189 := UInt<6>(54)
    wire T_194190 : UInt<1>
    T_194190 := T_194189
    when T_194082 : T_194190 := UInt<6>(55)
    wire T_194191 : UInt<1>
    T_194191 := T_194190
    when T_194081 : T_194191 := UInt<6>(56)
    wire T_194192 : UInt<1>
    T_194192 := T_194191
    when T_194080 : T_194192 := UInt<6>(57)
    wire T_194193 : UInt<1>
    T_194193 := T_194192
    when T_194079 : T_194193 := UInt<6>(58)
    wire T_194194 : UInt<1>
    T_194194 := T_194193
    when T_194078 : T_194194 := UInt<6>(59)
    wire T_194195 : UInt<1>
    T_194195 := T_194194
    when T_194077 : T_194195 := UInt<6>(60)
    wire T_194196 : UInt<1>
    T_194196 := T_194195
    when T_194076 : T_194196 := UInt<6>(61)
    wire T_194197 : UInt<1>
    T_194197 := T_194196
    when T_194075 : T_194197 := UInt<6>(62)
    wire T_194198 : UInt<1>
    T_194198 := T_194197
    when T_194074 : T_194198 := UInt<6>(63)
    node T_194199 = not(T_194198)
    node T_194200 = dshl(T_194073, T_194199)
    node T_194201 = subw(UInt<6>(0), UInt<3>(6))
    node T_194202 = not(T_194199)
    node T_194203 = cat(T_194201, T_194202)
    node T_194204 = bits(T_194200, 62, 11)
    wire T_194205 : UInt<7>
    T_194205 := T_194203
    when T_194069 : T_194205 := UInt<1>(0)
    wire T_194206 : UInt<11>
    T_194206 := T_194066
    when T_194068 : T_194206 := T_194205
    wire T_194207 : UInt<1>
    T_194207 := UInt<1>(1)
    when T_194072 : T_194207 := UInt<2>(2)
    node T_194208 = or(UInt<11>(1024), T_194207)
    wire T_194209 : UInt<11>
    T_194209 := T_194208
    when T_194070 : T_194209 := UInt<1>(0)
    node T_194210 = addw(T_194206, T_194209)
    node T_194211 = bits(T_194210, 11, 10)
    node T_194212 = eq(T_194211, UInt<1>(-1))
    node T_194213 = eq(T_194069, UInt<1>(0))
    node T_194214 = and(T_194212, T_194213)
    node T_194215 = dshl(T_194214, UInt<4>(9))
    node T_194216 = or(T_194210, T_194215)
    wire T_194217 : UInt<52>
    T_194217 := T_194067
    when T_194068 : T_194217 := T_194204
    node T_194218 = cat(T_194216, T_194217)
    node rec_d = cat(T_194065, T_194218)
    node T_194219 = asUInt(SInt<32>(-1))
    node T_194220 = cat(T_194219, rec_s)
    wire load_wb_data_recoded : UInt<64>
    load_wb_data_recoded := rec_d
    when load_wb_single : load_wb_data_recoded := T_194220
    cmem regfile : UInt<65>[32]
    when load_wb : 
      accessor T_194221 = regfile[load_wb_tag]
      T_194221 := load_wb_data_recoded
    reg ex_ra1 : UInt
    reg ex_ra2 : UInt
    reg ex_ra3 : UInt
    when valid : 
      when fp_decoder.sigs.ren1 : 
        
        node T_194222 = eq(fp_decoder.sigs.swap12, UInt<1>(0))
        when T_194222 : 
          node T_194223 = bits(inst__, 19, 15)
          ex_ra1 := T_194223
        when fp_decoder.sigs.swap12 : 
          node T_194224 = bits(inst__, 19, 15)
          ex_ra2 := T_194224
      when fp_decoder.sigs.ren2 : 
        when fp_decoder.sigs.swap12 : 
          node T_194225 = bits(inst__, 24, 20)
          ex_ra1 := T_194225
        when fp_decoder.sigs.swap23 : 
          node T_194226 = bits(inst__, 24, 20)
          ex_ra3 := T_194226
        
        
        node T_194227 = eq(fp_decoder.sigs.swap12, UInt<1>(0))
        node T_194228 = eq(fp_decoder.sigs.swap23, UInt<1>(0))
        node T_194229 = and(T_194227, T_194228)
        when T_194229 : 
          node T_194230 = bits(inst__, 24, 20)
          ex_ra2 := T_194230
      when fp_decoder.sigs.ren3 : 
        node T_194231 = bits(inst__, 31, 27)
        ex_ra3 := T_194231
    accessor ex_rs1 = regfile[ex_ra1]
    accessor ex_rs2 = regfile[ex_ra2]
    accessor ex_rs3 = regfile[ex_ra3]
    node T_194232 = bits(ex_reg_inst, 14, 12)
    node T_194233 = eq(T_194232, UInt<3>(7))
    node T_194234 = bits(ex_reg_inst, 14, 12)
    wire ex_rm : UInt<3>
    ex_rm := T_194234
    when T_194233 : ex_rm := fcsr_rm
    wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}
    req := ex_ctrl
    req.rm := ex_rm
    req.in1 := ex_rs1
    req.in2 := ex_rs2
    req.in3 := ex_rs3
    node T_194235 = bits(ex_reg_inst, 21, 20)
    req.typ := T_194235
    inst sfma of FPUFMAPipe
    node T_194236 = and(ex_reg_valid, ex_ctrl.fma)
    node T_194237 = and(T_194236, ex_ctrl.single)
    sfma.in.valid := T_194237
    sfma.in.bits := req
    inst dfma of FPUFMAPipe_160964
    node T_194238 = and(ex_reg_valid, ex_ctrl.fma)
    node T_194239 = eq(ex_ctrl.single, UInt<1>(0))
    node T_194240 = and(T_194238, T_194239)
    dfma.in.valid := T_194240
    dfma.in.bits := req
    inst fpiu of FPToInt
    node T_194241 = or(ex_ctrl.toint, ex_ctrl.div)
    node T_194242 = or(T_194241, ex_ctrl.sqrt)
    node T_194243 = and(ex_ctrl.cmd, UInt<4>(13))
    node T_194244 = eq(UInt<3>(5), T_194243)
    node T_194245 = or(T_194242, T_194244)
    node T_194246 = and(ex_reg_valid, T_194245)
    fpiu.in.valid := T_194246
    fpiu.in.bits := req
    store_data := fpiu.out.bits.store
    toint_data := fpiu.out.bits.toint
    inst ifpu of IntToFP
    node T_194247 = and(ex_reg_valid, ex_ctrl.fromint)
    ifpu.in.valid := T_194247
    ifpu.in.bits := req
    ifpu.in.bits.in1 := fromint_data
    inst fpmu of FPToFP
    node T_194248 = and(ex_reg_valid, ex_ctrl.fastpipe)
    fpmu.in.valid := T_194248
    fpmu.in.bits := req
    fpmu.lt := fpiu.out.bits.lt
    reg divSqrt_wen : UInt<1>
    divSqrt_wen := UInt<1>(0)
    wire divSqrt_inReady : UInt<1>
    divSqrt_inReady := UInt<1>(0)
    reg divSqrt_waddr : UInt
    wire divSqrt_wdata : UInt
    wire divSqrt_flags : UInt
    reg divSqrt_in_flight : UInt<1>
    onreset divSqrt_in_flight := UInt<1>(0)
    node T_194249 = asUInt(SInt<32>(-1))
    node T_194250 = cat(T_194249, sfma.out.bits.data)
    wire T_194251 : UInt<1>
    T_194251 := UInt<1>(0)
    when mem_ctrl.fastpipe : T_194251 := UInt<1>(1)
    wire T_194252 : UInt<1>
    T_194252 := UInt<1>(0)
    when mem_ctrl.fromint : T_194252 := UInt<2>(2)
    node T_194253 = and(mem_ctrl.fma, mem_ctrl.single)
    wire T_194254 : UInt<1>
    T_194254 := UInt<1>(0)
    when T_194253 : T_194254 := UInt<1>(1)
    node T_194255 = eq(mem_ctrl.single, UInt<1>(0))
    node T_194256 = and(mem_ctrl.fma, T_194255)
    wire T_194257 : UInt<1>
    T_194257 := UInt<1>(0)
    when T_194256 : T_194257 := UInt<2>(2)
    node T_194258 = or(T_194251, T_194252)
    node T_194259 = or(T_194258, T_194254)
    node memLatencyMask = or(T_194259, T_194257)
    reg wen : UInt<2>
    onreset wen := UInt<2>(0)
    wire T_194260 : UInt[2]
    T_194260[0] := T_194261
    T_194260[1] := T_194262
    reg winfo : UInt[2]
    node T_194263 = or(mem_ctrl.fma, mem_ctrl.fastpipe)
    node T_194264 = or(T_194263, mem_ctrl.fromint)
    node mem_wen = and(mem_reg_valid, T_194264)
    wire T_194265 : UInt<1>
    T_194265 := UInt<1>(0)
    when ex_ctrl.fastpipe : T_194265 := UInt<2>(2)
    wire T_194266 : UInt<1>
    T_194266 := UInt<1>(0)
    when ex_ctrl.fromint : T_194266 := UInt<3>(4)
    node T_194267 = and(ex_ctrl.fma, ex_ctrl.single)
    wire T_194268 : UInt<1>
    T_194268 := UInt<1>(0)
    when T_194267 : T_194268 := UInt<2>(2)
    node T_194269 = eq(ex_ctrl.single, UInt<1>(0))
    node T_194270 = and(ex_ctrl.fma, T_194269)
    wire T_194271 : UInt<1>
    T_194271 := UInt<1>(0)
    when T_194270 : T_194271 := UInt<3>(4)
    node T_194272 = or(T_194265, T_194266)
    node T_194273 = or(T_194272, T_194268)
    node T_194274 = or(T_194273, T_194271)
    node T_194275 = and(memLatencyMask, T_194274)
    node T_194276 = eq(T_194275, UInt<1>(0))
    node T_194277 = eq(T_194276, UInt<1>(0))
    node T_194278 = and(mem_wen, T_194277)
    wire T_194279 : UInt<1>
    T_194279 := UInt<1>(0)
    when ex_ctrl.fastpipe : T_194279 := UInt<3>(4)
    wire T_194280 : UInt<1>
    T_194280 := UInt<1>(0)
    when ex_ctrl.fromint : T_194280 := UInt<4>(8)
    node T_194281 = and(ex_ctrl.fma, ex_ctrl.single)
    wire T_194282 : UInt<1>
    T_194282 := UInt<1>(0)
    when T_194281 : T_194282 := UInt<3>(4)
    node T_194283 = eq(ex_ctrl.single, UInt<1>(0))
    node T_194284 = and(ex_ctrl.fma, T_194283)
    wire T_194285 : UInt<1>
    T_194285 := UInt<1>(0)
    when T_194284 : T_194285 := UInt<4>(8)
    node T_194286 = or(T_194279, T_194280)
    node T_194287 = or(T_194286, T_194282)
    node T_194288 = or(T_194287, T_194285)
    node T_194289 = and(wen, T_194288)
    node T_194290 = eq(T_194289, UInt<1>(0))
    node T_194291 = eq(T_194290, UInt<1>(0))
    node T_194292 = or(T_194278, T_194291)
    reg write_port_busy : UInt<1>
    when ex_reg_valid : write_port_busy := T_194292
    wire T_194293 : UInt<1>
    T_194293 := UInt<1>(0)
    when mem_ctrl.fastpipe : T_194293 := UInt<1>(0)
    wire T_194294 : UInt<1>
    T_194294 := UInt<1>(0)
    when mem_ctrl.fromint : T_194294 := UInt<1>(1)
    node T_194295 = and(mem_ctrl.fma, mem_ctrl.single)
    wire T_194296 : UInt<1>
    T_194296 := UInt<1>(0)
    when T_194295 : T_194296 := UInt<2>(2)
    node T_194297 = eq(mem_ctrl.single, UInt<1>(0))
    node T_194298 = and(mem_ctrl.fma, T_194297)
    wire T_194299 : UInt<1>
    T_194299 := UInt<1>(0)
    when T_194298 : T_194299 := UInt<2>(3)
    node T_194300 = or(T_194293, T_194294)
    node T_194301 = or(T_194300, T_194296)
    node T_194302 = or(T_194301, T_194299)
    node T_194303 = bits(mem_reg_inst, 11, 7)
    node mem_winfo = cat(T_194302, T_194303)
    
    node T_194304 = bit(wen, 1)
    when T_194304 : winfo[0] := winfo[1]
    node T_194305 = shr(wen, 1)
    wen := T_194305
    when mem_wen : 
      
      node T_194306 = eq(killm, UInt<1>(0))
      when T_194306 : 
        node T_194307 = shr(wen, 1)
        node T_194308 = or(T_194307, memLatencyMask)
        wen := T_194308
      
      
      node T_194309 = eq(write_port_busy, UInt<1>(0))
      node T_194310 = bit(memLatencyMask, 0)
      node T_194311 = and(T_194309, T_194310)
      when T_194311 : winfo[0] := mem_winfo
      
      
      node T_194312 = eq(write_port_busy, UInt<1>(0))
      node T_194313 = bit(memLatencyMask, 1)
      node T_194314 = and(T_194312, T_194313)
      when T_194314 : winfo[1] := mem_winfo
    node T_194315 = bits(winfo[0], 4, 0)
    wire waddr : UInt<5>
    waddr := T_194315
    when divSqrt_wen : waddr := divSqrt_waddr
    node wsrc = shr(winfo[0], 5)
    wire T_194316 : UInt<65>[4]
    T_194316[0] := fpmu.out.bits.data
    T_194316[1] := ifpu.out.bits.data
    T_194316[2] := T_194250
    T_194316[3] := dfma.out.bits.data
    accessor T_194317 = T_194316[wsrc]
    wire wdata : UInt<65>
    wdata := T_194317
    when divSqrt_wen : wdata := divSqrt_wdata
    wire T_194318 : UInt<5>[4]
    T_194318[0] := fpmu.out.bits.exc
    T_194318[1] := ifpu.out.bits.exc
    T_194318[2] := sfma.out.bits.exc
    T_194318[3] := dfma.out.bits.exc
    accessor wexc = T_194318[wsrc]
    
    
    node T_194319 = bit(wen, 0)
    node T_194320 = or(T_194319, divSqrt_wen)
    when T_194320 : 
      accessor T_194321 = regfile[waddr]
      T_194321 := wdata
    node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint)
    reg wb_toint_exc : UInt<5>
    when mem_ctrl.toint : wb_toint_exc := fpiu.out.bits.exc
    node T_194322 = or(wb_toint_valid, divSqrt_wen)
    node T_194323 = bit(wen, 0)
    node T_194324 = or(T_194322, T_194323)
    fcsr_flags.valid := T_194324
    wire T_194325 : UInt<1>
    T_194325 := UInt<1>(0)
    when wb_toint_valid : T_194325 := wb_toint_exc
    wire T_194326 : UInt<1>
    T_194326 := UInt<1>(0)
    when divSqrt_wen : T_194326 := divSqrt_flags
    node T_194327 = or(T_194325, T_194326)
    node T_194328 = bit(wen, 0)
    wire T_194329 : UInt<1>
    T_194329 := UInt<1>(0)
    when T_194328 : T_194329 := wexc
    node T_194330 = or(T_194327, T_194329)
    fcsr_flags.bits := T_194330
    node T_194331 = or(mem_ctrl.div, mem_ctrl.sqrt)
    node T_194332 = and(mem_reg_valid, T_194331)
    node T_194333 = eq(divSqrt_inReady, UInt<1>(0))
    node T_194334 = eq(wen, UInt<1>(0))
    node T_194335 = eq(T_194334, UInt<1>(0))
    node T_194336 = or(T_194333, T_194335)
    node units_busy = and(T_194332, T_194336)
    node T_194337 = and(ex_reg_valid, ex_ctrl.wflags)
    node T_194338 = and(mem_reg_valid, mem_ctrl.wflags)
    node T_194339 = or(T_194337, T_194338)
    node T_194340 = and(wb_reg_valid, wb_ctrl.toint)
    node T_194341 = or(T_194339, T_194340)
    node T_194342 = eq(wen, UInt<1>(0))
    node T_194343 = eq(T_194342, UInt<1>(0))
    node T_194344 = or(T_194341, T_194343)
    node T_194345 = or(T_194344, divSqrt_in_flight)
    node T_194346 = eq(T_194345, UInt<1>(0))
    fcsr_rdy := T_194346
    node T_194347 = or(units_busy, write_port_busy)
    node T_194348 = or(T_194347, divSqrt_in_flight)
    nack_mem := T_194348
    dec <> fp_decoder.sigs
    node T_194349 = or(UInt<1>(0), mem_ctrl.div)
    node T_194350 = or(T_194349, mem_ctrl.sqrt)
    reg T_194351 : UInt<1>
    T_194351 := T_194350
    node T_194352 = and(wb_reg_valid, T_194351)
    sboard_set := T_194352
    node T_194353 = bit(wen, 0)
    node T_194354 = and(T_194353, UInt<1>(0))
    node T_194355 = or(divSqrt_wen, T_194354)
    sboard_clr := T_194355
    sboard_clra := waddr
    node T_194356 = bit(ex_rm, 2)
    node T_194357 = and(T_194356, ex_ctrl.round)
    illegal_rm := T_194357
    divSqrt_wdata := UInt<1>(0)
    divSqrt_flags := UInt<1>(0)
    reg T_194358 : UInt<1>
    reg T_194359 : UInt
    reg T_194360 : UInt
    reg T_194361 : UInt
    inst T_194362 of divSqrtRecodedFloat64
    wire T_194363 : UInt<1>
    T_194363 := T_194362.inReady_div
    when T_194362.sqrtOp : T_194363 := T_194362.inReady_sqrt
    divSqrt_inReady := T_194363
    node T_194364 = or(T_194362.outValid_div, T_194362.outValid_sqrt)
    node T_194365 = eq(wen, UInt<1>(0))
    node T_194366 = eq(T_194365, UInt<1>(0))
    node T_194367 = eq(T_194366, UInt<1>(0))
    node T_194368 = and(mem_reg_valid, T_194367)
    node T_194369 = eq(divSqrt_in_flight, UInt<1>(0))
    node T_194370 = and(T_194368, T_194369)
    node T_194371 = eq(killm, UInt<1>(0))
    node T_194372 = and(T_194370, T_194371)
    node T_194373 = or(mem_ctrl.div, mem_ctrl.sqrt)
    node T_194374 = and(T_194372, T_194373)
    T_194362.inValid := T_194374
    T_194362.sqrtOp := mem_ctrl.sqrt
    T_194362.a := fpiu.as_double.in1
    T_194362.b := fpiu.as_double.in2
    T_194362.roundingMode := fpiu.as_double.rm
    
    node T_194375 = and(T_194362.inValid, divSqrt_inReady)
    when T_194375 : 
      divSqrt_in_flight := UInt<1>(1)
      T_194358 := mem_ctrl.single
      node T_194376 = bits(mem_reg_inst, 11, 7)
      divSqrt_waddr := T_194376
      T_194359 := T_194362.roundingMode
    when T_194364 : 
      divSqrt_wen := UInt<1>(1)
      T_194361 := T_194362.out
      divSqrt_in_flight := UInt<1>(0)
      T_194360 := T_194362.exceptionFlags
    node T_194377 = bit(T_194361, 64)
    node T_194378 = bits(T_194361, 51, 0)
    node T_194379 = bits(T_194361, 63, 52)
    node T_194380 = bits(T_194361, 63, 61)
    node T_194381 = bits(T_194361, 62, 52)
    node T_194382 = eq(T_194380, UInt<1>(-1))
    node T_194383 = bit(T_194378, 51)
    node T_194384 = eq(T_194383, UInt<1>(0))
    node T_194385 = and(T_194382, T_194384)
    node T_194386 = eq(T_194380, UInt<1>(0))
    node T_194387 = eq(T_194386, UInt<1>(0))
    node T_194388 = eq(T_194387, UInt<1>(0))
    node T_194389 = bits(T_194380, 2, 1)
    node T_194390 = eq(T_194389, UInt<1>(-1))
    node T_194391 = or(T_194388, T_194390)
    node T_194392 = geq(T_194379, UInt<11>(1898))
    node T_194393 = leq(T_194379, UInt<11>(1921))
    node T_194394 = and(T_194392, T_194393)
    node T_194395 = lt(T_194379, UInt<11>(1898))
    node T_194396 = eq(T_194391, UInt<1>(0))
    node T_194397 = and(T_194395, T_194396)
    node T_194398 = gt(T_194379, UInt<12>(2175))
    node T_194399 = eq(T_194391, UInt<1>(0))
    node T_194400 = and(T_194398, T_194399)
    node T_194401 = addw(UInt<11>(1921), UInt<1>(1))
    node T_194402 = subw(T_194401, T_194379)
    wire T_194403 : UInt<1>
    T_194403 := UInt<1>(0)
    when T_194394 : T_194403 := T_194402
    node T_194404 = bits(T_194403, 4, 0)
    node T_194405 = bits(T_194378, 51, 28)
    node T_194406 = cat(T_194405, UInt<24>(0))
    node T_194407 = cat(UInt<1>(1), T_194406)
    node T_194408 = dshr(T_194407, T_194404)
    node T_194409 = bits(T_194408, 23, 0)
    node T_194410 = neq(T_194409, UInt<1>(0))
    node T_194411 = bits(T_194378, 27, 0)
    node T_194412 = neq(T_194411, UInt<1>(0))
    node T_194413 = or(T_194410, T_194412)
    node T_194414 = bits(T_194408, 25, 24)
    node T_194415 = cat(T_194414, T_194413)
    node T_194416 = bits(T_194415, 1, 0)
    node T_194417 = neq(T_194416, UInt<1>(0))
    node T_194418 = eq(T_194391, UInt<1>(0))
    node T_194419 = and(T_194417, T_194418)
    node T_194420 = eq(ex_rm, UInt<2>(0))
    node T_194421 = bits(T_194415, 1, 0)
    node T_194422 = eq(T_194421, UInt<1>(-1))
    node T_194423 = bits(T_194415, 2, 1)
    node T_194424 = eq(T_194423, UInt<1>(-1))
    node T_194425 = or(T_194422, T_194424)
    node T_194426 = eq(ex_rm, UInt<2>(2))
    node T_194427 = and(T_194377, T_194419)
    node T_194428 = eq(ex_rm, UInt<2>(3))
    node T_194429 = eq(T_194377, UInt<1>(0))
    node T_194430 = and(T_194429, T_194419)
    wire T_194431 : UInt<1>
    T_194431 := UInt<1>(0)
    when T_194428 : T_194431 := T_194430
    wire T_194432 : UInt<1>
    T_194432 := T_194431
    when T_194426 : T_194432 := T_194427
    wire T_194433 : UInt<1>
    T_194433 := T_194432
    when T_194420 : T_194433 := T_194425
    node T_194434 = dshl(UInt<25>(33554431), T_194404)
    node T_194435 = bits(T_194434, 24, 0)
    node T_194436 = bits(T_194378, 51, 29)
    node T_194437 = cat(UInt<2>(1), T_194436)
    node T_194438 = not(T_194435)
    node T_194439 = or(T_194437, T_194438)
    node T_194440 = addw(T_194439, UInt<1>(1))
    wire T_194441 : UInt<25>
    T_194441 := T_194439
    when T_194433 : T_194441 := T_194440
    node T_194442 = bits(T_194379, 8, 0)
    node T_194443 = addw(T_194442, UInt<9>(256))
    node T_194444 = bit(T_194441, 24)
    node T_194445 = addw(T_194443, UInt<1>(1))
    wire T_194446 : UInt<9>
    T_194446 := T_194443
    when T_194444 : T_194446 := T_194445
    node T_194447 = eq(ex_rm, UInt<2>(2))
    node T_194448 = and(T_194447, T_194377)
    node T_194449 = eq(ex_rm, UInt<2>(3))
    node T_194450 = eq(T_194377, UInt<1>(0))
    node T_194451 = and(T_194449, T_194450)
    node T_194452 = or(T_194448, T_194451)
    node T_194453 = eq(ex_rm, UInt<2>(0))
    node T_194454 = or(T_194452, T_194453)
    node T_194455 = eq(T_194454, UInt<1>(0))
    node T_194456 = subw(UInt<23>(0), UInt<5>(23))
    wire T_194457 : UInt<9>
    T_194457 := UInt<9>(383)
    when T_194454 : T_194457 := UInt<9>(384)
    wire T_194458 : UInt<1>
    T_194458 := UInt<1>(0)
    when T_194452 : T_194458 := UInt<7>(107)
    node T_194459 = dshl(T_194380, UInt<3>(6))
    wire T_194460 : UInt<9>
    T_194460 := T_194446
    when T_194397 : T_194460 := T_194458
    wire T_194461 : UInt<9>
    T_194461 := T_194460
    when T_194400 : T_194461 := T_194457
    wire T_194462 : UInt<9>
    T_194462 := T_194461
    when T_194391 : T_194462 := T_194459
    node T_194463 = subw(UInt<23>(0), UInt<5>(23))
    node T_194464 = bits(T_194441, 22, 0)
    wire T_194465 : UInt<23>
    T_194465 := T_194464
    when T_194397 : T_194465 := UInt<1>(0)
    wire T_194466 : UInt<23>
    T_194466 := T_194465
    when T_194400 : T_194466 := T_194456
    wire T_194467 : UInt<23>
    T_194467 := T_194466
    when T_194391 : T_194467 := T_194463
    node T_194468 = cat(T_194462, T_194467)
    node T_194469 = cat(T_194377, T_194468)
    node T_194470 = and(T_194394, T_194419)
    node T_194471 = or(T_194397, T_194470)
    node T_194472 = eq(T_194379, UInt<12>(2175))
    node T_194473 = bit(T_194441, 24)
    node T_194474 = and(T_194472, T_194473)
    node T_194475 = or(T_194400, T_194474)
    node T_194476 = or(T_194419, T_194400)
    node T_194477 = or(T_194476, T_194397)
    node T_194478 = cat(T_194385, UInt<1>(0))
    node T_194479 = cat(T_194471, T_194477)
    node T_194480 = cat(T_194475, T_194479)
    node T_194481 = cat(T_194478, T_194480)
    wire T_194482 : UInt
    T_194482 := T_194361
    when T_194358 : T_194482 := T_194469
    divSqrt_wdata := T_194482
    wire T_194483 : UInt<1>
    T_194483 := UInt<1>(0)
    when T_194358 : T_194483 := T_194481
    node T_194484 = or(T_194360, T_194483)
    divSqrt_flags := T_194484
  module RocketTile : 
    output cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, r_type : UInt<3>, voluntary : UInt<1>}}}
    output uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<1>, addr_beat : UInt<2>, data : UInt<128>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, data : UInt<128>, client_xact_id : UInt<1>, manager_xact_id : UInt<2>, is_builtin_type : UInt<1>, g_type : UInt<4>}}}
    output host : {flip reset : UInt<1>, flip id : UInt<1>, flip pcr_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, pcr_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, ipi_req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, flip ipi_rep : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, debug_stats_pcr : UInt<1>}
    
    wire T_194485 : UInt<3>[3]
    T_194485[0] := UInt<3>(0)
    T_194485[1] := UInt<3>(1)
    T_194485[2] := UInt<3>(2)
    wire T_194486 : UInt<2>[2]
    T_194486[0] := UInt<2>(0)
    T_194486[1] := UInt<2>(1)
    wire T_194487 : UInt<2>[3]
    T_194487[0] := UInt<2>(1)
    T_194487[1] := UInt<2>(2)
    T_194487[2] := UInt<2>(3)
    wire T_194488 : UInt<2>[2]
    T_194488[0] := UInt<2>(2)
    T_194488[1] := UInt<2>(3)
    wire T_194489 : UInt<2>[1]
    T_194489[0] := UInt<2>(3)
    wire T_194490 : UInt<3>[3]
    T_194490[0] := UInt<3>(0)
    T_194490[1] := UInt<3>(1)
    T_194490[2] := UInt<3>(2)
    wire T_194491 : UInt<2>[2]
    T_194491[0] := UInt<2>(0)
    T_194491[1] := UInt<2>(1)
    wire T_194492 : UInt<2>[3]
    T_194492[0] := UInt<2>(1)
    T_194492[1] := UInt<2>(2)
    T_194492[2] := UInt<2>(3)
    wire T_194493 : UInt<2>[2]
    T_194493[0] := UInt<2>(2)
    T_194493[1] := UInt<2>(3)
    wire T_194494 : UInt<2>[1]
    T_194494[0] := UInt<2>(3)
    wire T_194495 : UInt<3>[3]
    T_194495[0] := UInt<3>(0)
    T_194495[1] := UInt<3>(1)
    T_194495[2] := UInt<3>(2)
    wire T_194496 : UInt<2>[2]
    T_194496[0] := UInt<2>(0)
    T_194496[1] := UInt<2>(1)
    wire T_194497 : UInt<2>[3]
    T_194497[0] := UInt<2>(1)
    T_194497[1] := UInt<2>(2)
    T_194497[2] := UInt<2>(3)
    wire T_194498 : UInt<2>[2]
    T_194498[0] := UInt<2>(2)
    T_194498[1] := UInt<2>(3)
    wire T_194499 : UInt<2>[1]
    T_194499[0] := UInt<2>(3)
    wire T_194500 : UInt<3>[3]
    T_194500[0] := UInt<3>(0)
    T_194500[1] := UInt<3>(1)
    T_194500[2] := UInt<3>(2)
    wire T_194501 : UInt<2>[2]
    T_194501[0] := UInt<2>(0)
    T_194501[1] := UInt<2>(1)
    wire T_194502 : UInt<2>[3]
    T_194502[0] := UInt<2>(1)
    T_194502[1] := UInt<2>(2)
    T_194502[2] := UInt<2>(3)
    wire T_194503 : UInt<2>[2]
    T_194503[0] := UInt<2>(2)
    T_194503[1] := UInt<2>(3)
    wire T_194504 : UInt<2>[1]
    T_194504[0] := UInt<2>(3)
    wire T_194505 : UInt<3>[3]
    T_194505[0] := UInt<3>(0)
    T_194505[1] := UInt<3>(1)
    T_194505[2] := UInt<3>(2)
    wire T_194506 : UInt<2>[2]
    T_194506[0] := UInt<2>(0)
    T_194506[1] := UInt<2>(1)
    wire T_194507 : UInt<2>[3]
    T_194507[0] := UInt<2>(1)
    T_194507[1] := UInt<2>(2)
    T_194507[2] := UInt<2>(3)
    wire T_194508 : UInt<2>[2]
    T_194508[0] := UInt<2>(2)
    T_194508[1] := UInt<2>(3)
    wire T_194509 : UInt<2>[1]
    T_194509[0] := UInt<2>(3)
    wire T_194510 : UInt<3>[3]
    T_194510[0] := UInt<3>(0)
    T_194510[1] := UInt<3>(1)
    T_194510[2] := UInt<3>(2)
    wire T_194511 : UInt<2>[2]
    T_194511[0] := UInt<2>(0)
    T_194511[1] := UInt<2>(1)
    wire T_194512 : UInt<2>[3]
    T_194512[0] := UInt<2>(1)
    T_194512[1] := UInt<2>(2)
    T_194512[2] := UInt<2>(3)
    wire T_194513 : UInt<2>[2]
    T_194513[0] := UInt<2>(2)
    T_194513[1] := UInt<2>(3)
    wire T_194514 : UInt<2>[1]
    T_194514[0] := UInt<2>(3)
    wire T_194515 : UInt<3>[3]
    T_194515[0] := UInt<3>(0)
    T_194515[1] := UInt<3>(1)
    T_194515[2] := UInt<3>(2)
    wire T_194516 : UInt<2>[2]
    T_194516[0] := UInt<2>(0)
    T_194516[1] := UInt<2>(1)
    wire T_194517 : UInt<2>[3]
    T_194517[0] := UInt<2>(1)
    T_194517[1] := UInt<2>(2)
    T_194517[2] := UInt<2>(3)
    wire T_194518 : UInt<2>[2]
    T_194518[0] := UInt<2>(2)
    T_194518[1] := UInt<2>(3)
    wire T_194519 : UInt<2>[1]
    T_194519[0] := UInt<2>(3)
    wire T_194520 : UInt<3>[3]
    T_194520[0] := UInt<3>(0)
    T_194520[1] := UInt<3>(1)
    T_194520[2] := UInt<3>(2)
    wire T_194521 : UInt<2>[2]
    T_194521[0] := UInt<2>(0)
    T_194521[1] := UInt<2>(1)
    wire T_194522 : UInt<2>[3]
    T_194522[0] := UInt<2>(1)
    T_194522[1] := UInt<2>(2)
    T_194522[2] := UInt<2>(3)
    wire T_194523 : UInt<2>[2]
    T_194523[0] := UInt<2>(2)
    T_194523[1] := UInt<2>(3)
    wire T_194524 : UInt<2>[1]
    T_194524[0] := UInt<2>(3)
    wire T_194525 : UInt<3>[3]
    T_194525[0] := UInt<3>(0)
    T_194525[1] := UInt<3>(1)
    T_194525[2] := UInt<3>(2)
    wire T_194526 : UInt<2>[2]
    T_194526[0] := UInt<2>(0)
    T_194526[1] := UInt<2>(1)
    wire T_194527 : UInt<2>[3]
    T_194527[0] := UInt<2>(1)
    T_194527[1] := UInt<2>(2)
    T_194527[2] := UInt<2>(3)
    wire T_194528 : UInt<2>[2]
    T_194528[0] := UInt<2>(2)
    T_194528[1] := UInt<2>(3)
    wire T_194529 : UInt<2>[1]
    T_194529[0] := UInt<2>(3)
    wire T_194530 : UInt<3>[3]
    T_194530[0] := UInt<3>(0)
    T_194530[1] := UInt<3>(1)
    T_194530[2] := UInt<3>(2)
    wire T_194531 : UInt<2>[2]
    T_194531[0] := UInt<2>(0)
    T_194531[1] := UInt<2>(1)
    wire T_194532 : UInt<2>[3]
    T_194532[0] := UInt<2>(1)
    T_194532[1] := UInt<2>(2)
    T_194532[2] := UInt<2>(3)
    wire T_194533 : UInt<2>[2]
    T_194533[0] := UInt<2>(2)
    T_194533[1] := UInt<2>(3)
    wire T_194534 : UInt<2>[1]
    T_194534[0] := UInt<2>(3)
    wire T_194535 : UInt<3>[3]
    T_194535[0] := UInt<3>(0)
    T_194535[1] := UInt<3>(1)
    T_194535[2] := UInt<3>(2)
    wire T_194536 : UInt<2>[2]
    T_194536[0] := UInt<2>(0)
    T_194536[1] := UInt<2>(1)
    wire T_194537 : UInt<2>[3]
    T_194537[0] := UInt<2>(1)
    T_194537[1] := UInt<2>(2)
    T_194537[2] := UInt<2>(3)
    wire T_194538 : UInt<2>[2]
    T_194538[0] := UInt<2>(2)
    T_194538[1] := UInt<2>(3)
    wire T_194539 : UInt<2>[1]
    T_194539[0] := UInt<2>(3)
    wire T_194540 : UInt<3>[3]
    T_194540[0] := UInt<3>(0)
    T_194540[1] := UInt<3>(1)
    T_194540[2] := UInt<3>(2)
    wire T_194541 : UInt<2>[2]
    T_194541[0] := UInt<2>(0)
    T_194541[1] := UInt<2>(1)
    wire T_194542 : UInt<2>[3]
    T_194542[0] := UInt<2>(1)
    T_194542[1] := UInt<2>(2)
    T_194542[2] := UInt<2>(3)
    wire T_194543 : UInt<2>[2]
    T_194543[0] := UInt<2>(2)
    T_194543[1] := UInt<2>(3)
    wire T_194544 : UInt<2>[1]
    T_194544[0] := UInt<2>(3)
    wire T_194545 : UInt<3>[3]
    T_194545[0] := UInt<3>(0)
    T_194545[1] := UInt<3>(1)
    T_194545[2] := UInt<3>(2)
    wire T_194546 : UInt<2>[2]
    T_194546[0] := UInt<2>(0)
    T_194546[1] := UInt<2>(1)
    wire T_194547 : UInt<2>[3]
    T_194547[0] := UInt<2>(1)
    T_194547[1] := UInt<2>(2)
    T_194547[2] := UInt<2>(3)
    wire T_194548 : UInt<2>[2]
    T_194548[0] := UInt<2>(2)
    T_194548[1] := UInt<2>(3)
    wire T_194549 : UInt<2>[1]
    T_194549[0] := UInt<2>(3)
    wire T_194550 : UInt<3>[3]
    T_194550[0] := UInt<3>(0)
    T_194550[1] := UInt<3>(1)
    T_194550[2] := UInt<3>(2)
    wire T_194551 : UInt<2>[2]
    T_194551[0] := UInt<2>(0)
    T_194551[1] := UInt<2>(1)
    wire T_194552 : UInt<2>[3]
    T_194552[0] := UInt<2>(1)
    T_194552[1] := UInt<2>(2)
    T_194552[2] := UInt<2>(3)
    wire T_194553 : UInt<2>[2]
    T_194553[0] := UInt<2>(2)
    T_194553[1] := UInt<2>(3)
    wire T_194554 : UInt<2>[1]
    T_194554[0] := UInt<2>(3)
    inst icache of Frontend
    inst dcache of HellaCache
    inst ptw of PTW
    inst core of Rocket
    dcache.cpu.invalidate_lr := core.dmem.invalidate_lr
    inst dcArb of HellaCacheArbiter
    dcArb.requestor[0] <> ptw.mem__
    dcArb.requestor[1] <> core.dmem
    dcArb.mem__ <> dcache.cpu
    ptw.requestor[0] <> icache.ptw
    ptw.requestor[1] <> dcache.ptw
    core.host <> host
    core.imem <> icache.cpu
    core.ptw <> ptw.dpath
    inst T_194555 of FPU
    T_194555 <> core.fpu
    cached <> dcache.mem__
    uncached <> icache.mem__
  module Queue_165173 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}
    output count : UInt<2>
    
    cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2]
    reg T_194556 : UInt<1>
    onreset T_194556 := UInt<1>(0)
    reg T_194557 : UInt<1>
    onreset T_194557 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_194556, T_194557)
    node T_194558 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_194558)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_194559 = and(enq.ready, enq.valid)
    node T_194560 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_194559, T_194560)
    node T_194561 = and(deq.ready, deq.valid)
    node T_194562 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_194561, T_194562)
    when do_enq : 
      accessor T_194563 = ram[T_194556]
      T_194563 := enq.bits
      node T_194564 = eq(T_194556, UInt<1>(1))
      node T_194565 = and(UInt<1>(0), T_194564)
      node T_194566 = addw(T_194556, UInt<1>(1))
      wire T_194567 : UInt<1>
      T_194567 := T_194566
      when T_194565 : T_194567 := UInt<1>(0)
      T_194556 := T_194567
    when do_deq : 
      node T_194568 = eq(T_194557, UInt<1>(1))
      node T_194569 = and(UInt<1>(0), T_194568)
      node T_194570 = addw(T_194557, UInt<1>(1))
      wire T_194571 : UInt<1>
      T_194571 := T_194570
      when T_194569 : T_194571 := UInt<1>(0)
      T_194557 := T_194571
    
    node T_194572 = neq(do_enq, do_deq)
    when T_194572 : maybe_full := do_enq
    node T_194573 = eq(empty, UInt<1>(0))
    node T_194574 = and(UInt<1>(0), enq.valid)
    node T_194575 = or(T_194573, T_194574)
    deq.valid := T_194575
    node T_194576 = eq(full, UInt<1>(0))
    node T_194577 = and(UInt<1>(0), deq.ready)
    node T_194578 = or(T_194576, T_194577)
    enq.ready := T_194578
    accessor T_194579 = ram[T_194557]
    wire T_194580 : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}
    T_194580 := T_194579
    when maybe_flow : T_194580 := enq.bits
    deq.bits := T_194580
    node ptr_diff = subw(T_194556, T_194557)
    node T_194581 = and(maybe_full, ptr_match)
    node T_194582 = cat(T_194581, ptr_diff)
    count := T_194582
  module Queue_165245 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}
    output count : UInt<2>
    
    cmem ram : UInt<64>[2]
    reg T_194583 : UInt<1>
    onreset T_194583 := UInt<1>(0)
    reg T_194584 : UInt<1>
    onreset T_194584 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_194583, T_194584)
    node T_194585 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_194585)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_194586 = and(enq.ready, enq.valid)
    node T_194587 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_194586, T_194587)
    node T_194588 = and(deq.ready, deq.valid)
    node T_194589 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_194588, T_194589)
    when do_enq : 
      accessor T_194590 = ram[T_194583]
      T_194590 := enq.bits
      node T_194591 = eq(T_194583, UInt<1>(1))
      node T_194592 = and(UInt<1>(0), T_194591)
      node T_194593 = addw(T_194583, UInt<1>(1))
      wire T_194594 : UInt<1>
      T_194594 := T_194593
      when T_194592 : T_194594 := UInt<1>(0)
      T_194583 := T_194594
    when do_deq : 
      node T_194595 = eq(T_194584, UInt<1>(1))
      node T_194596 = and(UInt<1>(0), T_194595)
      node T_194597 = addw(T_194584, UInt<1>(1))
      wire T_194598 : UInt<1>
      T_194598 := T_194597
      when T_194596 : T_194598 := UInt<1>(0)
      T_194584 := T_194598
    
    node T_194599 = neq(do_enq, do_deq)
    when T_194599 : maybe_full := do_enq
    node T_194600 = eq(empty, UInt<1>(0))
    node T_194601 = and(UInt<1>(0), enq.valid)
    node T_194602 = or(T_194600, T_194601)
    deq.valid := T_194602
    node T_194603 = eq(full, UInt<1>(0))
    node T_194604 = and(UInt<1>(0), deq.ready)
    node T_194605 = or(T_194603, T_194604)
    enq.ready := T_194605
    accessor T_194606 = ram[T_194584]
    wire T_194607 : UInt<64>
    T_194607 := T_194606
    when maybe_flow : T_194607 := enq.bits
    deq.bits := T_194607
    node ptr_diff = subw(T_194583, T_194584)
    node T_194608 = and(maybe_full, ptr_match)
    node T_194609 = cat(T_194608, ptr_diff)
    count := T_194609
  module Queue_165317 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
    output count : UInt<2>
    
    cmem ram : UInt<1>[2]
    reg T_194610 : UInt<1>
    onreset T_194610 := UInt<1>(0)
    reg T_194611 : UInt<1>
    onreset T_194611 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_194610, T_194611)
    node T_194612 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_194612)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_194613 = and(enq.ready, enq.valid)
    node T_194614 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_194613, T_194614)
    node T_194615 = and(deq.ready, deq.valid)
    node T_194616 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_194615, T_194616)
    when do_enq : 
      accessor T_194617 = ram[T_194610]
      T_194617 := enq.bits
      node T_194618 = eq(T_194610, UInt<1>(1))
      node T_194619 = and(UInt<1>(0), T_194618)
      node T_194620 = addw(T_194610, UInt<1>(1))
      wire T_194621 : UInt<1>
      T_194621 := T_194620
      when T_194619 : T_194621 := UInt<1>(0)
      T_194610 := T_194621
    when do_deq : 
      node T_194622 = eq(T_194611, UInt<1>(1))
      node T_194623 = and(UInt<1>(0), T_194622)
      node T_194624 = addw(T_194611, UInt<1>(1))
      wire T_194625 : UInt<1>
      T_194625 := T_194624
      when T_194623 : T_194625 := UInt<1>(0)
      T_194611 := T_194625
    
    node T_194626 = neq(do_enq, do_deq)
    when T_194626 : maybe_full := do_enq
    node T_194627 = eq(empty, UInt<1>(0))
    node T_194628 = and(UInt<1>(0), enq.valid)
    node T_194629 = or(T_194627, T_194628)
    deq.valid := T_194629
    node T_194630 = eq(full, UInt<1>(0))
    node T_194631 = and(UInt<1>(0), deq.ready)
    node T_194632 = or(T_194630, T_194631)
    enq.ready := T_194632
    accessor T_194633 = ram[T_194611]
    wire T_194634 : UInt<1>
    T_194634 := T_194633
    when maybe_flow : T_194634 := enq.bits
    deq.bits := T_194634
    node ptr_diff = subw(T_194610, T_194611)
    node T_194635 = and(maybe_full, ptr_match)
    node T_194636 = cat(T_194635, ptr_diff)
    count := T_194636
  module Queue_165389 : 
    input enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
    output deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}
    output count : UInt<2>
    
    cmem ram : UInt<1>[2]
    reg T_194637 : UInt<1>
    onreset T_194637 := UInt<1>(0)
    reg T_194638 : UInt<1>
    onreset T_194638 := UInt<1>(0)
    reg maybe_full : UInt<1>
    onreset maybe_full := UInt<1>(0)
    node ptr_match = eq(T_194637, T_194638)
    node T_194639 = eq(maybe_full, UInt<1>(0))
    node empty = and(ptr_match, T_194639)
    node full = and(ptr_match, maybe_full)
    node maybe_flow = and(UInt<1>(0), empty)
    node do_flow = and(maybe_flow, deq.ready)
    node T_194640 = and(enq.ready, enq.valid)
    node T_194641 = eq(do_flow, UInt<1>(0))
    node do_enq = and(T_194640, T_194641)
    node T_194642 = and(deq.ready, deq.valid)
    node T_194643 = eq(do_flow, UInt<1>(0))
    node do_deq = and(T_194642, T_194643)
    when do_enq : 
      accessor T_194644 = ram[T_194637]
      T_194644 := enq.bits
      node T_194645 = eq(T_194637, UInt<1>(1))
      node T_194646 = and(UInt<1>(0), T_194645)
      node T_194647 = addw(T_194637, UInt<1>(1))
      wire T_194648 : UInt<1>
      T_194648 := T_194647
      when T_194646 : T_194648 := UInt<1>(0)
      T_194637 := T_194648
    when do_deq : 
      node T_194649 = eq(T_194638, UInt<1>(1))
      node T_194650 = and(UInt<1>(0), T_194649)
      node T_194651 = addw(T_194638, UInt<1>(1))
      wire T_194652 : UInt<1>
      T_194652 := T_194651
      when T_194650 : T_194652 := UInt<1>(0)
      T_194638 := T_194652
    
    node T_194653 = neq(do_enq, do_deq)
    when T_194653 : maybe_full := do_enq
    node T_194654 = eq(empty, UInt<1>(0))
    node T_194655 = and(UInt<1>(0), enq.valid)
    node T_194656 = or(T_194654, T_194655)
    deq.valid := T_194656
    node T_194657 = eq(full, UInt<1>(0))
    node T_194658 = and(UInt<1>(0), deq.ready)
    node T_194659 = or(T_194657, T_194658)
    enq.ready := T_194659
    accessor T_194660 = ram[T_194638]
    wire T_194661 : UInt<1>
    T_194661 := T_194660
    when maybe_flow : T_194661 := enq.bits
    deq.bits := T_194661
    node ptr_diff = subw(T_194637, T_194638)
    node T_194662 = and(maybe_full, ptr_match)
    node T_194663 = cat(T_194662, ptr_diff)
    count := T_194663
  module MultiChannelTop : 
    output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}
    output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    
    wire mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    mem__[0] := T_194664
    inst uncore of Uncore
    inst T_194665 of RocketTile
    T_194665.host.id := UInt<1>(0)
    reg T_194666 : UInt<1>
    T_194666 := uncore.htif[0].reset
    reg T_194667 : UInt<1>
    T_194667 := T_194666
    T_194665.host.reset := T_194667
    inst T_194668 of Queue_165173
    T_194668.enq.valid := uncore.htif[0].pcr_req.valid
    T_194668.enq.bits := uncore.htif[0].pcr_req.bits
    uncore.htif[0].pcr_req.ready := T_194668.enq.ready
    T_194665.host.pcr_req <> T_194668.deq
    inst T_194669 of Queue_165245
    T_194669.enq.valid := T_194665.host.pcr_rep.valid
    T_194669.enq.bits := T_194665.host.pcr_rep.bits
    T_194665.host.pcr_rep.ready := T_194669.enq.ready
    uncore.htif[0].pcr_rep <> T_194669.deq
    inst T_194670 of Queue_165317
    T_194670.enq.valid := T_194665.host.ipi_req.valid
    T_194670.enq.bits := T_194665.host.ipi_req.bits
    T_194665.host.ipi_req.ready := T_194670.enq.ready
    uncore.htif[0].ipi_req <> T_194670.deq
    inst T_194671 of Queue_165389
    T_194671.enq.valid := uncore.htif[0].ipi_rep.valid
    T_194671.enq.bits := uncore.htif[0].ipi_rep.bits
    uncore.htif[0].ipi_rep.ready := T_194671.enq.ready
    T_194665.host.ipi_rep <> T_194671.deq
    uncore.htif[0].debug_stats_pcr := T_194665.host.debug_stats_pcr
    uncore.tiles_cached[0] <> T_194665.cached
    uncore.tiles_uncached[0] <> T_194665.uncached
    uncore.host <> host
    uncore.mem__[0] <> mem__[0]
    uncore.mem_backup_ctrl <> mem_backup_ctrl
  module MemIOArbiter_165478 : 
    input inner : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    output outer : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    
    wire inner : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}[1]
    inner[0] := T_194672
    inner[0] <> outer
  module Top : 
    output host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_pcr : UInt<1>}
    output mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}
    output mem__ : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<128>, tag : UInt<5>}}}
    
    inst temp of MultiChannelTop
    inst arb of MemIOArbiter_165478
    arb.inner[0] <> temp.mem__[0]
    mem__ <> arb.outer
    mem_backup_ctrl <> temp.mem_backup_ctrl
    host <> temp.host