blob: 3b120217cb9bac19fa233974a07e0b42f02f8cc7 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
;CHECK: Split Expressions
circuit Top :
module Top :
output out : UInt<1>
output out2 : UInt<1>
wire m : UInt<1>[3]
m[0] := UInt(0)
m[1] := UInt(0)
m[2] := UInt(0)
wire x : UInt<1>
x := not(UInt(1))
infer accessor a = m[x]
out := a
|
