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; RUN: firrtl %s abcdef cg | tee %s.out | FileCheck %s
;CHECK: Resolve Genders
circuit top :
module source :
output bundle : { data : UInt(16), flip ready : UInt(1) }
module sink :
input bundle : { data : UInt(16), flip ready : UInt(1) }
module top :
inst src of source
inst snk of sink
snk.bundle := src.bundle
; CHECK: Finished Resolve Genders
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