blob: 931372cb1af188a68e9a4a79e0e7a7cba4497643 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
|
; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s
;CHECK: Resolve Genders
circuit top :
module top :
wire m : UInt(32)[10][10][10]
wire i : UInt
accessor a = m[i] ;CHECK: accessor a = m@<g:male>[i@<g:male>]@<g:male>
accessor b = a[i] ;CHECK: accessor b = a@<g:male>[i@<g:male>]@<g:male>
accessor c = b[i] ;CHECK: accessor c = b@<g:male>[i@<g:male>]@<g:male>
wire j : UInt
j := c
accessor x = m[i] ;CHECK: accessor x = m@<g:female>[i@<g:male>]@<g:female>
accessor y = x[i] ;CHECK: accessor y = x@<g:female>[i@<g:male>]@<g:female>
accessor z = y[i] ;CHECK: accessor z = y@<g:female>[i@<g:male>]@<g:female>
z := j
; CHECK: Finished Resolve Genders
|
