1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
|
; RUN: firrtl -i %s -o %s.flo -x X -p cd | tee %s.out | FileCheck %s
; CHECK: Done!
circuit RegisterVecShift :
module RegisterVecShift :
input load : UInt(1)
output out : UInt(4)
input shift : UInt(1)
input ins : UInt(4)[4]
reg delays : UInt(4)[4]
when reset :
node T_38 = UInt(0, 4)
node T_39 = UInt(0, 4)
node T_40 = UInt(0, 4)
node T_41 = UInt(0, 4)
wire T_42 : UInt(4)[4]
T_42.0 := T_38
T_42.1 := T_39
T_42.2 := T_40
T_42.3 := T_41
delays := T_42
node T_43 = UInt(5, 3)
node T_44 = bit-and(Pad(T_43,?), Pad(load,?))
node T_45 = UInt(4, 3)
node T_46 = eq(Pad(T_44,?), Pad(T_45,?))
when T_46 :
delays.0 := Pad(ins.0,?)
delays.1 := Pad(ins.1,?)
delays.2 := Pad(ins.2,?)
delays.3 := Pad(ins.3,?)
else : when shift :
delays.0 := Pad(ins.0,?)
delays.1 := Pad(delays.0,?)
delays.2 := Pad(delays.1,?)
delays.3 := Pad(delays.2,?)
out := Pad(delays.3,?)
|
