test/passes/infer-widths/simple.fir


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; RUN: firrtl %s abcefghipjk cT | tee %s.out | FileCheck %s

;CHECK: Infer Widths
circuit top :
   module top :
      wire e : UInt(30)
      reg y : UInt
      y := e
   

; CHECK: Finished Infer Widths