test/errors/high-form/NegWidth.fir


1
2
3
4
5
6
7

; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
; CHECK: Width cannot be negative.

circuit Top : 
  module Top : 
    wire x : UInt<-3>