test/chisel3/Test.fir


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; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
; CHECK: Done!

circuit Test : 
  module Test : 
     wire x : UInt
     x := UInt(0)
     x := UInt(1)
     x := UInt(10)
     x := UInt(21474836)
     x := UInt("h21474836")