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|
;RUN: firrtl %s abcefghipjklmno c | tee %s.out | FileCheck %s
;CHECK: To Flo
circuit BundleWire :
module BundleWire :
output in : {flip y : UInt(32), flip x : UInt(32)}
output outs : {y : UInt(32), x : UInt(32)}[4]
wire coords : {y : UInt(32), x : UInt(32)}[4]
coords.0 := in
outs.0 := coords.0
coords.1 := in
outs.1 := coords.1
coords.2 := in
outs.2 := coords.2
coords.3 := in
outs.3 := coords.3
;CHECK: Finished To Flo
|
