aboutsummaryrefslogtreecommitdiff
path: root/src/test/scala/firrtlTests/transforms/DedupTests.scala
blob: bea352eff46929e86dc250c46150a501a6e4be8d (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
// See LICENSE for license details.

package firrtlTests
package transform

import java.io.StringWriter

import org.scalatest.FlatSpec
import org.scalatest.Matchers
import org.scalatest.junit.JUnitRunner

import firrtl.ir.Circuit
import firrtl.Parser
import firrtl.passes.PassExceptions
import firrtl.Annotations.{
   Named,
   CircuitName,
   Annotation,
   AnnotationMap
}
import firrtl.transforms.{DedupModules, DedupAnnotation}


/**
 * Tests inline instances transformation
 */
class DedupModuleTests extends HighTransformSpec {
   def transform = new DedupModules
   "The module A" should "be deduped" in {
      val input =
         """circuit Top :
           |  module Top :
           |    inst a1 of A
           |    inst a2 of A_
           |  module A :
           |    output x: UInt<1>
           |    x <= UInt(1)
           |  module A_ :
           |    output x: UInt<1>
           |    x <= UInt(1)
           """.stripMargin
      val check =
         """circuit Top :
           |  module Top :
           |    inst a1 of A
           |    inst a2 of A
           |  module A :
           |    output x: UInt<1>
           |    x <= UInt(1)
           """.stripMargin
      val writer = new StringWriter()
      val aMap = new AnnotationMap(Nil)
      execute(writer, aMap, input, check)
   }
   "The module A and B" should "be deduped" in {
      val input =
         """circuit Top :
           |  module Top :
           |    inst a1 of A
           |    inst a2 of A_
           |  module A :
           |    output x: UInt<1>
           |    inst b of B
           |    x <= b.x
           |  module A_ :
           |    output x: UInt<1>
           |    inst b of B_
           |    x <= b.x
           |  module B :
           |    output x: UInt<1>
           |    x <= UInt(1)
           |  module B_ :
           |    output x: UInt<1>
           |    x <= UInt(1)
           """.stripMargin
      val check =
         """circuit Top :
           |  module Top :
           |    inst a1 of A
           |    inst a2 of A
           |  module A :
           |    output x: UInt<1>
           |    inst b of B
           |    x <= b.x
           |  module B :
           |    output x: UInt<1>
           |    x <= UInt(1)
           """.stripMargin
      val writer = new StringWriter()
      val aMap = new AnnotationMap(Nil)
      execute(writer, aMap, input, check)
   }
}

// Execution driven tests for inlining modules
// TODO(izraelevitz) fix this test
//class InlineInstancesIntegrationSpec extends FirrtlPropSpec {
//  // Shorthand for creating annotations to inline modules
//  def inlineModules(names: Seq[String]): Seq[CircuitAnnotation] =
//    Seq(StickyCircuitAnnotation(InlineCAKind, names.map(n => ModuleName(n) -> TagAnnotation).toMap))
//
//  case class Test(name: String, dir: String, ann: Seq[CircuitAnnotation])
//
//  val runTests = Seq(
//    Test("GCDTester", "/integration", inlineModules(Seq("DecoupledGCD")))
//  )
//
//  runTests foreach { test =>
//    property(s"${test.name} should execute correctly with inlining") {
//      println(s"Got annotations ${test.ann}")
//      runFirrtlTest(test.name, test.dir, test.ann)
//    }
//  }
//}