1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
package firrtlTests.analyses
import java.io._
import org.scalatest._
import org.scalatest.prop._
import org.scalatest.Matchers._
import firrtl.analyses.InstanceGraph
import firrtl.graph.DiGraph
import firrtl.Parser.parse
import firrtl.passes._
import firrtlTests._
class InstanceGraphTests extends FirrtlFlatSpec {
private def getEdgeSet(graph: DiGraph[String]): collection.Map[String, collection.Set[String]] = {
(graph.getVertices map {v => (v, graph.getEdges(v))}).toMap
}
it should "recognize a simple hierarchy" in {
val input = """
circuit Top :
module Top :
inst c1 of Child1
inst c2 of Child2
module Child1 :
inst a of Child1a
inst b of Child1b
skip
module Child1a :
skip
module Child1b :
skip
module Child2 :
skip
"""
val circuit = ToWorkingIR.run(parse(input))
val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1", "Child2"), "Child1" -> Set("Child1a", "Child1b"), "Child2" -> Set(), "Child1a" -> Set(), "Child1b" -> Set())
}
it should "recognize disconnected hierarchies" in {
val input = """
circuit Top :
module Top :
inst c of Child1
module Child1 :
skip
module Top2 :
inst a of Child2
inst b of Child3
skip
module Child2 :
inst a of Child2a
inst b of Child2b
skip
module Child2a :
skip
module Child2b :
skip
module Child3 :
skip
"""
val circuit = ToWorkingIR.run(parse(input))
val graph = new InstanceGraph(circuit).graph.transformNodes(_.module)
getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1"), "Top2" -> Set("Child2", "Child3"), "Child2" -> Set("Child2a", "Child2b"), "Child1" -> Set(), "Child2a" -> Set(), "Child2b" -> Set(), "Child3" -> Set())
}
}
|
