1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/*
Copyright (c) 2014 - 2016 The Regents of the University of
California (Regents). All Rights Reserved. Redistribution and use in
source and binary forms, with or without modification, are permitted
provided that the following conditions are met:
* Redistributions of source code must retain the above
copyright notice, this list of conditions and the following
two paragraphs of disclaimer.
* Redistributions in binary form must reproduce the above
copyright notice, this list of conditions and the following
two paragraphs of disclaimer in the documentation and/or other materials
provided with the distribution.
* Neither the name of the Regents nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
MODIFICATIONS.
*/
package firrtlTests
import java.io._
import org.scalatest._
import org.scalatest.prop._
import firrtl._
import firrtl.ir.Circuit
import firrtl.passes._
import firrtl.Parser.IgnoreInfo
class WidthSpec extends FirrtlFlatSpec {
def parse (input:String) = Parser.parse(input.split("\n").toIterator, IgnoreInfo)
private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
val lines = c.serialize.split("\n") map normalized
expected foreach { e =>
lines should contain(e)
}
}
"Add of UInt<2> and SInt<2>" should "return SInt<4>" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths)
val input =
"""circuit Unit :
| module Unit :
| input x: UInt<2>
| input y: SInt<2>
| output z: SInt
| z <= add(x, y)""".stripMargin
val check = Seq( "output z : SInt<4>")
executeTest(input, check, passes)
}
"SInt<2> - UInt<3>" should "return SInt<5>" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths)
val input =
"""circuit Unit :
| module Unit :
| input x: UInt<3>
| input y: SInt<2>
| output z: SInt
| z <= sub(y, x)""".stripMargin
val check = Seq( "output z : SInt<5>")
executeTest(input, check, passes)
}
"Dshl by 32 bits" should "result in an error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths,
CheckWidths)
val input =
"""circuit Unit :
| module Unit :
| input x: UInt<3>
| input y: UInt<32>
| output z: UInt
| z <= dshl(x, y)""".stripMargin
intercept[CheckWidths.WidthTooBig] {
executeTest(input, Nil, passes)
}
}
}
|
