1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
|
// See LICENSE for license details.
package firrtlTests
import java.io._
import org.scalatest._
import org.scalatest.prop._
import firrtl._
import firrtl.ir.Circuit
import firrtl.passes._
import firrtl.Parser.IgnoreInfo
class WidthSpec extends FirrtlFlatSpec {
private def executeTest(input: String, expected: Seq[String], passes: Seq[Pass]) = {
val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
(c: Circuit, p: Pass) => p.run(c)
}
val lines = c.serialize.split("\n") map normalized
expected foreach { e =>
lines should contain(e)
}
}
"Dshl by 20 bits" should "result in an error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths,
CheckWidths)
val input =
"""circuit Unit :
| module Unit :
| input x: UInt<3>
| input y: UInt<32>
| output z: UInt
| z <= dshl(x, y)""".stripMargin
// Throws both DshlTooBig and WidthTooBig
// TODO check message
intercept[PassExceptions] {
executeTest(input, Nil, passes)
}
}
"Width >= MaxWidth" should "result in an error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths,
CheckWidths)
val input =
s"""circuit Unit :
| module Unit :
| input x: UInt<${CheckWidths.MaxWidth}>
""".stripMargin
intercept[CheckWidths.WidthTooBig] {
executeTest(input, Nil, passes)
}
}
"Circular reg depending on reg + 1" should "error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths,
CheckWidths)
val input =
"""circuit Unit :
| module Unit :
| input clock: Clock
| input reset: UInt<1>
| reg r : UInt, clock with :
| reset => (reset, UInt(3))
| node T_7 = add(r, r)
| r <= T_7
|""".stripMargin
intercept[CheckWidths.UninferredWidth] {
executeTest(input, Nil, passes)
}
}
"Add of UInt<2> and SInt<2>" should "error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths)
val input =
"""circuit Unit :
| module Unit :
| input x: UInt<2>
| input y: SInt<2>
| output z: SInt
| z <= add(x, y)""".stripMargin
val check = Seq( "output z : SInt<4>")
intercept[PassExceptions] {
executeTest(input, check, passes)
}
}
"SInt<2> - UInt<3>" should "error" in {
val passes = Seq(
ToWorkingIR,
CheckHighForm,
ResolveKinds,
InferTypes,
CheckTypes,
InferWidths)
val input =
"""circuit Unit :
| module Unit :
| input x: UInt<3>
| input y: SInt<2>
| output z: SInt
| z <= sub(y, x)""".stripMargin
val check = Seq( "output z : SInt<5>")
intercept[PassExceptions] {
executeTest(input, check, passes)
}
}
}
|
