blob: a3b04a94be2b952d0cd0077f276402a686cbc406 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
|
defpackage firrtl/compiler :
import core
import verse
import firrtl/passes
import firrtl/errors
; import firrtl/flo
import firrtl/verilog
import firrtl/ir2
import firrtl/ir-utils
;public defstruct StandardFlo <: Compiler :
; file: String with: (as-method => true)
;public defmethod passes (c:StandardFlo) -> List<Pass> :
; to-list $ [
; CheckHighForm(expand-delin)
; ;; TempElimination()
; ToWorkingIR()
; MakeExplicitReset()
; ResolveKinds()
; CheckKinds()
; InferTypes()
; CheckTypes()
; ResolveGenders()
; CheckGenders()
; ExpandAccessors()
; LowerToGround()
; ExpandIndexedConnects()
; ExpandWhens()
; InferWidths()
; Pad()
; Inline()
; SplitExp()
; ToRealIR()
; SpecialRename(`#,`_)
; SpecialRename(`$,`::)
; CheckHighForm(`::)
; CheckLowForm()
; Flo(file(c))
; ]
public defstruct StandardVerilog <: Compiler :
file: String with: (as-method => true)
public defmethod passes (c:StandardVerilog) -> List<Pass> :
to-list $ [
CheckHighForm(expand-delin)
TempElimination()
ToWorkingIR()
MakeExplicitReset()
ResolveKinds()
CheckKinds()
InferTypes()
CheckTypes()
ResolveGenders()
CheckGenders()
ExpandAccessors()
LowerToGround()
ExpandIndexedConnects()
ExpandWhens()
InferWidths()
Pad()
SplitExp()
ToRealIR()
SpecialRename(`#,`_)
SpecialRename(`$,`__)
CheckHighForm(`__)
CheckLowForm()
Verilog(file(c))
]
;============= DRIVER ======================================
public defn run-passes (c:Circuit,comp:Compiler) :
run-passes(c,passes(comp))
public defn run-passes (c:Circuit,ls:List<Pass>) :
var c*:Circuit = c
println("Compiling!")
if PRINT-CIRCUITS : println("Original Circuit")
if PRINT-CIRCUITS : print(c)
val start-time = current-time-us()
var t = start-time
for p in ls do :
if PRINT-CIRCUITS : println(name(p))
c* = pass(p)(c*)
if PRINT-CIRCUITS : print(c*)
if PRINT-CIRCUITS : println-all(["Finished " name(p) "\n"])
val current-time = current-time-us()
println-all(["Time since start: " current-time - start-time])
println-all(["Time for this pass: " current-time - t])
t = current-time
println("Done!")
|
