1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
// See LICENSE for license details.
package firrtl.passes
import firrtl._
import firrtl.ir._
import firrtl.Utils._
import firrtl.Mappers._
import annotation.tailrec
object CommonSubexpressionElimination extends Pass {
def name = "Common Subexpression Elimination"
private def cseOnce(s: Statement): (Statement, Long) = {
var nEliminated = 0L
val expressions = collection.mutable.HashMap[MemoizedHash[Expression], String]()
val nodes = collection.mutable.HashMap[String, Expression]()
def recordNodes(s: Statement): Statement = s match {
case x: DefNode =>
nodes(x.name) = x.value
expressions.getOrElseUpdate(x.value, x.name)
x
case _ => s map recordNodes
}
def eliminateNodeRef(e: Expression): Expression = e match {
case WRef(name, tpe, kind, gender) => nodes get name match {
case Some(expression) => expressions get expression match {
case Some(cseName) if cseName != name =>
nEliminated += 1
WRef(cseName, tpe, kind, gender)
case _ => e
}
case _ => e
}
case _ => e map eliminateNodeRef
}
def eliminateNodeRefs(s: Statement): Statement = s map eliminateNodeRefs map eliminateNodeRef
recordNodes(s)
(eliminateNodeRefs(s), nEliminated)
}
@tailrec
private def cse(s: Statement): Statement = {
val (res, n) = cseOnce(s)
if (n > 0) cse(res) else res
}
def run(c: Circuit): Circuit = {
val modulesx = c.modules.map {
case m: ExtModule => m
case m: Module => Module(m.info, m.name, m.ports, cse(m.body))
}
Circuit(c.info, modulesx, c.main)
}
}
|
