1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
|
// See LICENSE for license details.
package firrtl
import firrtl.transforms.IdentityTransform
sealed abstract class CoreTransform extends SeqTransform
/** This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting
* circuit has only IR nodes, not WIR.
*/
class ChirrtlToHighFirrtl extends CoreTransform {
def inputForm = ChirrtlForm
def outputForm = HighForm
def transforms = Seq(
passes.CheckChirrtl,
passes.CInferTypes,
passes.CInferMDir,
passes.RemoveCHIRRTL)
}
/** Converts from the bare intermediate representation (ir.scala)
* to a working representation (WIR.scala)
*/
class IRToWorkingIR extends CoreTransform {
def inputForm = HighForm
def outputForm = HighForm
def transforms = Seq(passes.ToWorkingIR)
}
/** Resolves types, kinds, and genders, and checks the circuit legality.
* Operates on working IR nodes and high Firrtl.
*/
class ResolveAndCheck extends CoreTransform {
def inputForm = HighForm
def outputForm = HighForm
def transforms = Seq(
passes.CheckHighForm,
passes.ResolveKinds,
passes.InferTypes,
passes.CheckTypes,
passes.Uniquify,
passes.ResolveKinds,
passes.InferTypes,
passes.ResolveGenders,
passes.CheckGenders,
passes.InferWidths,
passes.CheckWidths)
}
/** Expands aggregate connects, removes dynamic accesses, and when
* statements. Checks for uninitialized values. Must accept a
* well-formed graph.
* Operates on working IR nodes.
*/
class HighFirrtlToMiddleFirrtl extends CoreTransform {
def inputForm = HighForm
def outputForm = MidForm
def transforms = Seq(
passes.PullMuxes,
passes.ReplaceAccesses,
passes.ExpandConnects,
passes.RemoveAccesses,
passes.Uniquify,
passes.ExpandWhens,
passes.CheckInitialization,
passes.ResolveKinds,
passes.InferTypes,
passes.CheckTypes,
passes.ResolveGenders,
passes.InferWidths,
passes.CheckWidths,
passes.ConvertFixedToSInt,
passes.ZeroWidth,
passes.InferTypes)
}
/** Expands all aggregate types into many ground-typed components. Must
* accept a well-formed graph of only middle Firrtl features.
* Operates on working IR nodes.
*/
class MiddleFirrtlToLowFirrtl extends CoreTransform {
def inputForm = MidForm
def outputForm = LowForm
def transforms = Seq(
passes.LowerTypes,
passes.ResolveKinds,
passes.InferTypes,
passes.ResolveGenders,
passes.InferWidths,
passes.Legalize,
new firrtl.transforms.RemoveReset,
new firrtl.transforms.CheckCombLoops,
new firrtl.transforms.RemoveWires)
}
/** Runs a series of optimization passes on LowFirrtl
* @note This is currently required for correct Verilog emission
* TODO Fix the above note
*/
class LowFirrtlOptimization extends CoreTransform {
def inputForm = LowForm
def outputForm = LowForm
def transforms = Seq(
passes.RemoveValidIf,
new firrtl.transforms.ConstantPropagation,
passes.PadWidths,
new firrtl.transforms.ConstantPropagation,
passes.Legalize,
passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
new firrtl.transforms.ConstantPropagation,
passes.SplitExpressions,
new firrtl.transforms.CombineCats,
passes.CommonSubexpressionElimination,
new firrtl.transforms.DeadCodeElimination)
}
/** Runs runs only the optimization passes needed for Verilog emission */
class MinimumLowFirrtlOptimization extends CoreTransform {
def inputForm = LowForm
def outputForm = LowForm
def transforms = Seq(
passes.RemoveValidIf,
passes.Legalize,
passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
passes.SplitExpressions)
}
import CompilerUtils.getLoweringTransforms
import firrtl.transforms.BlackBoxSourceHelper
/** Emits input circuit with no changes
*
* Primarily useful for changing between .fir and .pb serialized formats
*/
class NoneCompiler extends Compiler {
def emitter = new ChirrtlEmitter
def transforms: Seq[Transform] = Seq(new IdentityTransform(ChirrtlForm))
}
/** Emits input circuit
* Will replace Chirrtl constructs with Firrtl
*/
class HighFirrtlCompiler extends Compiler {
def emitter = new HighFirrtlEmitter
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, HighForm)
}
/** Emits middle Firrtl input circuit */
class MiddleFirrtlCompiler extends Compiler {
def emitter = new MiddleFirrtlEmitter
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, MidForm)
}
/** Emits lowered input circuit */
class LowFirrtlCompiler extends Compiler {
def emitter = new LowFirrtlEmitter
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm)
}
/** Emits Verilog */
class VerilogCompiler extends Compiler {
def emitter = new VerilogEmitter
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++
Seq(new LowFirrtlOptimization)
}
/** Emits Verilog without optimizations */
class MinimumVerilogCompiler extends Compiler {
def emitter = new MinimumVerilogEmitter
def transforms: Seq[Transform] = getLoweringTransforms(ChirrtlForm, LowForm) ++
Seq(new MinimumLowFirrtlOptimization)
}
/** Currently just an alias for the [[VerilogCompiler]] */
class SystemVerilogCompiler extends VerilogCompiler {
Driver.dramaticWarning("SystemVerilog Compiler behaves the same as the Verilog Compiler!")
}
|
