blob: 8394d3f2d66ec3fd9f935b96a5addf79fde0f080 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
|
grammar FIRRTL;
/*------------------------------------------------------------------
* PARSER RULES
*------------------------------------------------------------------*/
/* TODO
* - Add [info] support (all over the place)
* - Add support for extmodule
*/
// Does there have to be at least one module?
circuit
: 'circuit' id ':' '{' module* '}'
;
module
: 'module' id ':' '{' port* block '}'
;
port
: dir id ':' type
;
dir
: 'input'
| 'output'
;
type
: 'UInt' ('<' IntLit '>')?
| 'SInt' ('<' IntLit '>')?
| 'Clock'
| '{' field* '}' // Bundle
| type '[' IntLit ']' // Vector
;
field
: 'flip'? id ':' type
;
// Much faster than replacing block with stmt+
block
: (stmt)*
;
stmt
: 'wire' id ':' type
| 'reg' id ':' type exp (exp exp)?
| 'mem' id ':' '{' 'data-type' '=>' type
'depth' '=>' IntLit
'read-latency' '=>' IntLit
'write-latency' '=>' IntLit
'read-under-write' '=>' ruw
('reader' '=>' id)*
('writer' '=>' id)*
('readwriter' '=>' id)*
'}'
| 'inst' id 'of' id
| 'node' id '=' exp
| exp '<=' exp
| exp '<-' exp
| exp 'is' 'invalid'
| 'when' exp ':' '{' block '}' ( 'else' ':' '{' block '}' )?
| 'stop(' exp exp IntLit ')'
| 'printf(' exp exp StringLit (exp)* ')'
| 'skip'
;
ruw
: 'old'
| 'new'
| 'undefined'
;
exp
: 'UInt' ('<' IntLit '>')? '(' IntLit ')'
| 'SInt' ('<' IntLit '>')? '(' IntLit ')'
| 'UBits' ('<' IntLit '>')? '(' StringLit ')'
| 'SBits' ('<' IntLit '>')? '(' StringLit ')'
| id // Ref
| exp '.' id
| exp '[' IntLit ']'
| exp '[' exp ']'
| 'mux(' exp exp exp ')'
| 'validif(' exp exp ')'
| primop exp* IntLit* ')'
;
id
: Id
| keyword
;
// TODO add all keywords
keyword
: dir
| 'inst'
;
// Parentheses are added as part of name because semantics require no space between primop and open parentheses
// (And ANTLR either ignores whitespace or considers it everywhere)
primop
: 'add('
| 'sub('
| 'mul('
| 'div('
| 'rem('
| 'lt('
| 'leq('
| 'gt('
| 'geq('
| 'eq('
| 'neq('
| 'pad('
| 'asUInt('
| 'asSInt('
| 'asClock('
| 'shl('
| 'shr('
| 'dshl('
| 'dshr('
| 'cvt('
| 'neg('
| 'not('
| 'and('
| 'or('
| 'xor('
| 'andr('
| 'orr('
| 'xorr('
| 'cat('
| 'bits('
| 'head('
| 'tail('
;
/*------------------------------------------------------------------
* LEXER RULES
*------------------------------------------------------------------*/
StringLit
: '"' .*? '"'
;
Id
: IdNondigit
( IdNondigit
| Digit
)*
;
fragment
IdNondigit
: Nondigit
| [~!@#$%^*-+=?/]
;
IntLit
: '0'
| ( '+' | '-' )? [1-9] ( Digit )*
| '"' 'h' ( HexDigit )+ '"'
;
fragment
Nondigit
: [a-zA-Z_]
;
fragment
Digit
: [0-9]
;
fragment
HexDigit
: [a-zA-Z0-9]
;
Comment
: ';' ~[\r\n]*
-> skip
;
Whitespace
: [ \t,]+
-> skip
;
Newline
: ( '\r'? '\n' )+
-> skip
;
|
