TODO


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TODO 
   change parser to use <> syntax (and update all tests)

   Write lowering step for primops
   Figure out how widths propogate for all updated primops (Adam)
   Add bit-reduce-and etc to primops (Jonathan)
   Write pass to rename identifiers (alpha-transform) (Adam)
   Add partial bulk connect (Scott, Stephen)
   Add FIFOs to the IR (Palmer)
   Registers/Memories only have data and enable fields, which can be written/read from. These are set by the front-end. This will probably have to wait (Palmer)
   Multi-streams for print statements (Jack)
   Consider def female node. (Patrick) 
   Think about supporting memories (Scott)
   Think about supporting generic primops on bundles and vecs (Adam) (wait until front-end more completed)

   Update spec
      add new field for sequential or combinational
      add assertions
   Future questions to address in spec:
      Introduction – motivation, and intended usage
      Philosophical justifications for all constructs
      More introduction for types, e.g. what is a ground type?
      What is a statement? What is an expression? What is a memory? Difference between vector type and memory? What are accessors for?
      Why would I ever write an empty statement? Mainly for use by compiler/passes
      What is a structural element? Duplication?
      Subtracting two unsigned numbers… Should talk to a math guy to figure it out
      What are shift left and shift right operations? HW doesn’t have these concepts. Need justification.
      What is lowered form? What is it for?


Checks:
   Subfields are only on bundles, before type inference 
   after adding dynamic assertions, insert bounds check with accessor expansion
   all things only assigned to once

Tests:
   Error if declare anything other than module in circuit
   Error if incorrectly assign stuff, like use = instead of :=
   Error: Node not parsed for stmts

Male node:
defnode n = e
==>
wire n
n := e

Female node:
defnode n = e
==>
wire n 
e := n